DISPLAY FACILITY

Abstract

A display device (100) comprises a substrate (110) with a plurality of pixel areas (UPA) spaced apart from one another, and a plurality of transmissive areas (TA) between the plurality of pixel areas (UPA), wherein each of the plurality of pixel areas (UPA) comprises a plurality of subpixels (SP 1, SP2, SP3); and a plurality of signal lines extending in a first direction on the substrate (110), wherein the plurality of subpixels comprises a plurality of pixel circuits, wherein the plurality of signal lines overlap the plurality of pixel circuits without the plurality of signal lines (DL) overlapping the plurality of transmissive areas (TA).Accordingly, the majority of pixel areas (UPA) and the majority of signal lines (DL) are located in the same area to reduce the size of the opaque area in the entire display device (100) and to increase the size of the transmissive area (TA) to implement a transparent display device.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Korean Patent Application No. 10-2023-0121471, filed with the Korean Intellectual Property Office on September 13, 2023. BACKGROUND area

[0002] The present disclosure relates to a transparent display device and, more particularly, to a transparent display device using a light emitting diode (LED). Description of the related technology

[0003] As display devices used for a computer monitor, a television, or a mobile phone, there are an organic light-emitting display (OLED), which is a self-emitting device, and a liquid crystal display (LCD), which requires a separate light source.

[0004] The applicable range of display devices is diverse, including personal digital assistants, computer monitors, and televisions. A display device with a large display area and reduced volume and weight is currently being investigated.

[0005] Furthermore, in recent years, LED displays have attracted attention as next-generation displays. Because LEDs are made of inorganic rather than organic materials, their reliability is excellent, resulting in a longer lifespan than liquid crystal displays or organic light-emitting displays. Furthermore, LEDs have fast illumination speeds, excellent luminous efficiency, and strong shock resistance, ensuring excellent stability and enabling the display of high-luminance images. SUMMARY

[0006] An object of the present disclosure is to provide a transparent display device with high transmittance.

[0007] Another object of the present disclosure is to provide a display device in which the size of a transmissive area is maximized.

[0008] Another object of the present disclosure is to provide a display device in which the interference between a driver transistor of the pixel region and a plurality of data lines is reduced.

[0009] Another object of the present disclosure is to provide a display device that reduces fluctuations in a voltage and a drive current of a drive transistor caused by a data line.

[0010] Another object of the present disclosure is to provide a display device that reduces the coupling between a data line and a driver transistor to improve display quality.

[0011] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following descriptions.

[0012] The present disclosure provides display devices according to the independent claims. Preferred embodiments are described in the dependent claims. According to one embodiment of the present disclosure, a display device comprises: a substrate having a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions between the plurality of pixel regions; and a plurality of data lines extending in a first direction on the substrate, wherein the plurality of pixel regions overlap the plurality of data lines without the plurality of data lines overlapping the plurality of transmissive regions. The first direction described here may be a column direction. A second direction described here may be a row direction.

[0013] In one embodiment, a display device comprises: a substrate having a pixel region and a light transmissive region that is more transparent than the pixel region; a first insulating layer on the substrate; a driving transistor on the first insulating layer in the pixel region; a signal line overlapping the driving transistor in the pixel region; a light-emitting element in the pixel region, the light-emitting element being electrically connected to the driving transistor, and a second insulating layer between the signal line and the driving transistor in the pixel region, the second insulating layer having a thickness that is greater than a thickness of the first insulating layer.

[0014] In one embodiment, a display device comprises: a substrate in which a plurality of pixel regions arranged to be spaced apart from each other and a plurality of transmissive regions arranged between the plurality of pixel regions are defined; and a plurality of wiring lines extending in a column direction on the substrate, wherein the plurality of pixel regions overlaps a region in which the plurality of wiring lines are arranged.

[0015] Further details of the exemplary embodiments are included in the detailed description and drawings.

[0016] According to one aspect of the present disclosure, a transparent display device with improved transmittance can be implemented.

[0017] According to another aspect of the present disclosure, opaque configurations among the configurations of the display device overlap to maximize the size of a transmissive area in the display device. According to some embodiments, an opaque pixel area and a plurality of wiring lines overlap to maximize the size of the transmissive area.

[0018] According to another aspect of the present disclosure, the voltage fluctuation of the driver transistor caused by the coupling of the data line and the driver transistor and a fluctuation of a driver current can thereby be reduced.

[0019] According to another aspect of the present disclosure, crosstalk and luminance change caused by the coupling of the data line and the driver transistor can be reduced.

[0020] The effects according to the present disclosure are not limited to the contents illustrated above, and the present description includes other effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features and other advantages of the present disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure; Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure; Fig. 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure; Fig. 3 is a schematic enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure; Fig. 4 is an enlarged top view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure; Fig. 5 is a cross-sectional view of a subpixel of a display device according to an exemplary embodiment of the present disclosure; Fig. 6 is a simulation result of measuring a crosstalk level corresponding to a thickness of an insulating layer; Fig. 7 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure; Fig. 8 is a cross-sectional view of a subpixel of a display device according to another exemplary embodiment of the present disclosure; Fig. 9A is a diagram obtained by measuring a voltage and a drive current of a drive gate electrode according to a data voltage in a display device according to a comparative embodiment; and Fig. 9B is a diagram obtained by measuring a voltage and a drive current of a drive gate electrode according to a data voltage in a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The advantages and features of the present disclosure, and a method for achieving the advantages and features, will become apparent with reference to the exemplary embodiments described in detail below, together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be embodied in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure.

[0023] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally indicate like elements throughout the specification. Furthermore, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted in order not to unnecessarily obscure the subject matter of the present disclosure. The terms "including," "with," and "comprising" as used herein are generally intended to allow the addition of other components unless the terms are used with the term "only." All references to the singular may include the plural unless expressly stated otherwise.

[0024] Components are interpreted to include a common error range, even if this is not explicitly stated.

[0025] When the positional relationship between two parts is described with terms such as "on", "over", "under" and "next to", one or more parts may be positioned between the two parts, unless the terms are used with the term "immediate" or "direct".

[0026] When an element or layer is disposed "on top of" another element or layer, the element or layer may be disposed directly on top of the other element or layer, or there may be another layer or element disposed between the element or layer and the other element or layer.

[0027] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0028] Like reference numerals generally identify like elements throughout the description.

[0029] The size and thickness of each component illustrated in the drawing are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated component.

[0030] The features of various embodiments of the present disclosure may remain together or be combined in part or in whole, and may be interconnected and operated in technically different ways, and the embodiments may be practiced independently of one another or in conjunction with one another.

[0031] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Fig. 1 is a schematic diagram of a display device 100 according to an exemplary embodiment of the present disclosure. In Fig. 1, for the convenience of description, among various components of the display device 100, a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are illustrated.

[0033] With reference to Fig. 1, the display device 100 comprises a display panel PN having a plurality of subpixels SP, a gate driver GD and a data driver DD, both of which supply different signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0034] The gate driver GD supplies a plurality of scanning signals to a plurality of scanning lines SL according to a plurality of gate control signals supplied from the timing controller TC. Although in Fig. 1 illustrates that a gate driver GD is arranged to be spaced from one side of the display panel PN, the number of gate drivers GD and their placement are not limited thereto.

[0035] The data driver DD supplies a data voltage to a plurality of data lines DL (e.g., signal lines) according to a plurality of data control signals and image data supplied by the timing controller TC. The data driver DD converts the image data into a data voltage using a reference gamma voltage and can supply the converted data voltage to the plurality of data lines DL.

[0036] The timing controller TC arranges externally input image data to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. Furthermore, the timing controller TC supplies the generated gate control signal and the data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0037] The display panel PN is a configuration that displays images to the user and has a plurality of subpixels SP. In the display panel PN, the plurality of scanning lines SL and the plurality of data lines DL intersect, and the plurality of subpixels SP are connected to the scanning lines SL and the data lines DL at the intersection points of the scanning lines SL and the data lines DL.

[0038] An active area AA and a non-active area NA can be defined in the display panel PN.

[0039] The active area AA is an area where images are displayed in the display device 100. In the active area AA, a plurality of subpixels SP configuring a plurality of pixels PX and a pixel circuit (or a plurality of pixel circuits) for driving the plurality of subpixels SP can be arranged. The plurality of subpixels SP is a minimum unit configuring the active area AA, and n subpixels SP form one pixel PX (e.g., n=3 or n=4). In each of the plurality of subpixels SP, a light-emitting diode 120 and a thin-film transistor for driving the light-emitting diode 120 can be arranged. The plurality of light-emitting diodes 120 of the plurality of subpixels SP can be defined in various ways depending on the type of the display panel PN.For example, when the display panel PN is an inorganic light-emitting display panel, each of the light-emitting diodes 120 may be a light-emitting diode (LED) or a micro-light-emitting diode (LED).

[0040] A plurality of signal lines are arranged in the active region AA, which transmit various signals to the plurality of subpixels SP. For example, the plurality of signal lines include a plurality of data lines DL that supply a data voltage to each of the plurality of subpixels SP, and a plurality of scan lines SL that supply a scan signal to each of the plurality of subpixels SP. The plurality of scan lines SL extend in one direction in the active region AA to be connected to the plurality of subpixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active region AA to be connected to the plurality of subpixels SP. In addition, a low-potential power line and a high-potential power line may be arranged in the active region AA, but the present disclosure is not limited thereto.

[0041] The non-active region NA is a region in which no images are displayed, so the non-active region NA can be defined as a region extending from the active region AA. In one embodiment, the non-active region NA surrounds the active region AA in the plan view of the display device. A connection line that transmits a signal to a subpixel SP of the active region AA, a pad electrode, or a driver IC, such as a gate driver IC or a data driver IC, can be arranged in the non-active region NA.

[0042] Meanwhile, the non-active area NA may be located on a rear surface of the display panel PN, ie, on a surface on which the subpixels SP are not arranged or can be omitted, and is not limited to, as illustrated in the drawing.

[0043] Meanwhile, a driver, such as a gate driver GD, a data driver DD, and a timing controller TC, can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active area NA in a gate-in-panel (GIP) manner or between the plurality of subpixels SP in the active area AA in a gate-in-active area (GIA) manner.

[0044] For example, the data driver DD and the timing controller TC are formed on separate flexible film and circuit board, and the display panel PN is electrically connected to the data driver DD and the timing controller TC by connecting the flexible film and circuit board to the pad electrode formed in the non-active area NA of the display panel PN.

[0045] As another example, if the gate driver GD is installed in the active area AA in the GIA manner, and a side line SRL connecting the signal line on the front surface of the display panel PN to the pad electrode on a rear surface of the display panel PN is used to connect the flexible film and the printed circuit board to a rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. Therefore, if the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, essentially a zero-frame can be implemented in which there is no frame, which can be described with reference to the Fig. 2A and Fig. 2B is described in more detail.

[0046] Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Fig. 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure.

[0047] In the non-active region NA of the display panel PN, a plurality of pad electrodes are arranged for transmitting various signals to the plurality of subpixels SP. For example, in a non-active region NA on the front surface of the display panel PN, a first pad electrode PAD1 is arranged, which transmits a signal to the plurality of subpixels SP. In a non-active region NA on the rear surface of the display panel PN, a second pad electrode PAD2 is arranged, which is electrically connected to a drive component, such as a flexible film, and the circuit board.

[0048] In this case, although not illustrated in the drawing, various signal lines connected to the plurality of subpixels SP, for example, a scan line SL or a data line DL, extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0049] Furthermore, the side line SRL is arranged along a side region of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the back surface of the display panel PN. Therefore, a signal from a driving component on the back surface of the display panel PN can be transmitted to the plurality of subpixels SP via the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Accordingly, a driving component is arranged on a back surface of the display panel PN, and a signal transmission path between the front surface and the back surface of the display panel PN is formed to minimize a size of the non-active area NA on the front surface of the display panel PN.

[0050] Furthermore, with reference to Fig. 2B, a tiled display device TD with a large screen size can be implemented by connecting a plurality of display devices 100. At the same time, as in Fig. 2A illustrates that when the tiled display TD is implemented using a display 100 with a minimized border, a seam area in which an image is not displayed between the display 100 is minimized, so that display quality can be improved.

[0051] For example, a pixel PX may include a plurality of subpixels SP, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in the one display device 100. Accordingly, the distance between pixels PX between the display devices 100 is configured to be constant to minimize the seam area.

[0052] The Fig. 2A and Fig. 2B are illustrative, so the display device 100 according to the exemplary embodiment of the present disclosure may be, but is not limited to, a general display device with a bezel.

[0053] Hereinafter, a display panel PN of a display device 100 according to an exemplary embodiment of the present disclosure will be described with reference to the Fig. 3 to 6 are described in more detail.

[0054] Fig. 3 is a schematic enlarged plan view of a pixel unit of an active area of ​​a display device according to an exemplary embodiment of the present disclosure. Fig. 4 is an enlarged top view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure. Fig. 5 is a cross-sectional view of a subpixel of a display device according to an exemplary embodiment of the present disclosure. Fig. 6 is a simulation result of measuring a crosstalk level corresponding to the thickness of an insulating layer. Fig. 3, for the convenience of description, only scanning lines SL and data lines DL are illustrated among a plurality of wiring lines, and only one pixel area UPA among a plurality of pixel areas UPA and a plurality of transmissive areas TA including the one pixel area UPA are illustrated.

[0055] With reference to Fig. 3, a pixel region UPA in which pixels PX are formed, and a plurality of transmissive regions TA enclosing the pixel region UPA are formed in the active region AA. In one embodiment, each transmissive region TA lacks pixels PX and is more transparent than the pixel region UPA. A pixel circuit including a driver element and a light-emitting diode 120 driven by the pixel circuit is formed in each pixel PX of the active region AA, such that the plurality of pixel regions UPA in which pixels PX are formed can be substantially opaque regions. Furthermore, the plurality of transmissive regions TA in which the pixels PX are not formed may be substantially transparent regions. In this case, the pixel region UPA defined by a pixel PX formed therein is a region in which light emitted by the light-emitting diode 120 is displayed, so it is also defined as an emission region. Furthermore, the pixel region UPA defined by the pixel PX formed therein is a region in which a pixel circuit including a driving element is formed, so it can also be defined as a circuit region.

[0056] A plurality of pixel regions UPA are formed in the active region AA. Each of the plurality of pixel regions UPA is a region in which a driving element and a light-emitting diode 120 are arranged to display images. The plurality of pixel regions UPA may be arranged to be spaced apart from each other, with the plurality of transmissive regions TA located therebetween. For example, the plurality of pixel regions UPA may be arranged by forming a plurality of rows and a plurality of columns.

[0057] A plurality of subpixels SP are arranged in each of the plurality of pixel regions UPA. Each of the plurality of subpixels SP includes a light-emitting diode 120 and a pixel circuit for independently emitting light. For example, the plurality of subpixels SP may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 that emit light of different colors. For example, the first subpixel SP1 is a red subpixel, the second subpixel SP2 is a green subpixel, and the third subpixel SP3 is a blue subpixel, but the present disclosure is not limited thereto.

[0058] In the following description, it is assumed that a pixel PX has two first subpixels SP1, two second subpixels SP2 and two third subpixels SP3, for example, two red subpixels, two green subpixels and two blue subpixels, but the configuration of the pixel PX is not limited to this.

[0059] Meanwhile, a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3 may be used as main subpixels SP and redundant subpixels SP, respectively. For example, a first subpixel SP1 of a pair of first subpixels SP1, a second subpixel SP2 of a pair of second subpixels SP2, and a third subpixel SP3 of a pair of third subpixels SP3 may be main subpixels SP, which are mainly used when driving the display device 100. When displaying an image, the main subpixels SP may be used according to one embodiment. Furthermore, the remaining first subpixel SP1 of the one pair of first subpixels SP1, the remaining second subpixel SP2 of the one pair of second subpixels SP2, and the remaining third subpixel SP3 of the pair of third subpixels SP3 may be redundant subpixels SP, so that when the main subpixel SP is defective, the redundant subpixel SP can be used instead of the main subpixel.

[0060] Furthermore, a placement order of the main subpixels SP may be configured to correspond to the placement order of the redundant subpixels SP. For example, the subpixels SP constituting the main subpixels SP may be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. Furthermore, the subpixels SP constituting the redundant subpixels SP may also be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0061] However, a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3 are not limited to the main subpixels SP and the backup subpixels SP, but all subpixels can always be used while driving the display device 100. Furthermore, the placement order of the subpixels SP is not limited to the placement order described above.

[0062] The pixel region UPA may overlap wiring lines of the plurality of wiring lines extending in a column direction, for example, data lines DL and reference lines RL. The column direction may be referred to as a first direction. The pixel region UPA is formed in a region where a plurality of opaque wiring lines are arranged to ensure a size of the transmissive area TA in the entire active area AA. In particular, the pixel region UPA, in which the plurality of subpixels SP are arranged, has a low transmittance and is substantially an opaque area due to the configurations such as the pixel circuit and the light-emitting diode 120 arranged in the plurality of subpixels SP.Therefore, the plurality of subpixels SP of the pixel region UPA may be arranged to overlap an opaque wiring line extending in a column direction, such as a data line DL, a reference line RL, a low-potential power line VSS, and a high-potential power line VDD. Accordingly, the plurality of subpixels SP of the pixel region UPA are arranged to overlap the plurality of wiring lines to reduce the size of the opaque region in the entire active region AA and maximize the size of the transmissive region TA.

[0063] The plurality of subpixels SP arranged in a pixel area UPA may be formed to have a rectangular shape or an "L" shape in a plan view of the display device. For example, a first subpixel SP1 (e.g., a first main subpixel), a second subpixel SP2 (e.g., a second main subpixel), and a third subpixel SP3 (e.g., a third main subpixel) may be arranged on one side (e.g., a first side) of the scanning line SL, and a first subpixel SP1 (e.g., a first redundant subpixel), a second subpixel SP2 (e.g., a second redundant subpixel), and a third subpixel SP3 (e.g., a third redundant subpixel) may be arranged on the other side (e.g., a second side) of the scanning line SL.In one embodiment, the first main subpixel SP1 and the first redundancy subpixel SP1 emit a first light color, the second main subpixel SP2 and the second redundancy subpixel SP2 emit a second light color, and the third main subpixel SP3 and the third redundancy subpixel SP3 emit a third light color.

[0064] On each side of the scan line SL, the first subpixel SP1 is arranged in a rectangular region, and the second subpixel SP2 is arranged in an L-shaped region enclosing two adjacent sides of the four sides of the first subpixel SP1. Furthermore, the third subpixel SP3 may be arranged in the "L"-shaped region enclosing an outer part of the L-shaped second subpixel SP2. Therefore, a pixel region UPA configured by the first subpixel SP1 having a rectangular shape and the second subpixel SP2 and the third subpixel SP3 having an L shape can jointly form a rectangular shape. In one embodiment, the second subpixel SP2 is located between the first subpixel SP1 and the third subpixel SP3 in the top view of the display device.

[0065] Each of the plurality of transmissive regions TA is a region of the active region AA except for a region where the plurality of wiring lines and the plurality of pixel regions UPA are arranged. That is, each transmissive region TA may be a region of the active region AA where none of the plurality of wiring lines are arranged. In other words, the transmissive regions TA may be free of any wiring lines, pixel circuits, and light-emitting diodes. A light transmittance of the plurality of transmissive regions TA is higher than that of the plurality of pixel regions UPA. Light is transmitted through the transmissive region TA, and a background located on the back surface of the display device 100 is visible from the front surface of the display device 100.The plurality of transmissive regions TA may be spaced apart from one another, with the plurality of wiring lines and the plurality of pixel regions UPA located therebetween. The plurality of transmissive regions TA may be arranged to enclose the plurality of pixel regions UPA. Accordingly, the display device 100 according to the exemplary embodiment of the present disclosure may be implemented as a transparent display device 100 having a plurality of transmissive regions TA.

[0066] With reference to Fig. 3 to 5, each of the plurality of subpixels SP includes a pixel circuit and one or more light-emitting diodes 120. The pixel circuit includes a plurality of transistors T1, T2, and DT, as well as a storage capacitor Cst for supplying a drive current to the light-emitting diode 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a drive transistor DT, and a storage capacitor Cst. Furthermore, the plurality of subpixels SP arranged in a pixel region UPA are connected to the scan line SL, the plurality of data lines DL, the reference line RL, the high-potential power line VDD, and the low-potential power line VSS to be supplied with various signals.

[0067] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be formed from an insulating material. For example, the substrate 110 may be formed from glass or resin. Furthermore, the substrate 110 may be configured to include polymers or plastics, or it may be formed from a material with flexibility.

[0068] A light-shielding layer LS is disposed in each of the plurality of subpixels SP on the substrate 110. The light-shielding layer LS blocks light incident from below the substrate 110 onto a driving active layer DACT of the driver transistor DT, which will be described below. Light incident on the driving active layer DACT of the driver transistor DT is blocked by the light-shielding layer LS to minimize leakage current.

[0069] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the permeation of moisture or contaminants through the substrate 110. The buffer layer 111 can be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. However, the buffer layer 111 can be omitted depending on the type of substrate 110 or the type of transistor, but the present disclosure is not limited thereto.

[0070] The driver transistor DT, the first transistor T1 and the second transistor T2 are arranged in each of the plurality of subpixels SP on the buffer layer 111.

[0071] The driver transistor DT, the first transistor T1, and the second transistor T2 of each of the plurality of subpixels SP may be P-type thin-film transistors or N-type thin-film transistors. For example, in a P-type thin-film transistor, since holes move from the source electrode to the drain electrode, the current flows from the source electrode to the drain electrode. In an N-type thin-film transistor, since electrons move from the source electrode to the drain electrode, the current flows from the drain electrode to the source electrode. Hereinafter, it is assumed that the driver transistor DT, the first transistor T1, and the second transistor T2 are P-type thin-film transistors in which the current flows from the source electrode to the drain electrode, but the present disclosure is not limited thereto.

[0072] First, the driver transistor DT is arranged in each of the plurality of subpixels SP on the buffer layer 111. The driver transistor DT is a transistor that controls a drive current supplied to the light-emitting diode 120. In a pixel region UPA, the driver transistor DT of each of the plurality of subpixels SP may be arranged in a line along the column direction. The plurality of driver transistors DT of the plurality of subpixels SP may be arranged in a line while overlapping an area where the reference line RL and the data line DL are arranged.

[0073] The driver transistor DT comprises a driver active layer DACT, a driver gate electrode DGE, a driver source electrode DSE and a driver drain electrode DDE.

[0074] The driver active layer DACT is arranged on the buffer layer 111. The driver active layer DACT may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0075] A gate insulating layer 112 is disposed on the driver active layer DACT. The gate insulating layer 112 is an insulating layer that insulates the driver active layer DACT from the driver gate electrode DGE. The gate insulating layer 112 can be configured from, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0076] The driver gate electrode DGE is disposed on the gate insulating layer 112. The driver gate electrode DGE may be configured from a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0077] A first interlayer insulating layer 113a is disposed on the driver gate electrode DGE. A contact hole is formed in the first interlayer insulating layer 113a through which the driver source electrode DSE contacts the driver active layer DACT. The first interlayer insulating layer 113a is an insulating layer that protects components beneath the first interlayer insulating layer 113a. The first interlayer insulating layer 113a may be composed of, but is not limited to, a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx.

[0078] The driver source electrode DSE is disposed on the first interlayer insulating layer 113a. The driver source electrode DSE is electrically connected to the driver active layer DACT via a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the driver source electrode DSE may be electrically connected to the second transistor T2. The driver source electrode DSE may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0079] A second interlayer insulating layer 113b is disposed on the driver source electrode DSE. The second interlayer insulating layer 113b is an insulating layer that protects components beneath the second interlayer insulating layer 113b. The second interlayer insulating layer 113b may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0080] A first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer that protects components beneath the first passivation layer 114a. The first passivation layer 114a may be configured from, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0081] The driver drain electrode DDE is disposed on the first passivation layer 114a. The driver drain electrode DDE is electrically connected to the driver active layer DACT via a contact hole formed in the first passivation layer 114a, the first interlayer insulating layer 113a, the second interlayer insulating layer 113b, and the gate insulating layer 112. Furthermore, the driver drain electrode DDE may be electrically connected to the low-potential power line VSS via a contact hole formed in the first passivation layer 114a. The driver drain electrode DDE may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0082] Furthermore, the first transistor T1 is arranged in each of the plurality of subpixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits a data voltage Vdata to the driver gate electrode DGE of the driver transistor DT and is referred to as a switching transistor. At the same time, the plurality of first transistors T1 of the plurality of subpixels SP are arranged to overlap the scanning line SL and a protruding part of the scanning line SL in a pixel area UPA and may be arranged in a line along the row direction. The row direction may be referred to as a second direction.

[0083] In particular, the scanning line SL extends in the row direction on the gate insulating layer 112 and may be arranged over the plurality of pixel regions UPA. At the same time, the scanning line SL may include a portion that protrudes on both sides of the scanning line SL toward the plurality of subpixels SP in an area that overlaps the plurality of pixel areas UPA. The portion that protrudes to one side of the scanning line SL may include a portion that extends in the column direction and a portion that extends from an end portion of the column-direction-extending portion in a row direction. That is, the scanning line SL may further include a projecting portion that has a portion that protrudes from the scanning line SL and extends at least partially in the row direction. For example, a portion that protrudes from one side of the scanning line SL may be L-shaped. Furthermore, a portion that protrudes from the other side of the scanning line SL may include a portion that extends in the column direction.

[0084] Furthermore, the first transistors T1 of the plurality of subpixels SP on one side of the scanning line SL may be arranged in a line along a portion of the protruding portion of the scanning line SL extending in the row direction. Furthermore, the first transistors T1 of the plurality of subpixels SP on the other side of the scanning line SL may be arranged in a line along the scanning line SL extending in the row direction. Accordingly, the plurality of first transistors T1 on one side of the scanning line SL are arranged in a line along the row direction on the protruding portion of the scanning line SL, and the plurality of first transistors T1 on the other side of the scanning line SL may be arranged in a line along the row direction on the scanning line SL.The scanning line SL is divided into two branches in a pixel area UPA, so that the first transistor T1 of the main subpixel SP and the first transistor T1 of the redundant subpixel SP are simply separated. Therefore, the main subpixel SP and the redundant subpixel SP are connected to different first transistors T1 to be controlled.

[0085] The first transistor T1 comprises a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1 and a first drain electrode DE1.

[0086] The first active layer ACT1 is disposed between the buffer layer 111 and the gate insulating layer 112. The first active layer ACT1 may be formed from a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0087] The first gate electrode GE1 is arranged on the gate insulating layer 112. The first gate electrode GE1 may be electrically connected to the scan line SL. For example, the first gate electrode GE1 may be formed integrally with the scan line SL. The first gate electrode GE1 may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0088] The first drain electrode DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 via a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. Furthermore, the first drain electrode DE1 may be electrically connected to the second gate electrode GE2 of the second transistor T2 via a contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 may be configured from a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0089] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 via a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. Further, the first source electrode SE1 may be electrically connected to the data line DL. For example, the first source electrode SE1 may be integrally formed with the data line DL. The first source electrode SE1 may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0090] Furthermore, the second transistor T2 is arranged in each of the plurality of subpixels SP on the buffer layer 111. The second transistor T2 is a transistor for compensating a threshold voltage of the driver transistor DT and is referred to as a sensor transistor. The second transistors T2 of the plurality of subpixels SP may be arranged in a line along a part of the protruding part of the scanning line SL extending in the column direction. For example, the second transistors T2 of the plurality of subpixels SP on one side of the scanning line SL are arranged to correspond to a part of the protruding part of the scanning line SL extending in the column direction. The second transistors T2 of the plurality of subpixels SP on the other side of the scanning line SL may be arranged to correspond to the protruding part of the scanning line SL.Therefore, the plurality of second transistors T2 arranged in a pixel region UPA may be arranged in a line along the column direction.

[0091] The second transistor T2 comprises a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2 and a second drain electrode DE2.

[0092] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be formed from a semiconductor material such as, but is not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0093] At the same time, the second active layers ACT2 of the plurality of adjacent subpixels SP may be connected to each other. For example, the second active layers ACT2 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, which are arranged on one side of the scanning line SL, may be connected to each other while extending in the column direction and connected to the second drain electrode DE2 arranged in the first subpixel SP1. Furthermore, the second active layers ACT2 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, which are arranged on the other side of the scanning line SL, may be connected to each other while extending in the column direction and connected to the second drain electrode DE2 arranged in the first subpixel SP1.That is, a connection part connecting the channel region of the second active layer ACT2 of the plurality of subpixels SP and the reference line RL is formed from a transparent material of the second active layer ACT2 rather than an opaque conductive material. Therefore, the transmittance at the outermost edge of the pixel region UPA can be improved. Furthermore, the connection part connecting the channel region of the second active layer ACT2 of the plurality of subpixels SP and the reference line RL is formed from a material of the second active layer ACT2, so that the contact hole can be omitted and the structure of the pixel region UPA can be simplified.

[0094] The second gate electrode GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 may be electrically connected to the scan line SL. For example, the second gate electrode GE2 may be integrally formed with the protruding part of the scan line SL to be electrically connected. The second gate electrode GE2 may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0095] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 via a contact hole of the first interlayer insulating layer 113a and the gate insulating layer 112. Further, the second source electrode SE2 is integrally formed with the driver source electrode DSE to be electrically connected to the driver source electrode DSE. The second source electrode SE2 may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0096] The second drain electrode DE2 is disposed between the first passivation layer 114a and a second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 via a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 is integrally formed with the reference line RL to be electrically connected to the reference line RL. The second drain electrode DE2 may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0097] Further, the storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst stores a potential difference between the driver gate electrode DGE and the driver source electrode DSE of the driver transistor DT while the light-emitting diode 120 emits light, so that a constant drive current can be supplied to the light-emitting diode 120. The storage capacitor Cst includes a first capacitor electrode C1 electrically connected to the driver gate electrode DGE and a second capacitor electrode C2 electrically connected to the driver source electrode DSE. Therefore, the storage capacitor Cst can maintain a constant voltage between the driver gate electrode DGE and the driver source electrode DSE.

[0098] Specifically, the first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 is integrally formed with the driver gate electrode DGE. The second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be disposed so as to overlap with the first interlayer insulating layer 113a therebetween. At the same time, the second capacitor electrode C2 is integrally formed with the driver source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may be configured by a single layer or a plurality of layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but the present disclosure is not limited thereto.

[0099] Furthermore, an auxiliary electrode AE ​​is arranged on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driver source electrode DSE and a first reflective electrode RE1. The driver source electrode DSE and the first reflective electrode RE1 are electrically connected to each other via the auxiliary electrode AE. The auxiliary electrode AE ​​can be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0100] A low-potential power line VSS is arranged on the second interlayer insulating film 113b. The low-potential power line VSS is arranged along the column direction and overlaps the plurality of pixel regions UPA. The low-potential power line VSS may be electrically connected to the driver drain electrode DDE. The low-potential power line VSS may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0101] The reference line RL is arranged on the first passivation layer 114a. In one embodiment, the reference line RL overlaps the driver transistor DT. The reference line RL is arranged along the column direction and overlaps the plurality of pixel regions UPA. The reference line RL is arranged to be adjacent to a protruding part of the scan line SL and may be electrically connected to the plurality of second transistors T2 arranged on the protruding part of the scan line SL. The reference line RL may be configured by a single layer or a plurality of layers of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0102] A plurality of data lines DL are arranged on the first passivation layer 114a. The plurality of data lines DL extend in the column direction and overlap the plurality of pixel regions UPA. The plurality of data lines DL includes a data line DL connected to the first transistors T1 of the plurality of first subpixels SP1, a data line DL connected to the first transistors T1 of the plurality of second subpixels SP2, and a data line DL connected to the first transistors T1 of the plurality of third subpixels SP3. In one embodiment, as shown in Fig. 5, each data line DL has a corresponding driver transistor DT.

[0103] Furthermore, the second passivation layer 114b is disposed on the driver transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b is an insulating layer that protects components beneath the second passivation layer 114b and may be configured from, but is not limited to, a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx.

[0104] The first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize an upper portion of the substrate 110 on which the plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115a may be configured as a single layer or a double layer and may be formed from, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0105] However, although not illustrated in the drawing, an additional passivation layer may be disposed on the first planarization layer 115a. For example, a passivation layer consisting of a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx may be formed on the first planarization layer 115a to protect configurations beneath the passivation layer.

[0106] Furthermore, a plurality of first reflective electrodes RE1 are arranged on the first planarization layer 115a. The plurality of first reflective electrodes RE1 are arranged in each of the plurality of subpixels SP to electrically connect the driver transistor DT and the light-emitting diode 120 and to reflect light emitted from the light-emitting diode 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be arranged to be adjacent to the driver source electrode DSE in each of the plurality of subpixels SP. The plurality of first reflective electrodes RE1 may be formed of an opaque conductive material with high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but the present disclosure is not limited thereto.

[0107] A second reflective electrode RE2 and the high-potential power line VDD are arranged on the first planarization layer 115a. The second reflective electrode RE2 and the high-potential power line VDD are integrally formed to reflect light emitted from the light-emitting diode 120 to the outside of the display device 100 while supplying a high-potential power supply voltage to the light-emitting diode 120. The second reflective electrodes RE2 of the plurality of subpixels SP are connected to each other to be integrally formed. The second reflective electrode RE2 and the high-potential power line VDD extend in the column direction and overlap the light-emitting diode 120. The second reflective electrode RE2 and the high-potential power line VDD may be arranged to overlap the plurality of data lines DL, the reference line RL, and the low-potential power line VSS.The second reflective electrode RE2 and the high-potential power line VDD may be formed of an opaque conductive material with high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but the present disclosure is not limited thereto.

[0108] A third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and the second reflective electrode RE2. The third passivation layer 114c is an insulating layer that protects components beneath the third passivation layer 114c and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx.

[0109] An adhesive layer AD is disposed on the third passivation layer 114c. The adhesive layer AD is formed on the front surface of the substrate 110 to fix the light-emitting diode 120 disposed on the adhesive layer AD. The adhesive layer AD may be made of a photocurable adhesive material that is cured by light. For example, the adhesive layer AD may be selected from any adhesive polymer, epoxy resin, UV resin, polyimide, acrylate, urethane, and polydimethylsiloxane (PDMS), but is not limited to these.

[0110] The plurality of light-emitting diodes 120 are arranged in each of the plurality of subpixels SP on the adhesive layer AD. Each light-emitting diode 120 is an element that emits light through a current. And each light-emitting diode 120 can be a red light-emitting diode 120R that emits red light, a green light-emitting diode 120G that emits green light, or a blue light-emitting diode 120B that emits blue light. Light of various colors, including white, can be generated by a combination of the plurality of light-emitting diodes 120, for example, by a combination of a red light-emitting diode 120R, a green light-emitting diode 120G, and a blue light-emitting diode 120B. For example, each light emitting diode 120 may be, but is not limited to, a light emitting diode (LED) or a micro-LED.

[0111] The red light-emitting diode 120R may be arranged in the first subpixel SP1, the green light-emitting diode 120G may be arranged in the second subpixel SP2, and the blue light-emitting diode 120B may be arranged in the third subpixel SP3. The plurality of light-emitting diodes 120 arranged in a pixel region UPA may be arranged in a line along the column direction. Furthermore, the plurality of light-emitting diodes 120 may be arranged to overlap the second reflective electrode RE2 in each of the plurality of subpixels SP.

[0112] Meanwhile, when the plurality of subpixels SP are divided into the main subpixel SP and the backup subpixel SP as described above, the plurality of light-emitting diodes 120 may also be divided into a main light-emitting diode 120 and a backup light-emitting diode 120. For example, one of a pair of first subpixels SP1, one of a pair of second subpixels SP2, and one of a pair of third subpixels SP3 are main subpixels SP. Therefore, the red light-emitting diode 120R, the green light-emitting diode 120G, and the blue light-emitting diode 120B arranged in each main subpixel SP may be main light-emitting diodes 120. For example, the other subpixel of one pair of first subpixels SP1, the other subpixel of one pair of second subpixels SP2 and the other subpixel of one pair of third subpixels SP3 are redundancy subpixels SP.Therefore, the red light-emitting diode 120R, the green light-emitting diode 120G, and the blue light-emitting diode 120B arranged in the respective redundancy subpixel SP may be redundancy light-emitting diodes 120.

[0113] Each of the plurality of light-emitting diodes 120 includes a first semiconductor layer 121, an emission layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0114] The first semiconductor layer 121 is disposed on the adhesive layer AD, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited to these.

[0115] The emission layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The emission layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The emission layer 122 may be formed by a single layer or a multi-quantum well (MQW) structure and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0116] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 may be disposed on the upper surface of the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driver transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with an n-type impurity, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on an upper surface of the first semiconductor layer 121 exposed from the emission layer 122 and the second semiconductor layer 123.The first electrode 124 may be made of a conductive material, such as, but not limited to, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0117] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects the high-potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with a p-type impurity, and the second electrode 125 may be an anode. The second electrode 125 may be configured from a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as, but not limited to, titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0118] Furthermore, the encapsulation film 126 is arranged to enclose the first semiconductor layer 121, the emission layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is made of an insulating material to protect the first semiconductor layer 121, the emission layer 122, and the second semiconductor layer 123. A contact hole exposing the first electrode 124 and a contact hole exposing the second electrode 125 are formed in the encapsulation film 126 to electrically connect a first connection electrode CE1 and a second connection electrode CE2 to the first electrode 124 and the second electrode 125, respectively.

[0119] Meanwhile, a part of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126 (in other words, the part of the side surface may not be covered by the encapsulation film 126). During the manufacture of the display device 100, the light-emitting diode 120 formed on a wafer is separated from the wafer to be transferred to the display panel PN. However, during the separation process of the light-emitting diode 120 from the wafer, a part of the encapsulation film 126 may crack. For example, a part of the encapsulation film 126 adjacent to a lower edge of the first semiconductor layer 121 of the light-emitting diode 120 may crack during the separation process of the light-emitting diode 120 from the wafer. Accordingly, a part of a lower side surface of the first semiconductor layer 121 may be exposed to the outside.Although the lower part of the light-emitting diode 120 is exposed from the encapsulation film 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121 are formed. Accordingly, a short-circuit failure can be reduced or prevented.

[0120] Furthermore, the second planarization layer 115b and the third planarization layer 115c are arranged on the adhesive layer AD and the light-emitting diode 120.

[0121] The second planarization layer 115b overlaps a portion of the side surfaces of the plurality of light-emitting diodes 120 to fix and protect the plurality of light-emitting diodes 120. A cracked portion of the encapsulation film 126 protecting the side surface of the first semiconductor layer 121 of the light-emitting diode 120 can be covered by the second planarization layer 115b. This can subsequently suppress contact and short-circuit defects between the connecting electrodes and the first semiconductor layer 121.

[0122] The third planarization layer 115c is formed to cover the second planarization layer 115b and upper portions of the light-emitting diode 120. A contact hole exposing the first electrode 124 and a contact hole exposing the second electrode 125 of the light-emitting diode 120 are formed in the third planarization layer 115c. The first electrode 124 and the second electrode 125 of the light-emitting diode 120 are exposed by the third planarization layer 115c (in other words, at least a part of the first electrode 124 and at least a part of the second electrode 125 may not be covered by the third planarization layer 115c), and the third planarization layer 115c is partially disposed in a region between the first electrode 124 and the second electrode 125 to reduce a short-circuit defect.The second planarization layer 115b and the third planarization layer 115c may be configured as a single layer or a double layer and may be made of, for example, photoresist or an acrylic-based organic material, but the present disclosure is not limited thereto.

[0123] The first connection electrode CE1 and the second connection electrode CE2 are arranged on the third planarization layer 115c.

[0124] The first connection electrode CE1 is an electrode that electrically connects the first electrode 124 of the light-emitting diode 120 and the driver transistor DT. The first connection electrode CE1 is electrically connected to the first electrode 124 exposed from the third planarization layer 115c and is electrically connected to the first reflective electrode RE1 via a contact hole simultaneously formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Therefore, the first electrode 124 and the driver source electrode DSE can be electrically connected via the first connection electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0125] The second connection electrode CE2 is an electrode that electrically connects the second electrode 125 of the light-emitting diode 120 and the high-potential power line VDD. The second connection electrode CE2 is electrically connected to the second electrode 125 exposed from the third planarization layer 115c. The second connection electrode CE2 is electrically connected to the second reflective electrode RE2 and the high-potential power line VDD via a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Accordingly, the second electrode 125 and the high-potential power line VDD are electrically connected via the second connection electrode CE2.

[0126] The first connection electrode CE1 and the second connection electrode CE2 may be formed of a transparent conductive material such as, but not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0127] Meanwhile, the drawing illustrates that the driver source electrode DSE of the driver transistor DT and the first electrode 124 of the light-emitting diode 120 are electrically connected. However, the driver drain electrode DDE of the driver transistor DT and the second electrode 125 of the light-emitting diode 120 may be electrically connected depending on the type of the driver transistor DT and a pixel circuit configuration.

[0128] Furthermore, in the pixel region UPA, a bank BB is arranged on the third planarization layer 115c, the first connection electrode CE1, and the second connection electrode CE2. The bank BB may be arranged to be spaced from the light-emitting diode 120 by a predetermined distance. The bank BB is arranged at a boundary between the plurality of subpixels SP and covers a part of the first connection electrode CE1 and the second connection electrode CE2. The bank BB may be arranged to be spaced from a transmissive region TA. The bank BB may be formed of an opaque material to reduce color mixing between the plurality of subpixels SP, and may be formed of, for example, but not limited to, black resin.

[0129] A protective layer 116 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 116 is a layer for protecting configurations beneath the protective layer 116. The protective layer 116 can be configured as a single layer or a double layer, for example, it can be configured from, but is not limited to, benzocyclobutene (BCB), light-transmissive epoxy, photoresist, an organic acrylic-based material, or an inorganic material such as silicon oxide SiOx or silicon nitride SiNx.

[0130] Meanwhile, the plurality of subpixels SP may be arranged to overlap the plurality of wiring lines to expand the size of the transmissive area TA. At the same time, fluctuations in the drive current in each of the plurality of subpixels SP may occur due to some wiring lines. For example, the drive transistor DT and the storage capacitor Cst of each of the plurality of subpixels SP overlap the data line DL to be coupled to the data line DL. As shown in Fig. As shown in Figure 5, the data line DL overlaps at least one of the following: the driving source electrode DSE, the driving gate electrode DGE, or the driving active layer DACT. In this case, the voltage of the driving gate electrode DGE may fluctuate due to a data line to which a different voltage is applied every image frame. When the voltage of the driving gate electrode DGE fluctuates, a driving current flowing through the light-emitting diode 120 fluctuates, and a change in luminance due to crosstalk occurs, thereby degrading the display quality.

[0131] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a thickness of an insulating layer is adjusted taking into account a dielectric constant of the insulating layer disposed between the storage capacitor Cst and the driver transistor DT and the data line DL. Accordingly, the voltage fluctuation of the driver gate electrode DGE caused by the data line DL can be reduced. For example, inorganic insulating layers disposed on the substrate 110, that is, the insulating layers such as the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a, and the second passivation layer 114b, can be formed to have a thickness of several thousand angstroms (Å).However, the thicknesses of the first passivation layer 114a and the second interlayer insulating layer 113b, which are insulating layers disposed between the data line DL and the storage capacitor Cst, differ from the thicknesses of the other insulating layers by at least a few micrometers (µm). In this way, the voltage fluctuation of the driver transistor DT caused by the data line DL can be minimized. Therefore, a thickness of the insulating layer between the data line DL and the storage capacitor Cst can be greater than a thickness of the buffer layer 111, a thickness of the gate insulating layer 112, a thickness of the first interlayer insulating layer 113a, and a thickness of the second passivation layer 114b.

[0132] With reference to Fig. 6, when the width of the data line DL is 1 µm, the thickness of the insulating layer can be determined by the material and dielectric constant of the insulating layer disposed beneath the data line DL. Increasing the thickness of the insulating layer can reduce the degree of luminance change caused by crosstalk. At the same time, when the insulating layer is made of silicon nitride SiNx with a dielectric constant of about 6.69 and the target crosstalk is 2%, the thickness of the insulating layer is set to about 16.55 µm or more to keep the degree of luminance change caused by crosstalk below 2%. At the same time, when the insulating layer is made of silicon oxide SiOx with a dielectric constant of about 4.3 and the target crosstalk is 2%, the thickness of the insulating layer is set to about 10.64 µm or more in order to keep the luminance change rate due to the crosstalk below 2%.Therefore, when the width of the data line DL is 1 µm, a total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b of at least 10.64 µm or more is formed to minimize the voltage fluctuation of the driver transistor DT and the storage capacitor Cst connected to the driver transistor DT caused by the data line DL. Furthermore, when the width of the data line DL is increased, it may be necessary to use a thicker insulating layer to implement the same crosstalk level.

[0133] Accordingly, the total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b can be determined by considering the width of the data line DL, the dielectric constant of the first passivation layer 114a and the second interlayer insulating layer 113b, and a target crosstalk level. Furthermore, the drive current can be kept constant while minimizing the interference between the data line DL and the drive transistor DT and the storage capacitor Cst connected to the drive transistor DT.

[0134] In the display device 100 according to the exemplary embodiment of the present disclosure, the plurality of pixel regions UPA are arranged in an area where a plurality of wiring lines extending in a column direction are arranged to maximize a size of the transmissive area TA. The pixel region UPA, which includes the pixel circuit and the light-emitting diode 120, which are to be substantially opaque, is arranged together with an opaque wiring line to reduce the size of the opaque area in the active area AA. For example, a data line DL and / or a reference line RL (as an example of an opaque wiring line extending in the column direction) may be arranged to overlap with the light-emitting diode 120 in a plan view of the display device 100.For example, in a cross-sectional view of the display device 100, the data line DL and / or the reference line RL may be arranged between the light-emitting diode 120 and a thin-film transistor (e.g., the driver transistor DT) and / or the storage capacitor Cst of the pixel circuit. Therefore, the size of the transmissive area TA is maximized to improve the overall transmittance of the display device 100 and implement a transparent display device 100.

[0135] In the display device 100 according to the exemplary embodiment of the present disclosure, the voltage fluctuation of the driver transistor DT caused by the data line DL can be minimized or at least reduced. When the data line DL and the pixel region UPA are configured to overlap to ensure the size of the transmissive area TA, the configuration of the data line DL and the pixel region UPA may be coupled, causing voltage fluctuations. For example, the data line DL, which overlaps the driver transistor DT and the storage capacitor Cst, may be coupled to the driver transistor DT and the storage capacitor Cst, and the voltages of the driver transistor DT and the storage capacitor Cst may fluctuate, causing the luminance to fluctuate and degrading the display quality.Therefore, the insulating layer between the data line DL and the driver transistor DT and the storage capacitor Cst is formed thick to minimize or at least reduce the influence of the data line DL. At the same time, the thickness of the insulating layer can be determined by considering the dielectric constant of the insulating layer, the width of the data line DL, and a target crosstalk level. Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, a thickness of an insulating layer, among the plurality of insulating layers, between the data line DL and the driver transistor DT is formed relatively thick. Therefore, the fluctuation of the drive current caused by the data line DL is minimized or at least reduced, and the display quality can be improved.

[0136] Fig. 7 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Fig. 8 is a cross-sectional view of a subpixel of a display device according to another exemplary embodiment of the present disclosure. Fig. 9A is a diagram obtained by measuring a voltage and a drive current of a drive gate electrode according to a data voltage in a display device according to a comparative embodiment. Fig. 9B is a diagram obtained by measuring a voltage and a drive current of a drive gate electrode according to a data voltage in a display device according to another exemplary embodiment of the present disclosure. In a display panel PN' of the Fig. 7 and Fig. 8 only one low-potential power line VSS differs from the display panel PN of the Fig. 1 to 5, but the other configurations are essentially the same, so redundant description is omitted.

[0137] With reference to Fig. 7 and Fig. 8, the low-potential power line VSS is arranged to overlap the plurality of data lines DL between the second interlayer insulating layer 113b and the first passivation layer 114a. The low-potential power line VSS can overlap a region where the plurality of data lines DL are arranged. The low-potential power line VSS has a relatively large width, so that one low-potential power line VSS and the plurality of data lines DL overlap. The low-potential power line VSS can cover the storage capacitor Cst and the driver transistor DT of the plurality of subpixels SP'. Only the low-potential power line VSS is arranged between the second interlayer insulating layer 113b and the first passivation layer 114a, so that the low-potential power line VSS can be easily formed in a remaining region except for a region where a contact hole is arranged.

[0138] An opening may be formed in the low-potential power line VSS, overlapping the contact hole. For example, an opening may be formed in the low-potential power line VSS, overlapping a contact hole through which the first source electrode SE1 and the first active layer ACT1 are connected, and a contact hole through which the driver-drain electrode DDE and the driver active layer DACT are connected. The first source electrode SE1 and the driver-drain electrode DDE are arranged on the low-potential power line VSS, and the first active layer ACT1 and the driver active layer DACT are arranged below the low-potential power line VSS. Therefore, the opening is formed in the low-potential power line VSS to easily connect configurations connected to an upper portion and a lower portion of the low-potential power line VSS.

[0139] The low-potential power line VSS is arranged between the storage capacitor Cst and the plurality of data lines DL, and between the driver transistor DT and the plurality of data lines DL to serve as a barrier film that blocks the voltage fluctuation of the driver transistor DT caused by the data line DL. The low-potential power line VSS, to which a constant voltage is applied, is arranged between the storage capacitor Cst and the driver transistor DT and the data lines DL to suppress the coupling of the data line DL and the storage capacitor Cst and the driver transistor DT. The low-potential power line VSS is arranged to cover at least the driver gate electrode DGE of the driver transistor DT to protect the voltage DTG of the driver gate electrode DGE from fluctuations caused by the data line DL.

[0140] Below, an effect of extending the low-potential power line VSS is described with reference to the Fig. 9A and Fig. 9B.

[0141] With reference to Fig. 9A, a display device 10 according to a comparative embodiment has a structure in which a low-potential power line VSS is not disposed between the data line DL and the driving transistor DT. In the display panel 10 according to a comparative embodiment, no separate barrier film is disposed between the data line DL and the driving transistor DT, so it is confirmed that a voltage DTG of the driving gate electrode DGE fluctuates according to the voltage fluctuation of the data line DL. It is also confirmed that when the voltage DTG of the driving gate electrode DGE fluctuates, the driving current ILED flowing through the light-emitting diode 120 also fluctuates. In this case, the luminance fluctuates, so the display quality may be degraded.

[0142] With reference to Fig.9B, in a display panel PN' according to another exemplary embodiment of the present disclosure, a low-potential power line VSS serving as a barrier film is disposed between the data line DL and the drive transistor DT, and between the data line DL and the storage capacitor Cst. Therefore, the voltage DTG and the drive current ILED of the drive gate electrode DGE can be kept constant even when the voltage of the data line DL fluctuates. Accordingly, the luminance is kept constant, and the display quality can be improved.

[0143] In the display panel PN' according to another exemplary embodiment of the present disclosure, the low-potential power line VSS is formed between the data line DL and the driving transistor DT to minimize the voltage fluctuation of the driving transistor DT caused by the data line DL. The low-potential power line VSS can be arranged to cover the driving transistor DT and the storage capacitor Cst below the plurality of data lines DL. The low-potential power line VSS, which always maintains a constant voltage, can prevent the plurality of data lines DL from interfering with the driving transistor DT and the storage capacitor Cst. In this case, the voltage DTG and the driving current ILED of the driving gate electrode DGE can be kept constant without requiring a thick insulating layer between the plurality of data lines DL and the driving transistor DT and the storage capacitor Cst.Furthermore, instead of forming a separate barrier film, a size of the existing low-potential power line VSS is expanded to correspond to an area where the plurality of data lines DL are arranged, so that the low-potential power line VSS is used as a barrier film. Further, the manufacturing process of the display panel PN' can be simplified. Accordingly, in the display panel PN' according to another exemplary embodiment of the present disclosure, the low-potential power line VSS is formed with an enlarged size so that it overlaps all of the plurality of data lines DL. Therefore, the drive current ILED of the sub-pixel SP' is stably maintained constant, and the reliability of the display panel PN' is improved.

[0144] Meanwhile, in the related technology, the main light-emitting diode and the backup light-emitting diode are arranged together in a subpixel, and the main light-emitting diode and the backup light-emitting diode are connected in parallel in a pixel circuit. In this case, the first electrode and the second electrode of the main light-emitting diode and the first electrode and the second electrode of the backup light-emitting diode are connected to the same node, that is, the same electrode. In this structure, when a short-circuit failure of the light-emitting diode or the pixel circuit occurs, both the main light-emitting diode and the backup light-emitting diode, which are connected in parallel and share a certain electrode, are darkened, causing a defect. Furthermore, it is difficult to separate and repair only one defective light-emitting diode.

[0145] In contrast, in the display panels PN and PN' according to various exemplary embodiments of the present disclosure, as described above, the plurality of subpixels SP and SP' are divided into main subpixels SP and SP' including the main light-emitting diode 120, and redundant subpixels SP and SP' including the redundant light-emitting diode 120. Furthermore, the main light-emitting diode 120 of the main subpixels SP and SP' and the redundant light-emitting diode 120 of the redundant subpixels SP and SP' can be independently driven. That is, a pixel circuit for driving the main light-emitting diode 120 and a pixel circuit for driving the redundant light-emitting diode 120 can be separately formed. For example, an L-shaped protrusion is further formed in the scanning line SL extending in the row direction.One of a first transistor T1 for driving the main light-emitting diode 120 and a first transistor T1 for driving the backup light-emitting diode 120 is formed on the scanning line SL, and the other transistor is formed on the L-shaped protrusion. Therefore, the first transistor T1 for driving the main light-emitting diode 120 and the first transistor T1 for driving the backup light-emitting diode 120 can be formed separately. Accordingly, a protrusion is further formed in the scanning line SL to individually form the first transistor T1 for the main light-emitting diode 120 and the first transistor T1 for the backup light-emitting diode 120, and to individually drive the main light-emitting diode 120 and the backup light-emitting diode 120.Therefore, in the display panels PN and PN' according to various exemplary embodiments of the present disclosure, the main light-emitting diode 120 and the backup light-emitting diode 120 are connected to different pixel circuits. Accordingly, a defect in a particular subpixel SP or SP' does not affect another subpixel SP or SP', and only the defective subpixel SP or SP' can be easily detected and repaired.

[0146] Exemplary embodiments of the present disclosure may also be described as follows:

[0147] According to one aspect of the present disclosure, a display device includes a substrate defining a plurality of pixel regions arranged to be spaced apart from each other, a plurality of transmissive regions arranged between the plurality of pixel regions, and a plurality of data lines extending in a column direction on the substrate. The plurality of pixel regions overlap a region in which the plurality of data lines are arranged.

[0148] The display device may further include a plurality of subpixels arranged in each of the plurality of pixel regions. The plurality of subpixels may include a first subpixel having a rectangular shape, a second subpixel including two adjacent sides of four sides of the first subpixel, and a third subpixel including an outer portion of the second subpixel. The first subpixel, the second subpixel, and the third subpixel may form a rectangular shape.

[0149] The display device may further comprise a scanning line extending in a row direction across the plurality of pixel regions on the substrate. The plurality of subpixels of each of the plurality of pixel regions may be formed by a first subpixel, a second subpixel, and a third subpixel arranged on one side of the scanning line, and a first subpixel, a second subpixel, and a third subpixel arranged on the other side (e.g., the opposite side) of the scanning line.

[0150] Each of the plurality of subpixels may further comprise: a first transistor arranged between the plurality of data lines and the substrate and to which the plurality of data lines are electrically connected, a driver transistor arranged between the plurality of data lines and the substrate and electrically connected to the first transistor, a second transistor arranged between the plurality of data lines and the substrate and electrically connected to the driver transistor, a storage capacitor arranged between the plurality of data lines and the substrate and electrically connected to a gate electrode of the driver transistor, and a light-emitting diode arranged on the plurality of data lines and electrically connected to the driver transistor.

[0151] In a pixel region of the plurality of pixel regions, the first transistors of the first subpixel, the second subpixel, and the third subpixel may be arranged in a line along a row direction.

[0152] In a pixel region of the plurality of pixel regions, the scanning line may have a protruding part that protrudes from the scanning line and extends at least partially in the row direction, wherein the first transistors of a first subpixel, a second subpixel, and a third subpixel arranged on one side of the scanning line may be arranged on the protruding part of the scanning line, and the first transistors of a first subpixel, a second subpixel, and a third subpixel arranged on the other side of the scanning line may be arranged on the scanning line.

[0153] In one pixel region of the plurality of pixel regions, the second transistors of the first subpixel, the second subpixel, and the third subpixel may be arranged in a line along a column direction.

[0154] In one pixel region of the plurality of pixel regions, the driver transistors of the first subpixel, the second subpixel, and the third subpixel may be arranged in a line along a column direction.

[0155] In one pixel region of the plurality of pixel regions, the light-emitting diodes of the first subpixel, the second subpixel, and the third subpixel may be arranged in a line along a column direction.

[0156] The plurality of data lines may be arranged on the driver transistor and the storage capacitor and overlap the driver transistor and the storage capacitor.

[0157] The display device may further include a buffer layer disposed between the substrate and the driver transistor, a gate insulating layer disposed between a driver gate electrode and a driver active layer on the buffer layer, a first interlayer insulating layer covering the driver transistor, and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer. The plurality of data lines may be disposed on one or more insulating layers, and a thickness of the one or more insulating layers may be greater than a thickness of the buffer layer, a thickness of the gate insulating layer, and a thickness of the first interlayer insulating layer.

[0158] The display device may further comprise a low-potential power line arranged between the storage capacitor and the plurality of data lines. The low-potential power lines may overlap a region in which the plurality of data lines are arranged.

[0159] The low-potential power lines can overlap the driver transistor and the storage capacitor.

[0160] A driver active layer of the driver transistor and a first active layer of the first transistor may be disposed below the low-potential power line, a driver drain electrode of the driver transistor and a first source electrode of the first transistor may be disposed on the low-potential power line, and the low-potential power line may have a plurality of openings overlapping a contact hole through which the driver active layer and the driver drain electrode are connected and a contact hole through which the first active layer and the first source electrode are connected.

[0161] According to another aspect of the present disclosure, a display device may comprise: a substrate having a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions between the plurality of pixel regions, each of the plurality of pixel regions having a plurality of subpixels; and a plurality of signal lines extending in a first direction on the substrate, the plurality of subpixels comprising a plurality of pixel circuits, the plurality of signal lines overlapping the plurality of pixel circuits without the plurality of signal lines overlapping the plurality of transmissive regions.

[0162] Each subpixel may include a light-emitting diode, and each signal line of the plurality of signal lines may be arranged to overlap at least one of the light-emitting diodes in a plan view of the display device.

[0163] Each pixel circuit may include a thin-film transistor and a storage capacitor, wherein each signal line of the plurality of signal lines may be arranged between at least one of the light-emitting diodes and at least one of the thin-film transistors and / or storage capacitors in a cross-sectional view of the display device.

[0164] The plurality of transmissive regions may be arranged directly adjacent to the plurality of pixel regions.

[0165] The display device may further comprise: a scan line extending in a second direction across the plurality of pixel regions on the substrate, the second direction being different from the first direction, wherein the plurality of subpixels of each of the plurality of pixel regions may include a first main subpixel, a second main subpixel, and a third main subpixel on a first side of the scan line, and a first redundancy subpixel, a second redundancy subpixel, and a third redundancy subpixel on a second side of the scan line, wherein the first main subpixel and the first redundancy subpixel emit a first color of light, the second main subpixel and the second redundancy subpixel emit a second color of light, and the third main subpixel and the third redundancy subpixel emit a third color of light.

[0166] The plurality of signal lines may include at least one of a plurality of data lines and a plurality of reference lines.

[0167] Each of the plurality of subpixels may further comprise: a first transistor between a data line of the plurality of data lines and the substrate, the first transistor being electrically connected to the data line; a driver transistor between the data line and the substrate, the driver transistor being electrically connected to the first transistor; a second transistor between the data line and the substrate, the second transistor being electrically connected to the driver transistor; a storage capacitor between the data line and the substrate, the storage capacitor being electrically connected to a driver gate electrode; and a light-emitting diode over the data line, the light-emitting diode being electrically connected to the driver transistor.

[0168] In one pixel region of the plurality of pixel regions, the first transistor of the first subpixel, the first transistor of the second subpixel, and the first transistor of the third subpixel may be arranged in a line along a second direction different from the first direction.

[0169] In the one pixel region, a scanning line may have a protruding part that protrudes from the scanning line in the first direction and extends at least partially in the second direction, wherein the first transistor of a first main subpixel, the first transistor of a second main subpixel, and the first transistor of a third main subpixel may be located on a first side of the scanning line on the protruding part of the scanning line, and the first transistor of a first redundant subpixel, the first transistor of a second redundant subpixel, and the first transistor of a third redundant subpixel may be located on a second side of the scanning line on the scanning line, wherein the first main subpixel and the first redundant subpixel may emit a first color of light,the second main subpixel and the second redundancy subpixel can emit a second light color and the third main subpixel and the third redundancy subpixel can emit a third light color.

[0170] In one pixel region of the plurality of pixel regions, the second transistor of the first subpixel, the second transistor of the second subpixel, and the second transistor of the third subpixel may be arranged in a line along the first direction.

[0171] In one pixel region of the plurality of pixel regions, the driver transistor of the first subpixel, the driver transistor of the second subpixel, and the driver transistor of the third subpixel may be arranged in a line along the first direction.

[0172] In one pixel region of the plurality of pixel regions, the light-emitting diode of the first sub-pixel, the light-emitting diode of the second sub-pixel, and the light-emitting diode of the third sub-pixel may be arranged in a line along the first direction.

[0173] The plurality of signal lines may be located above the driver transistor and the storage capacitor and may overlap the driver transistor and the storage capacitor.

[0174] The display device may further comprise: a buffer layer between the substrate and the driver transistor; a gate insulating layer on the buffer layer, the gate insulating layer being between a driver gate electrode and a driver active layer of the driver transistor; a first interlayer insulating layer covering the driver transistor; and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer, wherein the plurality of signal lines may be located on the one or more insulating layers, and a thickness of the one or more insulating layers may be greater than a thickness of the buffer layer, a thickness of the gate insulating layer, and a thickness of the first interlayer insulating layer.

[0175] The display device may further comprise: a power line between the storage capacitor and the plurality of signal lines, wherein the power line overlaps the plurality of signal lines.

[0176] The power line may comprise or be a low-potential power line or a high-potential power line.

[0177] The power line can overlap the driver transistor and the storage capacitor.

[0178] A driver active layer of the driver transistor and a first active layer of the first transistor may be located below the power line, a driver drain electrode of the driver transistor and a first source electrode of the first transistor may be located on the power line, and the power line may have a plurality of openings overlapping a contact hole through which the driver active layer and the driver drain electrode are connected and a contact hole through which the first active layer and the first source electrode are connected.

[0179] The display device may include a reference line, wherein the reference line extends in the first direction on the substrate and overlaps the plurality of pixel regions.

[0180] The reference line does not need to overlap the majority of transmissive areas.

[0181] The reference line may overlap with at least one of the light-emitting diodes in a plan view of the display device.

[0182] The reference line may be arranged in a cross-sectional view of the display device between at least one of the light-emitting diodes and at least one of the driver transistors and / or storage capacitors.

[0183] The reference lines may be connected to the second transistor and the reference lines may be arranged at the same level as the data lines.

[0184] The reference lines may be formed integrally with a second drain electrode of the second transistor.

[0185] The plurality of subpixels may include: a first subpixel having a rectangular shape in a plan view of the display device; a second subpixel including, in plan view, two adjacent sides of four sides of the first subpixel; and a third subpixel including, in plan view, an outer part of the second subpixel, wherein the first subpixel, the second subpixel, and the third subpixel together form a rectangular shape.

[0186] According to another aspect of the present disclosure, a display device may comprise: a substrate having a pixel region and a light transmissive region that is more transparent than the pixel region; a driver transistor in the pixel region; a power line across the driver transistor in the pixel region; a signal line across the power line in the pixel region; a light-emitting element in the pixel region, the light-emitting element being electrically connected to the driver transistor.

[0187] The driver transistor may include a gate electrode, a source electrode, a drain electrode, and an active layer, wherein the signal line overlaps at least one of the source electrode, the gate electrode, or the active layer.

[0188] In a cross-sectional view, the signal line may be located between the driver transistor and the power line and may overlap the driver transistor and the power line.

[0189] The signal line may be a data line configured to provide a data voltage.

[0190] The display device may comprise a first insulating layer on the substrate.

[0191] The display device may have a second insulating layer between the signal line and the driver transistor.

[0192] The first insulating layer may be located between the substrate and the driver transistor, or between different layers of the driver transistor, or between the driver transistor and the second insulating layer.

[0193] The second insulating layer may have a thickness greater than the thickness of the first insulating layer.

[0194] The first insulating layer may include at least one of a buffer layer between the substrate and the driver transistor, a gate insulating layer between the gate electrode and the active layer of the driver transistor, or a first interlayer insulating layer covering the driver transistor.

[0195] The power line may be a low-potential power line that overlaps the signal line and the driver transistor.

[0196] The display device may further comprise: a scanning line in the pixel area, the scanning line having a first part protruding from the scanning line in a first direction and a second part extending at least partially in a second direction different from the first direction in the pixel area.

[0197] The pixel region may include a plurality of main subpixels on a first side of the second part of the scan line and a plurality of redundancy subpixels on a second side of the second part of the scan line.

[0198] The plurality of main subpixels may include a first main subpixel configured to emit light of a first color, a second main subpixel configured to emit light of a second color, and a third main subpixel configured to emit light of a third color, and the plurality of redundancy subpixels may include a first redundancy subpixel configured to emit light of the first color, a second redundancy subpixel configured to emit light of the second color, and a third redundancy subpixel configured to emit light of the third color, wherein each of the plurality of main subpixels and each of the plurality of redundancy subpixels may include a corresponding pixel driver circuit.

[0199] According to another aspect of the present disclosure, a display device may include: a substrate in which the plurality of pixel regions arranged to be spaced apart from each other and the plurality of transmissive regions arranged between the plurality of pixel regions are defined; and a plurality of wiring lines extending in a column direction on the substrate, wherein the plurality of pixel regions overlaps a region in which the plurality of wiring lines are arranged.

[0200] The wiring lines may include one or more lines of a data line, a reference line, a low-potential power line, and a high-potential power line.

[0201] In a plan view of the display device, at least one of the plurality of wiring lines may overlap with a light-emitting diode and / or a thin-film transistor of a pixel circuit arranged in the pixel regions.

[0202] In a cross-sectional view of the display device, at least one of the plurality of wiring lines may be arranged between a light-emitting diode and a thin-film transistor of a pixel circuit arranged in the pixel regions.

[0203] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all respects and do not limit the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0121471

[0001]

Claims

[1] Display device (100) comprising: a substrate (110) having a plurality of pixel regions (UPA) spaced apart from one another and a plurality of transmissive regions (TA) between the plurality of pixel regions (UPA), each of the plurality of pixel regions (UPA) having a plurality of subpixels (SP1, SP2, SP3); and a plurality of signal lines (DL) extending in a first direction on the substrate (110), wherein the plurality of subpixels comprise a plurality of pixel circuits, wherein the plurality of signal lines overlap the plurality of pixel circuits without the plurality of signal lines (DL) overlapping the plurality of transmissive regions (TA). [2] The display device (100) of claim 1, further comprising: a scanning line (SL) extending in a second direction across the plurality of pixel areas (UPA) on the substrate (110), the second direction being different from the first direction, wherein the plurality of subpixels (SP1, SP2, SP3) of each of the plurality of pixel areas (UPA) comprise a first main subpixel (SP1), a second main subpixel (SP2) and a third main subpixel (SP3) on a first side of the scanning line (SL) and a first redundancy subpixel (SP1), a second redundancy subpixel (SP2) and a third redundancy subpixel (SP3) on a second side of the scanning line (SL), wherein the first main subpixel (SP1) and the first redundancy subpixel (SP1) emit a first light color, the second main subpixel (SP2) and the second redundancy subpixel (SP2) emit a second light color, and the third main subpixel (SP3) and the third redundancy subpixel (SP3) emit a third light color. [3] The display device (100) according to claim 1 or 2, wherein the plurality of signal lines comprises at least one of a plurality of data lines and a plurality of reference lines. [4] The display device (100) of claim 3, wherein each of the plurality of subpixels (SP1, SP2, SP3) further comprises: a first transistor (T1) between a data line (DL) of the plurality of data lines (DL) and the substrate (110), wherein the first transistor (T1) is electrically connected to the data line (DL); a driver transistor (DT) between the data line (DL) and the substrate (110), the driver transistor (DT) being electrically connected to the first transistor (T1); a second transistor (T2) between the data line (DL) and the substrate (110), the second transistor (T2) being electrically connected to the driver transistor (DT); a storage capacitor (Cst) between the data line (DL) and the substrate (110), the storage capacitor (Cst) being electrically connected to a gate electrode of the driver transistor (DT); and a light-emitting diode (120) over the data line (DL), the light-emitting diode (120) being electrically connected to the driver transistor (DT). [5] The display device (100) according to claim 4, wherein in one pixel region (UPA) of the plurality of pixel regions (UPA), the first transistor (T1) of the first subpixel (SP1), the first transistor (T1) of the second subpixel (SP2) and the first transistor (T1) of the third subpixel (SP3) are arranged in a line along a second direction different from the first direction. [6] The display device (100) according to claim 5, wherein in said one pixel region (UPA), a scanning line (SL) has a protruding part that protrudes from the scanning line (SL) in the first direction and extends at least partially in the second direction, wherein the first transistor (T1) of a first main subpixel (SP1), the first transistor (T1) of a second main subpixel (SP2), and the first transistor (T1) of a third main subpixel (SP3) are on a first side of the scanning line (SL) on the protruding part of the scanning line (SL), and the first transistor (T1) of a first redundant subpixel (SP1), the first transistor (T1) of a second redundant subpixel (SP2), and the first transistor (T1) of a third redundant subpixel (SP3) are on a second side of the scanning line (SL) on the scanning line (SL), wherein the first main subpixel (SP1) and the first redundancy subpixel (SP1) are configured to emit a first light color,the second main subpixel (SP2) and the second redundancy subpixel (SP2) are configured to emit a second light color, and the third main subpixel (SP3) and the third redundancy subpixel (SP3) are configured to emit a third light color. [7] Display device (100) according to one of claims 4 to 6, wherein in a pixel area (UPA) of the plurality of pixel areas (UPA), the second transistor (T2) of the first subpixel (SP1), the second transistor (T2) of the second subpixel (SP2) and the second transistor (T2) of the third subpixel (SP3) are arranged in a line along the first direction. [8] Display device (100) according to one of claims 4 to 7, wherein in one pixel area (UPA) of the plurality of pixel areas (UPA), the driver transistor (DT) of the first subpixel (SP1), the driver transistor (DT) of the second subpixel (SP2) and the driver transistor (DT) of the third subpixel (SP3) are arranged in a line along the first direction. [9] The display device (100) according to any one of claims 4 to 8, wherein in one pixel region (UPA) of the plurality of pixel regions (UPA), the light-emitting diode (120) of the first sub-pixel (SP1), the light-emitting diode (120) of the second sub-pixel (SP2) and the light-emitting diode (120) of the third sub-pixel (SP3) are arranged in a line along the first direction. [10] The display device (100) according to any one of claims 4 to 9, wherein the plurality of signal lines are over the driver transistor (DT) and the storage capacitor (Cst) and overlap the driver transistor (DT) and the storage capacitor (Cst). [11] Display device (100) according to one of claims 4 to 10, further comprising: a buffer layer (111) between the substrate (110) and the driver transistor (DT); a gate insulating layer (112) on the buffer layer (111), the gate insulating layer (112) being between a driver gate electrode (DGE) and a driver active layer (DACT) of the driver transistor (DT); a first interlayer insulating layer (113a) covering the driver transistor (DT); and one or more insulating layers (113b, 114a) covering the storage capacitor (Cst) on the first interlayer insulating layer (113a), wherein the plurality of signal lines are located on the one or more insulating layers (113b, 114a), and a thickness of the one or more insulating layers (113b, 114a) is greater than a thickness of the buffer layer (111), a thickness of the gate insulating layer (112), and a thickness of the first interlayer insulating layer (113a). [12] Display device (100) according to one of claims 4 to 11, further comprising: a power line between the storage capacitor (Cst) and the plurality of signal lines, wherein the power line overlaps the plurality of signal lines. [13] The display device (100) of claim 12, wherein the power line comprises a low potential power line (VSS) or a high potential power line (VDD). [14] A display device (100) according to claim 12 or 13, wherein the current line overlaps the driver transistor (DT) and the storage capacitor (Cst). [15] The display device (100) according to claim 13 or 14, wherein a driver active layer (DACT) of the driver transistor (DT) and a first active layer (ACT1) of the first transistor (T1) are under the power line, a driver drain electrode (DDE) of the driver transistor (DT) and a first source electrode (SE1) of the first transistor (T1) are on the power line, and the power line has a plurality of openings overlapping a contact hole through which the driver active layer (DACT) and the driver drain electrode (DDE) are connected, and a contact hole through which the first active layer (ACT1) and the first source electrode (SE1) are connected. [16] Display device (100) according to one of claims 4 to 15, wherein the reference lines (RL) are electrically connected to the second transistor (T2) and the reference lines (RL) are arranged at the same level as that of the data lines (DL). [17] The display device (100) of claim 16, wherein the reference lines (RL) are formed integrally with a second drain electrode (DE2) of the second transistor (T2). [18] Display device (100) according to one of claims 1 to 17, wherein the plurality of subpixels (SP1, SP2, SP3) comprise: a first subpixel (SP1) having a rectangular shape in a plan view of the display device (100); a second subpixel (SP2) enclosing two adjacent sides of four sides of the first subpixel (SP1) in plan view; and a third subpixel (SP3) enclosing an outer part of the second subpixel (SP2) in plan view, and wherein the first subpixel (SP1), the second subpixel (SP2) and the third subpixel (SP3) together form a rectangular shape. [19] Display device (100) comprising: a substrate (110) having a pixel area (UPA) and a light transmissive area that is more transparent than the pixel area (UPA); a driver transistor (DT) in the pixel area (UPA); a power line across the driver transistor (DT) in the pixel area (UPA); a signal line above the power line in the pixel area (UPA); a light-emitting element in the pixel area (UPA), the light-emitting element being electrically connected to the driver transistor (DT). [20] A display device (100), wherein in a cross-sectional view the signal line is between the driver transistor and the power line and overlaps the driver transistor and the power line.

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