Semiconductor component and manufacturing process thereof

Abstract

The semiconductor device comprises a buried insulating layer, a semiconductor layer, an insulating structure, a recess, a first gate structure, and a first n-doped source / drain region. The semiconductor layer and the insulating structure are arranged on top of the buried insulating layer, and the semiconductor layer includes a first active region surrounded by the insulating structure. The recess is located within the first active region, which comprises a first section and a second section. The first section is located below the recess, the second section is connected to the first section, and the thickness of the second section is greater than that of the first section.The first gate structure is located on the first section, the first n-doped source / drain region is located in the first active region, and the second n-doped source / drain region is located partly in the second section and partly in the first section.

Description

BACKGROUND OF THE INVENTION 1. AREA OF THE INVENTION

[0001] The present invention relates to a semiconductor component and a manufacturing method thereof, and in particular to a semiconductor component having an active area with different thicknesses, and a manufacturing method thereof. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] In the field of semiconductor manufacturing, the functional components in integrated circuits are becoming increasingly smaller to improve chip performance. However, with the increasing density of functional components, the influence of many electrical properties on the operating performance of the components becomes ever more apparent, hindering further miniaturization. For example, in high-frequency switching devices, the on-resistance (RDS(on)) is a significant factor. on ) and the turn-off capacitance (C offKey performance indicators (KPIs) are important. The ratio of signals passing through the switch during the turn-on phase is related to the turn-on resistance, and the leakage ratio of signals during the turn-off phase is related to the turn-off capacitance. The figure of merit (FOM), calculated by multiplying the turn-on resistance and the turn-off capacitance, can be considered the performance index of the high-frequency switching device. Improving the figure of merit and reducing other negative influences through structural and / or process design is an ongoing area of ​​research for those in related fields. SUMMARY OF THE INVENTION

[0003] The present invention provides a semiconductor component and a manufacturing method for it. An active area is partially thinned by forming a recess in the active area in order to improve the operating performance of the semiconductor component.

[0004] According to one embodiment of the present invention, a semiconductor device is provided. The semiconductor device comprises a buried insulating layer, a semiconductor layer, an insulating structure, a recess, a first gate structure, and a first n-doped source / drain region. The semiconductor layer and the insulating structure are arranged on top of the buried insulating layer. The semiconductor layer comprises a first active region surrounded by the insulating structure. The recess is located in the first active region, which comprises a first section and a second section. The first section is located below the recess, the second section is connected to the first section, and the thickness of the second section is greater than the thickness of the first section.The first gate structure is located on the first section, the first n-doped source / drain region is located in the first active region, and the second n-doped source / drain region is located partly in the second section and partly in the first section.

[0005] According to one embodiment of the present invention, a semiconductor device manufacturing process is provided. The manufacturing process comprises the following steps: A buried insulating layer is provided, a semiconductor layer and an insulating structure are formed on the buried insulating layer, and the semiconductor layer comprises a first active region surrounded by the insulating structure. A recess is formed in the first active region, and the first active region comprises a first section and a second section after the recess has been formed. The first section is located below the recess, the second section is connected to the first section, and the thickness of the second section is greater than the thickness of the first section.A first gate structure is formed on the first section, a first n-doped source / drain region is formed in the first active region, and the second n-doped source / drain region is formed partly in the second section and partly in the first section.

[0006] These and other features of the present invention will become clear to the person skilled in the art upon reading the following detailed description of the preferred embodiment, which is shown in the various figures and drawings. BRIEF DESCRIPTION OF THE FIGURES Fig. Figure 1 is a schematic view illustrating a semiconductor component according to a first embodiment of the present invention. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. Figure 8 are schematic views illustrating a semiconductor component manufacturing process according to an embodiment of the present invention, wherein Fig. 3 a schematic view in a Fig. The next step is: Fig. 4 a schematic view in a Fig. The next step is: Fig. 5 a schematic view in a Fig. The next step is: Fig. 6 a schematic view in a Fig. The next step is: Fig. 7 a schematic view in a Fig. The next step is 6, and Fig. 8 a schematic view in a Fig. The next step is 7. Fig. Figure 9 is a schematic view illustrating a semiconductor component manufacturing process according to another embodiment of the present invention. Fig. Figure 10 is a schematic view illustrating a semiconductor component according to a second embodiment of the present invention. Fig. Figure 11 is a schematic view illustrating the layout design of a semiconductor component according to a third embodiment of the present invention. Fig. Figure 12 is a schematic view illustrating a cross-sectional view of the semiconductor component according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0007] The present invention has been presented and described in particular with regard to certain embodiments and their specific features. The embodiments presented herein serve more for illustration than for limitation. It should be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made without deviating from the scope of the disclosure.

[0008] Before further describing the preferred embodiment, the specific terms used throughout the text are explained below.

[0009] The terms “on”, “over” and “above” used herein are to be interpreted in such a way that “on” does not only mean “directly on” something, but also includes the meaning of “on” something with an intermediate feature or layer in between, and that “over” or “above” does not only mean the meaning of “over” or “above” something, but can also include the meaning of “over” or “above” something without an intermediate feature or layer in between (i.e. directly on something).

[0010] The ordinal numbers used in the description and claims, such as "first," "second," etc., serve to modify the elements in the claims and do not imply that the claim itself has an earlier ordinal number. They do not represent the order of one claimed element and another, nor do they represent the order of manufacturing processes unless further description is provided. The use of these ordinal numbers serves only to distinguish one claimed element with a particular name from another claimed element with the same name.

[0011] The terms "formation" and "arrangement" are used below to describe the application of a layer to the substrate. These terms are intended to encompass all possible methods for forming layers, including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

[0012] It will be on Fig. 1 referred. Fig. Figure 1 is a schematic view illustrating a semiconductor component 100 according to a first embodiment of the present invention. As shown in Fig. As illustrated in Figure 1, the semiconductor device 100 comprises a buried insulating layer 26, a semiconductor layer 28, an insulating structure 32, a recess RC, a first gate structure GS1, and a first n-doped source / drain region SD1. The semiconductor layer 28 and the insulating structure 32 are arranged on top of the buried insulating layer 26, and the semiconductor layer 28 includes a first active region AC1, which is surrounded by the insulating structure 32 in a horizontal direction (e.g., in a horizontal direction D2 and in a horizontal direction D3). The recess RC is located in the first active region AC1, and the first active region AC1 comprises a first section P1 and a second section P2. The first section P1 is located below the recess RC in a vertical direction D1, the second section P2 is connected to the first section P1, and the thickness of the second section P2 (e.g.,The thickness TK2 is greater than the thickness of the first section P1 (e.g., the thickness TK1). The first gate structure GS1 is located on the first section P1, the first n-doped source / drain region SD1 is located in the first active region AC1, and the first n-doped source / drain region SD1 is located partly in the second section P2 and partly in the first section P1. The thickness of the active region located beneath the first gate structure GS1 (like the first section P1 of the first active region AC1) can be reduced by forming the recess RC to improve the operating performance of the device corresponding to the first gate structure GS1 (like a first device 110).For example, if the first component 110 is a high-frequency switching device, the measure (FOM) obtained by multiplying the on-resistance and off-capacitance can be improved without affecting the breakdown voltage, although this is not limited to the breakdown voltage. Furthermore, the first component 110 is not limited to the high-frequency switching device and can include a low-noise amplifier (LNA), a power amplifier (PA), or other suitable components.

[0013] In particular, in some embodiments, the semiconductor device 100 may further comprise a substrate 22 and an adhesion-rich layer 24. The buried insulating layer 26 may be arranged on the substrate 22, and the adhesion-rich layer 24 may be arranged between the substrate 22 and the buried insulating layer 26. The substrate 22, the adhesion-rich layer 24, the buried insulating layer 26, and the semiconductor layer 28 may, but are not limited to, forming a semiconductor substrate 30 (SOI). The vertical direction D1 described above may be considered a thickness direction of the substrate 22 and / or a thickness direction of the buried insulating layer 26. The buried insulating layer 26 may have an upper surface 26TS and a lower surface 26BS, which faces the upper surface 26TS in the vertical direction D1.The semiconductor layer 28, the insulating structure 32, and the first gate structure GS1 can be arranged on one side of the upper surface 26TS. The adhesion-rich layer 24 and the substrate 22 can be arranged on one side of the lower surface 26BS. Horizontal directions that are substantially orthogonal to the vertical direction D1 (such as horizontal direction D2 and horizontal direction D3) can be substantially parallel to the upper surface 26TS and / or the lower surface 26BS, but are not restricted to this. Furthermore, in this description, a distance between the lower surface 26BS of the buried insulating layer 26 and a relatively higher point and / or portion in the vertical direction D1 can be greater than a distance between the lower surface 26BS of the buried insulating layer 26 and a relatively lower point and / or portion in the vertical direction D1.The lower or a lower section of each component may be closer to the lower surface 26BS of the buried insulating layer 26 in the vertical direction D1 than the upper or upper section of that component, but is not limited to this. It should be noted that in this description, the upper surface of a given component may include the uppermost surface of that component in the vertical direction D1, and the lower surface of a given component may include the lowest surface of that component in the vertical direction D1, but is not limited to this. Furthermore, in this description, the condition that a given component is located between two other components in a given direction may include, in particular, the condition that the given component is enclosed between the two other components in the given direction, but is not limited to this.

[0014] In some embodiments, the storage device 100 may further comprise a gate oxide layer 44A and a plurality of first n-doped source / drain regions SD1. The gate oxide layer 44A is arranged on the first active region AC1, and the first gate structure GS1 is arranged on the gate oxide layer 44A. The gate oxide layer 44A may be arranged partially within the recess RC and partially outward, and the first gate structure GS1 may be arranged within the recess RC and on the gate oxide layer 44A located within the recess RC. In some embodiments, the first gate structure GS1 may extend substantially in the horizontal direction D3, and at least a portion of two first n-doped source / drain regions SD1 may each be located on two opposite sides of the first gate structure GS1 in the horizontal direction D2.Furthermore, channel region CH1 can be considered a section of the first active region AC1, located beneath the first gate structure GS1 and adjacent to the first n-doped source / drain regions SD1. Channel region CH1 can be situated within the first section P1, which is relatively thin in the first active region AC1. An upper surface TS1 of channel region CH1 can be lower than an upper surface TS2 of the first n-doped source / drain region SD1, which is located in the second section P2 in the vertical direction D1. Similarly, an upper surface TS3 of the first source / drain region SD1, located in the first section P1, can be lower than the upper surface TS2 of the first n-doped source / drain region SD1, which is located in the second section P2 in the vertical direction D1.In some embodiments, the upper surface TS1 and the upper surface TS3 can be essentially coplanar, the upper surface TS1 and the upper surface TS3 can also be considered as an upper surface of the first section P1 of the first active region AC1, and the upper surface TS2 can be considered as an upper surface of the second section P2 of the first active region AC1, but is not limited to this.

[0015] In some embodiments, due to the influence of the shape of the recess RC, the first active region AC1 may further comprise a side wall SW that is directly connected to the upper surface TS2 or the upper surface TS3, wherein the side wall SW is an inclined side wall that is not parallel to, but not restricted to, the vertical direction D1. Therefore, the first section P1 may comprise the portion of the first active region AC1 that lies below the side wall SW in the vertical direction D1, and the thickness TK1 described above may be considered the minimum thickness of the first section P1.In some embodiments, the first source / drain-doped region SD1, which is arranged in the first section P1, can be directly connected to the first n-doped source / drain region SD1, which is arranged in the second section P2; the minimum thickness of the first source / drain region SD1, which is arranged in the first section P1, can be substantially equal to the thickness TK1; and the thickness of the first source / drain region SD1, which is arranged in the second section P2, can be less than, but is not limited to, the thickness TK2 of the second section P2.In some embodiments, the first component 110 can comprise the first active region AC1, the first n-doped source / drain region SD1, the channel region CH1, the gate oxide layer 44A, and the first gate structure GS1, and the semiconductor layer 28 can further comprise other active regions surrounded by the insulating structure 32 to form structures that differ from the first component 110. For example, the semiconductor layer 28 can further comprise a second active region AC2, which is surrounded horizontally by the insulating structure 32, wherein the second active region AC2 can be separated from the first active region AC1 by the insulating structure 32, and an upper surface TS4 of the second active region AC2 can be vertically D1 higher than the upper surface of the first section P1 of the first active region AC1 (such as the upper surface TS1 and / or the upper surface TS3).

[0016] In some embodiments, the semiconductor device 100 may further comprise a second gate structure GS2, a gate oxide layer 44B, and a second n-doped source / drain region SD2. The second gate structure GS2 and the gate oxide layer 44B are arranged on the second active region AC2, and at least a portion of the gate oxide layer 44B is located between the second gate structure GS2 and the second active region AC2 in the vertical direction D1.The second n-doped source / drain region SD2 is located in the second active region AC2, wherein a top surface of the second n-doped source / drain region SD2 (like a top surface TS4, but not limited to it) and the top surface TS2 of the first n-doped source / drain region SD1, which is located in the second section P2 of the first active region AC1, may be substantially coplanar, and a thickness of the second active region AC2 (like a thickness TK3) may be substantially equal to, but not limited to, the thickness TK2 of the second section P2 of the first active region AC1.In some embodiments, the storage device 100 can comprise a plurality of second source / drain-doped regions SD2, wherein at least one part of two second source / drain-doped regions SD2 can be arranged on two opposite sides of the second gate structure GS2 in a horizontal direction, and a channel region CH2 can be considered as part of the second active region AC2, which is arranged side by side under the second gate structure GS2 and between the second source / drain-doped regions SD2. The second gate structure GS2, the gate oxide layer 44B, the second n-doped source / drain regions SD2, and the second active region AC2 can form a second component 120. The second active region AC2 in the second component 120 can have a substantially uniform and consistent thickness to meet the requirements of other components that differ from the first component 110.In some embodiments, the first gate structure GS1 and the second gate structure GS2 can be formed simultaneously by the same process, and due to the influence of the recess RC, an upper surface TS6 of the second structure GS2 can be higher than an upper surface TS5 of the first gate structure GS1 in the vertical direction D1, but not limited to this.

[0017] In some embodiments, the substrate 22 may comprise a silicon substrate or a substrate made of other suitable materials. The buried insulating layer 26 may comprise an oxide insulating layer, such as a buried oxide layer (BOX), or other suitable insulating materials. The adhesion-rich layer 24 may comprise undoped polysilicon, silicon oxide, silicon nitride, silicon oxynitride, or other materials with a better free electron-trapping ability, different from the material of the substrate 22 and the material of the buried insulating layer 26. The semiconductor layer 28 may comprise a silicon-containing semiconductor layer (e.g., a single-crystal silicon semiconductor layer) or other types of semiconductor materials. The insulating structure 32 may comprise a single layer or multiple layers of insulating materials, such as an oxide insulating material and an oxynitride insulating material.The first n-doped source / drain region SD1 and the second n-doped source / drain region SD2 can each comprise a lightly doped region (not illustrated) and a major-doped region (not illustrated) connected to that lightly doped region, and the lightly doped region and the major-doped region can be doped with N-type or P-type dopants. The first gate structure GS1 and the second gate structure GS2 can comprise non-metallic gates, such as polysilicon gates, or gate structures made of other suitable electrically conductive materials, and a spacer (not illustrated) can be arranged on the sidewall of the gate structure according to some design considerations. Furthermore, in some embodiments, a doped trough region can be formed in the first active region AC1 and / or in the second active region AC2 (e.g.,a basin area WR, which is located in the first active area AC1), but is not limited to that.

[0018] It will be directed to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. 8 referred. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. Figure 8 are schematic views illustrating a semiconductor component manufacturing process according to an embodiment of the present invention, wherein Fig. 3 a schematic view in a Fig. The next step is: Fig. 4 a schematic view in a Fig. The next step is: Fig. 5 a schematic view in a Fig. The next step is: Fig. 6 a schematic view in a Fig. The next step is: Fig. 7 a schematic view in a Fig. The next step is 6, and Fig. 8 a schematic view in a Fig. The next step is 7. In some embodiments, it can Fig. 1 as a schematic view in a Fig. The following step will be considered, but is not limited to it. As in Fig. As illustrated in Figure 1, the manufacturing process in this embodiment can comprise the following steps. First, the buried insulating layer 26 is provided. The semiconductor layer 28 and the insulating structure 32 are formed on the buried insulating layer 26, and the semiconductor layer 28 comprises the first active region AC1, which is surrounded by the insulating structure 32. The recess RC is formed in the first active region AC1, and the first active region AC1 comprises the first section P1 and the second section P2 after the recess RC has been formed. The first section P1 is located below the recess RC, the second section P2 is connected to the first section P1, and the thickness of the second section P2 (for example, thickness TK2) is greater than the thickness of the first section P1 (for example, thickness TK1).The first gate structure GS1 is formed on the first section P1, the first n-doped source / drain region SD1 is formed in the first active region AC1, and the first n-doped source / drain region SD1 is formed partly in the second section P2 and partly in the first section P1.

[0019] In particular, the semiconductor device manufacturing process in this embodiment may, but is not limited to, the following steps. As in Fig. As shown in Figure 2, in some embodiments the buried insulating layer 26 can be formed on the trap-rich layer 24, the trap-rich layer 24 can be formed on the substrate 22, and the semiconductor layer 28 can comprise the first active region AC1 and the second active region AC2, which are surrounded and defined by the insulating structure 32. Furthermore, in some embodiments a pad oxide layer 34 can be formed on the semiconductor layer 28 before the insulating structure 32 is formed, and the pad oxide layer 34 can be arranged partially on the first active region AC1 and partially on the second active region AC2 after the insulating structure 32 is formed. As shown in Figure 2 Fig. As illustrated in Figure 3, a structured mask layer 36 can be formed on the semiconductor layer 28, and the structured mask layer 36 can include an opening OP1 that overlaps a portion of the first active region AC1. The material of the structured mask layer 36 can be silicon nitride or other suitable mask materials. Furthermore, the pad oxide layer 34 is formed prior to the formation of the structured mask layer 36. The structured mask layer 36 can be formed on the pad oxide layer 34 and the insulating structure 32 accordingly, and the opening OP1 of the structured mask layer 36 can expose a portion of the pad oxide layer 34, for example, a portion of the pad oxide layer 34 that is located above the first active region AC1.Furthermore, in some embodiments, a mask material layer can be formed on the pad oxide layer 34 and the insulating structure 32. A structured photoresist layer 38 can be formed on the mask material layer, and an etching process can be carried out on the mask material layer using the structured photoresist layer 38 as a mask to mask the mask material layer, so that it becomes the structured mask layer 36 including the opening OP1, although this is not the only possible method. In some embodiments, the structured mask layer 36, which includes the opening OP1, can also be formed by other methods.

[0020] As in the Fig. 3 and Fig. As illustrated in Figure 4, the structured photoresist layer 38 can be removed after the opening OP1 has been formed, and an oxidation process 91 can be performed on the first active region AC1 after the structured photoresist layer 38 has been formed to form an oxide layer 40 in the first active region AC1. A portion of the first active region AC1 can be oxidized to form at least a portion of the oxide layer 40 by the oxidation process 91. The structured mask layer 36, which encompasses the opening OP1, can be used to control the position at which the oxide layer 40 is formed. The first active region AC1, located beneath the opening OP1, can be partially consumed to become a section of the oxide layer 40, and the pad oxide layer 34, exposed through the opening OP1, can become another section of the oxide layer 40, but is not limited to this.Furthermore, oxidation process 91 may include a thermal oxidation process or other suitable oxidation processes. As in the . Fig. 4 and Fig. As illustrated in Figure 5, the oxide layer 40 can be removed to form the recess RC in the first active region AC1. The recess RC can extend downwards from the upper surface of the first active region AC1, and the recess RC can include an inclined side wall and a relatively flat bottom (such as a section corresponding to the upper surface TS1). After the recess RC is formed, a pad oxide layer 42 can be formed in the recess RC, and the pad oxide layer 42 can be bonded to the pad oxide layer 34 arranged on the first active region AC1. It should be noted that the method for forming the recess within the scope of the present invention is the one described in Figure 5. Fig. 3, Fig. 4 to Fig. The process may include the 5 illustrated steps, but is not limited to them, and the recess RC can also be formed by other suitable approaches according to some design considerations.

[0021] As in Fig. As illustrated in Figure 6, in some embodiments, after the formation of the pad oxide layer 42, a doping process 92 can be carried out to form the basin area WR in the first active area AC1, and the area of ​​the basin area WR can be set by the process conditions of the doping process 92 and is not limited to the section directly below the opening OP1 in the vertical direction D1. As shown in Fig. 6 and Fig. As illustrated in Figure 7, after the doping process 92, the structured mask layer 36, the pad oxide layer 34, and the pad oxide layer 42 can be removed, and the gate oxide layer 44A and the gate oxide layer 44B can be formed on the first active region AC1 and the second active region AC2, respectively. Subsequently, as shown in Fig. Figure 8 illustrates that the first gate structure GS1 and the second structure GS2 are formed on the first active region AC1 and the second active region AC2, respectively. In some embodiments, the first gate structure GS1 and the second gate structure GS2 can be formed simultaneously by the same process, and due to the influence of the recess RC, the upper surface TS6 of the second structure GS2 can be higher than the upper surface TS5 of the first gate structure GS1 in the vertical direction D1, but is not limited to this. Furthermore, as shown in the Fig. 6, Fig. 7 to Fig. Figure 8 illustrates that the structured mask layer 36, the pad oxide layer 34, and the pad oxide layer 42 can be removed after the formation of the recess RC and before the formation of the first gate structure GS1 and the second gate structure GS2, and that the gate oxide layer 44A and the gate oxide layer 44B can be formed on the semiconductor layer 28 after the pad oxide layer 34, the pad oxide layer 42, and the structured mask layer 36 have been removed and before the first gate structure GS1 and the second gate structure GS2 are formed. Furthermore, the first gate structure GS1 and the second gate structure GS2 can be formed on the gate oxide layer 44A and the gate oxide layer 44B, respectively, and that the gate oxide layer 44A can be formed partially within the recess RC and partially extending outwards.

[0022] As in Fig. 8 and Fig. As illustrated in Figure 1, after the formation of the first gate structure GS1 and the second gate structure GS2, the first n-doped source / drain region SD1 and the second n-doped source / drain region SD2 can be formed in the first active region AC1 and the second active region AC2, respectively. In some embodiments, the first source / drain region SD1 and the second n-doped source / drain region SD2 can be formed by the same process or by different processes, depending on the considerations and / or the doping conditions.The upper surface of the first n-doped source / drain region SD1, formed in the first section P1 of the first active region AC1 (like the upper surface TS3), may be lower than the upper surface of the first n-doped source / drain region SD1, formed in the second section P2 of the first active region AC1 (like the upper surface TS2), in the vertical direction D1. The first source / drain-doped region SD1 formed in the first section P1 may be directly connected to the first n-doped source / drain region SD1 formed in the second section P2. The upper surface of the second n-doped source / drain region SD2 (like the upper surface TS4) and the upper surface TS2 of the first n-doped source / drain region SD1 formed in the second section P2 may be essentially coplanar, but are not restricted to being so. Furthermore, it should be noted that in . Fig. 1 The semiconductor component 100 shown can be formed by the manufacturing process described above and that the manufacturing process in this embodiment can also be applied to other embodiments according to some design considerations.

[0023] The different embodiments of the present invention are described in detail below. To simplify the description, the differences between the various embodiments are described in detail below, and identical features are not described redundantly. Furthermore, identical components in each of the following embodiments are marked with identical symbols to facilitate understanding of the differences between the embodiments.

[0024] It will be directed to the Fig. 5 and Fig. 9 referred. Fig. Figure 9 is a schematic view illustrating a semiconductor device manufacturing process according to another embodiment of the present invention. In some embodiments, Fig. 9 as a schematic view in a Fig. The following step will be considered. As in the Fig. 5 and Fig. As illustrated in Figure 9, in some embodiments, after the recess RC and the pad oxide layer 42 are formed, a further structuring process can be performed on the structured mask layer 36 to enlarge the opening OP1 to an opening OP2. After the opening OP2 is formed, the structured mask layer 36 cannot be positioned directly over the first active area AC1, and the well area WR, formed by the doping process 92, can in this case be positioned over the entire first active area AC1. Therefore, in the manufacturing process of this embodiment, an additional photomask and the corresponding photolithographic and etching process can be used to ensure the formation area of ​​the well area WR, and the operational performance of the corresponding component can be improved accordingly.

[0025] It will be on Fig. 10 referred. Fig. Figure 10 is a schematic drawing illustrating a semiconductor component 200 according to a second embodiment of the present invention. As shown in Fig. As illustrated in Figure 10, the semiconductor device 200 can comprise a first device 210 and a second device 220. The first device 210 can contain the first active region AC1, the first n-doped source / drain region SD1, the channel region CH1, the gate oxide layer 44A, and the first gate structure GS1. The second device 220 can contain the second active region AC2, the second n-doped source / drain region SD2, the channel region CH2, the gate oxide layer 44B, and the second gate structure GS2. In the first device 210, the first n-doped source / drain region SD1 can be located partially in the first section P1, which is located below the recess RC, and partially in the second section P2.The thickness of the first n-doped source / drain region SD1, located in the second section P2, can be essentially equal to the thickness of the second section P2 (such as thickness TK2), and the thickness of the first n-doped source / drain region SD1, located in the second section P2, can be greater than the thickness of the first n-doped source / drain region SD1, located in the first section P1 (such as thickness TK1). Furthermore, in the second component 220, the thickness of the second n-doped source / drain region SD2 can be essentially equal to, but is not limited to, the thickness of the second active region AC2 (e.g., thickness TK3).In the semiconductor device manufacturing process 200, the base of the first source / drain doped region SD1 and the base of the second n-doped source / drain region SD2 can each extend to the base of the first active region AC1 and the base of the second active region AC2, respectively, by adjusting the thickness of the semiconductor layer 28 and / or the process condition of the doping process described above. Due to the influence of the recess RC, the thickness of the first n-doped source / drain region SD1 formed in the second section P2 can be greater than the thickness of the first n-doped source / drain region SD1 formed in the first section P1. In some embodiments, the first device 210 and the second device 220 can be considered fully depleted devices, but are not limited to this.

[0026] It will be directed to the Fig. 11 and Fig. 12 referred. Fig. Figure 11 is a schematic view illustrating the layout of a semiconductor component 300 according to the third embodiment of the present invention, and Fig. Figure 12 is a schematic view showing a cross-sectional view of the semiconductor component 300 in this embodiment. In some embodiments, Fig. 12 as a partially cross-sectional view along a line AA' in Fig. 11 are considered without illustrating some components (e.g., the electrically conductive pattern ML3 in Fig. 12 not shown). As in the Fig. 11 and Fig. As illustrated in Figure 12, the semiconductor device 300 can contain the semiconductor on the insulating substrate 30, the insulating layer 32, the gate oxide layer 44A, and a plurality of the recesses RC described above. The semiconductor device 300 can further contain an electrically conductive pattern PL, an electrically conductive pattern ML1, an electrically conductive pattern ML2, electrically conductive patterns ML3, contact structures CT1, contact structures CT2, and contact structures CT3. A portion of the electrically conductive pattern PL can be used as the first gate structures GS1 described above. Each of the first gate structures GS1 can extend in the horizontal direction D3, and the first gate structures GS1 can be arranged in the horizontal direction D2 substantially orthogonal to the horizontal direction D3.The first gate structures GS1 can be interconnected via the other section of the electrically conductive pattern PL (such as the section extending in the horizontal direction D2), and the electrically conductive pattern PL can comprise a structured layer of polysilicon or other suitable structured electrically conductive materials. In some embodiments, the electrically conductive structure ML1, the electrically conductive structure ML2, and the electrically conductive structure ML3 can be separate sections of the same structured metal layer, and the structured metal layer is arranged above the electrically conductive structure PL in the vertical direction D1.

[0027] The mask patterns MP in Fig. 11 can be arranged according to the position at which the recesses RC are formed, and the mask patterns MP can be viewed as opening patterns in a photomask used to expose the aforementioned structured photoresist layer 38 in Fig. 3 to form, but are not limited to that. Furthermore, one can be in Fig. Figure 11 illustrates doping region DR1 and doping region DR2 as mask opening regions for forming different doped regions in the first active region AC1. For example, a variety of the first n-doped source / drain regions SD1 in the first active region AC1 can be formed via doping region DR1 and the corresponding doping process, and a doped region with a conductivity type complementary to that of the first n-doped source / drain regions SD1 can be formed in the first active region AC1 via doping region DR2 and the corresponding doping process, but is not limited to it.Furthermore, the electrically conductive pattern ML1 can be electrically connected via the contact structures CT1 to the electrically conductive pattern PL and the first gate structures GS1 in the electrically conductive pattern PL; the electrically conductive pattern ML2 can be electrically connected via the contact structures CT2 to the doped region formed by the doping region DR2; and the electrically conductive patterns ML3 can be electrically connected via the contact structures CT3 to the corresponding first n-doped source / drain regions SD1. In some embodiments, the semiconductor device 300 can be considered a high-frequency switching device, and the one described in . Fig. The illustrated layout design 11 can be considered a layout design for the high-frequency switching device, but is not limited to this. As shown in Fig. 11 and Fig.As illustrated in Figure 12, in this embodiment, the first active region AC1 can comprise a plurality of first sections P1 due to the influence of the recesses RC, with each of the first sections P1 extending in the horizontal direction D3 and the first sections P1 being arranged in the horizontal direction D2. Each of the first gate structures GS1 can be arranged in the corresponding recess RC and correspond to the corresponding first section P1. Furthermore, the first source / drain-doped region SD1, located between the first gate structures GS1 arranged side by side in the horizontal direction D2, can be partially arranged side by side in two of the first sections P1, and the channel regions CH1 and the first source / drain-doped regions SD1 can be arranged alternately in the horizontal direction D2.

[0028] In summary, it can be stated that in the semiconductor component and its manufacturing process according to the invention, the thickness of the active area located under the gate structure can be reduced by the recess in order to improve the operating performance of the semiconductor component. For example, the figure (FOM), which results from the multiplication of the on-resistance (R) on ) and the turn-off capacitance (C off ) results in improvements without affecting the breakdown voltage relatively, but this is not limited to that.

[0029] The person skilled in the art will readily recognize that numerous modifications and changes to the apparatus and the method can be made while retaining the teachings of the invention. Accordingly, the foregoing disclosure should be regarded as limited only by the limits and objectives of the appended claims.

Claims

[1] Semiconductor component, comprising: a buried insulating layer; a semiconductor layer arranged on the buried insulating layer; an insulating structure arranged on the buried insulating layer, wherein the semiconductor layer comprises a first active region surrounded by the insulating structure; a recess arranged in the first active area, wherein the first active area comprises: a first section that is arranged below the recess; and a second section connected to the first section, wherein the thickness of the second section is greater than the thickness of the first section; a first gate structure arranged on the first section; and a first n-doped source / drain region arranged in the first active region, wherein the first n-doped source / drain region is arranged partly in the second section and partly in the first section. [2] Semiconductor device according to claim 1, wherein a channel region is arranged in the first section and below the first gate structure and an upper surface of the channel region is lower than an upper surface of the first n-doped source / drain region arranged in the second section in a vertical direction. [3] Semiconductor device according to claim 1, wherein an upper surface of the first n-doped source / drain region arranged in the first section is lower than an upper surface of the first n-doped source / drain region arranged in the second section in a vertical direction. [4] Semiconductor component according to claim 1, wherein the first n-doped source / drain region arranged in the first section is directly connected to the first n-doped source / drain region arranged in the second section. [5] Semiconductor component according to claim 1, wherein the thickness of the first n-doped source / drain region arranged in the second section is greater than the thickness of the first n-doped source / drain region arranged in the first section. [6] Semiconductor component according to claim 1, wherein the semiconductor layer further comprises a second active region surrounded by the insulating layer, wherein the second active region is separated from the first active region by the insulating layer, and wherein an upper surface of the second active region is higher than an upper surface of the first section of the first active region in a vertical direction. [7] Semiconductor component according to claim 6, further comprising: a second gate structure arranged on the second active area, wherein an upper surface of the second gate structure is higher than an upper surface of the first gate structure in the vertical direction. [8] Semiconductor component according to claim 6, further comprising: a second n-doped source / drain region arranged in the second active region, wherein a top surface of the second n-doped source / drain region and a top surface of the first n-doped source / drain region arranged in the second section of the first active region are coplanar. [9] Semiconductor device manufacturing processes, including: Providing a buried insulation layer; Formation of a semiconductor layer on the buried insulating layer; Forming an insulating structure on the buried insulating layer, wherein the semiconductor layer comprises a first active region surrounded by the insulating structure; Forming a recess in the first active area, wherein, after the recess is formed, the first active area comprises: a first section that is arranged below the recess; and a second section connected to the first section, wherein the thickness of the second section is greater than the thickness of the first section; Forming a first gate structure on the first section; and Forming a first n-doped source / drain region in the first active region, wherein the first n-doped source / drain region is formed partly in the second section and partly in the first section. [10] Semiconductor component manufacturing method according to claim 9, comprising a method for forming the recess: Forming a structured mask layer on the semiconductor layer, wherein the structured mask layer includes an opening that overlaps part of the first active region; Performing an oxidation process on the first active region to form an oxide layer in the first active region, wherein a portion of the first active region is oxidized by the oxidation process to form the oxide layer; and Removing the oxide layer to form the recess in the first active area. [11] Semiconductor component manufacturing process according to claim 10, further comprising: Forming a pad oxide layer on the semiconductor layer before the structured mask layer is formed, wherein the structured mask layer is formed on the pad oxide layer, and the opening of the structured mask layer exposes part of the pad oxide layer. [12] Semiconductor component manufacturing process according to claim 11, further comprising: Removal of the pad oxide layer and the structured mask layer after the recess has been formed and before the first gate structure is formed. [13] Semiconductor component manufacturing process according to claim 12, further comprising: Forming a gate oxide layer on the semiconductor layer after the pad oxide layer and the structured mask layer have been removed and before the first gate structure is formed, wherein the first gate structure is formed on the gate oxide layer and the gate oxide layer is formed partly in the recess and partly outside the recess. [14] Semiconductor device manufacturing method according to claim 9, wherein a channel region is arranged in the first section and below the first gate structure and an upper surface of the channel region is lower than an upper surface of the first n-doped source / drain region formed in the second section in a vertical direction. [15] Semiconductor device manufacturing method according to claim 9, wherein an upper surface of the first n-doped source / drain region formed in the first section is lower than an upper surface of the first n-doped source / drain region formed in the second section in a vertical direction. [16] Semiconductor device manufacturing method according to claim 9, wherein the first n-doped source / drain region formed in the first section is directly connected to the first source / drain region formed in the second section. [17] Semiconductor device manufacturing method according to claim 9, wherein the thickness of the first n-doped source / drain region formed in the second section is greater than the thickness of the first n-doped source / drain region formed in the first section. [18] Semiconductor device manufacturing method according to claim 9, wherein the semiconductor layer further comprises a second active region surrounded by the insulating structure, wherein the second active region is separated from the first active region by the insulating structure and an upper surface of the second active region is higher than an upper surface of the first section of the first active region in a vertical direction. [19] Semiconductor component manufacturing process according to claim 18, further comprising: Forming a second gate structure on the second active area, wherein an upper surface of the second gate structure is higher than an upper surface of the first gate structure in the vertical direction. [20] Semiconductor component manufacturing process according to claim 18, further comprising: Forming a second n-doped source / drain region in the second active region, wherein a top surface of the second n-doped source / drain region and a top surface of the first n-doped source / drain region formed in the second section of the first active region are coplanar.

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