Multi-phase controller with constant switch-on time and current rectifier with this controller

Abstract

In a power converter, a phase controller splits a complete COT control signal into a master COT control signal and at least one slave COT control signal. The master COT control signal addresses a master PWM signal generator to produce a corresponding master PWM signal, and each slave COT control signal addresses a corresponding slave PWM signal generator to produce the slave PWM signal for a corresponding slave driver by adjusting the width of each pulse of the corresponding slave COT control signal according to a comparison between a sensing current of a master driver and a sensing current of the corresponding slave driver.Then the master driver provides a master current output for a load device according to a master PWM signal, and each slave driver provides a slave current output for the load device according to the associated slave PWM signal by reducing the width of each pulse of the slave COT control signal when the current of the slave driver is greater than the current of the master driver, provided that the width of each pulse of the slave COT control signal is not shorter than the width of each pulse of the full COT control signal.

Description

BACKGROUND OF THE INVENTION This disclosure relates to a multiphase (hereinafter referred to as "multiphase") constant duty cycle (hereinafter referred to as "COT") controller and a power converter. More precisely, this disclosure relates to a multiphase COT controller for the multiphase interleaving of a power converter and the power converter that incorporates the multiphase COT controller. COT refers to a control scheme in which the turn-on time of a switch (e.g., a transistor) is kept constant, while the turn-off time varies depending on the load conditions. In a multiphase converter, i.e., a multiphase circuit in which several power stages (phases) work together, it is important to maintain the consistency of the converter in each stage to reduce ripple (i.e., current balancing), especially when the sensed current differs in each stage. Given this, there is a pressing need for a good method for the multiphase interleaving of converters based on COT. A pulse-width modulator is known from US 2014 / 0 097 818 A1, as well as from KR 10 2024 0 057 646 A. For further technical background, see also MAZUMDER, Sudip K.; TAHIR, Muhammad; ACHARYA, Kaustuva.Master-slave current-sharing control of a parallel DC-DC converter system over an RF communication interface. IEEE transactions on industrial electronics, 2008, 55. Jg., Nr. 1, S. 59-66 . ; und UL AIN, Qurat [et al]: A high-efficiency fast transient COT control DC-DC buck converter with current reused current sensor. IEEE Transactions on Power Electronics, 2021, 36. Jg., Nr. 8, S. 9521-9535 . ZUSAMMENFASSUNG DER ERFINDUNG To solve at least the aforementioned problem, the present invention provides a multi-phase COT controller according to claim 1. The multi-phase COT controller can comprise a master PWM signal generator for a master driver, at least one slave PWM signal generator for each of at least one slave driver, and a phase controller. The phase controller can be electrically connected to the master PWM signal generator and each slave PWM signal generator and can be configured to split a complete COT control signal into a master COT control signal and at least one slave COT control signal. The master COT control signal is configured to address the master PWM signal generator, and each slave COT control signal is configured to address the corresponding slave PWM signal generator.The master PWM signal generator can be configured to generate a master PWM signal according to the master COT control signal, and each slave PWM signal generator can be configured to generate a slave PWM signal by adjusting the width of each pulse of the corresponding slave COT control signal according to a comparison between a detected current of the master driver and a detected current of the corresponding slave driver. To solve at least the aforementioned problem, the present invention also provides a power converter according to claim 13. The power converter can comprise a master driver, at least one slave driver, a master PWM signal generator for the master driver, at least one slave PWM signal generator for each of the at least one slave driver, a master PWM signal generator for the master driver that is electrically connected to the master driver, and a phase controller. The master driver can be configured to provide a master current output for a load device according to a master PWM signal. The at least one slave driver can be electrically connected to the master driver, and each slave driver can be configured to provide a slave current output for the load device according to a corresponding slave PWM signal.The phase controller can be electrically connected to the master driver, the master PWM signal generator, and each slave PWM signal generator, and can be configured to divide a complete COT control signal into a master COT control signal and at least one slave COT control signal. The master COT control signal is arranged to address the master PWM signal generator, and each slave COT control signal is arranged to address the corresponding slave PWM signal generator.The master PWM signal generator can be electrically connected to the master driver and arranged to generate the master PWM signal according to the master COT control signal, and each slave PWM signal generator can be arranged to generate the slave PWM signal corresponding to one of the at least one slave drivers by adjusting the width of each pulse of the corresponding slave COT control signal according to a comparison between a measured current of the master driver and a measured current of the corresponding slave driver. The present invention balances the current outputs between multiple phases / channels (i.e., the master driver and the at least one slave driver) by adjusting the width of each pulse in the corresponding COT control signals according to the comparison between the sensed currents of the master driver and each slave driver. In this way, the COT characteristic is maintained in each phase / channel while simultaneously providing a current balancing function. The present disclosure also offers improved performance in terms of reduced ripple, better thermal management, and higher efficiency. This summary describes the core concept of the present invention and addresses the problem to be solved, the means of solving the problem, and the effect of the present invention, in order to provide a person skilled in the art with a basic understanding of the present invention. However, this summary is not intended to include all embodiments of the present invention, but merely serves to present the core concept of the present invention in a simplified form and as an introduction to the detailed description that follows. The detailed technology and preferred embodiments of the present invention are described in the following paragraphs, which are accompanied by the drawings, so that persons with normal technical knowledge can readily assess the features of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS The drawings serve to describe the embodiments of the present disclosure, wherein: Fig. 1 shows a schematic view of a power converter and a multiphase COT controller according to one or more embodiments of the present disclosure; Fig. 2 shows a more detailed schematic view of the power converter and the multiphase COT controller in Fig. 1; Fig. 3 shows a schematic view of the signals transmitted in a power converter according to one or more embodiments of the present disclosure; and Fig. 4 shows a slave PWM signal generator and the corresponding parts of the phase controller that controls the slave PWM signal generator according to one or more embodiments of the present disclosure. The contents shown in Figs. 1-4 serve only to provide helpful illustrations of the embodiments of the present disclosure, without limiting the scope of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION The embodiments disclosed below are not intended to limit the claimed invention to any particular environment, application, structure, process, or situation. Elements not directly related to the claimed invention are not shown in the accompanying drawings. Dimensions and ratios between individual elements in the accompanying drawings are for illustrative purposes only and are not intended to limit the claimed invention. Unless expressly stated otherwise, identical reference numerals may refer to the same elements in the following description without contradicting the claimed invention. The terminology used here serves only to describe the embodiments and is not intended to limit the claimed invention. The singular forms "a" and "an" also include the plural forms unless the context clearly indicates otherwise. The terms "comprises," "containing," "includes," "including," etc., specify the presence of the indicated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes all combinations of one or more of the listed elements. Although the terms "first," "second," "third," etc., may be used here to describe different elements, these elements should not be limited by these terms.These terms are used solely to distinguish one element from another. For example, a first element described below could also be referred to as a second element without this deviating from the spirit and scope of the claimed invention. See Fig. 1; a first embodiment of the present disclosure can be a power converter 1. The power converter 1 can essentially comprise a master driver 11, at least one slave driver (hereinafter referred to as "slave driver 12_1-12_n"), and a multiphase COT controller 13, which is electrically connected to the master circuit 11 and the at least one slave circuit. Each of the slave drivers 12_1-12_n can be electrically connected to the master driver 11. The power converter 1 can be configured to provide a current output VT for a load device 2. The current output VT can consist of a master current output MO1, provided by the master driver 11, and at least one slave current output, provided by the slave driver(s) 12_1-12_n (hereinafter referred to as "slave current output(s) SO_1-SO_n"). To provide such a current output, the master driver 11 can generally provide a complete COT control signal CF1 for the multi-phase COT controller 13, and the multi-phase COT controller 13 can process the complete COT control signal CF1 to provide a master PWM signal P1 for the master driver 11 and at least one slave PWM signal (hereinafter referred to as "slave PWM signal(s) P21-P2n") for the slave driver(s) 12_1-12_n.The master driver 11 can then be configured to provide the master current output MO1 for the load device 2 according to a master PWM signal P1, while the slave driver(s) 12_1-12_n can be similarly configured to provide the slave current output(s) SO_1-SO_n for the load device 2 according to the corresponding slave PWM signal(s) P21-P2n. Please refer to Fig. 1 and Fig. 2 together. The master driver 11 can comprise a COT controller 11a, a master current sensor 11b, and a PWM driver 11c. Each of the slave drivers 12_1-12_n, with slave driver 12_1 serving as an example, can comprise a slave current sensor 12_1a and a PWM driver 12_1b. The multiphase COT controller 13 can comprise a master PWM signal generator 131, at least one slave PWM signal generator (hereinafter referred to as "slave PWM signal generator(s) 132_1-132_n"), and a phase controller 133. The slave PWM signal generator(s) 132_1-132_n each correspond to the slave drivers 12_1-12_n. Each of the slave PWM signal generators 132_1-132_n, where the slave PWM signal generator 132_1 serves as an example, can include a comparator 132_1a, an up / down counter 132_1b and a pulse width regenerator 132_1c. The phase controller 133 can essentially consist of a counter 133a, a demultiplexer 133b, and a reset signal generator 133c. The counter 133a can be electrically connected to the COT controller 11a and the demultiplexer 133b. In some embodiments, the phase controller 133 can also include a further counter 133d, which is electrically connected to the COT controller 11a and each up / down counter in the slave PWM signal generator(s) 132_1-132_n. Please refer to Fig. 3 with reference to Fig. 1 and Fig. 2. Fig. 3 shows a schematic representation of the signals for the case where the power converter 1 comprises a master driver and a slave driver. This serves only to simplify the description of the transitions between the master driver and the slave driver and the corresponding signals, and does not represent a limitation on the number of drivers that the power converter 1 can have. The COT controller 11a can be configured to generate the complete COT control signal CF1, which can originally be used to control a PWM signal generator of a single-phase power converter to generate PWM signals. As shown in Fig. 3, the complete COT control signal CF1 can comprise a series of pulses with the same pulse width, which is consistent with the concept of COT. For COT control of a multiphase converter such as converter 1, the complete COT control signal CF1 can be divided by the phase controller 133 into a plurality of COT control signals corresponding to the master PWM signal generator 131 or the slave PWM signal generator(s) 132_1-132_n. The majority of the COT control signals can consist of one master COT control signal CSM1 and at least one slave COT control signal (hereinafter referred to as "slave COT control signal(s) CSS1-CSSn"). In general, the master COT control signal CSM1 can be arranged to address the master PWM signal generator 131, and the slave COT control signal(s) CSS1-CSSn can be arranged to address the corresponding slave PWM signal generator(s) 132_1-132_n. In some embodiments, the COT controller 11a can accept the current output VT of the power converter 1 as a feedback signal FB and generate / adjust the complete COT control signal CF1 according to the feedback signal FB. To split the complete COT control signal CF1 into multiple COT control signals, the COT controller 11a can be electrically connected to the counter 133a and the demultiplexer 133b, and the complete COT control signal CF1 can be fed to the counter 133a and the demultiplexer 133b. The counter 133a can be configured to generate a selection signal SEL based on the complete COT control signal CF1 as a clock signal. The selection signal SEL can specify a series of numbers for selecting phases, one after the other. These numbers can be, for example, but are not limited to, binary numbers, decimal numbers, hexadecimal numbers, etc. In the example shown in Fig. 3, the selection signal SEL indicates the binary numbers "0" and "1". The CNT signal shown in Fig. 3 represents the counting of the selection signal SEL, where "0" represents the master phase and "1" the slave phase. In some other embodiments, where the selection signal displays, for example, binary numbers from "00" to "11", the counted number "00" can represent the master phase, and the counted numbers "01", "10", and "11" can represent three slave phases, each corresponding to three slave drivers. The counting of the selection signal SEL can begin at a number corresponding to the master phase, for example, "0" in the case shown in Fig. 3, which means that the master driver 11 can operate before the slave driver(s) 12_1-12_n. The demultiplexer 133b can be electrically connected to the counter 133a, the master PWM signal generator 131, and the slave PWM signal generator(s) 132_1-132_n, and can generate the master COT control signal CSM1 and the slave COT control signal CSS1 based on the complete COT control signal CF1 and according to the selection signal SEL. The master COT control signal CSM1 can then be fed to the master PWM signal generator 131, and the slave COT control signal(s) (e.g., the slave COT control signal CSS1) can be fed to the corresponding slave PWM signal generator (e.g., the slave PWM signal generator 132_1c) so that they generate their PWM signals accordingly. In some embodiments, the pulses in the master COT control signal CSM1 and in the slave COT control signals CSS1-CSSn can have the same pulse width as the pulses in the complete COT control signal CF1. The reset signal generator 133c can be electrically connected to the counter 133a and generate a reset signal RST so that the counter 133a switches from the last slave phase back to the master phase. Each comparator in a slave PWM signal generator can be electrically connected to the master current sensor 11b and the slave current sensor belonging to the same slave PWM signal generator. The master current sensor 11b can be configured to provide a detected current CS11 from the master driver 11, and each slave current sensor can be configured to provide the detected current of the corresponding slave driver for the corresponding slave PWM signal generator. Therefore, each comparator in a slave PWM signal generator can compare the detected current in the corresponding slave driver with the detected current CS11 in the master driver 11 and provide a comparison result for the corresponding up / down counter. Each up / down counter can be electrically connected to the corresponding comparator to obtain the comparison result. Each up / down counter can also be electrically connected to the corresponding pulse width regenerator belonging to the same slave PWM signal generator to provide pulse width matching information for it. Furthermore, each up / down counter can be electrically connected to the other counter 133d of the phase controller 133 to receive a clock signal CLK (not shown in Fig. 3) from counter 133d. The clock signal CLK can be provided by counter 133d based on the complete COT control signal CF1. Each pulse width regenerator can be electrically connected to the demultiplexer 133b to receive the corresponding slave COT control signal CSS1 and can adjust the width of each pulse in the received slave COT control signal CSS1 according to the pulse width setting information. The pulse width setting information may include a pulse width increase signal if the detected current of the corresponding slave driver is weaker than the detected current CS11 of the master driver 11, meaning that this specific slave phase requires a longer on-time for the purpose of current balancing between the phases. Conversely, the pulse width setting information may include a pulse width decrease signal if the detected current of the corresponding slave driver is stronger than the detected current CS11 of the master driver 11, meaning that this specific phase may have a shorter on-time. In some embodiments, the information for setting the pulse width may also include one or more instructions for operating each pulse width regenerator. Each adapted slave COT control signal can be output by the corresponding pulse width regenerator as a slave PWM signal to the corresponding PWM driver. Each PWM driver within a slave driver can be electrically connected to the corresponding pulse width regenerator to receive the slave PWM signal and provide the corresponding slave current output for load device 2 according to the received slave PWM signal. In some embodiments, each pulse width regenerator, apart from increasing or decreasing the width of each pulse in the corresponding slave COT control signal, can maintain the current pulse width of the corresponding slave COT control signal when the sensing current of the corresponding slave driver is equal to the sensing current CS11 of the master driver 11. The slave current sensors in the slave drivers 12_1-12_n, as shown in Fig. 1, can supply detected currents CS21-CS2n for the corresponding slave PWM signal generators 132_1-132_n. However, only the slave driver 12_1 and its corresponding slave PWM signal generator 132_1 are considered here as an example, and a person with normal technical knowledge can understand the similar operating principles of other slave drivers and their corresponding slave PWM signal generators in accordance with the following descriptions regarding the slave driver 12_1 and its corresponding slave PWM signal generator 132_1. As shown in Fig. 2, the comparator 132_1a can first receive the detected current CS11 from the master current sensor 11b and a detected current CS21 from the slave current sensor 12_1a. The comparator 132_1a can then compare the measured current CS21 with the measured current CS11 and provide a comparison result PR for the up-down counter 132_1b. The up-down counter 132_1b can generate a pulse-width-enlarging signal UP1 if the comparison result PR indicates that the detected current CS21 of the slave driver 12_1 is weaker than the detected current CS11 of the master driver 11. Conversely, the up-down counter 132_1b can generate a pulse-width-decreasing signal DW1 if the comparison result PR indicates that the detected current CS21 of the slave driver 12_1 is stronger than the detected current CS11 of the master driver 11. The pulse width regenerator 132_1c can adjust the width of each pulse of the slave COT control signal CSS1 according to the pulse width-enlarging signal UP1 or the pulse width-decreasing signal DW1. See Fig. 4 with reference to Figs. 1-3, which show a schematic view of the pulse width regenerator 132_1c. In some embodiments, the pulse width regenerator 132_1c may include an inverter Z1, a PMOS transistor Z2, an NMOS transistor Z3, a current source Z4, a capacitor Z5, an inverting Schmitt trigger Z6, and another inverter Z7. The inverter Z1 may be coupled to the demultiplexer 133b to receive the slave COT control signal CSS1. The gates of transistors Z2 and Z3 may be electrically connected to each other and to the output of inverter Z1. The power source Z4 can be connected between the NMOS transistor Z3 and ground.The pulse width enlarging signal UP1 or the pulse width enlarging signal DW1 can be provided to control the current source Z4, so that the width of each pulse of the input slave COT control signal CSS1 is adjusted. The drain of the PMOS transistor Z2 and the source of the NMOS transistor Z3 can be coupled together, as can the capacitor Z5 and the input of the inverting Schmitt trigger Z6. The inverter Z7 can accept the output of the inverting Schmitt trigger Z6 and finally output the slave PWM signal P21. The adapted slave COT control signal CSS1 can be output by the pulse width regenerator 132_1c as a slave PWM signal P21 to the corresponding PWM driver 12_1b. The PWM driver 12_1b can receive the slave PWM signal P21 and provide the corresponding slave current output SO_1 for the load device 2 according to the slave PWM signal P21. The remaining slave current outputs can be provided in the same way as with the master driver 11 and the slave PWM signal generator 132_1. Regarding the master driver 11, the master PWM signal generator 131 can have similar hardware to the pulse width regenerator 132_1c, since they are both used to supply PWM signals. The master PWM signal generator 131 can generate the master PWM signal P1 for the PWM driver 11c in accordance with the master COT control signal CSM1, so that the PWM driver 11c outputs the master current output MO1 in accordance with the master PWM signal P1. In some embodiments, as shown in Fig. 3, the master PWM signal generator 131 can increase the width of each pulse of the master COT control signal CSM1 before providing it to the PWM driver 11c, as indicated by the dashed line on the first pulse of the master COT control signal CSM1. Each pulse width regenerator (e.g., the pulse width generator 132_1c) can also first increase the width of each pulse of the corresponding slave COT control signal and then perform the adjustments as indicated by the pulse matching information for the corresponding slave COT control signal, as shown by the first dotted line on the first pulse of the slave COT control signal CSS1. The width of each pulse of each slave COT control signal can be increased to the same pulse width as the master COT control signal CSM1 by each corresponding slave pulse width regenerator. According to the invention, the width of each pulse of each slave COT control signal, when reduced, must not be shorter than the width of each pulse of the master COT control signal CSM1. A second embodiment of the present disclosure can be the multi-phase COT controller 13, as described above. In some embodiments, the multi-phase COT controller 13 can be a standalone device that works in conjunction with the master driver 11 and the slave driver(s) 12_1-12_n, as shown in Fig. 1. In some other embodiments, the master PWM signal generator 131 can be integrated into the master driver 11, while each of the slave PWM signal generators 132_1-132_n can be integrated into the corresponding slave driver(s) 12_1-12_n, as shown in Fig. 2. As explained above, the multiphase COT controller 13 of this disclosure offers an excellent opportunity for the multiphase interleaving of the power converter 1. The width of each pulse in the at least one slave COT control signal is adjusted according to the comparison of the detected currents of the master driver 11 and each slave driver, which also affects the turn-on time in each slave phase. The current output(s) in the slave phase(s) can therefore be adjusted to match the current output of the master phase. This creates an overall current balancing mechanism for the power converter 1, maintaining the COT characteristics in all phases. Furthermore, the current balancing mechanism is designed to adjust the pulse widths for the slave driver(s) and not for all drivers in the power converter 1. This provides a more efficient method of multiphase current balancing. The foregoing disclosure relates to the detailed technical content and inventive features of the invention. Based on the described disclosures and proposals of the invention, skilled persons can make a multitude of modifications and substitutions without departing from the features of the invention.

Claims

Multiphase COT controller (13) comprising: a master PWM signal generator (131) for a master driver (11); at least one slave PWM signal generator (132-1, 132_n) for at least one slave driver (12_1, 12_n); and a phase controller (133) electrically connected to the master PWM signal generator (131) and each slave PWM signal generator (132_1, 132_n) and arranged to split a complete COT control signal (CF1) into a master COT control signal (CSM1) and at least one slave COT control signal (CSS1, CSSn), wherein the master COT control signal (CSM1) is arranged to drive the master PWM signal generator (131), and each slave COT control signal (CSS1, CSSn) is arranged to drive the corresponding slave PWM signal generator (132_1, 132_n); wherein: the master PWM signal generator (131) is arranged to generate a master PWM signal (P1) according to the master COT control signal (CSM1);and each slave PWM signal generator (132_1, 132_n) is arranged to generate a slave PWM signal (P21, P2n) by adjusting the width of each pulse of the corresponding slave COT control signal (CSS1, CSSn) according to a comparison between a sensed current (CS11) of the master driver (11) and a sensed current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n); each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by decreasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the sensed current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is greater than the sensed current (CS11) of the master driver (11); and wherein the width of each pulse of the slave COT control signal (CSS1, CSSn) is not shorter than the width of each pulse of the complete COT control signal (CF1).; Multiphase COT controller (13) according to claim 1, wherein the master PWM signal generator (131) generates the master PWM signal (P1) by increasing the width of each pulse of the master COT control signal (CSM1). Multiphase COT controller (13) according to claim 1, wherein each of the slave PWM signal generators (132_1, 132_n) adapts the corresponding slave COT control signal (CSS1, CSSn) by increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the sensed current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is weaker than the sensed current (CS11) of the master driver (11). Multiphase COT controller (13) according to claim 3, wherein each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by first increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) and then increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the detected current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is weaker than the detected current (CS11) of the master driver (11). Multiphase COT controller (13) according to claim 1, wherein each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by first increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) and then decreasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the detected current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is greater than the detected current (CS11) of the master driver (11). Multiphase COT controller (13) according to claim 5, wherein the width of each pulse of the slave COT control signal (CSS1, CSSn) is not shorter than the width of each pulse of the complete COT control signal (CF1). Multiphase COT controller (13) according to claim 1, wherein the phase controller (133) comprises: a counter (133a) arranged to generate a selection signal (SEL) based on the complete COT control signal (CF1); and a demultiplexer (133b) electrically connected to the counter (133a) and arranged to generate the master COT control signal (CSM1) and the at least one slave COT control signal (CSS1, CSSn) according to the selection signal (SEL) and the complete COT control signal (CF1). Multiphase COT controller (13) according to claim 7, wherein the selection signal (SEL) indicates that the master COT control signal (CSM1) is output by the demultiplexer (133b) before the at least one slave COT control signal (CSS1, CSSn). Multiphase COT controller (13) according to claim 7, wherein the phase controller (133) further comprises a reset signal generator (133c) which is electrically connected to the counter (133a), wherein the reset signal generator (133c) is arranged such that it generates a reset signal (RST) for the counter (133a). Multiphase COT controller (13) according to claim 3, wherein each of the at least one slave PWM signal generators (132_1, 132_n) comprises: a comparator (132_1a) arranged to compare the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) corresponding to the slave PWM signal generator (132_1, 132_n) with the detected current (CS11) of the master driver (11); an up-down counter (132_1b) electrically connected to the comparator (132_1a) and arranged to generate a pulse-width-enhancing signal (UP1) when the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) is lower than the detected current (CS11) of the master driver (11). Master driver (11);and a pulse width regenerator (132_1c) which is electrically connected to the up-down counter (132_1b) and the phase controller (133) and is arranged such that it increases the width of each pulse of the slave COT control signal (CSS1, CSSn) as the slave PWM signal (P21, P2n) in response to the pulse width enlarging signal (UP1). Multiphase COT controller (13) according to claim 1, wherein each of the at least one slave PWM signal generators (132_1, 132_n) comprises: a comparator (132_1a) arranged to compare the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) corresponding to the slave PWM signal generator (132_1, 132_n) with the detected current (CS11) of the master driver (11); an up-down counter (132_1b) electrically connected to the comparator (132_1a) and arranged to generate a pulse width-reducing signal (DW1) when the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) is greater than the detected current (CS11) of the master driver (11). Master driver (11);and a pulse width regenerator (132_1c) which is electrically connected to the up-down counter (132_1b) and the phase controller (133) and is arranged to reduce the width of each pulse of the slave COT control signal (CSS1, CSSn) as the slave PWM signal (P21, P2n) in response to the pulse width reducing signal (DW1). Multiphase COT controller (13) according to claim 1, wherein the complete COT control signal (CF1) is generated by the master driver (11) and the phase controller (133) is further arranged to receive the complete COT control signal (CF1) from the master driver (11). A power converter (1) comprising: a master driver (11) arranged to provide a master current output (MO1) for a load device (2) according to a master PWM signal (P1); at least one slave driver (12_1, 12_n) electrically connected to the master driver (11), each slave driver (12_1, 12_n) arranged to provide a slave current output (SO-1, SO-n) for the load device (2) according to a corresponding slave PWM signal (P21, P2n); a master PWM signal generator (131) for the master driver (11) electrically connected to the master driver (11); and at least one slave PWM signal generator (132_1, 132_n) for each of the at least one slave driver (12_1, 12_n).and a phase controller (133) electrically connected to the master driver (11), the master PWM signal generator (131), and each slave PWM signal generator (132_1, 132_n), and arranged to split a complete COT control signal (CF1) into a master COT control signal (CSM1) and at least one slave COT control signal (CSS1, CSSn), wherein the master COT control signal (CSM1) is arranged to address the master PWM signal generator (131), and each slave COT control signal (CSS1, CSSn) is arranged to address the corresponding slave PWM signal generator (132_1, 132_n); wherein: the master PWM signal generator (131) is arranged to generate the master PWM signal (P1) according to the master COT control signal (CSM1);and each slave PWM signal generator (132_1, 132_n) is arranged to generate the slave PWM signal (P21, P2n) corresponding to one of the at least one slave drivers (12_1, 12_n) by adjusting the width of each pulse of the corresponding slave COT control signal (CSS1, CSSn) according to a comparison between a sensed current (CS11) of the master driver (11) and a sensed current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n); each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by decreasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the sensed current (CS21, CS2n) of the corresponding the slave driver (12_1, 12_n) is stronger than the detected current (CS11) of the master driver (11); and wherein the width of each pulse of the slave COT control signal (CSS1, CSSn) is not shorter than the width of each pulse of the full COT control signal (CF1).; Power converter (1) according to claim 13, wherein the master PWM signal generator (131) generates the master PWM signal (P1) by increasing the width of each pulse of the master COT control signal (CSM1). Power converter (1) according to claim 13, wherein each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the detected current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is weaker than the detected current (CS11) of the master driver (11). Power converter (1) according to claim 15, wherein each of the slave PWM signal generators (132_1, 132_n) adjusts the corresponding slave COT control signal (CSS1, CSSn) by first increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) and then increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the detected current (CS21; CS2n) of the corresponding slave driver (12_1, 12_n) is weaker than the detected current (CS11) of the master driver (11). Power converter (1) according to claim 13, wherein each of the slave PWM signal generators (132_1, 132_n) sets the corresponding slave COT control signal (CSS1, CSSn) by first increasing the width of each pulse of the slave COT control signal (CSS1, CSSn) and then decreasing the width of each pulse of the slave COT control signal (CSS1, CSSn) when the detected current (CS21, CS2n) of the corresponding slave driver (12_1, 12_n) is greater than the detected current (CS11) of the master driver (11). Power converter (1) according to claim 17, wherein the width of each pulse of the slave COT control signal (CSS1, CSSn) is not shorter than the width of each pulse of the complete COT control signal (CF1). Power converter (1) according to claim 13, wherein the phase controller (133) comprises: a counter (133a) arranged to generate a selection signal (SEL) based on the complete COT control signal (CF1); and a demultiplexer (133b) electrically connected to the counter (133a) and arranged to generate the master COT control signal (CSM1) and the at least one slave COT control signal (CSS1, CSSn) according to the selection signal (SEL) and the complete COT control signal (CF1). Power converter (1) according to claim 19, wherein the selection signal (SEL) indicates that the master COT control signal (CSM1) is output by the demultiplexer (133) before the at least one slave COT control signal (CSS1, CSSn). Power converter (1) according to claim 19, wherein the phase controller (133) further comprises a reset signal generator (133c) which is electrically connected to the counter (133a), wherein the reset signal generator (133c) is arranged such that it generates a reset signal (RST) for the counter (133a). Power converter (1) according to claim 15, wherein each of the at least one slave PWM signal generators (132_1, 132_n) comprises: a comparator (132_1a) arranged to compare the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) corresponding to the slave PWM signal generator (132_1, 132_n) with the detected current (CS11) of the master driver (11); an up-down counter (132_1b) electrically connected to the comparator (132_1a) and arranged to generate a pulse-width-enhancing signal (UP1) when the detected current (CS21; CS2n) of the slave driver (12_1, 12_n) is lower than the detected current (CS11) of the master driver. (11);and a pulse width regenerator (132_1c) which is electrically connected to the up-down counter (132_1b) and the phase controller (133) and is arranged such that it increases the width of each pulse of the slave COT control signal (CSS1, CSSn) as the slave PWM signal (P21, P2n) in response to the pulse width enlarging signal (UP1). Power converter (1) according to claim 13, wherein each of the at least one slave PWM signal generators (132_1, 132_n) comprises: a comparator (132_1a) arranged to compare the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) corresponding to the slave PWM signal generator (132_1, 132_n) with the detected current (CS11) of the master driver (11); an up-down counter (132_1b) electrically connected to the comparator (132_1a) and arranged to generate a pulse-width-reducing signal (DW1) when the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) is greater than the detected current (CS11) of the master driver. (11);and a pulse width regenerator (132_1c) which is electrically connected to the up-down counter (132_1b) and the phase controller (133) and is arranged to reduce the width of each pulse of the slave COT control signal (CSS1, CSSn) as the slave PWM signal (P21, P2n) in response to the pulse width reducing signal (DW1). Power converter (1) according to claim 13, wherein the complete COT control signal (CF1) is generated by the master driver (11) and the phase controller (133) is further arranged to receive the complete COT control signal (CF1) from the master driver (11). Power converter (1) according to claim 13, wherein the master PWM signal generator (131) is integrated into the master driver (11). Power converter (1) according to claim 13, wherein the master driver (11) comprises: a COT controller (11a) electrically connected to the phase controller (133) and arranged to generate the complete COT control signal (CF1) corresponding to a total current output (VT) of the power converter (1), the total current output (VT) being formed jointly by the master current output (MO1) and the slave current output (SO_1, SO_n); a master current sensor (11b) electrically connected to the at least one slave PWM signal generator (132_1, 132_n) and arranged to provide the detected current (Cs11) of the master driver (11) to the at least one slave PWM signal generator (132_1, 132_n); and a PWM driver (11c) which is electrically connected to the master PWM signal generator (131) and arranged to provide the master current output (MO1) according to the master PWM signal (P1). Power converter (1) according to claim 13, wherein each of the slave drivers (12_1, 12_n) comprises: a slave current sensor (12_1a) electrically connected to the slave PWM signal generator (132_1, 132_n) and arranged to provide the detected current (CS21, CS2n) of the slave driver (12_1, 12_n) to the slave PWM signal generator (132_1, 132_n); and a PWM driver (12_1b) electrically connected to the slave PWM signal generator (132_1, 132_n) and arranged to provide the slave current output (SO_1, SO_n) according to the slave PWM signal (P21, P2n).

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