SIGNAL AMPLIFICATION CIRCUIT AND DISPLAY DEVICE

Abstract

The application provides a signal amplifier circuit and a display device. In the signal amplifier circuit, the gate of the drive transistor of the first inverter is connected to the output end of the reset module. When the impedance of the optoelectronic device changes, the potential of the gate of the drive transistor of the first inverter changes, causing potential changes at all nodes of the first inverter to amplify the signal.At the same time, the first compensation transistor is connected between the second gate of the first drive transistor and the first output node, the potential of the first output node is precharged to the second gate of the first drive transistor to adjust the threshold voltage of the first drive transistor, improve the difference in threshold voltage between different transistors, and solve the technical problem of signal unevenness after amplification by the inverter.

Description

TECHNICAL FIELD

[0001] The application relates to the field of display technology, in particular a signal amplifier circuit and a display device. STATE OF THE ART

[0002] Non-touch screens have attracted much attention due to their unique 3D touch advantages, and the use of photodetectors as gesture motion sensing units is a good choice for non-touch screens. The working principle of photoelectric sensors is to cause changes in the resistance of optoelectronic diodes through changes in the optical signal, thereby achieving changes in the photoelectric signal. The gesture position is determined by the changes in the photoelectric signal. However, the human hands cannot emit light themselves, so a certain ambient light is needed for support. However, under dim lighting, the light signal in the environment is small, and the corresponding photoelectric signal is also small, difficult to detect, and easily affected by noise.

[0003] Existing non-touch screens amplify signals through inverters to obtain signals in low-light conditions. However, due to the difference in threshold voltage between different transistors, the signal becomes uneven after being amplified by inverters, resulting in poor response accuracy in low-light conditions. DISCLOSURE OF THE INVENTION

[0004] The present embodiment of the present application provides a signal amplification circuit and a display device for improving the technical problem of the uneven signal after amplification by an inverter in existing non-touch screens.

[0005] The present embodiment of the present application provides a signal amplification circuit comprising: a reset module, wherein an input end of the reset module is connected to an input signal end; a photoelectric device, wherein a first end of the photoelectric device is connected to an output end of the reset module, a second end of the photoelectric device is connected to the input signal end and the input end of the reset module; a positive feedback module, wherein a first end of the positive feedback module is connected to a first constant voltage signal end, a second end of the positive feedback module is connected to a second constant voltage signal end, wherein the positive feedback module comprises at least a first inverter, wherein the first inverter comprises a first load transistor, a first drive transistor and a first output node, wherein the first load transistor is connected to the first drive transistor at the first output node within the first inverter, wherein the first output node is electrically connected to the output signal end, wherein a potential of the second constant voltage signal end is greater than that of the first constant voltage signal end; wherein the first inverter further comprises a first compensation transistor, wherein the first drive transistor comprises a first gate and a second gate, wherein the first gate of the first drive transistor is connected to the output end of the reset module, wherein a first electrode of the first compensation transistor is connected to the first output node, wherein a second electrode of the first compensation transistor is connected to the second gate of the first drive transistor.

[0006] In the signal amplification circuit of the present application, the first inverter further comprises a first storage capacitor, wherein a first electrode plate of the first storage capacitor is connected to the second gate of the first drive transistor, wherein a second electrode plate of the first storage capacitor is connected to the first constant voltage signal end.

[0007] In the signal amplification circuit of the present application, the first load transistor comprises a first gate and a second gate, wherein the first gate of the first load transistor is connected to the first electrode of the first load transistor, the second gate of the first load transistor is connected to the first output node.

[0008] In the signal amplification circuit of the present application, the positive feedback module further comprises a second inverter, the second inverter comprising a second load transistor, a second drive transistor, a second compensation transistor, and a second output node, the gate of the second load transistor being connected to the second constant voltage signal end, the first electrode of the second load transistor being connected to the second constant voltage signal end, the second electrode of the second load transistor being connected to the first electrode of the second drive transistor at the second output node, the gate of the first load transistor being connected to the second output node, the second electrode of the second drive transistor being connected to the first constant voltage signal end; wherein the second drive transistor comprises a first gate and a second gate, wherein the first gate of the second drive transistor is connected to the first output node, wherein the first electrode of the second compensation transistor is connected to the second output node, wherein the second electrode of the second compensation transistor is connected to the second gate of the second drive transistor.

[0009] In the signal amplification circuit of the present application, the reset module comprises a reset transistor, wherein the first electrode of the reset transistor is connected to the input signal end, wherein the second electrode of the reset transistor is connected to the first end of the optoelectronic device, wherein the gate of the reset transistor is connected to a first scan signal line.

[0010] In the signal amplification circuit of the present application, the signal amplification circuit further comprises a voltage follower comprising at least a third load transistor, a third drive transistor, and a third output node, wherein the gate of the third drive transistor is connected to the first output node, wherein the first electrode of the third drive transistor is connected to the second constant voltage signal end, wherein the second electrode of the third drive transistor is connected to the first electrode of the third load transistor at the third output node, wherein the gate of the third load transistor is connected to the second scan signal line, wherein the second electrode of the third load transistor is connected to the first constant voltage signal end.

[0011] In the signal amplification circuit of the present application, the third drive transistor comprises a first gate and a second gate, wherein the first gate of the third drive transistor is connected to the first output node, wherein the second gate of the third drive transistor is connected to the third output node; wherein the third load transistor comprises a first gate and a second gate, wherein the first gate of the third load transistor is connected to the second scanning signal line, wherein the second gate of the third load transistor is connected to the first constant voltage signal end.

[0012] In the signal amplification circuit of the present application, the signal amplification circuit further comprises an addressing module, the addressing module comprising at least one addressing transistor, the first electrode of the addressing transistor being connected to the third output node, the gate of the addressing transistor being connected to the third scan signal line, the second electrode of the addressing transistor being connected to the output signal end.

[0013] In the signal amplification circuit of the present application, the reset transistor comprises a first gate and a second gate, wherein the first gate of the reset transistor is connected to the first scanning signal line, wherein the second gate of the reset transistor is connected to the fourth scanning signal line; wherein the first compensation transistor comprises a first gate and a second gate, wherein the first gate of the first compensation transistor is connected to the first scanning signal line, wherein the second gate of the first compensation transistor is connected to the fourth scanning signal line; wherein the addressing transistor comprises a first gate and a second gate, wherein the first gate of the addressing transistor is connected to the third scan signal line, wherein the second gate of the addressing transistor is connected to the fourth scan signal line.

[0014] The present application provides a display device comprising a plurality of pixel units, at least one of which comprises a signal amplification circuit according to any one of the preceding embodiments and a pixel circuit.

[0015] Advantageous effect: A signal amplification circuit and a display device are provided. The signal amplification circuit comprises: a reset module, a photoelectric device, and a positive feedback module, wherein an input end of the reset module is connected to an input signal end, wherein a first end of the photoelectric device is connected to an output end of the reset module, a second end of the photoelectric device is connected to the input signal end and the input end of the reset module, wherein a first end of the positive feedback module is connected to a first constant voltage signal end, wherein a second end of the positive feedback module is connected to a second constant voltage signal end, wherein the positive feedback module comprises at least a first inverter, wherein the first inverter comprises a first load transistor,a first drive transistor and a first output node, wherein the first load transistor is connected to the first drive transistor at the first output node within the first inverter, wherein the first output node is electrically connected to the output signal end, wherein a potential of the second constant voltage signal end is greater than that of the first constant voltage signal end, wherein the first drive transistor comprises a first gate and a second gate, wherein the first gate of the first drive transistor is connected to the output end of the reset module, wherein a first electrode of the first compensation transistor is connected to the first output node, wherein a second electrode of the first compensation transistor is connected to the second gate of the first drive transistor. In the signal amplification circuit, the gate of the drive transistor of the first inverter is connected to the output end of the reset module,When the impedance of the optoelectronic device changes, the potential of the gate of the drive transistor of the first inverter changes, causing potential changes at all nodes of the first inverter to amplify the signal. At the same time, the first compensation transistor is connected between the second gate of the first drive transistor and the first output node. The potential of the first output node is precharged to the second gate of the first drive transistor to adjust the threshold voltage of the first drive transistor, improve the difference in threshold voltage between different transistors, and solve the technical problem of signal unevenness after amplification by the inverter. PRESENTATION OF THE DRAWINGS

[0016] With reference to the accompanying drawings, a detailed description of the specific embodiments of this application will make the technical solutions and other advantageous effects of this application apparent. Fig. 1 shows a first circuit diagram of the signal amplification circuit provided in the present embodiment. Fig. Fig. 2 shows a second circuit diagram of the signal amplification circuit provided in the present embodiment. Fig. 3 shows a schematic diagram of the structure of the display device provided in the present embodiment. Fig. 4 shows the circuit diagrams of the signal amplification circuit and pixel circuit within the pixel unit in Fig. 3. CONCRETE EMBODIMENTS

[0017] The following provides a clear and complete description of the technical solution in the embodiments of this application in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not the entire embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the relevant technical field without creative effort fall within the scope of this application.

[0018] This embodiment of the present application aims to address the problem of poor amplification effect of multi-level inverters on existing non-touch screens, resulting in low response accuracy in low light conditions, and to provide a signal amplification circuit and a display device to alleviate the above-mentioned technical problem.

[0019] Please refer to Fig. 1 and Fig. 2. The present embodiment of the present application provides a signal amplification circuit 100 that includes a reset module 110, a photoelectric device 120, and a positive feedback module 130.

[0020] In this embodiment, the input end of the reset module 110 is connected to the input signal end Vin, the first end of the optoelectronic device 120 is connected to the output end of the reset module 110, the second end of the optoelectronic device 120 is connected to the input signal end Vin and the input end of the reset module 110, the first end of the positive feedback module 130 is connected to the first constant voltage signal end Vgnd, the second end of the positive feedback module 130 is connected to the second constant voltage signal end Vdd.

[0021] In this embodiment, the positive feedback module 130 includes at least a first inverter 131, which includes a first load transistor T1, a first drive transistor T2, and a first output node Q. The first load transistor T1 is connected to the first drive transistor T2 at the first output node Q within the first inverter 131, the first output node Q is electrically connected to the output signal end Vout, and the potential of the second constant voltage signal end Vdd is greater than the potential of the first constant voltage signal end Vgnd.

[0022] In this embodiment, the first inverter 131 further comprises a first compensation transistor T6, the first drive transistor T2 comprises a first gate and a second gate, the first gate of the first drive transistor T2 is connected to the output end of the reset module 110, the first electrode of the first compensation transistor T6 is connected to the first output node Q, the second electrode of the first compensation transistor T6 is connected to the second gate of the first drive transistor T2.

[0023] In the signal amplifier circuit 100 of this application, the gate of the first drive transistor T2 of the first inverter 131 is connected to the output end of the reset module 110. When the impedance of the optoelectronic device 120 changes, the potential of the gate of the first drive transistor T2 of the first inverter 131 changes, causing the potential of each node of the first inverter 131 to change to amplify the signal. At the same time, the first compensation transistor T6 is connected between the second gate of the first drive transistor T2 and the first output node Q.The potential of the first output node Q is precharged to the second gate of the first drive transistor T2 to adjust the threshold voltage of the first drive transistor T2, improve the difference in threshold voltage between different transistors, and solve the technical problem of signal unevenness after amplification by the inverter.

[0024] In this embodiment, the present application illustrates the optoelectronic device 120 with a diode PD, a current source Iph, and a capacitor Cpd. The optoelectronic device 120 has a fixed capacitor Cpd. When no electrical signal is input, the optoelectronic device 120 can be simplified as a diode PD. When the optoelectronic device 120 is illuminated, a reverse current source Iph is generated.

[0025] In this embodiment, the optoelectronic device 120 may be one of the optoelectronic diode, the optoelectronic transistor, and the photoresistor.

[0026] In this embodiment, the first end of the photoelectric device 120 may be a cathode, and the second end of the photoelectric device 120 may be an anode; At the same time, the first end of the photoelectric device 120 may be the input end of the photoelectric transistor, and the second end of the photoelectric device 120 may be the output end of the photoelectric transistor.

[0027] Please note that in the accompanying drawings of the present embodiment, a solid dot is used between intersecting routes to indicate the connection. If two intersecting routes are not indicated by a solid dot, it means that the two intersecting routes are not connected.

[0028] In this embodiment, the optoelectronic device 120 may include one of a perovskite photodetector, a hydrogenated amorphous silicon photodetector, and a metal oxide photodetector.

[0029] In this embodiment, please refer to Fig. 1. The reset module 110 includes a reset transistor T5. The first electrode of the reset transistor T5 is connected to the input signal end Vin, the second electrode of the reset transistor T5 is connected to the first end of the optoelectronic device 120, and the gate of the reset transistor T5 is connected to the first scanning signal line Scan1. The reset module 110 of this application includes a reset transistor T5, so that the first reset transistor T5 can control whether the signal is input to the signal amplification circuit 100, thereby causing the signal amplification circuit 100 to operate or stop operating.

[0030] This application takes the reset module 110 including a reset transistor T5 as an example for explanation, but the embodiments of this application are not limited thereto. The reset module 110 may include multiple reset transistors T5.

[0031] In this embodiment, the reset transistor T5 can be single-gate or double-gate. If the reset transistor T5 is single-gate, the gate of the reset transistor T5 is connected to the first scan signal line Scan1. If the reset transistor T5 is double-gate, as in Fig. 1, the first gate of the reset transistor T5 is connected to the first scanning signal line Scan1, the second gate of the reset transistor T5 may be connected to the fourth scanning signal line Scan4.

[0032] In this embodiment, by connecting the first gate of the reset transistor T5 to the scan signal line in the previous row, an increased on-state current and a reduced off-state current can be obtained. When the scan signal in the previous row is turned on, one end of the optoelectronic device 120 can be charged to the input voltage of the input signal end Vin. Second, this application adjusts the threshold voltage of the reset transistor T5 by adjusting the value of the input voltage of the fourth scan signal line Scan4.

[0033] For this embodiment, please refer to Fig. 1. In the first inverter 131 of the present application, the gate of the first load transistor T1 is connected to the second constant voltage signal end Vdd, the first electrode of the first load transistor T1 is connected to the second constant voltage signal end Vdd, the second electrode of the first load transistor T1 is connected to the first output node Q; the first electrode of the first drive transistor T2 is connected to the first output node Q, the second electrode of the first drive transistor T2 is connected to the first constant voltage signal end Vgnd, the first electrode of the first compensation transistor T6 is connected to the first output node Q, and the second electrode of the first compensation transistor T6 is connected to the second gate of the first drive transistor T2.

[0034] In the present application, a first compensation transistor T6 connecting the second gate of the first drive transistor T2 and the first output node Q is provided within the first inverter 131. When the first compensation transistor T6 is turned on, the first compensation transistor T6 precharges the potential of the first output node Q to the second gate of the first drive transistor T2 to adjust the threshold voltage of the first drive transistor T2, thereby improving the difference in threshold voltage between different transistors. The technical problem of the uneven signal after amplification by the inverter is solved.

[0035] In this embodiment, the first compensation transistor T6 may be a single gate or a double gate. If the first compensation transistor T6 is a single gate, the gate of the first compensation transistor T6 is connected to the first scanning signal line Scan1. If the first compensation transistor T6 is a double gate, as in Fig. As shown in Figure 1, the first gate of the first compensation transistor T6 is connected to the first scanning signal line Scan1, and the second gate of the first compensation transistor T6 may be connected to the fourth scanning signal line Scan4. This application can obtain an increased on-state current and a reduced off-state current by connecting the first gate of the first compensation transistor T6 to the previous row of scanning signal lines. When the previous row of scanning signals is on, the potential of the first output node Q may be precharged to the second gate of the first drive transistor T2. Second, this application adjusts the threshold voltage of the first compensation transistor T6 by adjusting the value of the input voltage of the fourth scanning signal line Scan4.

[0036] In this embodiment, the gate of the first load transistor T1 may be a single gate or a double gate. For example, the first load transistor T1 may include a first gate and a second gate. The first gate of the first load transistor T1 is connected to the first electrode of the first load transistor T1. The second gate of the first load transistor T1 is connected to the first output node Q. This application can improve the controllability of the first load transistor T1 and enhance the stability of the circuit by constructing the first load transistor T1 as a double gate.

[0037] Please refer to Fig. 1. The first inverter 131 may further comprise a first storage capacitor C1, wherein the first electrode plate of the first storage capacitor C1 is connected to the second gate of the first drive transistor T2, the second electrode plate of the first storage capacitor C1 is connected to the first constant voltage signal source Vgnd.

[0038] In this embodiment, when the first compensation transistor T6 is turned on, the first compensation transistor T6 precharges the potential of the first output node Q to the second gate of the first drive transistor T2. At the same time, the potential of the first output node Q is stored in the first storage capacitor C1, and the first storage capacitor C1 can maintain the potential of the second gate of the first drive transistor T2 at the same potential as the first output node Q.The adjustment of the first storage capacitor C1 can continuously adjust the threshold voltage of the first drive transistor T2, thereby avoiding the potential of the second gate of the first drive transistor T2 being unable to maintain the same potential as the first output node Q due to current leakage, thereby improving the stability of the potential of the second gate of the first drive transistor T2 and further improving the difference in threshold voltage between different transistors, and solving the technical problem of the uneven signal after amplification by the inverter.

[0039] For this embodiment, please refer to Fig. 1. The signal amplification circuit 100 further includes a voltage follower 140 comprising at least a third load transistor T4, a third drive transistor T3, and a third output node P. The gate of the third drive transistor T3 is connected to the first output node Q, the first electrode of the third drive transistor T3 is connected to the second constant voltage signal end Vdd. The second electrode of the third drive transistor T3 is connected to the first electrode of the third load transistor T4 at the third output node P, the gate of the third load transistor T4 is connected to the second scan signal line Scan2, and the second electrode of the third load transistor T4 is connected to the first constant voltage signal end Vgnd.In this application, a voltage follower 140 is provided so that the voltage follower 140 follows the output amplified signal, so that the electrical signal output by the positive feedback module 130 is output by the voltage follower 140 to avoid signal interference, and buffering can be performed by the voltage follower 140.

[0040] In this embodiment, the gate of the third drive transistor T3 may be a single gate; The gate of the third drive transistor T3 may further comprise a first gate and a second gate, as shown in Fig. 1. The third drive transistor T3 comprises a first gate and a second gate. The first gate of the third drive transistor T3 is connected to the first output node Q, and the second gate of the third drive transistor T3 is connected to the third output node P.

[0041] In this embodiment, the gate of the third load transistor T4 may be a single gate; The gate of the third load transistor T4 may also comprise a first gate and a second gate, as in Fig. 1. The third load transistor T4 includes a first gate and a second gate. The first gate of the third load transistor T4 is connected to the second scanning signal line Scan2, and the second gate of the third load transistor T4 is connected to the first constant voltage signal end Vgnd.

[0042] For this embodiment, please refer to the Fig. 1. The signal amplification circuit 100 further includes an addressing module 150, which includes at least one addressing transistor T7. The first electrode of the addressing transistor T7 is connected to the third output node P, the gate of the addressing transistor T7 is connected to the third scanning signal line Scan3, and the second electrode of the addressing transistor T7 is connected to the output signal end Vout. In this application, the addressing transistor T7 is provided such that the gate of the addressing transistor T7 is connected to the third scanning signal line Scan3. When the row-by-row scanning of the square wave signal achieves these objectives, the voltage of the output signal end Vout is read by the addressing transistor T7.

[0043] In this embodiment, the gate of the addressing transistor T7 may be a single gate; The gate of the addressing transistor T7 may also comprise a first gate and a second gate, as in Fig. 1. The first gate of the addressing transistor T7 is connected to the third scanning signal line Scan3, and the second gate of the addressing transistor T7 is connected to the fourth scanning signal line Scan4. The addressing transistor T7 can receive an increased on-state current and a reduced off-state current. Second, this application adjusts the threshold voltage of the addressing transistor T7 by adjusting the value of the input voltage of the fourth scanning signal line Scan4.

[0044] In this embodiment, the first scanning signal line Scan1 can be the upper-level scanning signal line, the third scanning signal line Scan3 can be the current-level scanning signal line, the input voltage of the second scanning signal line Scan2 can turn on the third load transistor T4, and the third load transistor T4 is in a normally-on state. The fourth scanning signal line Scan4 is mainly used to adjust the threshold voltage of the reset transistor T5, the first compensation transistor T6, and the addressing transistor T7.

[0045] In this embodiment, the first and second electrodes in the transistor differ from each other in terms of source and drain, respectively. The function and structure of the first and second electrodes are identical, with only a name difference.

[0046] In this embodiment, the first gates in the reset transistor T5, first drive transistor T2, first load transistor T1, first compensation transistor T6, second load transistor T9, second drive transistor T10, and addressing transistor T7 may all be one of the lower or upper gates, and the second gates may be the other of the lower or upper gates.

[0047] In this embodiment, the aspect ratio of the load transistor is smaller than that of the drive transistor, which enables signal amplification. For example, the aspect ratio of the first load transistor T1 is smaller than that of the first drive transistor T2, and the aspect ratio of the second load transistor T9 is smaller than that of the second drive transistor T10.

[0048] In this embodiment, each transistor mentioned in the present embodiment may be a hydrogenated amorphous silicon transistor, a metal oxide transistor, or a low-temperature polycrystalline silicon transistor.

[0049] Specifically, the above embodiments have explained the signal amplification circuit 100 of various modules, elements, or transistors. It can be understood that if there is no conflict between the embodiments, better technical effects can be achieved by combining the embodiments.

[0050] The following is an explanation of the working process of the signal amplification circuit 100 in this application using the circuit structure in Fig. 1.

[0051] When the first scan signal line Scan1 inputs a turn-on signal, the reset transistor T5 is turned on, the input signal end Vin writes the input signal (which may be a positive voltage signal) to one end of the optoelectronic device 120. When the optoelectronic device 120 does not sense light, the input signal from the input signal end Vin is applied to the upper gate of the first drive transistor T2 due to the antibias state of the optoelectronic device 120.

[0052] The anode of the photoelectric device 120 is connected to the input signal terminal Vin, and the cathode of the photoelectric device 120 is connected to the first gate of the first drive transistor T2. When the photoelectric device 120 is not illuminated, the potential of the cathode of the photoelectric device 120 is Vi; when the optoelectronic device 120 is illuminated, it generates a photocurrent that is positively correlated with the light intensity. At this time, the cathode potential changes to (Vi Voc), Voc being the open circuit voltage of the optoelectronic device 120. Voc is positively correlated with the light intensity. Therefore, when light is irradiated onto the optoelectronic device 120, the input signal applied to the first gate of the first drive transistor T2 decreases.Therefore, when the photoelectric device 120 is illuminated by light and the photoelectric device 120 is not illuminated by light, there is a voltage difference at the gate of the first drive transistor T2. The voltage difference is amplified by the positive feedback module 130 and output by the voltage follower 140 as the voltage of the third output node P.

[0053] Specifically, the second constant voltage signal end Vdd continuously inputs a signal to turn on the first load transistor T1, the first output node Q is connected to the third drive transistor T3 to turn on the third drive transistor T3, the second scan signal line Scan2 is connected to the gate of the third load transistor T4 to turn on the third load transistor T4, the third scan signal line Scan3 is connected to the gate of the addressing transistor T7 to turn on the addressing transistor T7, that is, when the second scan signal line Scan2, the third scan signal line Scan3 and the second constant voltage signal end Vdd input signals, the first load transistor T1, the fourth drive transistor and the fourth load transistor are in the on state.

[0054] In particular, when the first scanning signal line Scan1, the second scanning signal line Scan2 and the third scanning signal line Scan3 input low potential, the output signal end Vout has no signal output.

[0055] Specifically, when the first scanning signal line Scan1 inputs the turn-on signal and the input signal terminal Vin writes the input signal to one end of the optoelectronic device 120, there is a voltage difference at the gate of the first driving transistor T2 in the absence and presence of light, causing a change in the potential of the first output node Q. When the signal of the third scanning signal line Scan3 is output at the gate of the third driving transistor T3 and the third scanning signal line Scan3 inputs the turn-on signal, the signal is transmitted to the output signal terminal Vout. The signal output by the output signal terminal Vout exhibits the amplification of the difference in the photoelectric signal, thereby improving the gain of the photoelectric signal and improving the response accuracy under low light.

[0056] In particular, for example, if there is no light radiation on the optoelectronic device 120, the potential of the gate of the first drive transistor T2 is the input voltage Vi of the input signal terminal Vin. If there is light radiation on the optoelectronic device 120, the potential of the first gate of the first drive transistor T2 is Vg1. If there is no light radiation on the optoelectronic device 120 and if there is light radiation on the optoelectronic device 120, there is a voltage difference (Vi-Vg1). The amplification circuit of this application amplifies the voltage difference to m1*(Vi-Vg1), where m1 is the amplification factor of the first inverter 131 and m1 is (W2 / L2). 0.5 *(W1 / L1) 0.5where W1 is the channel width of the first load transistor T1, L1 is the channel length of the first load transistor T1, W2 is the channel width of the first drive transistor T2 and L2 is the channel length of the first drive transistor T2.

[0057] It should be noted that in order to ensure gesture recognition at low light energy, the inverter requires a certain amplification factor. Therefore, the channel length of the first drive transistor T2 is usually small, which makes the switching characteristics of the first drive transistor T2 more susceptible to the influence of short channels, causing the threshold voltage of the first drive transistor T2 to drift. And the drift of the threshold voltage of different transistors is different, which causes the technical problem of uneven signal amplification after amplification by the inverter. For example, if the threshold voltage of the first drive transistor T2 drifts by ΔV, after amplification by the first inverter 131, the drifted voltage will be amplified by m1 times, that is, m1*ΔV, which makes the amplified voltage difference inaccurate.

[0058] The setting of the first compensation transistor T6 in this application can compensate the threshold voltage of the first drive transistor T2, and the specific compensation principle is as follows.

[0059] W1 is the channel width of the first load transistor T1, L1 is the channel length of the first load transistor T1, Vth1 is the threshold voltage of the first load transistor T1, the potential of the first output node Q is Vs, and the potential of the first output node Q is the same as the potential of the second gate in the first drive transistor T2, W2 is the channel width of the first drive transistor T2, L2 is the channel length of the first drive transistor T2, Vth2 is the threshold voltage of the first drive transistor T2, Vin is the potential of the first gate in the first drive transistor T2, and according to the equality of the current I2 flowing through the first drive transistor T2 and the current I1 flowing through the first load transistor T1, equation (1) can be obtained: 12CoxμW1L1(Vdd−Vs−Vth1)2=12CoxμW2L2(Vs+Vin−Vth2)2;

[0060] By transforming equation (1) and replacing m1 as (W2 / L2)0.5*(W1 / L1)0.5 in equation (1), the potential Vs of the first output node Q can be obtained as follows: Vs=1m1+1Vdd−m1m1+1Vin−Vth1m1+1+m1*Vth2m1+1;

[0061] According to the potential Vs when the threshold voltage of the first drive transistor T2 does not drift, the difference Vs1 between Vgs and Vth of the first drive transistor T2 is expressed as equation (2): Vs1+Vin1.5−Vth2=1m1+1Vdd−m1m1+1⋅Vin1.5−Vth1m1+1+Vin1.5−Vth2m1+1;

[0062] According to the potential Vs, when the threshold voltage of the first drive transistor T2 drifts, the difference Vs2 between Vgs and Vth of the first drive transistor T2 is expressed as equation (3): Vs2+Vin1.5−(Vth2+ΔV)=1m1+1Vdd−m1m1+1⋅Vin1.5−Vth1m1+1+Vin1.5−Vth2+ΔVm1+1;

[0063] According to the difference between equations (2) and (3), equation (4) is obtained: [Vs1+Vin1.5−Vth2]−[Vs2+Vin1.5−(Vth2+ΔV)]=ΔVm1+1;

[0064] According to equation (4), it can be seen that for the signal amplification circuit 100 with the first compensation transistor T6, the difference between Vgs and Vth before and after the threshold voltage drift of the first drive transistor T2 decreases from ΔV to ΔV / (m1+1), and after amplification by the amplifier, the drift voltage decreases from m1*ΔV to (m1*ΔV) / (m1+1), which corresponds to a decrease of m1* / (m1+1) times.

[0065] According to the above, the setting of the first compensation transistor T6 in this application can compensate the threshold voltage of the first drive transistor T2 to reduce the drift part of the threshold voltage of the first drive transistor T2 by 1 / (m1+1) times, improve the difference of the threshold voltage between different transistors, and solve the technical problem of signal unevenness after amplification by the inverter.

[0066] It should be noted that the above-mentioned change from Vin to Vin / 1.5 is due to the modulation capability ratio between the lower gate and the upper gate being 1:1.5. This value varies due to the difference in modulation capability between the upper gate and the lower gate. This application only uses 1:1.5 as an example to explain the compensation principle of this application.

[0067] Please refer to Fig. 2. The circuit structure in Fig. 2 is identical or similar to that in Fig. 1, except that the positive feedback module 130 further comprises a second amplifier.

[0068] In this embodiment, the second inverter 132 includes a second load transistor T9, a second drive transistor T10, a second compensation transistor T8, a second storage capacitor C2, and a second output node M. The gate of the second load transistor T9 is connected to the second constant voltage signal end Vdd, the first electrode of the second load transistor T9 is connected to the second constant voltage signal end Vdd. The second electrode of the second load transistor T9 is connected to the first electrode of the second drive transistor T10 at the second output node M, the gate of the first load transistor T1 is connected to the second output node M, and the second electrode of the second drive transistor T10 is connected to the first constant voltage signal end Vgnd.

[0069] In this embodiment, the second drive transistor T10 comprises a first gate and a second gate. The first gate of the second drive transistor T10 is connected to the first output node Q, the first electrode of the second compensation transistor T8 is connected to the second output node M, and the second electrode of the second compensation transistor T8 is connected to the second gate of the second drive transistor T10.

[0070] In this embodiment, the second compensation transistor T8 can be single-gate or double-gate. If the second compensation transistor T8 is single-gate, the gate of the second compensation transistor T8 is connected to the first scanning signal line Scan1. If the second compensation transistor T8 is double-gate, see Fig. 2, the first gate of the second compensation transistor T8 is connected to the first scanning signal line Scan1, and the second gate of the first compensation transistor T6 can be connected to the fourth scanning signal line Scan4. This application can obtain an increased on-state current and a reduced off-state current by connecting the first gate of the second compensation transistor T8 to the scanning signal line in the previous row. When the scanning signal in the previous row is on, the potential of the first output node Q can be precharged to the second gate of the second drive transistor T10; Second, this application adjusts the threshold voltage of the second compensation transistor T8 by adjusting the value of the input voltage of the fourth scanning signal line Scan4.

[0071] In this embodiment, the gate of the second load transistor T9 may be single-gate or double-gate. For example, the second load transistor T9 may include a first gate and a second gate. The first gate of the second load transistor T9 is connected to the first electrode of the second load transistor T9. The second gate of the second load transistor T9 is connected to the second output node M. This application can improve the controllability of the second load transistor T9 and improve the stability of the circuit by constructing the second load transistor T9 as a double-gate.

[0072] Please refer to Fig. 2. The first electrode plate of the second storage capacitor C2 is connected to the second gate of the second drive transistor T10, the second electrode plate of the second storage capacitor C2 is connected to the first constant voltage signal end Vgnd.

[0073] In this embodiment, when the second equalizing transistor T8 is turned on, the second equalizing transistor T8 precharges the potential of the second output node M to the second gate of the second driving transistor T10, and the potential of the second output node M is stored in the second storage capacitor C2. The second storage capacitor C2 can maintain the potential of the second gate of the first driving transistor T2 at the same potential as the second output node M. Adjusting the second storage capacitor C2 can continuously adjust the threshold voltage of the second driving transistor T10, thereby preventing the potential of the second gate of the second driving transistor T10 from being unable to maintain the same potential as the second output node M due to current leakage.

[0074] In the following, the working process of the signal amplification circuit 100 is explained based on the circuit structure shown in Fig. 2 is shown: When the first scanning signal line Scan1 inputs a turn-on signal, the reset transistor T5 is turned on, and the input signal end Vin writes the input signal (which may be a positive voltage signal) to the second end of the optoelectronic device 120. When the photoelectric device 120 is not detecting light, because the optoelectronic device 120 is in the antibias state, the input signal from the input signal end Vin is applied to the first gate of the first drive transistor T2. When the light is irradiated to the optoelectronic device 120, the input signal applied to the first gate of the first drive transistor T2 decreases, resulting in a voltage difference at the gate of the first drive transistor T2 when the light is irradiated to the optoelectronic device 120 and not to the optoelectronic device 120.After the voltage difference is amplified by the positive feedback module 130 and passes through the voltage follower 140, it is used as the output voltage of the third output node P.

[0075] Specifically, the second constant voltage signal end Vdd continuously inputs a signal, causing the second load transistor T9 to be in an on-state. The second output node M is connected to the first gate of the first load transistor T1, thereby turning on the first load transistor T1. The first output node Q is connected to the first gate of the second drive transistor T10, and the first output node Q is connected to the third drive transistor T3, thereby turning on the second drive transistor T10 and the fourth drive transistor. The second scan signal line Scan2 is connected to the gate of the third load transistor T4, thereby turning on the third load transistor T4.That is, when the second scanning signal line Scan2 and the second constant voltage signal end Vdd input the signal, the first load transistor T1, the second load transistor T9, the second drive transistor T10, the fourth drive transistor and the fourth load transistor are in the on state.

[0076] In particular, when the first scanning signal line Scan1, the second scanning signal line Scan2 and the third scanning signal line Scan3 input low potential, the output signal end Vout has no signal output.

[0077] Specifically, when the first scan signal line Scan1 inputs a turn-on signal and the input signal terminal Vin writes the input signal to one end of the optoelectronic device 120, there is a voltage difference at the gate of the first drive transistor T2 in the absence and presence of light, causing a change in the potential at the first output node Q. The change in the potential of the first output node Q causes a change in the partial voltage of the second drive transistor T10, resulting in a change in the potential of the second output node M. The change in the potential of the second output node M causes the change in the potential of the gate of the first load transistor T1, thereby causing the change in the potential of the first output node Q.As this process continues, the potential fluctuations of the first output node Q and the second output node M are caused, causing the output signals of all inverters to be close to or even within the range of the optimal input signal of the next inverter. Then, the signal is output to the gate of the third drive transistor T3, so that the multi-level inverter determines the optimal gain through the potential change of the output node. When the turn-on signal is input through the third scan signal line Scan3, the signal is transmitted to the output signal end Vout. The signal output from the output signal end Vout indicates the gain of the difference in the photoelectric signal, thereby improving the gain of the photoelectric signal and improving the response accuracy under low light.

[0078] In particular, for example, when there is no light radiation on the optoelectronic device 120, the potential of the gate of the first drive transistor T2 is the input voltage Vi of the input signal terminal Vin. When there is light radiation on the optoelectronic device 120, the potential of the gate of the first drive transistor T2 is Vg1. Therefore, there will be a voltage difference (Vi-Vg1) at the gate of the first drive transistor T2 when there is no light radiation on the optoelectronic device 120 and there is light radiation on the optoelectronic device 120. By the amplification circuit of this application, the voltage difference is amplified to m1 * m2 * (Vi-Vg1), where m1 and m2 are amplification factors.In particular, taking a two-stage inverter as an example, when the gain of the first inverter 131 is m1 and the gain of the second inverter 132 is m2, the gain obtained by using the amplification circuit of this application can be close to m1*m2.

[0079] In this embodiment, m1 (W2 / L2) 0.5 *(W1 / L1) 0.5 , W1 is the channel width of the first load transistor T1, L1 is the channel length of the first load transistor T1, W2 is the channel width of the first drive transistor T2, L2 is the channel length of the first drive transistor T2; M2 is (W4 / L4) 0.5 *(W3 / L3) 0.5 , W4 is the channel width of the second load transistor T9, L4 is the channel length of the second load transistor T9, W3 is the channel width of the second drive transistor T10, L3 is the channel length of the second drive transistor T10.

[0080] When the threshold voltage of the first drive transistor T2 drifts by ΔV1, setting the first compensation transistor T6 in this application can reduce the drift threshold voltage to ΔV1 / (m1+1); when the threshold voltage of the second drive transistor T10 drifts by ΔV2, setting the second compensation transistor T8 in this application can reduce the drift threshold voltage to ΔV2 / (m2+1). Therefore, for multi-stage inverters, the compensation transistors in all stages can compensate the threshold voltage in the drive transistor, improve the difference in threshold voltage between different transistors, and solve the technical problem of signal unevenness after amplification by the inverter.

[0081] Similarly, for inverters of more than three stages, reference can be made to the above embodiments for setting.

[0082] Please refer to Fig. 3 and Fig. 4. The present embodiment of the present application provides a display device 200 further comprising a plurality of pixel units 210. At least one pixel unit 210 comprises a signal amplification circuit 100 according to any one of the previous embodiments and a pixel unit 211.

[0083] See Fig. 4. The pixel circuit 211 includes a scanning line, a data line Vdata, a control transistor T11, and a light-emitting unit 212. The gate of the control transistor T11 is connected to the scanning line, the first electrode of the control transistor T11 is connected to the data line Vdata, and the second electrode of the control transistor T11 is electrically connected to the light-emitting unit 212. By arranging the pixel circuit 211 and the signal amplification circuit 100 within the same pixel, the accuracy of detecting photoelectric signals can be improved.

[0084] In this embodiment, the control transistor T11 may be a single gate; the gate of the control transistor T11 may also include a first gate and a second gate. The first gate and the second gate of the control transistor T11 differ from each other with respect to the lower gate and upper gate, respectively. See Fig. 3. When both the first and second gates of control transistor T11 are connected to the third scanning signal line Scan3, an increased on-state current and a reduced off-state current can be obtained. When the row-by-row scanning of the square wave signal reaches this row, the data voltage input through the data line Vdata can be loaded onto the light-emitting unit 212.

[0085] Please refer to Fig. 4. The scanning line includes a second scanning signal line Scan2. By simultaneously connecting the second scanning signal line Scan2 to the gate of the addressing transistor T7 in the signal amplification circuit 100 and the control transistor T11 in the pixel circuit 211, the number of scanning lines can be reduced without disturbing the signal amplification circuit 100 and the pixel circuit 211.

[0086] See Fig. 4, the light emitting unit 212 includes a liquid crystal light emitting unit and an organic light emitting diode light emitting unit.

[0087] See Fig. 4, the light emitting unit 212 includes a liquid crystal capacitor Clc and a storage capacitor Cst.

[0088] In the above embodiments, the descriptions of each embodiment have their own focus. For parts not detailed in one embodiment, please refer to the corresponding descriptions of other embodiments.

[0089] The above embodiments provide a detailed introduction to the display panel and the display device. This application uses specific examples to explain the principles and embodiments of the present application. The above embodiments are only for understanding the technical solutions and their core idea of ​​the present application. Those skilled in the relevant technical field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features with equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of this application.

Claims

[1] Signal amplification circuit, characterized by that it includes: a reset module, wherein an input end of the reset module is connected to an input signal end; a photoelectric device, wherein a first end of the photoelectric device is connected to an output end of the reset module, a second end of the photoelectric device is connected to the input signal end and the input end of the reset module; a positive feedback module, wherein a first end of the positive feedback module is connected to a first constant voltage signal end, a second end of the positive feedback module is connected to a second constant voltage signal end, wherein the positive feedback module comprises at least a first inverter, wherein the first inverter comprises a first load transistor, a first drive transistor, and a first output node, wherein the first load transistor is connected to the first drive transistor at the first output node within the first inverter, wherein the first output node is electrically connected to the output signal end, wherein a potential of the second constant voltage signal end is greater than that of the first constant voltage signal end; wherein the first inverter further comprises a first compensation transistor, wherein the first drive transistor comprises a first gate and a second gate, wherein the first gate of the first drive transistor is connected to the output end of the reset module, wherein a first electrode of the first compensation transistor is connected to the first output node, wherein a second electrode of the first compensation transistor is connected to the second gate of the first drive transistor. [2] Signal amplification circuit according to claim 1, characterized by that the first inverter further comprises a first storage capacitor, wherein a first electrode plate of the first storage capacitor is connected to the second gate of the first drive transistor, wherein a second electrode plate of the first storage capacitor is connected to the first constant voltage signal end. [3] Signal amplification circuit according to claim 1, characterized bythat the first load transistor comprises a first gate and a second gate, wherein the first gate of the first load transistor is connected to the first electrode of the first load transistor, the second gate of the first load transistor is connected to the first output node. [4] Signal amplification circuit according to claim 1, characterized bythat the positive feedback module further comprises a second inverter, wherein the second inverter comprises a second load transistor, a second drive transistor, a second compensation transistor and a second output node, wherein the gate of the second load transistor is connected to the second constant voltage signal end, wherein a first electrode of the second load transistor is connected to the second constant voltage signal end, wherein a second electrode of the second load transistor is connected to the first electrode of the second drive transistor at the second output node, wherein the gate of the first load transistor is connected to the second output node, wherein the second electrode of the second drive transistor is connected to the first constant voltage signal end; wherein the second drive transistor comprises a first gate and a second gate, wherein the first gate of the second drive transistor is connected to the first output node, wherein the first electrode of the second compensation transistor is connected to the second output node, wherein the second electrode of the second compensation transistor is connected to the second gate of the second drive transistor. [5] Signal amplification circuit according to one of claims 1 to 4, characterized by that the reset module comprises a reset transistor, wherein a first electrode of the reset transistor is connected to the input signal end, wherein a second electrode of the reset transistor is connected to the first end of the optoelectronic device, wherein the gate of the reset transistor is connected to a first scan signal line. [6] Signal amplification circuit according to claim 5, characterized byin that the signal amplification circuit further comprises a voltage follower comprising at least a third load transistor, a third drive transistor and a third output node, wherein the gate of the third drive transistor is connected to the first output node, wherein a first electrode of the third drive transistor is connected to the second constant voltage signal end, wherein a second electrode of the third drive transistor is connected to a first electrode of the third load transistor at the third output node, wherein the gate of the third load transistor is connected to a second scanning signal line, wherein a second electrode of the third load transistor is connected to the first constant voltage signal end. [7] Signal amplification circuit according to claim 6, characterized bythat the third drive transistor comprises a first gate and a second gate, wherein the first gate of the third drive transistor is connected to the first output node, wherein the second gate of the third drive transistor is connected to the third output node; wherein the third load transistor comprises a first gate and a second gate, wherein the first gate of the third load transistor is connected to the second scanning signal line, wherein the second gate of the third load transistor is connected to the first constant voltage signal end. [8] Signal amplification circuit according to claim 6, characterized byin that the signal amplification circuit further comprises an addressing module, wherein the addressing module comprises at least one addressing transistor, wherein a first electrode of the addressing transistor is connected to the third output node, wherein the gate of the addressing transistor is connected to a third scan signal line, wherein a second electrode of the addressing transistor is connected to the output signal end. [9] Signal amplification circuit according to claim 8, characterized by that the reset transistor comprises a first gate and a second gate, wherein the first gate of the reset transistor is connected to the first scanning signal line, wherein the second gate of the reset transistor is connected to a fourth scanning signal line; wherein the first compensation transistor comprises a first gate and a second gate, wherein the first gate of the first compensation transistor is connected to the first scanning signal line, wherein the second gate of the first compensation transistor is connected to the fourth scanning signal line; wherein the addressing transistor comprises a first gate and a second gate, wherein the first gate of the addressing transistor is connected to the third scan signal line, wherein the second gate of the addressing transistor is connected to the fourth scan signal line. [10] Display device, characterized by in that it comprises a plurality of pixel units, at least one of which comprises a signal amplification circuit according to any one of claims 1 to 9 and a pixel circuit.

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