Self-adjusting rear-facing contacts in CFETs and methods for their production

Abstract

A process comprises the following: creating a lower source / drain region above a substrate; creating a gate stack laterally to the lower source / drain region; creating an upper source / drain region above the lower source / drain region; performing a backside thinning process to thin the substrate and expose a sacrificial region; removing the sacrificial region to expose the lower source / drain region; and creating a backside contact pin for electrical connection to the lower source / drain region.

Description

Priority claim and cross-reference

[0001] The present application claims priority over the preliminary US patent application filed on September 27, 2024, with file number 63 / 699.911 and entitled “Self-aligned CFET BMD”, which is incorporated by reference into the present application. background

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0003] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed. Brief description of the drawings

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1 to 9 show representations of intermediate stages in the manufacture of complementary field-effect transistors (CFETs) and of backside interconnect structures according to some embodiments. The Fig. Figures 10 to 16 show representations of intermediate stages in the manufacture of CFETs and of back-side interconnection structures according to alternative embodiments. The Fig. Figures 17 to 20 show representations of intermediate stages in the manufacture of CFETs and of back-side interconnection structures according to alternative embodiments. Fig. Figure 21 shows a flowchart for manufacturing CFETs and back-side interconnect structures according to some embodiments. Detailed description

[0005] The disclosure below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] A complementary field-effect transistor (CFET), backside interconnect structures, and a method for fabricating them are provided. According to some embodiments, a CFET is fabricated from a front side of a wafer, and the backside interconnect structures are fabricated from a back side of the wafer. The fabrication of the backside interconnect structures comprises: pre-fabrication of sacrificial regions such that they are aligned with lower source / drain regions; removal of the sacrificial regions to expose lower source / drain regions; and fabrication of backside contact pins (also called backside contacts) in recesses left by the removed sacrificial regions. Pre-fabrication of the sacrificial regions allows the backside contact pins to be precisely aligned with the lower source / drain regions.This reduces the overlap displacement of the rear contact pins from the lower source / drain areas.

[0008] Although gate-all-around transistors (GAA transistors) (such as nanostructured FETs) are discussed, it is understood that the principle of the present disclosure can also be used for the fabrication of back-side contacts of CFETs made from other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), and the like. Throughout this description, the terms "FET" and "transistor" are used synonymously.

[0009] Fig. Figure 1 shows the fabrication of an exemplary CFET 10, which, according to some embodiments, comprises FETs (transistors) 10U and 10L. The corresponding process is specified as process 202 in process flow 200, which is described in Fig. Figure 21 shows that CFETs can have vertically stacked FETs. For example, CFET 10 can have a lower nanostructure FET 10L of a first device type (e.g., n / p) and an upper nanostructure FET 10U of a second device type (e.g., p / n) opposite to the first device type. The nanostructure FETs 10U and 10L have semiconductor nanostructures 26' (comprising lower semiconductor nanostructures 26'L and upper semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' acting as channel regions for the nanostructure FETs. The lower semiconductor nanostructures 26'L are designated for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26'U are designated for the upper nanostructure FET 10U.

[0010] As in Fig. As shown in Figure 1, a wafer 2 is provided, which has a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The SOI substrate may have a layer of semiconductor material deposited on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or a combination thereof.

[0011] In the example shown, the upper FET 10U and the lower FET 10L each contain two semiconductor layers 26'U and 26'L, respectively, as channels. It is understood that the upper FET 10U and the lower FET 10L can contain any number of channel regions, such as 1, 2, 3, or more. The portions of gate stacks 90 located above and / or below the channel regions 26 form multilayer stacks with corresponding channel regions 26'U and 26'L.

[0012] Gate stacks 90 are fabricated between the semiconductor layers 26, comprising upper gate stacks 90U and lower gate stacks 90L. The upper gate stacks 90U contain gate dielectrics 78 and upper gate electrodes 80U. The lower gate stacks 90L contain gate dielectrics 78 and lower gate electrodes 80L. In side views, the gate dielectrics 78 enclose the respective semiconductor nanostructures 26. The gate electrodes 80 (comprising the upper gate electrode 80U and the lower gate electrode 80L) are arranged above the gate dielectrics 78. Dielectric insulating layers 56 are fabricated to isolate the gate stack 90U of the upper FETs 10U from the gate stack 90L of the lower FETs 10L. Dummy semiconductor layers 26'M can be fabricated to contact the dielectric insulating layers 56.

[0013] Source / drain regions 62 (comprising lower source / drain regions 62L and upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. A source / drain region can, depending on the context, designate a source or a drain individually or collectively.

[0014] Internal spacers 54, which are dielectric spacers, are manufactured on opposite sides of parts of the gate stack 90 located between the semiconductor layers 26. The internal spacers 54 electrically isolate the source / drain regions 62L and 62U from the corresponding parts of the gate stack 90 to prevent or reduce leakage.

[0015] Gate spacers 44 are fabricated above the multilayer stacks and on the side walls of the gate stacks 90. The gate spacers 44 can be fabricated by conformal fabrication of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. Suitable dielectric materials can include silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbonitride, or the like, which can be fabricated by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0016] Source / drain epitaxy regions 62L and 62U are generated between the multilayer stacks containing the channel regions 26 and the gate stacks 90. The lower source / drain epitaxy regions 62L are generated above and in contact with a substrate comprising a semiconductor substrate 20 and sacrificial regions 102. The lower source / drain epitaxy regions 62L are also in contact with the lower semiconductor nanostructures 26'L, but they are not in contact with the upper semiconductor nanostructures 26'U.

[0017] The lower source / drain epitaxy regions 62L are grown epitaxially and have a conductivity type suitable for the device type (p or n) of the lower nanostructure FETs. If the lower source / drain epitaxy regions 62L are n-source / drain regions, the respective material can include silicon or carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. If the lower source / drain epitaxy regions 62L are p-source / drain regions, the respective material can include silicon or silicon germanium doped with a p-type dopant such as boron, indium, or the like. The lower source / drain epitaxy regions 62L can be doped in situ, and they may or may not be doped with the appropriate p- or n-type dopants.

[0018] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are fabricated over the lower source / drain epitaxy regions 62L. A suitable dielectric material for the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like. The first CESL 66 can be fabricated from a dielectric material exhibiting high etch selectivity with respect to the etching of the first ILD 68. For example, the first CESL 66 can contain silicon nitride, silicon oxide, silicon oxide nitride, or the like, which can be fabricated by a suitable deposition method such as CVD, ALD, or the like.

[0019] The upper source / drain epitaxy regions 62U are created to overlap the first CESL 66 and the first ILD 68, as well as the lower source / drain regions 62L. Depending on the desired conductivity type for the upper source / drain epitaxy regions 62U, the materials for these regions can be selected from the same group of suitable materials as those used to create the lower source / drain regions 62L.

[0020] The conductivity type of the upper source / drain epitaxy regions 62U can be opposite to the conductivity type of the lower source / drain regions 62L. In other words, the upper source / drain epitaxy regions 62U can be doped in the opposite way to the lower source / drain epitaxy regions 62L. The upper source / drain epitaxy regions 62U can be doped in situ, and / or they can be doped with an n-type or a p-type dopant.

[0021] A second CESL 70 and a second ILD 72 are fabricated above the upper source / drain epitaxy regions 62U. The materials and fabrication methods may be similar to, the same as, or different from those used for the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here.

[0022] Gate masks 92 are fabricated over the gate stacks 90. The fabrication process may include: recessing the gate stacks 90; filling the resulting recesses with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxide nitride, silicon oxide carbonitride, or the like; and performing a planarization process to remove excess dielectric material over the second ILD 72. Further dielectric layers (shown but not labeled), such as etch stop layers, interlayer dielectrics, or the like, may be fabricated over the gate masks 92 and the second ILD 72.

[0023] Silicidal regions 94 and source / drain contact pins 96U and 96L are provided for electrical connection to the upper source / drain region 62U and the lower source / drain region 62L, respectively. The contact pin 96L can penetrate the upper source / drain region 62U to reach the lower source / drain region 62L. Although not shown, in some embodiments the lower source / drain contact pin 96L can be enclosed by a dielectric coating. The source / drain contact pins 96L can thus be decoupled from the upper source / drain region 62U that they penetrate.

[0024] In alternative embodiments, no dielectric coating is produced to enclose the lower source / drain contact pin 96L. Accordingly, the lower source / drain contact pin 96L can still be electrically connected to the upper source / drain region 62U and can electrically connect the upper source / drain region 62U to the lower source / drain region 62L.

[0025] As also in Fig. As shown in Figure 1, 20 sacrificial regions 102 are created in the substrate, arranged below and overlapped by the lower source / drain regions 62L. In some embodiments, the sacrificial regions 102 contain semiconductor materials and may have sacrificial layers 102A and 102B, with the sacrificial layers 102B being arranged between the sacrificial layers 102A and above the lower source / drain regions 62L. The sacrificial regions 102 may also be in physical contact with the lower source / drain regions 62L.

[0026] In some embodiments, the creation of the sacrificial areas 102 is performed before the fabrication of higher-lying CFETs 10. The creation of the sacrificial areas 102 can be performed before or after the creation of STI areas (not shown; STI: shallow trench isolation), which are created beneath the CFETs and used to isolate adjacent CFETs from one another. The sacrificial areas 102 can also be created if the wafer 2 is an uncoated wafer.

[0027] In some embodiments, the production of the sacrificial regions 102 comprises etching the semiconductor substrate 20 to create recesses; and filling the recesses with one or more desired materials. In some embodiments, the sacrificial layers 102A contain silicon germanium, with the germanium atom content being approximately 10% to approximately 40%. The fabrication process may include epitaxy, and therefore the sacrificial layers 102A may have crystalline structures.

[0028] The sacrificial layers 102A may be left undoped with p-type dopants (such as boron, indium, or the like) or n-type dopants (such as phosphorus, arsenic, or the like). Alternatively, the sacrificial layers 102A can be doped in situ with a p-type or an n-type dopant, which can help to equalize the doping concentration of the well regions. Doping the sacrificial layers 102A can also prevent the doping concentrations of the well regions from being undesirably reduced due to diffusion into the sacrificial regions 102 during CFET fabrication.

[0029] Sacrificial layers 102B are produced above the sacrificial layers 102A. The sacrificial layers 102B contain a material that differs from the materials of the lower source / drain regions 62L and the materials of the sacrificial layers 102A. In some embodiments, the sacrificial layers 102B contain silicon but no germanium. The sacrificial layers 102B may also contain a dopant such as boron. In alternative embodiments, the sacrificial layers 102B contain silicon-germanium with a lower percentage of germanium atoms than the sacrificial layers 102A. The sacrificial layers 102B can also be produced by epitaxy and therefore also have a crystalline structure.

[0030] After the sacrificial layers 102B have been fabricated, a planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a machine grinding process, can be performed to level the top surfaces of the sacrificial layers 102B with the top surface of the substrate 20. The resulting structure, which includes the substrate 20 (which can be a semiconductor substrate) and the sacrificial areas 102, can also be referred to as a (composite) substrate.

[0031] In alternative embodiments, the sacrificial regions 102 can contain materials other than semiconductor materials. For example, the sacrificial regions 102 can be made of or contain dielectric materials. In some embodiments, the entire sacrificial region 102 can be made of a homogeneous dielectric material such as silicon nitride, silicon oxide, silicon oxide nitride, or the like. In alternative embodiments, the sacrificial regions 102 also contain more than one layer, such as sacrificial layers 102A and 102B. The corresponding sacrificial layers 102A and 102B can be made of different dielectric materials, selected from silicon nitride, silicon oxide, silicon oxide nitride, silicon oxide carbide, and the like.

[0032] In further alternative embodiments, the sacrificial layers 102B are made of a different type of material than the sacrificial layers 102A. For example, the sacrificial layers 102A can be made of a semiconductor material different from the material of the substrate 20, and the sacrificial layers 102B can be made of a dielectric material so that they can act as an effective etch stop layer during the subsequent removal of the sacrificial layers 102A.

[0033] In some embodiments, the sacrificial areas 102 are created directly beneath the depicted lower source / drain area 62L. In alternative embodiments, a sacrificial layer 102A is created directly beneath the source / drain area 62L and overlapped by it. However, no sacrificial area 102 is created in a dashed area 104. In other words, no sacrificial area 102 is created directly beneath and adjacent to the lower source / drain area 62L, which has already been electrically connected to the source / drain contact 96L. Since the lower source / drain area 62L has already been electrically connected from the front, no rear contact pin needs to be created in the dashed area 104.

[0034] In some embodiments, the widths of the sacrificial regions 102 can be greater than the widths of the corresponding higher-lying lower source / drain regions 62L. The sacrificial regions 102 can thus extend beyond the corresponding edges of the lower source / drain regions 62L, as shown in Fig. 1 is shown in an example.

[0035] In alternative embodiments, the widths of the sacrificial areas 102 are equal to the widths of the lower source / drain areas 62L. Edges 102E1 of the sacrificial areas 102 can be oriented vertically to the corresponding edges of the corresponding higher-lying lower source / drain areas 62L. In still further alternative embodiments, the widths of the sacrificial areas 102 are smaller than the widths of the lower source / drain areas 62L, and edges 102E2 of the sacrificial areas 102 can be recessed laterally from the corresponding edges of the lower source / drain areas 62L.

[0036] Since the sacrificial areas 102 can be created by etching the substrate 20 and subsequently filling it, they can have an upper width W1 and a lower width W2 that is smaller than the upper width W1. The edges of the sacrificial areas 102 can therefore be straight or inclined.

[0037] In Fig. In step 2, the wafer 2 is turned over. To remove some parts of the substrate 20, a back-side thinning process, such as a CMP process or a machine grinding process, is performed. The corresponding process is specified as process 204 in process sequence 200, which is described in Fig. 21 is shown. This exposes the victim areas 102.

[0038] As in Fig. As shown in Figure 3, the substrate 20 is then removed by an etching process. The corresponding process is specified as process 206 in process sequence 200, which is shown in Fig. Figure 21 shows that after the etching process, the internal spacers 54 and the gate dielectrics 78 are exposed. The etching process is selective so that the substrate 20 is removed while the sacrificial areas 102 are not removed. The etching process is also selective so that the internal spacers 54 and the gate dielectrics 78 are not damaged.

[0039] Fig. Figure 4 shows the fabrication of a dielectric layer 106, which is also referred to as a dielectric substrate 106. The corresponding process is specified as process 208 in process sequence 200, which is described in Fig. Figure 21 shows that the fabrication process involves depositing a dielectric material until the sacrificial regions 102 are completely embedded in the dielectric material, with substantially all surfaces of the dielectric material being higher than the top surfaces of the sacrificial regions 102. In some embodiments, the dielectric layer 106 comprises silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbide, silicon oxide carbonitride, or the like. The deposition process can be carried out by ALD, CVD, plasma-enhanced CVD (PECVD), or the like.

[0040] Then a planarization process, such as a CMP process or a machine grinding process, is performed to remove the portions of the dielectric material above the sacrificial regions 102. This re-exposes the top surfaces of the sacrificial regions 102. The remaining dielectric material thus forms the dielectric layer 106.

[0041] Fig. Figure 5 shows an etching process 108 for removing the sacrificial layers 102A and for creating contact openings 110. The corresponding process is specified as a process 210 in the process sequence 200, which is described in Fig. Figure 21 shows that the etching process 108 can be carried out using a dry etching process, which can be isotropic or anisotropic. This creates contact openings 110 in the dielectric layer 106. The etching process can also be carried out using a wet etching process. The etching chemical (a gas or a wet etching solution) is selected such that it attacks the sacrificial layers 102A but not the dielectric layer 106. The etching rate of the sacrificial layers 102B is also lower than the etching rate of the sacrificial layers 102A. Accordingly, the sacrificial layers 102B are used as etch-stop layers to terminate the etching process 108.

[0042] In Fig. 6. An etching process 112 is carried out to remove the sacrificial layers 102B, thereby exposing the deeper lower source / drain areas 62L. The corresponding process is specified as a process 212 in the process flow 200, which is described in Fig. Figure 21 shows that the etching process 112 can be a dry etching process, which can be isotropic. Alternatively, the etching process 112 can be a wet etching process.

[0043] As in Fig. As shown in Figure 6, the openings 110 can have a lower width W1' and an upper width W2'. Since the lower width W1' and the upper width W2' differ from the upper width W1 ( Fig. 1) and the lower width W2 are determined (and can be equal to these), the upper width W2' can be smaller than the lower width W1'. The edges of the dielectric layer 106, which point towards the openings 110, can also be straight and inclined.

[0044] In embodiments where the dashed area 104 does not contain a sacrificial area 102, the opening 110 in the dashed area 104 is also Fig. 6 is not generated. Instead, the dashed area 104 contains the dielectric layer 106, which covers the respective deeper source / drain area 62L.

[0045] In Fig. 7. Dielectric contact spacers 116 are manufactured in the contact openings 110 and on the side walls of the dielectric layer 106. The corresponding process is specified as process 214 in process sequence 200, which is described in Fig. Figure 21 shows that in some embodiments, the fabrication of the dielectric contact spacers 116 involves a conformal deposition process such as CVD or ALD to produce a conformal dielectric layer. The material of the dielectric contact spacers 116 can include silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbonitride, or the like. The dielectric contact spacers 116 can also have a dielectric constant (k-value) greater than 3.9, thus providing good insulating properties. Suitable materials include Al x O y , HfO2 or the like. The thickness of the dielectric contact spacers 116 can, for example, be approximately 2 nm to approximately 6 nm.

[0046] After deposition of the conformal dielectric layer, an anisotropic etching process is performed to remove the horizontal parts of the conformal dielectric layer, while the vertical parts of the conformal dielectric layer remain in the contact openings 110 to form the dielectric contact spacers 116. When viewed from the top of the wafer 2, the dielectric contact spacers 116 can form rings that enclose the contact openings 110.

[0047] Depending on the widths of the sacrificial areas 102 discussed above, the undersides of the dielectric contact spacers 116 can contact one or more of various possible areas (materials). In some embodiments, the undersides of the dielectric contact spacers 116 contact the tops of the internal spacers 54, and they may or may not contact the tops of the lower source / drain areas 62L. Due to a precise alignment of subsequently manufactured rear contact pins 122 ( Fig. 8) The width of the rear contact pins can be increased for the lower source / drain areas without the risk of overlap displacement problems. The widths of the contact openings 110 can be larger than, equal to, or smaller than the corresponding widths of the lower source / drain areas 62L.

[0048] In some embodiments, the undersides of the dielectric contact spacers 116 contact the tops of the lower source / drain regions, but they are not in contact with the tops of the inner spacers 54. The widths of the contact openings 110 can therefore be smaller than the corresponding widths of the lower source / drain regions 62L.

[0049] In Fig. 8. Silicide layers 120 are produced on the upper surfaces of the lower source / drain areas 62L. The corresponding process is specified as process 216 in process flow 200, which is in Fig. Figure 21 shows the manufacturing process. The process may involve the deposition of a metal layer (not shown), for example, using a conformal deposition process such as physical vapor deposition (PVD). A barrier layer (not shown), which may be a metal nitride layer such as titanium nitride or tantalum nitride, is then deposited over the metal layer. Subsequently, an annealing process is carried out to react the metal layer with the silicon (and germanium, if present) in the lower source / drain regions 62L. This results in source / drain silicide layers 120. The annealing process may be carried out by rapid thermal annealing (RTA), furnace annealing, or the like.

[0050] In some embodiments, which are in the Fig. 5, Fig. 6 and Fig. As shown in Figure 8, the sacrificial layers 102B are removed, and silicide layers 120 are produced by reacting a metal with the lower source / drain regions 62L. In alternative embodiments, the sacrificial layers 102B are not removed but remain in the structures shown in the Fig. 6 and Fig. 7 are shown. Thus, the ones in the Fig. 8 and Fig. The silicide layers 120 shown in Figure 9 are produced by reacting a metal with the sacrificial layers 102B (and optionally also with the lower source / drain areas 62L), which can be silicon layers.

[0051] The barrier layer and the remaining metal layer can then be removed. Next, rear contact pins 122 are fabricated to fill the opening 110 and establish an electrical connection with the silicide layers 120. The corresponding process is specified as process 218 in process flow 200, which is described in Fig. Figure 21 shows that in some embodiments, the fabrication of the rear contact pins 122 may include the production of a barrier layer, which may contain titanium nitride, tantalum nitride, or the like. A metallic material is then deposited over and in contact with the barrier layer. The metallic material may include tungsten, cobalt, or the like. Subsequently, a planarization process, such as a CMP process or a machine grinding process, is performed to remove excess portions of the barrier layer and the metallic material, leaving the rear contact pins 122.

[0052] In Fig. In step 9, an etch stop layer 124 and a dielectric layer 126 are produced. The corresponding process is specified as process 220 in process sequence 200, which is described in Fig. Figure 21 shows that the etch stop layer 124 can contain AlN, AlO, SiOC, or the like, or multiple layers thereof. The dielectric layer 126 can contain silicon oxide, silicon nitride, silicon oxide nitride, silicon carbide, or the like.

[0053] Subsequently, a conductive structural element 130, such as a metal conductor or a metal via, is brought into contact with the rear contact pin 122. The corresponding process is specified as process 222 in process sequence 200, which is described in Fig. Figure 21 shows that in some embodiments a dielectric coating 128 can be produced such that it surrounds the conductive structural element 130. In alternative embodiments the dielectric coating 128 is not produced.

[0054] In some embodiments, the conductive structural element 130 is made from a homogeneous conductive material, such as tungsten, cobalt, aluminum, or the like. In alternative embodiments, the conductive structural element 130 has a conductive barrier layer and a conductive region above the conductive barrier layer. The conductive barrier layer may contain Ti, TiN, Ta, TaN, or the like. The conductive barrier layer may contain copper. The manufacturing process for the conductive structural element 130 may include a Damascene process.

[0055] It is understood that the rear contact pin 122 in the dashed area 104 cannot be used to conduct current. Since the lower source / drain area 62L is on the left side of Fig. 9 is electrically connected to the source / drain contact pin 96L, the current passing through the lower transistor 10L on the left side of Fig. Current 9 flows through the source / drain contact pin 96L. The rear contact pin 122 in the dashed area 104 can have the same voltage as the respective lower source / drain area 62L. The currents flowing through the lower source / drain area 62L on the left side of Fig. 9 flow, but do not flow through the rear contact pin 122 in the dashed area 104.

[0056] In some embodiments, the entire top surface of the rear contact pin 122 in the dashed area 104 is in contact with the etch stop layer 124, and here too, no currents can flow through the respective rear contact pin 122. In other words, the rear contact pin 122 in the dashed area 104 is a terminal element for currents and voltages, at which the currents and voltages terminate.

[0057] In alternative embodiments, the rear contact pin 122 remains connected to the rear metal conductors (not shown) in the dashed area 104. Accordingly, the rear contact pin 122 is electrically connected to the contact pin 96L in the dashed area 104, and currents can flow between the rear contact pin 122 and the contact pin 96L, with the lower source / drain area 62L acting as a connecting element.

[0058] In some embodiments, the lower width W1" of the rear contact pin 122 can be greater than, equal to, or less than the upper width W3 of the lower source / drain regions 62L. The outer width W4 of the combined structural elements comprising the dielectric contact spacer 116 and the rear contact pin 122 can also be greater than, equal to, or less than the upper width W3 of the lower source / drain regions 62L. Since the rear contact pins 122 are based on the sacrificial regions 102 ( Fig. 1) can be manufactured, the upper width W2" of the rear contact pins 122 can be less than or equal to the lower width W1" of the rear contact pins 122.

[0059] In alternative embodiments, where there is no contact opening 110 in the area 104 ( Fig. 6) is generated, no silicide layer 120 and no rear contact pin 122 are produced in the dashed area 104. Accordingly, the dielectric layer 106 is in physical contact with the top surface of the lower source / drain area 62L to form an interface. The electrical connection with the lower source / drain area 62L is also made via the source / drain contact pin 96L.

[0060] The rear contact pins 122 are self-aligned by the sacrificial areas 102, which are precisely vertically aligned with the lower source / drain areas 62L. Accordingly, the rear contact pins 122 are aligned with the lower source / drain areas 62L, regardless of overlap displacement or misalignment. Furthermore, it is possible to manufacture wider rear contact pins 122 without the risk of misalignment (which would cause an electrical short circuit between the lower source / drain areas 62L and metal gates). The rear contact pin 122 can thus be manufactured to extend laterally beyond opposite edges of the respective lower source / drain areas 62L.However, if the rear contact pins 122 are not manufactured using the self-adjusting process according to the embodiments of the present disclosure, the lower width W1" of the rear contact pins 122 would have to be manufactured smaller than the upper width W3 of the lower source / drain areas 62L in order to allow for some process margin for process variations and overlap displacement.

[0061] The Fig. Figures 10 to 16 show a manufacture of the rear contact pins according to alternative embodiments of the present disclosure. These embodiments are the ones described in the Fig. The embodiments shown in Figures 1 to 9 are similar, except that two rear contact pins are manufactured in separate processes and can therefore extend to different heights. Unless otherwise specified, the materials, structures, and manufacturing processes for the components in these embodiments (and other embodiments throughout the description) are essentially the same as those of similar components designated by similar reference numerals in the preceding embodiments. The details of the materials, structures, and manufacturing processes given in each embodiment throughout the description may, where appropriate, also apply to any other embodiment.

[0062] The initial processes of these embodiments are essentially the same as those described in the Fig. 1 to 4 are shown. As in Fig. As shown in Figure 10, an etching mask 134 is then produced and textured. The etching mask 134 may have a textured photoresist, and it may or may not contain hard masks. The etching mask 134 covers the sacrificial area 102 on the left side of Figure 10. Fig. 10 and leaves some other victim areas 102, such as victim area 102 on the right side of Fig. 4, uncovered.

[0063] As in Fig. As shown in 10, an etching process 108 is then carried out to remove the right sacrificial layer 102A (which is in Fig. (as shown in section 4) is removed, thereby exposing the deeper sacrificial layer 102B, which acts as an etch stop layer. This creates a contact opening 110. This exposes the sacrificial layer 102B. Subsequently, the etch mask 134 is removed. During the removal of the etch mask 134, the sacrificial layer 102B protects the deeper lower source / drain area 62L.

[0064] Fig. Figure 11 shows an etching process 112 which removes the sacrificial layer 102B, thereby exposing the deeper lower source / drain region 62L, which also acts as an etch stop layer due to the difference between the materials of the sacrificial layer 102B and the lower source / drain region 62L.

[0065] As in Fig. As shown in Figure 12, a dielectric contact spacer 116 is then manufactured, which includes performing a conformal deposition process to deposit a dielectric layer and etching the dielectric layer with an anisotropic etching process.

[0066] Fig. Figure 13 shows the fabrication of a silicide layer 120 (also referred to as a silicide layer 120A) and a rear contact pin 122 (also referred to as a rear contact pin 122A). The materials, structures, and fabrication processes have been discussed in the preceding embodiments and are not repeated here.

[0067] In Fig. 14. An etch stop layer 124 and a dielectric layer 126 are then deposited. As in Fig. As shown in Figure 15, a contact opening 110' is subsequently created by one or more etching processes 113. The contact opening 110' has parts in the dielectric layer 126 and the etch stop layer 124, such that the deeper sacrificial area 102 ( Fig. 14) is exposed. Then the exposed sacrificial layer 102A is removed, and subsequently an etching process is carried out to remove the sacrificial layer 102B, thereby exposing the lower source / drain region 62L. The etching of the sacrificial region 102 can be carried out using the etch stop layer 124, the sacrificial layer 102A, and the sacrificial layer 102B as etch stop layers in a sequence of etching processes.

[0068] In a subsequent process, which took place in Fig. As shown in Figure 16, a silicide layer 120 (also referred to as a silicide layer 120B) is produced on the top surface of the lower source / drain region 62L. Additionally, a backside contact pin 122 (also referred to as a backside contact pin 122B) is produced. The silicide layers 120A and 120B are referred to individually and collectively as silicide layers 120. The backside contact pins 122A and 122B are referred to individually and collectively as backside contact pins 122.

[0069] In some embodiments, the lower width W1" of the rear contact pin 122, the upper width W2" of the rear contact pins 122, the upper width W3 of the lower source / drain regions 62L, and the outer width W4 of the combined structural elements comprising the dielectric contact spacer 116 and the rear contact pin 122 can have the relationship described with reference to Fig. 9 has been discussed.

[0070] The Fig. Figures 17 to 20 show the manufacture of rear contact pins according to further alternative embodiments of the present disclosure. These embodiments are the ones described in the Fig. The embodiments shown in Figures 10 to 16 are similar, except that the rear contact pin is manufactured in a dual damascene structure which also includes metal conductors for horizontal routing.

[0071] The initial processes of these embodiments are essentially the same as those described in the Fig. Figures 1 to 4 are shown. The resulting structure is in Fig. Figure 17 shows that an etching mask 134 is then produced and structured, and an opening 136 is created in the etching mask 134. The opening 136 extends laterally in opposite directions beyond the edges of the deeper sacrificial area 102.

[0072] As in Fig. As shown in Figure 18, the dielectric layer 126 is then etched, and the etching is terminated on the etch stop layer 124. The etching is anisotropic. Subsequently, the etch stop layer 124 is etched to expose the underlying sacrificial layer 102A, whereby the etching can be anisotropic or isotropic.

[0073] In some embodiments, the etching mask 134 is removed, and then the sacrificial layer 102A is etched to create a contact opening 110. The resulting structure is in Fig. Figure 19 shows that in alternative embodiments, the etching mask 134 is removed after the removal of the sacrificial layer 102A and before the removal of the sacrificial layer 102B. During the removal of the etching mask 134, the sacrificial layer 102A or the sacrificial layer 102B protects the lower source / drain region 62L from damage.

[0074] In Fig. In the 20th embodiment, a metal conductor 142 and a via 144 are produced. The via 144 also functions as the rear contact pin. In some embodiments, the metal conductor 142 and the via 144 have a barrier layer 146 and a metallic material 148 over the barrier layer 146. The barrier layer 146 contains Ti, TiN, Ta, TaN, or the like. The metallic material 148 can contain copper or other materials, such as tungsten, cobalt, or the like.

[0075] In some embodiments, the lower width W1" of the rear contact pin 122, the upper width W2" of the rear contact pins 122, the upper width W3 of the lower source / drain regions 62L, and the outer width W4 of the combined structural elements comprising the dielectric contact spacer 116 and the rear contact pin 122 can have the relationship described with reference to Fig. 9 has been discussed. The relationship of the relative values ​​can also apply to the via 144 and the rear contact pin 122.

[0076] In the embodiments described in the Fig. 10 to 20 are shown, the victim layers 102B ( Fig. 10, Fig. 14 and Fig. 18) also be removed (or not), so that the remaining sacrificial layers 102B can be used to produce the silicide layers 120.

[0077] The embodiments of the present disclosure have several advantages. By pre-generating sacrificial regions in a substrate and generating lower source / drain regions such that they are positioned above the sacrificial regions and vertically aligned with them, the rear contact pins can be manufactured in a self-aligned manner with respect to the sacrificial regions and thus be vertically aligned with the lower source / drain regions. This ensures precise alignment and avoids problems such as source / drain metal gate short circuits or leakage. Replacing the semiconductor substrate with a dielectric layer also eliminates the detrimental leakage from the rear contact pin to the substrate.

[0078] According to some embodiments of the present disclosure, a method comprises the following: creating a lower source / drain region above a substrate; creating a gate stack laterally to the lower source / drain region; creating an upper source / drain region above the lower source / drain region; performing a backside thinning process to thin the substrate and expose a sacrificial region; removing the sacrificial region to expose the lower source / drain region; and creating a backside contact pin for electrical connection to the lower source / drain region. In one embodiment, removing the sacrificial region includes removing a semiconductor region.

[0079] In one embodiment, removing the semiconductor region includes removing a silicon-germanium layer. In another embodiment, removing the sacrificial region further includes etching a silicon layer after removing the semiconductor region. In another embodiment, removing the sacrificial region includes isotropic etching processes. In another embodiment, the process, after the backside thinning process and before removing the sacrificial region, further includes removing a semiconductor substrate and fabricating a dielectric substrate to embed the sacrificial region therein.

[0080] In one embodiment, the sacrificial area is removed from the dielectric substrate. In another embodiment, the method further comprises fabricating a dielectric contact spacer prior to fabricating the backside contact pin, wherein the backside contact pin is enclosed by the dielectric contact spacer. In another embodiment, the gate stack has a lower portion laterally adjacent to and in contact with an internal spacer, wherein the dielectric contact spacer contacts the internal spacer to form an interface. In yet another embodiment, the backside contact pin extends laterally beyond an edge of the lower source / drain region.

[0081] According to some embodiments of the present disclosure, a method comprises the following: creating a sacrificial region in a semiconductor substrate; fabricating a lower transistor having a lower source / drain region arranged above and contacting the sacrificial region, a gate stack, and a dielectric spacer between the gate stack and the lower source / drain region; fabricating an upper transistor having an upper source / drain region, the upper source / drain region overlapping the lower source / drain region; fabricating a front-side contact pin above and in electrical contact with the upper source / drain region; thinning the semiconductor substrate to expose the sacrificial region; replacing the semiconductor substrate with a dielectric substrate; and removing the sacrificial region to create a recess in the dielectric substrate.and creating a rear contact pin in the recess for electrical connection to the lower source / drain area.

[0082] In one embodiment, the method further comprises fabricating a dielectric contact spacer in the recess, wherein the rear contact pin is enclosed by the dielectric contact spacer. In one embodiment, the dielectric contact spacer is in contact with the dielectric inner spacer. In one embodiment, the rear contact pin physically contacts the dielectric inner spacer. In one embodiment, part of the rear contact pin forms an interface with the dielectric inner spacer. In one embodiment, the method further comprises fabricating a silicide layer, wherein the silicide layer is positioned between the rear contact pin and the lower source / drain region.

[0083] According to some embodiments of the present disclosure, a method comprises the following: generating a lower source / drain region over a semiconductor substrate; generating a dielectric region over and in contact with the lower source / drain region; generating an upper source / drain region over and in contact with the dielectric region; thinning the semiconductor substrate from the back side to expose a sacrificial region; replacing the semiconductor substrate with a dielectric substrate; performing an isotropic etching process to remove the sacrificial region; and producing a backside contact pin in a free space left by the isotropic etching process.

[0084] In one embodiment, the isotropic etching process comprises etching a first semiconductor layer in a first etching process. In another embodiment, the isotropic etching process further comprises etching a second semiconductor layer in a second etching process to expose the lower source / drain region. In one embodiment, the sacrificial region contains a crystalline semiconductor material.

[0085] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure.

Claims

[1] Procedure, encompassing: Creating a lower source / drain area above a substrate; Creating a gate stack to the side of the lower source / drain area; Creating an upper source / drain area above the lower source / drain area; Performing a back-thinning process to thin the substrate and expose a sacrificial area; Removing the sacrificial area to expose the lower source / drain area; and Creating a rear contact pin for electrical connection to the lower source / drain area. [2] Method according to claim 1, wherein the removal of the sacrificial area comprises the removal of a semiconductor area. [3] Method according to claim 1 or 2, wherein the removal of the semiconductor area comprises the removal of a silicon germanium layer. [4] Method according to claim 2 or 3, wherein the removal of the sacrificial area after the removal of the semiconductor area further comprises etching a silicon layer. [5] Method according to any of the preceding claims, wherein the removal of the sacrificial area comprises isotropic etching processes. [6] A method according to any of the preceding claims, further comprising: After the backside thinning process and before the removal of the sacrificial area, removal of a semiconductor substrate; and Creating a dielectric substrate to embed the sacrificial area within it. [7] Method according to any of the preceding claims, wherein the sacrificial area is removed from the dielectric substrate. [8] A method according to any of the preceding claims, further comprising: Prior to manufacturing the rear contact pin, manufacture a dielectric contact spacer, wherein the rear contact pin is enclosed by the dielectric contact spacer. [9] Method according to claim 8, wherein the gate stack has a lower part laterally adjacent to and in contact with an internal spacer, and The dielectric contact spacer contacts the inner spacer to form an interface. [10] Method according to any of the preceding claims, wherein the rear contact pin extends laterally beyond an edge of the lower source / drain area. [11] Procedure, encompassing: Creating a lower source / drain region over a semiconductor substrate; Creating a dielectric region above and in contact with the lower source / drain region; Creating an upper source / drain region above and in contact with the dielectric region; Thinning of the semiconductor substrate from a back side to expose a sacrificial area; Replacing the semiconductor substrate with a dielectric substrate; Performing an isotropic etching process to remove the sacrificial area; and Creating a rear contact pin in an empty space left by the isotropic etching process. [12] Method according to claim 11, wherein the isotropic etching process comprises etching a first semiconductor layer in a first etching process. [13] Method according to claim 12, wherein the isotropic etching process further comprises etching a second semiconductor layer in a second etching process to expose the lower source / drain region. [14] Method according to any one of claims 11 to 13, wherein the sacrificial region contains a crystalline semiconductor material. [15] Device with: a lower transistor which has the following features: a lower source / drain area, a gate stack, and a dielectric internal spacer between the gate stack and the lower source / drain area; an upper transistor having an upper source / drain region, wherein the upper source / drain region overlaps the lower source / drain region; a front-facing contact pin above and in electrical connection with the upper source / drain area; and a rear contact pin located below and in electrical connection with the lower source / drain region, wherein the rear contact pin has a first width measured at a first height and a second width measured at a second height, the first height being closer to the lower source / drain region than the second height and the first width being greater than the second width. [16] Device according to claim 15, further comprising a dielectric contact spacer that surrounds and contacts the rear contact pin. [17] Device according to claim 15 or 16, wherein the dielectric contact spacer is in contact with the dielectric inner spacer. [18] Device according to any one of claims 15 to 17, wherein the rear contact pin physically contacts the dielectric internal spacer. [19] Device according to one of claims 15 to 18, wherein a part of the rear contact pin forms an interface with the dielectric internal spacer. [20] Device according to one of claims 15 to 19, further comprising a silicide layer, wherein the silicide layer is arranged between the rear contact pin and the lower source / drain area.

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