TRANSISTOR ASSEMBLY WITH TEMPERATURE SENSOR CIRCUIT

Abstract

A transistor assembly comprises a transistor device and a temperature sensing circuit. The temperature sensing circuit is thermally coupled to the transistor device. The temperature sensing circuit includes a temperature sensing resistor. The temperature sensing resistor comprises an insulator-to-metal junction (IMT) material or a metal-to-insulator junction (MIT) material.

Description

TECHNICAL AREA

[0001] This disclosure relates generally to a transistor arrangement. BACKGROUND

[0002] Transistor devices, such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), are widely used as electronic switches in various types of electronic applications. During operation, a transistor device can generate significant heat resulting from the power inevitably dissipated within the device.

[0003] DE 10 2011 007 271 A1 discloses a variable-gate field-effect transistor (FET) designed to suppress a reduction in current between a source and a drain due to heat while the temperature of the FET decreases, and an electrical and electronic device containing the variable-gate FET. The variable-gate FET comprises a FET and a gate control device attached to a surface or heat-generating section of the FET and connected to a gate terminal of the FET to change the voltage at the gate terminal. The gate control device, which changes the voltage at the gate terminal when the temperature of the FET increases above a predetermined temperature, controls the channel current between the source and the drain.

[0004] KR 10 2016 092 336 A discloses an electronic device comprising: a power MOS element; a gate input resistor element installed in a gate line connected to the power MOS element; and a temperature-variable resistor element connected to the gate line between the gate input resistor element and the power MOS element, wherein the temperature-variable resistor element reduces a voltage applied to a gate of the power MOS element to less than an operating voltage of the power MOS element when the power MOS element overheats, thereby blocking the operation of the power MOS element.

[0005] EP 4 213 607 A1 discloses a semiconductor device comprising a semiconductor body, a first electrode, a gate electrode, and a variable resistance element. The variable resistance element is electrically connected to the gate electrode and the first electrode. The variable resistance element has at least a first and a second state. In the first state, the variable resistance element acts as an electrical insulator to prevent electric current from flowing through the variable resistance element from the first electrode to the gate electrode or vice versa. In the second state, the variable resistance element acts as an electrical conductor, allowing electric current to flow through the variable resistance element from the first electrode to the gate electrode or vice versa.The variable resistance element is configured to transition from the first state to the second state when the temperature of the variable resistance element rises above a critical temperature Tc.

[0006] US 2020 / 0312792 A1 discloses a semiconductor chip comprising a functional area, a first end, a second end, a third end, and a connection section. The functional area has a first and a second side, which are opposite each other. The first end is located on the first side, and the third end is also located on the first side. The semiconductor chip is turned on or off according to the control signal received between the third end and the first end. The connection section is located on the first side of the functional area and is connected to the first and third ends. The connection section is in a conducting state when the temperature rises above a first temperature, and the connection section is in an insulating state when the temperature falls below a third temperature.

[0007] KR 10 2020 071 534 A discloses a field-effect transistor based on insulator-metal junction elements. SUMMARY

[0008] It is therefore the task for the person skilled in the art to provide an improved MOSFET that incorporates an insulator-to-metal transition material.

[0009] This problem is solved by the subject matter of independent claims.

[0010] Preferred embodiments are given by the dependent claims.

[0011] A thermal protection circuit can be used to protect a transistor device from overheating. The thermal protection can include a temperature sensor configured to monitor the temperature of the transistor device and provide a temperature sensing signal, and an evaluation circuit configured to detect the temperature based on the temperature sensing signal and take appropriate action when the detected temperature reaches a predefined temperature threshold. The appropriate action can include activating cooling systems, reducing the current through the transistor device, or switching off the transistor device. The temperature sensor could, for example, be a PN diode exhibiting a forward voltage that depends on the temperature.

[0012] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Further examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are depicted. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 schematically illustrates an example of a transistor arrangement that includes a transistor device and a temperature sensing circuit; Fig. Figure 2 illustrates the temperature dependence of the specific resistance of an IMT material according to an example; Fig. Figure 3 shows a circuit diagram of a transistor arrangement with a temperature sensing resistor incorporating an IMT material and connected between a first and a second node of a transistor device; Fig. Figure 4 schematically illustrates a transistor arrangement comprising a vertical transistor device and a temperature sensing resistor comprising an IMT material connected between a gate pad and a source pad of the vertical transistor device; Fig. 5- Fig. Figure 11 schematically illustrates various examples of implementing the temperature sensing resistor in an arrangement of the in Fig. 4 illustrated types; Fig. 12A- Fig. Figure 12E schematically illustrates a transistor arrangement comprising a vertical transistor device with a plurality of transistor cells, each comprising a gate electrode and a field electrode arranged in a respective trench, and IMT material layers arranged between the gate electrode and the field electrode of the transistor cells; Fig. Figure 13 illustrates a modification of the transistor arrangement according to Fig. 12A- Fig. 12D; Fig. Figure 14 illustrates a further modification of the transistor arrangement according to Fig. 12A- Fig. 12D; Fig. 15A- Fig. Figure 15D schematically illustrates a transistor arrangement comprising a vertical transistor device with gate and source vias extending through an insulating layer and an IMT layer arranged in the insulating layer and connected to the gate and source vias; Fig. Figure 16 illustrates a modification of the transistor arrangement according to Fig. 15A- Fig. 15D; Fig. Figure 17 illustrates a further modification of the transistor arrangement according to Fig. 15A- Fig. 15D; Fig. 18- Fig. Figure 19 illustrates further examples of a transistor arrangement of the in Fig. 15A- Fig. 15D illustrated type; Fig. Figure 20 shows a circuit diagram of a transistor arrangement with a temperature sensing resistor connected between an external gate node and an internal gate node of a transistor device; Fig. Figure 21 schematically illustrates an example of an implementation of a transistor arrangement of the in Fig. 20 illustrated types; Fig. Figure 22 illustrates a transistor arrangement comprising a first transistor device and a second transistor device connected in parallel, and a temperature sensing resistor connected between a gate node and a source node of the first transistor device; Fig. 23 illustrates a modification of the transistor arrangement according to Fig. 22; Fig. Figure 24 illustrates a transistor arrangement comprising a first transistor device, a second transistor device, and a temperature sensing resistor connected between the source nodes; Fig. Figure 25 schematically illustrates an example of an implementation of a transistor arrangement of the in Fig. 24 illustrated types; Fig. 26-29 illustrate examples of transistor arrangements that include a transistor device and a temperature sensing circuit with multiple temperature sensing resistors, configured to be connected to an evaluation circuit; and Fig. Figure 30 illustrates a transistor arrangement comprising a transistor device, a temperature sensing circuit, an evaluation circuit and a control circuit configured to control the transistor device and receive a temperature signal from the evaluation circuit.

[0014] The following detailed description refers to the accompanying drawings. The drawings form part of the description and show examples of how the invention can be used and implemented. It is understood that the features of the various embodiments described herein can be combined unless expressly stated otherwise. DETAILED DESCRIPTION

[0015] Fig. Figure 1 schematically illustrates a transistor arrangement according to an example. The transistor arrangement comprises a transistor device 1 and a resistor 21 (hereinafter also referred to as the temperature sensing resistor). In some examples, the transistor arrangement comprises a transistor device 1 and a temperature sensing circuit 2, which is thermally coupled to the transistor device 1 and includes a temperature sensing resistor 21. The temperature sensing resistor 21 comprises one of an IMT (insulator-to-metal) material or a MIT (metal-to-insulator) material. In some examples, the resistor 21 is thermally and electrically coupled to the transistor device 1.

[0016] An IMT material is a material with a specific resistance that decreases rapidly as its temperature rises and reaches a predefined first temperature threshold. The absolute value of this first temperature threshold depends, among other things, on the specific type of IMT material. Various examples of IMT materials are explained below.

[0017] For illustrative purposes, illustrated Fig. 2. The dependence of the specific resistance on the temperature of an IMT material according to an example. In the Fig. The second illustrated example is the IMT material vanadium dioxide (VO2). As shown in the diagram, Fig. As can be seen in Figure 2, the specific resistance of the IMT material decreases rapidly as the temperature rises and reaches an initial temperature threshold. In the Fig. In the illustrated example 2, the decrease in specific resistance is more than four orders of magnitude and the first temperature threshold is approximately 75 °C.

[0018] The decreasing resistivity of an IMT material is reversible. That is, if the temperature reaches values ​​higher than the first temperature threshold and then decreases, the resistivity increases rapidly when the temperature reaches a second temperature threshold. For example, the first and second temperature thresholds differ, with the second being lower than the first (as in...). Fig. (2 illustrated), resulting in hysteresis in the resistance-temperature curve. The temperature difference between the two threshold values ​​depends on the type of IMT material. For example, with VO2 as the IMT material, the temperature difference lies in a range between 2 °C and 5 °C.

[0019] An MIT material exhibits a resistance-temperature curve that matches the one in Fig. The resistance-temperature curve illustrated in Figure 2 is similar, with the difference that the resistivity rises rapidly as the temperature increases and reaches a predefined first temperature threshold. If the temperature has risen above the first temperature threshold and then decreases, the resistivity rises rapidly as the temperature reaches a second temperature threshold. This second temperature threshold is, for example, lower than the first.

[0020] Transistor device 1 is configured to operate in an on-state or an off-state. In the on-state, transistor device 1 is configured to conduct a load current between a first load path node 12 and a second load path node 13. In the off-state, transistor device 1 is configured to block the load current.

[0021] As an example, the temperature sensing circuit 2 with the temperature sensing resistor 21 is used to protect the transistor device 1 from overheating. An overheating condition of the transistor device 1 can occur when the transistor device is in the on state and the load current flowing through the transistor device 1 causes excessive power dissipation in the transistor device 1.

[0022] According to one example, the temperature sensing circuit 2 acts simultaneously as a temperature sensor, detecting the temperature of the transistor device 1, and as an actuator, reducing the power dissipation in the transistor device 1 to prevent a further increase in temperature. Reducing the power dissipation in the transistor device 1 can include switching off the transistor device 1 to interrupt the load current flowing between the first and second load path nodes 12, 13.

[0023] According to another example, the temperature sensing circuit 2 acts only as a temperature sensor, providing temperature information to a control circuit configured to drive the transistor device. The control circuit can be configured to switch off the transistor device 1 if the temperature information provided by the temperature sensing circuit 2 indicates an excessive temperature of the transistor device 1.

[0024] Examples of transistor arrangements in which the temperature sensing circuit 2 acts as a temperature sensor and an actuator, and of transistor arrangements in which the temperature sensing circuit 2 acts only as a temperature sensor, are explained in detail below.

[0025] Fig. Figure 3 illustrates an example of a transistor arrangement comprising a transistor device 1 and a temperature sensing circuit 2, where the temperature sensing circuit 2 acts as both a temperature sensor and an actuator. In this example, the transistor device 1 is a voltage-controlled transistor device configured to operate in an on state (conducting state) or an off state (blocking state) depending on the voltage level of a drive voltage received between a first node and a second node of a drive input of the transistor device 1.

[0026] In the ON state, transistor device 1 is configured to conduct a load current through the load path between the first and second load path nodes 12 and 13. In the OFF state, transistor device 1 is configured to block the load current.

[0027] According to an example, transistor device 1 is in the ON state when the voltage level of the drive voltage is higher than a threshold voltage of the transistor device, and transistor device 1 is in the OFF state when the voltage level of the drive voltage is lower than the threshold voltage.

[0028] According to an example (as in Fig. Figure 3 shows that the voltage-controlled transistor device 1 is a MOSFET (Metal Oxide Field-Effect Transistor) comprising a gate node 11 as the first node of the drive input, a source node 12 as the second node of the drive input and the second load path node, and a drain node 13 as the second load path node. Thus, the MOSFET switches on or off depending on a drive voltage Vgs (usually referred to as the gate-source voltage) applied between the gate node 11 and the source node 12.

[0029] According to an example (as in Fig. Figure 3 shows that the MOSFET is an enhancement MOSFET, such as an N-type or P-type enhancement MOSFET. An enhancement MOSFET is on when the gate-source voltage exceeds a predefined threshold. An N-type enhancement MOSFET has a positive threshold voltage and is on when the gate-source voltage (Vgs) is positive and higher than the threshold voltage. A P-type enhancement MOSFET has a negative threshold voltage and is on when the gate-source voltage (Vgs) is negative and lower than the threshold voltage. The magnitude of the threshold voltage depends on the specific implementation of transistor device 1. For example, the threshold voltage is in a range between 5 V and 15 V.Each of an N-type enhancement MOSFET and a P-type enhancement MOSFET is in the off state when the gate-source voltage Vgs is essentially zero.

[0030] It should be noted that transistor device 1 is not limited to being implemented as a MOSFET. According to another example, transistor device 1 is implemented as an IGBT (Insulated Gate Bipolar Transistor), which is a bipolar transistor that can be operated similarly to an N-type enhancement MOSFET. In an IGBT, the first node is usually called the gate node, and the first and second load path nodes are usually called the emitter and collector nodes, respectively.

[0031] Although the transistor device is not limited to being implemented as a MOSFET, the first and second nodes of the drive input are referred to below as the gate and source nodes, and the first and second load path nodes of the load paths are referred to below as the source and drain nodes.

[0032] Transistor device 1 includes an internal capacitance between the gate node 11 and the source node 12. This capacitance is usually referred to as the gate-source capacitance of transistor device 1. For illustrative purposes only, in Fig. 3 This capacitance is shown as a capacitor Cgs connected between the gate node 11 and the source node 12. The transistor device 1 is in the on state when the gate-source capacitance Cgs has been charged to such an extent that the gate-source voltage Vgs is greater than the threshold voltage.

[0033] In the transistor arrangement according to Fig. 3. The temperature sensing resistor 21 incorporates an IMT material and is connected between the first and second nodes (gate and source nodes) 11, 12 of the drive input. As the temperature rises, the temperature sensing resistor 21 has a first resistance R1 before the temperature reaches the first temperature threshold, and a second resistance R2 after the temperature has reached the first temperature threshold. As an example, the second resistance R2 is at least three orders of magnitude lower than the first resistance R1.

[0034] Activating the transistor device 1 in the on-state can be achieved by providing a drive current Igs to the gate node 11 via a drive circuit (in Fig. (3 not illustrated) until the gate-source capacitance has been charged to a predefined voltage level higher than the threshold voltage. The first resistor R1 of the temperature sensing resistor 21 is such that the temperature sensing resistor 21 does not prevent the transistor device 1 from being driven in the on-state. That is, when the temperature sensing resistor 21 has the first resistor R1, it provides a high-impedance current path in parallel with the gate-source capacitance Cgs, with this high-impedance current path carrying a current that is significantly lower than the drive current Igs provided by the drive circuit. Thus, the temperature sensing resistor 21 does not significantly discharge the gate-source capacitance Cgs, so the transistor device 1 is kept in the on-state.

[0035] It should be noted that the “temperature sensing resistor 21”, as used here, is a device that exhibits a temperature-dependent resistance, but is not necessarily a pure (ideal) resistor. Instead, the temperature sensing resistor 21 may additionally include a capacitive and / or an inductive component.

[0036] However, if the temperature rises, causing the resistance of the temperature sensing resistor 21 to decrease from the first resistor R1 to the second resistor R2, the temperature sensing resistor 21 discharges the gate-source capacitance Cgs, causing the drive voltage Vgs to fall below the voltage threshold and switch off the transistor device 1. More precisely, a discharge current flowing through the temperature sensing resistor 21 when the temperature sensing resistor has the second resistance R2 is higher than the drive current Igs. Thus, the temperature sensing resistor 21 can override the drive circuit and can switch off the transistor device 1 and / or keep the transistor device 1 in the off state.

[0037] The first and second resistances R1, R2 of the temperature sensing resistor 21 can be adjusted by appropriately implementing the temperature sensing resistor 21 using the IMT material. The temperature sensing resistor 21 can be implemented similarly to a conventional resistor, comprising a conventional type of resistive material and potentially including a layer of the IMT material, where the thickness and length of the IMT material layer, among other things, define the first and second resistances R1, R2.

[0038] Fig. Figure 3 shows an equivalent circuit diagram of the transistor arrangement. The following are various examples for implementing a temperature sensing resistor 21 of the [reference missing]. Fig. 3 illustrated type explained, which is connected between a gate node 11 and a source node 12 of a transistor device 1.

[0039] Fig. Figure 4 shows a transistor arrangement with a transistor device 1 and a temperature sensing circuit 2 according to an example. With reference to Fig. 4 The transistor device 1 comprises a semiconductor body 100 in which transistor cells 10 of the transistor device 1 are integrated. The transistor cells 10 are arranged in Fig. 4 is not illustrated in detail. Instead, the transistor cells are represented by a transistor circuit symbol. This is shown in Fig. The illustrated circuit symbol 4 represents an N-type MOSFET. However, this is only for illustrative purposes.

[0040] The transistor device 1 is not limited to being implemented as an N-type MOSFET, but can also be implemented as a P-type enhancement MOSFET or an IGBT.

[0041] Each of the transistor cells 10 can comprise a source region connected to the source node 12, a body region, a drift region, and a drain region connected to the drain node. Furthermore, each transistor cell 10 can comprise a gate electrode connected to the gate node 11. This is generally known, so no further explanation is required in this respect.

[0042] With reference to Fig. The transistor device 1 comprises a gate pad 111 and a source pad 112, each formed over a first surface 101 of the semiconductor body 100. The gate pad 111 is connected to the gate electrodes of the transistor cells 10. Furthermore, the gate pad 111 is connected to the gate node 11 or forms the gate node 11 of the transistor device. The source pad 112 is connected to the source regions of the transistor cells 10. Furthermore, the source pad is connected to the source node 12 or forms the source node 12 of the transistor device.

[0043] The gate pad 111 and the source pad 112 can be formed on an insulating layer 114. In this example, one or more electrically conductive gate vias can extend through the insulating layer 114 from the gate pad 111 to the one or more gate electrodes, and electrically conductive source vias can extend through the insulating layer 114 from the source pad 112 to the source regions.

[0044] With reference to Fig. In section 4, the gate pad 111 and the source pad 112 are spaced apart, and the temperature sensing resistor 21 is connected between the gate pad 111 and the source pad 112. The temperature sensing resistor 21 is in Fig. Figure 1 is only shown schematically. Examples for implementing the temperature sensing resistor 21 are explained further below.

[0045] With reference to Fig. 4 The transistor device further comprises a drain pad 113. The drain pad 113 is connected to the drain regions of the transistor cells 10.

[0046] Furthermore, the drain pad 113 forms the drain node 13 or is connected to the drain node 13. In the Fig. In the illustrated example 18, the drain pad 113 is formed on a second surface 102 opposite the first surface 101 of the semiconductor body 100. In this example, the transistor device is a vertical transistor device in which the load current flows essentially between the opposite first and second surfaces 101, 102 when the transistor device 1 is in the on state.

[0047] The transistor device 1 and the temperature sensing circuit 2 with the temperature sensing resistor 21 can be arranged in a common housing (not illustrated), such as a housing made of a molding compound. The housing can include terminals (pins) accessible on an exterior surface. Such terminals include, for example, a gate terminal connected to the gate pad 111 and a source terminal connected to the source pad 112. The gate pad 111 is configured to have a connector, such as a bond wire or a clamp, for connecting the gate pad 111 to the associated gate terminal. The source pad 112 is configured to have another connector, such as a bond wire or a clamp, for connecting the source pad 112 to the associated source terminal.Connecting a gate pad of a transistor device to a gate terminal accessible on the outside of a package, and connecting a source pad of a transistor device to a source terminal accessible on the outside of a package, is generally known, so no further explanation is needed in this respect.

[0048] Several examples of implementing the temperature sensing resistor 21 are given in Fig. 5- Fig. Figure 8B illustrates and explains below. In each of the examples, the temperature sensing resistor 21 comprises an IMT material layer 221 extending between the gate pad 111 and the source pad 112, and adjacent to each of the gate pad 111 and the source pad 112 for electrical connection. It should be noted that each of the Fig. 5- Fig. Figure 8B illustrates only a section of the gate pad 111 and the source pad 112 and the semiconductor body 100.

[0049] In the Fig. In the illustrated example 5, the gate pad 111 and the source pad 112 are spaced apart laterally. The IMT material layer 221 extends laterally from the gate pad 111 to the source pad 112 and overlaps both the gate pad 111 and the source pad 112. In the region between the gate pad 111 and the source pad 112, the IMT material layer 221 is formed over the insulating layer 114 on which the gate pad 111 and the source pad 112 are formed. A temperature sensing resistor 21 of the Fig. The type 5 illustrated can be formed by depositing and structuring the IMT material layer after the gate pad 111 and the source pad 112 have been formed.

[0050] In the Fig. In the illustrated example 6, both the gate pad 111 and the source pad 112 overlap the IMT material layer 221, which is formed on the insulating layer 114. A temperature sensing resistor 21 of the in Fig. The type 6 illustrated can be formed by forming the gate pad 111 and the source pad 112 after forming the IMT material layer 221 on the insulating layer.

[0051] The resistance of the temperature sensing resistor 21 depends on (a) a vertical cross-sectional area of ​​the IMT material layer 221 in a section plane perpendicular to the one in the Fig. 5 and Fig. 6 illustrated plane; and (b) a distance between the contact positions where the IMT material layer 221 is in contact with the gate pad 111 and the source pad 112. Basically, for a given distance between the gate pad 111 and the source pad 112, the resistance decreases as the vertical cross-sectional area increases, and vice versa. Furthermore, for a given vertical cross-sectional area, the resistance increases as the distance between the gate pad 111 and the source pad 112 increases, and vice versa.

[0052] In the in the Fig. 5 and Fig. In the 6 illustrated examples, the shortest distance between positions where the IMT layer 221 contacts the gate pad 111 and the source pad 112 is essentially equal to the distance between the gate pad 111 and the source pad 112.

[0053] According to another in Fig. In the illustrated example 7, the IMT material layer 221 is formed on a further insulating layer 115, wherein the further insulating layer 115 overlaps both the gate pad 111 and the source pad 112. In this example, the further insulating layer 115 defines the distance between the contact positions. Thus, for a given distance between the gate pad 111 and the source pad 112, the further insulating layer 115 can be used to adjust the resistance of the temperature sensing layer 221.

[0054] In the Fig. In the illustrated example 7, the additional insulating layer 115 overlaps both the gate pad 111 and the source pad 112. However, this is only one example. According to another (unillustrated) example, the additional insulating layer 115 overlaps only one of the gate pad 111 and the source pad 112.

[0055] According to another example, one of the gate pad 111 and the source pad 112 overlaps the other of the gate pad 111 and the source pad 112, and the IMT material layer 221 is formed between the gate pad 111 and the source pad 112. Examples of a transistor arrangement of this type are in Fig. 8A and Fig. 8B illustrates.

[0056] In the Fig. In the illustrated example 8A, the source pad 112 overlaps a section of the gate pad 111, and the IMT material layer 221 is formed between the section of the gate pad 111 that is overlapped by the source pad 112 and the overlapping section of the source pad 112. A temperature sensing resistor 21 of the Fig. The type illustrated in 8A can be formed, for example, by forming the gate pad 111, forming the IMT material layer 221 such that it overlaps the gate pad 111, and forming the source pad 112 such that it overlaps both the IMT material layer 221 and the gate pad 111.

[0057] In the Fig. In the illustrated example 8B, the gate pad 111 overlaps a section of the source pad 112, and the IMT material layer 221 is formed between the section of the source pad 112 that is overlapped by the gate pad 111 and the overlapping section of the gate pad 111. A temperature sensing resistor 21 of the Fig. The type illustrated in 8B can be formed, for example, by forming the source pad 112, forming the IMT material layer 221 such that it overlaps the source pad 112, and forming the gate pad 111 such that it overlaps both the IMT material layer 221 and the source pad 111.

[0058] Each of the Fig. 5- Fig. Figure 8B shows a vertical cross-sectional view of the IMT material layer 221, a section of the gate pad 111, and a section of the source pad 112. In lateral directions, which are directions parallel to the first surface 101, the gate and source pads 111 and 112, and the IMT material layer 221, can be implemented in various ways. Several examples are shown in Fig. 9- Fig. 11 illustrates and explains below. Each of the Fig. 9- Fig. Figure 11 shows a top view of the first surface 101 of the semiconductor body 100 according to a corresponding example.

[0059] In the Fig. In the illustrated example 9, the source pad 112 is essentially rectangular and includes a cutout. The gate pad 111 is essentially rectangular and is located in the region where the source pad 112 has a cutout. Furthermore, the IMT layer 221, which forms the temperature sensing resistor 21, is connected to both the gate pad 111 and the source pad 112.

[0060] In the Fig. In the 9 illustrated example, the cutout of the source pad 112 is located in a corner region of the source pad 112, so that the source pad 112 is essentially L-shaped. However, this is only one example. According to another example, the cutout of the source pad 112 is located between two corners of the source pad 112, so that the source pad is U-shaped. A U-shaped source pad 112 is in Fig. 10 illustrated.

[0061] According to the same or a different example, as in Fig. As illustrated in Figure 10, the transistor device 1 includes, in addition to the gate pad 111 and the source pad 112, at least one gate runner 116 which is connected to the gate pad 111. As shown in Fig. As illustrated in Figure 10, an IMT layer 221 is connected between the source pad 112 and the at least one gate runner 116. In the Fig. In the illustrated example 10, the transistor device 1 includes two gate runners 116, each connected to the gate pad 111 and spaced apart from each other. In this example, the source pad 112 is arranged laterally between the gate runners 116. In the example according to Fig. 10. The IMT layers 221 are connected to the gate pad 111 by the gate runner 116.

[0062] In each of the in Fig. 9- Fig. The 10 illustrated examples show that IMT layer 221 can be used according to one of the [documents / guidelines / etc.] in [documents / guidelines / etc.]. Fig. 5- Fig. The examples illustrated in 8B are implemented. Thus, although the Gate Pad 111 (or the Gate Runner(s) 116) and the Source Pad 112 are shown in the examples in Fig. 9- Fig. The 10 illustrated examples, shown spaced apart from each other, also allow the Gate Pad 111 (or the Gate Runner(s) 116) and the Source Pad 112 to be shown according to the diagram in Fig. 8A and Fig. 8B to implement the example explained, in which one of the Gate-Pad 111 and the Source-Pad 112 overlaps the other of the Gate-Pad 111 and the Source-Pad 112.

[0063] Fig. Figure 11 illustrates an example of a transistor arrangement based on the one described in Fig. The transistor arrangement illustrated in 10 is based on this. Fig. The illustrated transistor arrangement 11 differs from the transistor arrangement according to Fig. 10 by including only one IMT layer 221, which extends in a lateral direction from one of the gate runners 116 across the source pad 112 to the other gate runner 116. According to one example, the IMT layer 221 is adjacent to the source pad 112 at every position where the IMT layer 221 overlaps the source pad 112. According to another example, the IMT layer 221 is connected to the source pad 112 in some regions, and other regions of the IMT layer 221 are separated from the source pad 112 by an insulating layer.

[0064] In the Fig. 5- Fig. In the 11 illustrated examples, the temperature sensing resistor 21 is connected between the gate pad 111 and the source pad 112, wherein the gate pad 111 is connected to gate electrodes of transistor cells 10 integrated into the semiconductor body 100, and the source pad 112 is connected to source regions of transistor cells 10 integrated into the semiconductor body 100.

[0065] Fig. 12A- Fig. Figure 12E illustrates an example of a transistor arrangement in which each transistor cell 10 includes a section of the temperature sensing resistor 21.

[0066] Fig. Figure 12A shows a vertical cross-sectional view of the semiconductor body 100 in a vertical section plane A1-A1, which intersects a source pad 112, Fig. Figure 12B shows a vertical cross-sectional view of the semiconductor body 100 in a vertical section plane BB intersecting a gate runner 116. Fig. Figure 12C shows a vertical cross-sectional view of the semiconductor body 100 in another vertical section plane A2-A2, which intersects the source pad 112, Fig. Figure 12D shows a vertical cross-sectional view of the semiconductor body 100 in another vertical section plane A3-A3, which intersects the source pad 112, and Fig. Figure 12C shows a top view of semiconductor body 100.

[0067] With reference to Fig. In Figure 12A, the transistor device comprises a plurality of transistor cells 10. Each transistor cell 10 includes a gate electrode 15 and a field electrode 17 arranged in a trench 19 extending from the first surface 101 in a vertical direction z into the semiconductor body 100. The "vertical direction z" is a direction that is essentially perpendicular to the first and second surfaces 101 and 102. By way of example, the trenches 19 containing the gate electrodes 15 and the field electrodes 17 are spaced apart in a first lateral direction x and are extended in a second lateral direction y perpendicular to the first lateral direction x. Consequently, the gate electrodes 15 and the field electrodes 17 are extended in the second lateral direction y. The first and second lateral directions x and y are, for example, essentially perpendicular to the vertical direction z and essentially parallel to the first surface 101.

[0068] Furthermore, each transistor cell 10 comprises a source region 1011 of a first doping type, a body region 1012 of a second doping type complementary to the first doping type, a drift region 1014 of the first doping type, and a drain region 1013. The drift region 1014 is located between the body region 1012 and the drain region 1013. According to one example, the transistor device is implemented as a MOSFET. In this example, the drain region 1013 has the first doping type. According to another example, the transistor device is implemented as an IGBT (Insulated Gate Bipolar Transistor). In this example, the drain region 1013 (which can also be called the collector region) has the second doping type. According to one example, the first doping type is an N-type and the second doping type is a P-type to form an N-type MOSFET or an IGBT.According to another example, the first doping type is a P-type and the second doping type is an N-type to form a P-type MOSFET.

[0069] The gate electrode 15 is dielectrically isolated from the semiconductor body 100 by a gate dielectric 16, is located adjacent to the body region 1012, and is configured to control a conducting channel in the body region 1012 along the gate dielectric 16. The field electrode 17 is dielectrically isolated from the semiconductor body 100 by a field electrode dielectric 18 and is located adjacent to the drift region 1014.

[0070] In the conventional manner, the gate electrode 15 of each transistor cell 10 serves to control a conducting channel in the body region 1012 along the gate dielectric 16. Furthermore, the field electrode 17 serves to shape the electric field in the drift region 1014 when the transistor device is in the off-state, that is, when conducting channels in the body regions 1012 are open and a voltage is applied between the drain and source regions 1013, 1011, which reverse-biases the PN junctions formed between the body and drift regions 1012, 1014.

[0071] According to a Fig. In the example illustrated in Figure 12A, the gate electrodes 15 of two adjacent transistor cells 10 can be formed together by a first electrode, and the field electrodes 17 of two adjacent transistor cells 10 can be formed together by a second electrode formed in a respective trench 19. Furthermore, the body regions 1012 of two (other) adjacent transistor cells can be formed by a continuous doped region of the second doping type, the drift regions 1014 of the transistor cells 10 can be formed by a continuous doped region of the second doping type, and the drain region 1013 can be formed by a continuous doped region of either the first doping type (MOSFET) or the second doping type (IGBT).

[0072] With reference to Fig. 12A Each of the source regions 1011 and the body regions 1012 is connected to the source pad 112. For this purpose, the transistor device can comprise a plurality of electrically conductive source vias 112', each source via 112' extending from the source pad 112 through the insulating layer 114 down to the respective source and body regions 1011, 1012.

[0073] Each of the gate electrodes 15 is connected to the gate pad 111. According to an example, the gate electrodes 15 are connected to the gate pad 111 via at least one gate rail 116.

[0074] Fig. Figure 12B shows a vertical cross-sectional view of the transistor arrangement in a vertical section plane BB intersecting the at least one gate rail 116 and illustrates an example of connecting the gate electrodes 15 to the gate rail 116. For this purpose, the transistor device can comprise a plurality of electrically conductive gate vias 116', each gate via 116' extending from the gate rail 116 through the insulating layer 114 downwards to a respective gate electrode 15.

[0075] With reference to the above, the field electrodes 17 are connected to the source node 12. According to an example, to connect the field electrodes 17 to the source node 12, the field electrodes 17 are connected to the source pad 112. An example of how the field electrodes 17 can be connected to the source pad 112 is shown in Fig. 12C illustrated.

[0076] Fig. Figure 12C shows a vertical cross-sectional view of the transistor arrangement in a vertical section plane A2-A2, which differs from the one in Fig. Figure 12A illustrates the section plane A1-A1, which differs and intersects the source pad 112. In this example, the transistor arrangement includes contact electrodes 17' that are located in the grooves 19 with the gate electrodes 15 (in Fig. (Figure 12C not illustrated) and the field electrodes 17 extend from the field electrodes 17 towards the first surface 101 of the semiconductor body 100. The contact electrodes 17' are electrically connected to the source pad 112 by electrically conductive vias 112'' that extend from the source pad 112 through the insulating layer 114 to the contact electrodes 17'. The contact electrodes 17' can be made of the same material as the field electrodes 17, which is, for example, a metal or doped polysilicon.

[0077] Fig. Figure 12D shows a vertical cross-sectional view in a vertical section plane A3-A3 (see also Fig. 12C), which extends in a longitudinal direction of a trench 19 with a gate electrode 15 and a field electrode 17 arranged therein. With reference to Fig. 12D is the contact electrode 17', which extends from the field electrode 17 to the first surface 101, dielectrically insulated from the gate electrode 15, which is located in the same trench 19. As can be seen from Fig. As can be seen in Figure 12D, the contact electrode 17' can divide the gate electrode into two gate electrode sections. In this example, the contact electrode 17' is spaced apart from the longitudinal ends of the trench 19. The "longitudinal ends" of the trench 19 terminate the trench 19 in its longitudinal direction. In the Fig. 12A- Fig. In the 12D illustrated examples, the longitudinal direction of the trench 19 corresponds to the second lateral direction y. Fig. Insulating material 16'' can electrically insulate the conductive vias 112'' from the gate electrode 15. Insulating material 16'' can comprise one or more layers of an oxide (such as a thermally grown oxide or a deposited oxide) and a nitride.

[0078] The arrangement of the contact electrode 17', which is spaced apart from the longitudinal ends of the trench 19, as shown in Fig. Figure 12D is only one example. According to another example (not illustrated), the contact electrode 17' extends from the field electrode 17 to the first surface 101 at one longitudinal end of the trench 19.

[0079] With reference to the above, the source regions 1012 and the field electrodes 17 are connected to the source pad 112, and the gate electrodes 15 are connected to a gate runner 116. The source pad 112 and the gate runner 116 can be implemented in various ways. An example of how to implement the source pad 112 and the gate runner 116 is shown in Fig. 12E illustrates.

[0080] In the Fig. The illustrated example in Figure 12E includes the transistor arrangement with two gate runners 116, each connected to the gate pad 111, extending longitudinally in the first lateral direction x and spaced apart in the second lateral direction y. Furthermore, the transistor arrangement includes a source pad 112, spaced laterally from the gate pad 111 and the gate runners 116, and positioned between the two gate runners 116.

[0081] In the Fig. In the example illustrated in Figure 12E, the contact electrodes 17', which connect the field electrodes 17 to the source pad 112, can be spaced apart from the longitudinal ends of the trenches 19 containing the gate electrodes 15 and the field electrodes 17. For illustrative purposes only, the position of two of these trenches 19 under the source pad 112 and the gate runner 116 in Figure 12E is shown. Fig. 12E illustrated by dashed lines. The trenches 19 can end below the gate runners 116, so that the longitudinal ends of the trenches 19 can be located below the two gate runners 116. As with reference to Fig. As explained in Figure 12D, the contact electrodes 17' can divide the gate electrodes 15 into two gate electrode sections. In this example, each of these gate electrode sections can be connected to one of the two gate runners 116 at its respective longitudinal end to a Fig. 12B illustrated how it can be connected.

[0082] According to another in Fig. In the illustrated example 13, the transistor arrangement includes only one gate runner 116'', which is connected to the gate pad 111 and extends longitudinally in the first lateral direction x. In this example, the gate runner 116'' divides the source pad 112 into two source pad sections, each isolated from the gate runner 116''. A gate runner 116'' of the in Fig. The 13 illustrated types can also be called gate fingers.

[0083] In the Fig. In the illustrated example 13, the gate electrodes 15 are connected to the gate runner (gate finger) 116'' at positions spaced apart from the longitudinal ends of the trenches 19. Furthermore, each of the field electrodes 17 is connected to at least one of the two source pad sections 112 at a respective longitudinal end of the respective trench 19. According to one example, each of the field electrodes 17 is connected to each of the two source pad sections 112.

[0084] Fig. Figure 14 illustrates a top view of a transistor arrangement that combines the components described in Fig. 12E and Fig. The transistor arrangements illustrated in section 13 are shown. In this example, the transistor arrangement includes two gate runners 116 of the type shown in the diagram. Fig. 12E illustrated type and a gate runner (gate finger) 116'' of the in Fig. Figure 13 illustrates the type. The gate runners 116, 116'' are connected to the gate pad 111, each extending longitudinally in the first lateral direction x and spaced apart from each other in the second lateral direction y. Furthermore, the transistor arrangement includes a source pad 112 with two source pad sections, each source pad section being located between the gate finger 116'' and one of the respective gate runners 116. Each field electrode 17 is also connected to at least one of the source pad sections, and each gate electrode is connected to at least one of the gate runners 116, 116''.

[0085] With reference to Fig. In 12A, an IMT layer 221 is arranged between the gate electrode 15 and the field electrode 17 in at least one of the trenches 19. According to one example, an IMT layer 221 is arranged between the gate electrode 15 and the field electrode 17 in each of the trenches 19. According to another example, an IMT layer 221 is arranged between the gate electrode 15 and the field electrode 17 in fewer than each of the trenches 19, with the gate electrode 15 and the field electrode 17 being electrically insulated from each other in the remaining trenches. According to one example, IMT layers 221 are formed between the gate electrode 15 and the field electrode 17 in more than 30% or more than 50% of the trenches.

[0086] According to one example, in trenches containing an IMT layer 221, the IMT layer 221 is located under the source pad 112, but not under the gate runner 116. According to another example (in Fig. (Illustrated in dashed lines in Figure 12B) IMT layer 221 is also located below gate runner 116.

[0087] By selecting the number of grooves containing an IMT layer 221 between the gate electrode 15 and the field electrode 17, and by adjusting the dimensions of the IMT layers 221 along the longitudinal direction of the grooves, the total area of ​​the IMT layers 221 arranged between the gate electrodes 15 and the field electrodes 17, and therefore the resistance of the temperature sensing resistor 21, can be set. In principle, for a given thickness of the IMT layers 221, the electrical resistance of the temperature sensing resistor 21 is lower the larger the total area of ​​the IMT layers 221 in a plane parallel to the first and second surfaces 101, 102, both when the temperature is below and when the temperature is above the temperature threshold of the respective IMT material.

[0088] Fig. 15A- Fig. 15D illustrates a modification of the in Fig. 12A- Fig. 12C, Fig. 13 and Fig. 14 illustrated transistor arrangements. Fig. Figure 15A shows a vertical cross-sectional view of the semiconductor body 100 in a vertical section plane C1-C1, which intersects a source pad 112, Fig. Figure 15B shows a vertical cross-sectional view of the semiconductor body 100 in a vertical section plane DD, which intersects a gate runner 116. Fig. Figure 15C shows a vertical cross-sectional view of the semiconductor body 100 in a vertical section plane C2-C2, which differs from the section plane C1-C1 and intersects the source pad 112, and Fig. Figure 15D shows a top view of semiconductor body 100.

[0089] In the transistor arrangement according to Fig. 15A- Fig. In 15C, the IMT material layer 221 is arranged within the insulating layer 114. As explained above, the insulating layer 114 is located between the first surface 101 of the semiconductor body 100 on one side and the gate pad 111, the at least one gate runner 116, and the source pad 112 on the other side. The IMT layer 221 borders at least one of the electrically conductive source vias 112', which connect the source pad 112 to the source and body regions 1011, 1012 of the transistor cells 10, and at least one of the electrically conductive gate vias 116', which connect a gate runner 116 to the gate electrodes 15.

[0090] The transistor arrangement includes at least one IMT layer 221 connected between at least one source via 112' and at least one gate via 116', wherein the at least one IMT layer 221 forms the temperature sensing resistor 21. According to one example, the transistor arrangement includes exactly one IMT layer 221. According to another example, the transistor arrangement includes two or more IMT layers 221 spaced apart from each other, with each IMT layer 221 connected between at least one source via 112' and at least one gate via 116'. By connecting the gate vias 116' to the gate pad 111 and the source vias 112' to the source pad 112, the at least one IMT layer forming the temperature sensing transistor 21 is connected between the gate pad 111 and the source pad 112.According to one example, at least 30% of the Source-Vias 112' and at least 30% of the Gate-Vias 116' are interconnected by at least one of the IMT layers 221.

[0091] In the Fig. 15A- Fig. In the transistor arrangement illustrated in Figure 15C, the field electrodes 17 connected to the source pad 112 are optional and therefore illustrated in dashed lines. If the transistor arrangement includes transistor cells 10 with field electrodes 17 arranged in the same grooves 19 as the gate electrodes 15, the field electrodes 17 are connected to the source pad 112. In this case, as shown in Figure 15C, the field electrodes 17 are optional and therefore illustrated in dashed lines. Fig. Figure 15C illustrates the transistor arrangement including contact electrodes 17' extending from the field electrodes 17 towards the first surface 101 and connected to the source pad 112 by gate vias 12'' in the same manner as previously described herein with reference to Fig. 12C explained.

[0092] In the transistor arrangement of the in Fig. 15A- Fig. In the illustrated type 15C, the source regions 1012 and the optional field electrodes 17 are connected to the source pad 112, and the gate electrodes 15 are connected to a gate runner 116. The source pad 112 and the gate runner 116 can be implemented in various ways. An example of how to implement the source pad 112 and the gate runner 116 is shown in Fig. 12E illustrates.

[0093] In the transistor arrangement according to Fig. 15D includes transistor device 1, similar to the one in Fig. Figure 12E illustrates two gate runners 116 extending laterally in the first lateral direction x and spaced apart in the second lateral direction y. Furthermore, the source pad 112 is positioned between the gate runners 116 and isolated from them.

[0094] In a transistor arrangement of the in Fig. In the type illustrated in Figure 15D, when the transistor cells are free of field electrodes 17, each gate electrode 15 can be connected to a first gate runner 116 at a first longitudinal end and to a second gate runner 116 at a second longitudinal end opposite the first longitudinal end.

[0095] When the transistor arrangement field electrodes 17 and contact electrodes 17' of the in Fig. 15C of the illustrated type, the contact electrodes can be connected to the gate electrodes 15 in the same way as described above. Fig. 12C and Fig. Figure 12D explains how to divide the gate electrode sections into two. In this example, each of the gate electrode sections can be connected to one of the two gate runners at its respective longitudinal end, and the field electrodes 17 are connected to the source pad 112 by the contact electrodes 17 and the Fig. 15C illustrated vias 112'' connected.

[0096] Implementing the transistor arrangement with two gate runners 116 of the in Fig. The type illustrated in 15D is just one example. According to another in Fig. In the illustrated example 16, the transistor device 1 includes only one gate runner 116'' (which can also be called a gate finger) extending longitudinally in the first lateral direction x and dividing the source pad 112 into two source pad sections. In this example, each gate electrode 15 is connected to the gate runner 116' at a position spaced apart from the longitudinal ends of the gate electrode 15. Furthermore, each of the optional field electrodes 17 is connected to the one described with reference to Fig. 15C is connected in the manner described with at least one of the source pad sections.

[0097] Fig. Figure 17 illustrates a top view of a transistor arrangement that combines the components described in Fig. 15D and Fig. The transistor arrangements illustrated in section 16 are shown. In this example, the transistor arrangement includes two gate runners 116 of the type shown in the diagram. Fig. 15D illustrated type and a gate runner (gate finger) 116'' of the in Fig. Figure 16 illustrates the type of gate runners 116 and 116''. The gate runners are connected to the gate pad 111, each extending longitudinally in the first lateral direction x and spaced apart in the second lateral direction y. The transistor arrangement also includes a source pad 112 with two source pad sections, each section being located between the gate finger 116'' and one of the gate runners 116. Furthermore, each gate electrode is connected to at least one of the gate runners 116 and 116'', and each optional field electrode 17 is connected to at least one of the source pad sections.

[0098] In the Fig. 15A- Fig. In the example illustrated in Figure 15C, the IMT layer 221 is spaced in the vertical direction z from both the source pad 112 and the first surface 101 of the semiconductor body 100. However, this is only one example.

[0099] According to another in Fig. In the illustrated example 18, at least one IMT layer 221 borders the source pad 112 and is spaced away from the first surface 101.

[0100] According to another in Fig. In the illustrated example 19, the at least one IMT layer 221 borders the first surface 101 and is spaced away from the source pad 112. In the region of the first surface 101, the at least one IMT layer 221 can be connected to one or more source regions 1011 in addition to the at least one source via 116' and one or more gate electrodes 15.

[0101] Fig. Figure 20 shows an equivalent circuit diagram of a transistor arrangement according to another example. In this example, the temperature sensing circuit 2 with the temperature sensing resistor 21 is connected between an external drive node 11 and an internal drive node 11' of the transistor device 1. The external drive node 11 is, for example, the gate described earlier. A transistor arrangement of the in Fig. The type illustrated in Figure 20 can be implemented by placing an IMT layer between the gate pad and at least one gate runner of the transistor array. An example of implementing the transistor array in this way is given in Figure 20. Fig. 21 illustrates, where Fig. Figure 21 shows a top view of the semiconductor body 100 in which transistor cells 10 of the transistor device are integrated.

[0102] With reference to Fig. 21 The transistor device comprises a gate pad 111 and a source pad 112 of the type previously described. Furthermore, the transistor device comprises at least one gate runner 116. In the Fig. In the illustrated example 21, the transistor device includes two gate runners 116, each extending longitudinally in the first lateral direction x, spaced apart in the second lateral direction y, and connected by a connecting runner 117. In this example, the source pad 112 is located between the two gate runners 116.

[0103] The temperature sensing resistor 21 is formed by an IMT layer 221 that connects the gate pad 111 to the interconnect runner 117. The IMT layer connecting the gate pad 111 to the interconnect runner 117 can be implemented according to any of the examples previously described. In this example, the gate pad 111 forms the external drive node (gate node) 11 or is connected to the external drive node 11, and the at least one gate runner 116, which is connected to the gate electrodes of the transistor cells integrated into the semiconductor body 100, forms the internal drive node 11'.

[0104] Implementing the transistor arrangement with two gate runners 116 of the in Fig. The type illustrated in diagram 21 is only one example. According to another example (not illustrated), the transistor arrangement includes a 116'' gate runner (gate finger) of the type shown in diagram 21. Fig. 13 and Fig. 16 illustrated types, and the IMT layer is connected between the gate finger 116'' and the gate pad 111. According to another example (not illustrated), the transistor arrangement includes two gate runners 116 of the type shown in Fig. 21 illustrated types and a gate finger 116'' of the in Fig. 13 and Fig. 16 illustrated types. In this example, a first IMT layer 221 can be applied to the one in Fig. 21 illustrated way can be connected between the gate runner 116 and the gate pad 111, and a second IMT layer 221 can be connected between the gate finger 116'' and the gate pad 111.

[0105] It should be noted that the implementation of transistor device 1 with two gate runners 116 is only one example. According to another example, the transistor device includes only one gate runner 116, and the IMT layer 221 is connected between the gate pad 111 and a connecting runner 117 extending from the single gate runner 116 towards the gate pad 111.

[0106] In each of the in Fig. 4- Fig. 19 and Fig. In the 21 illustrated examples, good thermal coupling between the temperature sensing resistor 21 and the transistor device 1 is achieved by placing the IMT layer 21 in close proximity to the first surface 101 of the semiconductor body 100 in which the transistor device 1 is integrated.

[0107] With reference to the above, the temperature sensing resistor 21 in the transistor arrangements can be described as follows: Fig. 20 and Fig. 21 includes the IMT layer 221. However, this is just one example. According to another example, the temperature sensing resistor 21 in the Fig. 20 and Fig. Figure 21 illustrates an MIT layer such that the resistance of the temperature sensing resistor 21 increases as the temperature rises and reaches the first temperature threshold of the MIT material. In this example, the temperature sensing resistor 21 slows down the switching of transistor device 1 when the temperature of the temperature sensing resistor 21 exceeds the first temperature threshold of the MIT material. "Slowing down the switching of transistor device 1" implies that there is an increased delay between the time at which the drive voltage Vgs changes from an on level to an off level, or vice versa, when the increased resistance of the temperature sensing resistor 21 slows down the charging and discharging of the internal capacitance Cgs by a suitable drive circuit (not illustrated).

[0108] Fig. Figure 22 shows a transistor arrangement according to another example. In this example, the transistor arrangement includes a first transistor device 1a and a second transistor device 1b, each comprising a respective gate node 11a, 11b, a respective source node 12a, 12b, and a respective drain node 13a, 13b. Each of the first and second transistor devices 1a, 1b has a load path between the source node 12a, 12b and the drain node 13a, 13b, and a drive input formed by the gate node 11a, 11b and the source node 12a, 12b. For illustrative purposes only, each of the first and second transistor devices 1a, 1b is a MOSFET.

[0109] With reference to Fig. 22 The load paths of the first and second transistor devices 1a, 1b are connected in parallel and form the load path of the transistor arrangement between a first load path node 12 and a second load path node 13 of the transistor arrangement. Furthermore, the gate nodes 11a, 11b are connected to form a common gate node 11 of the transistor arrangement.

[0110] With reference to Fig. 22 the temperature sensing circuit 2 with the temperature sensing resistor 21 is connected between the gate node 11a and the source node 12a of the first transistor device 1a, wherein the second transistor device 1b is free of a respective temperature sensing circuit.

[0111] As an example, the temperature sensing resistor 21 comprises an IMT material, so that the resistance of the temperature sensing resistor 21 decreases when the temperature reaches the respective temperature threshold. Since the gate nodes 11a, 11b of the first and second transistor devices 1a, 1b are connected to each other, and since the source nodes 12a, 12b of the first and second transistor devices 1a, 1b are connected to each other, the temperature sensing circuit 2 protects not only the first transistor device 1a, but also the second transistor device 1b from high temperatures. That is, the temperature sensing circuit 2 switches off both the first transistor device 1a and the second transistor device 1b when the temperature reaches the respective temperature threshold.Thus, in an arrangement with two (or more) transistor devices 1a, 1b, whose gate nodes 11a, 11b are connected to each other and whose load paths are connected in parallel, it may be sufficient to implement one of the two (or more) transistor devices 1a, 1b with a temperature sensing circuit 2, which reduces the cost compared to an arrangement in which two (or more) transistor devices 1a, 1b are implemented with a respective temperature sensing circuit 2.

[0112] With reference to Fig. 22 controls a control circuit 4 both the first and the second transistor device 1a, 1b.

[0113] Fig. Figure 23 illustrates a transistor arrangement according to another example. The transistor arrangement according to Fig. 23 is a modification of the transistor arrangement according to Fig. 20 and includes a first transistor device 1a with a gate node 11a and a load path between a source node 12a and a drain node 13a. A temperature sensing circuit 2 with a temperature sensing resistor 21 is connected between the gate node 11a and an internal gate node 11a'. The transistor device 1a and the temperature sensing circuit 2 can be configured according to one of the references to Fig. The 20 explained examples should be implemented.

[0114] In addition to the first transistor device 1a, the transistor arrangement according to Fig. 23 a second transistor device 1b comprising a load path between a source node 12b and a drain node 13b, which is connected in parallel to the load path of the first transistor device 1a, and a gate node 11b, which is connected to the gate node 11a of the first transistor device 1a at a common gate node 11.

[0115] In the transistor arrangement according to Fig. 23 Both transistor devices 1a, 1b can be driven by a common drive circuit 4, which is connected to the common gate node 11 and a common source node 12. The common source node 12 is a circuit node to which the source nodes 12a, 12b of transistor devices 1a, 1b are connected. In this transistor arrangement, the temperature sensing circuit 2 slows down the switching of the first transistor device 1a when the temperature (a) falls below a predefined temperature threshold or rises above (b). In the first case (a), the temperature sensing resistor 21 can comprise an MIT material whose resistance increases when the temperature rises above the predefined temperature threshold. In the second case (b), the temperature sensing resistor can comprise an IMT material whose resistance increases when the temperature falls below the predefined temperature threshold.

[0116] Fig. Figure 24 illustrates a transistor arrangement with a first transistor device 1a and a second transistor device 1b according to another example. In this example, the gate nodes 11a, 11b of the first and second transistor devices 1a, 1b are connected to each other to form a gate node (control node) 11 of the transistor arrangement. Furthermore, the drain nodes 13a, 13b are connected to each other to form the second load path node 13 of the transistor arrangement. The source node 12a of the first transistor device 1a is connected to the second load path node 12 of the transistor arrangement via the temperature sensing circuit 2 with the temperature sensing resistor 21, and the source node 12b of the second transistor device 1b is directly connected to the first load path node 12 of the transistor arrangement. According to one example, the temperature sensing resistor 21 incorporates an IMT material.In this example, a load current through the first transistor device 1a, which is a current between the drain and source nodes 13a, 12a of the first transistor device 1a, is reduced when the temperature reaches a temperature threshold associated with the IMT material.

[0117] Fig. Figure 25 illustrates an example of implementing a transistor arrangement of the in Fig. 24 illustrated types. In this example, transistor cells of the first transistor device 1a are integrated into a first semiconductor body 100a, and transistor cells of the second transistor device 1b are integrated into a second semiconductor body 100b. Furthermore, the first transistor device 1a comprises a source pad 112a and a gate pad (from the perspective in Fig. 25), which are formed over a first surface of the first semiconductor body 100a, and a drain pad 113a, which is formed over a second surface opposite the first surface of the first semiconductor body 100a. The second transistor device 1b comprises a source pad 112b and a gate pad (from the perspective in Fig. 25), which are formed over a first surface of the second semiconductor body 100b, and a drain pad 113b, which is formed over a second surface opposite the first surface of the second semiconductor body 100b. The drain pads 113a, 113b are optional and can be omitted.

[0118] With reference to Fig. 25 The transistor arrangement comprises an electrically conductive carrier 313 on which the first and second semiconductor bodies 100a, 100b are arranged such that the second surfaces with the drain pads 113a, 113b face the carrier 313 and the drain regions (in Fig. (25 not illustrated) of the first and second transistor devices 1a, 1b are connected to the carrier 313. The carrier 313 forms the second load path node 13 or is connected to the second load path node 13 of the transistor arrangement.

[0119] With reference to Fig. 25 is an IMT layer 221 that forms the temperature sensing resistor 21, between source regions (in Fig. 25 not illustrated) of transistor cells of the first transistor device 1a and the source pad 112a. Furthermore, the source pad 112b of the second transistor device 1b is directly connected to source regions (in Fig. 25 (not illustrated) of transistor cells of the second transistor device 1b connected.

[0120] A conductor 312 borders each of the source pad 112a of the first transistor device 1a and the source pad 112b of the second transistor device 1b. The conductor 312 forms the first load path node 12 or is connected to the first load path node 12 of the transistor arrangement.

[0121] In the examples described above, the temperature sensing resistor 21 acts as both a temperature sensor and an actuator. That is, because it is thermally coupled to the transistor device 1, the temperature sensing resistor 21 detects the temperature of the transistor device 1 and changes the operating state of the transistor device 1 when the temperature rises and reaches the first temperature threshold of the temperature-sensitive material of the temperature sensing resistor 21. Examples of transistor arrangements in which the temperature sensing circuit 2 acts only as a temperature sensor are explained below.

[0122] Fig. Figure 26 illustrates a transistor arrangement of the in Fig. Figure 3 illustrates a type comprising a transistor device 1 and a temperature sensing circuit 2 with a temperature sensing resistor 21. Unlike the one in Fig. In the illustrated example 3, the temperature sensing circuit 2 is not connected between the gate and source nodes 11 and 12, which form the drive input of the transistor device 1. The temperature sensing circuit 2 is thermally coupled to the transistor device 1, so that the resistance of the temperature sensing resistor 21 depends on the temperature of the transistor device 1. The temperature sensing resistor 21 comprises an IMT material or an MIT material.

[0123] The transistor arrangement can further include an evaluation circuit 3 (illustrated in dashed lines) configured to detect a resistance of the temperature sensing resistor 21 in order to detect whether the temperature of the transistor device 1 is higher or lower than the first temperature threshold of the temperature-sensitive material (IMT material or MIT material) of the temperature sensing resistor 21, which rapidly changes its resistance. In one example, the evaluation circuit 3 is configured to drive a detection current I3 through the temperature sensing resistor 21 and detect a voltage V21 across the temperature sensing resistor 21. The evaluation circuit 3 is configured to detect, based on the detected voltage V21, whether the temperature of the transistor device 1 is higher or lower than the first temperature threshold.According to one example, evaluation circuit number 3 is configured to compare the detected voltage V21 with a voltage threshold and, depending on whether the detected voltage V21 is higher or lower than the voltage threshold, detects that the temperature of the transistor device 1 is higher or lower than the first temperature threshold of the temperature-sensitive material. According to another example, the temperature detection resistor 21 comprises an IMT material, and evaluation circuit 3 is configured to compare the detected voltage V21 with a voltage threshold and detects that the temperature of the transistor device 1 is higher than the temperature threshold of the IMT material if the detected voltage V21 is lower than the voltage threshold.

[0124] Fig. 27 shows a modification of the transistor arrangement according to Fig. 26. In the transistor arrangement according to Fig. Figure 27 of the current sensing circuit comprises two or more temperature sensing resistors 21a, 21b, 21c connected in series. According to an example, the temperature sensing resistors 21a, 21b, 21c comprise different temperature-sensitive materials, each of which is either an IMT material or an MIT material.

[0125] According to an example, the evaluation circuit 3 is configured to drive the detection current I3 through the series resistor circuit and to detect the voltages V21a, V21b, V21c across each of the temperature detection resistors 21a, 21b, 21c connected in series. Since the temperature-sensitive materials of the temperature detection resistors 21a, 21b, 21c connected in series have different first temperature thresholds, the evaluation circuit 3, by detecting the voltages V21a, V21b, V21c across each of the temperature detection resistors 21a, 21b, 21c, is able to detect whether the temperature of the transistor device 1 is higher or lower than the first temperature threshold of the temperature-sensitive material of each of the temperature detection resistors 21a, 21b, 21c.

[0126] In the Fig. 26 and Fig. In the 27 illustrated examples, each of the temperature sensing resistors 21a, 21b, 21c can be implemented as an IMT or MIT material layer formed over a source pad and electrically isolated from the source pad 112 of the transistor device 1.

[0127] Fig. 28 shows a modification of the in Fig. 27 illustrated transistor arrangement. The transistor arrangement according to Fig. 23 differs from the transistor arrangement according to Fig. 27 by the fact that the series circuit with the temperature sensing resistors 21a, 21b, 21c has a first 22 of the two circuit nodes, between which the resistors 21a, 21b, 21c are connected in series, which is connected to the first load path node 12 of the transistor device 1. Thus, within the transistor arrangement, the first circuit node of the resistor series circuit can be connected to the source pad 112 of the transistor device 1, so that the first circuit node 22 of the resistor series circuit can be connected to the evaluation circuit 3 via the source pad 112, so that no additional contact pad is required to connect the first circuit node 22 to the evaluation circuit 3.

[0128] It should be noted that this in Fig. The principle illustrated in Figure 28 can also be applied to a temperature sensing circuit 2 that includes only one temperature sensing resistor 21. In this example, a first circuit node of the temperature sensing resistor 21 is connected to the source node 12 of the transistor device 2, and the evaluation circuit 3 is connected to the source node 12 of the transistor devices 1 and to a second circuit node that is located away from the first circuit node of the temperature sensing resistor 21.

[0129] Fig. 29 shows a combination of the in Fig. 3 and Fig. 28 illustrated examples. In this example, a first temperature sensing resistor 21i is connected between the gate nodes 11 and the source nodes 12 of the transistor device 1. The first temperature sensing resistor 21i comprises, for example, an IMT material. Furthermore, at least one second temperature sensing resistor 21ii ​​is connected between the source nodes 12 of the transistor device 1 and an evaluation circuit 3, wherein the evaluation circuit 3 is configured to detect a voltage V21ii across the second temperature sensing resistor 21b. The second temperature sensing resistor 21ii ​​comprises an IMT material or an MIT material.

[0130] In the Fig. In the illustrated example 29, only a second temperature sensing resistor 21ii ​​is connected between the evaluation circuit 3 and the source node 12 of the transistor device 1. However, this is only one example. In the same way as in Fig. Figure 28 illustrates that two or more temperature sensing resistors can be connected in series between the source nodes 12 of the transistor device 1 and the evaluation circuit 3, wherein the evaluation circuit 3 can be configured to detect the voltage across each of the temperature sensing resistors connected in series.

[0131] In transistor arrangements of the in Fig. 26- Fig. In the type illustrated in Figure 29, the evaluation circuit 3 receives temperature information by detecting the voltage across at least one temperature sensing resistor. According to a diagram in Fig. In the illustrated example 30, the evaluation circuit 3 is configured to supply a temperature signal Sot, containing the received temperature information, to a control circuit 4, which is configured to control the transistor device 1. The temperature sensing circuit 2 is in Fig. 30 is only schematically illustrated and can be used according to one of the in Fig. 26- Fig. 29 illustrated temperature sensing circuits 2 must be implemented.

[0132] According to one example, the control circuit 4 switches the transistor device 1 on or off depending on an input signal Sin received by the control circuit 4. According to another example, the control circuit 4 switches the transistor device 1 on when the input signal Sin has a first signal level (on level), and switches the transistor device 1 off when the input signal Sin has a second signal level (off level).

[0133] According to one example, the control circuit 4 is configured to override the input signal Sin and switch off the transistor device 1 when the temperature signal Sot received by the evaluation circuit 3 indicates that an excessively high temperature of the transistor device 1 has occurred. Thus, the control circuit 4 switches off the transistor device 1 even when the input signal Sin is at a level, in order to prevent the transistor device 1 from being damaged due to excessively high temperatures.

[0134] With reference to the above, the electrical resistance of the at least one temperature sensing resistor depends, among other things, on the thickness of the temperature-sensitive material layer (IMT layer or MIT layer), such as the IMT layer 221 described earlier. As an example, the layer thickness is selected from between 10 nanometers (nm) and 300 micrometers (µm), in particular between 50 nanometers and 10 micrometers.

[0135] Various types of materials that exhibit IMT or MIT behavior are available. In addition to the vanadium dioxide discussed above, examples of MIT materials include, but are not limited to, NiS 2-x See x ; RNiO3, where R is selected from Ho, Y, Er, Lu; BaCoS; BaCo 1-x Ni x S2; VO2-doped semiconductor material with a suitable semiconductor material, for example Ge (germanium) or GaAs (gallium arsenide); VO2-doped metal with a suitable metal, such as Cr (chromium), Fe (iron), Mn (manganese), Co (cobalt) or Nickel (Ni); Sr2IrO4; and doped Sr2IrO4 with a lanthanide (such as lanthanum, yttrium and ytterbium), which is, for example, a suitable dopant.

[0136] Examples of MIT materials include, but are not limited to, Cr-doped V2O3; V2O3-doped Ti2O3; Ca2RuO4.

[0137] In the examples where the temperature-sensitive material is a doped material, the temperature threshold can be adjusted by appropriately adjusting the doping concentration of the respective dopant.

[0138] The examples described herein provide: Example 1: Transistor arrangement, comprising: a transistor device (1); and a temperature sensing circuit (2) which is thermally coupled to the transistor device (1) and includes a temperature sensing resistor (21), wherein the temperature sensing resistor (21) comprises an insulator-to-metal transition (IMT) material or a metal-to-insulator transition (MIT) material. Example 2: Transistor arrangement according to Example 1, wherein the IMT material is configured to exhibit the insulator-to-metal transition when the temperature rises and reaches a predefined temperature threshold. Example 3. Transistor arrangement according to Example 1 or 2, wherein the transistor device (1) is a voltage-controlled transistor device comprising a control input with a first node (11) and a second node (12), and wherein the temperature sensing resistor (21) is connected between the first node (11) and the second node (12). Example 4. Transistor arrangement according to Example 3, wherein the transistor device (1) is a MOSFET, where the first node (11) is a gate node of the MOSFET, and where the second node (12) is a source node of the MOSFET. Example 5. Transistor arrangement according to Example 4, where the MOSFET (1) comprises: a semiconductor body (100); a gate pad (111) formed over a first surface (101) of the semiconductor body (100) and forming the gate node (11) or connected to the gate node (11); and a source pad (112) formed over the first surface (101) of the semiconductor body (100) and forming the source node (12) or being connected to the source node (12). Example 6. Transistor arrangement according to Example 5, wherein the gate pad (111) is spaced apart from the source pad (112), and wherein the temperature sensing resistor (21) comprises an IMT material layer (221) that is adjacent to each of the gate pad (111) and the source pad (112) and extends between the gate pad (111) and the source pad (112). Example 7. Transistor arrangement according to Example 5 or 6, where the Source Pad (112) at least partially overlaps the Gate Pad (111), and wherein the temperature sensing resistor (21) comprises an IMT material layer (221) arranged between the gate pad (111) and a section of the source pad (112) that overlaps the gate pad (111). Example 8. Transistor arrangement according to Example 5, wherein the MOSFET (1) further comprises a gate runner (116, 116") which is connected to the gate pad (111), and wherein the temperature sensing resistor (21) is an IMT material layer (221) includes, which is adjacent to each of the Gate-Runner (116) and the Source-Pad (112) and extends between the Gate-Pad (111) and the Source-Pad (112). Example 9. Transistor arrangement according to Example 5, wherein the MOSFET (1) further comprises a plurality of transistor cells (10), each comprising a gate electrode (15) connected to the gate pad (111) and a field electrode (17) connected to the source pad (112), wherein the gate electrode (15) and the field electrode (17) of each transistor cell (10) are arranged in a trench extending from the first surface (101) into the semiconductor body (100), and wherein the temperature sensing element (21) comprises at least one IMT material layer (221) arranged between the gate electrode (15) and the field electrode (17) of at least one of the plurality of transistor cells (10). Example 10. Transistor arrangement according to Example 9, wherein each transistor cell (10) further comprises a source region (1011) and a body region (1012) which are connected to the source pad (112) and are dielectrically isolated from the gate electrode (15) by a gate dielectric (16). Example 11. Transistor arrangement according to Example 5, wherein the MOSFET (1) further comprises: a plurality of transistor cells (10), each comprising a gate electrode (15) connected to the gate pad (111), and a source region (1011) and a body region (1012) connected to the source pad (112); an insulating layer (114) formed between the semiconductor body (100) and the source pad (112); Source vias (112') extending from the source pad (112) through the insulating layer (114) to the source and body regions (1011, 1012) and connected to the source pad (112); and Gate vias (111') extending through the insulating layer (114) to the gate electrodes (15) and connected to the gate pad (111), and wherein the temperature sensing resistor (21) comprises at least one IMT material layer (221) arranged in the insulating layer (114) and adjacent to at least one of the source vias (112') and at least one of the gate vias (111'). Example 12. Transistor arrangement according to one of examples 6 to 11, wherein the thickness of the IMT material layer (221) is in a range between 10 nanometers and 300 micrometers, in particular between 50 nanometers and 10 micrometers. Example 13. Transistor arrangement according to Example 1 or 2, wherein the transistor device (1) is a voltage-controlled transistor device comprising an external drive input (11) and an internal drive input (11'), and wherein the temperature sensing resistor (21) is connected between the external control input (11) and the internal control input (11'). Example 14. Transistor arrangement according to Example 13, wherein the transistor device (1) is a MOSFET comprising: a semiconductor body (100); a gate pad (111) formed over a first surface (101) of the semiconductor body (100) and forming the external control input (11); and a gate runner (116) which is formed above the first surface (101) of the semiconductor body (100) and forms the internal control input (11'). Example 15. Transistor arrangement according to one of examples 1 to 12, wherein the transistor device is a first transistor device (1a), and the transistor arrangement further comprises: a second transistor device (1b) with a load path connected in parallel to a load path of the first transistor device (1a). Example 16. Transistor arrangement according to Example 1 or 2, wherein the transistor device is a first transistor device (1a), wherein the transistor arrangement further comprises a second transistor device (1b), and wherein the temperature sensing resistor (21) is connected between a second node (12a) of the first transistor device (1a) and a second node (12b) of the second transistor device (1b). Example 17. Transistor arrangement according to Example 1, the MIT material is designed to exhibit the insulator-to-metal transition as the temperature decreases and reaches a predefined temperature threshold. Example 18. Transistor arrangement according to Example 2 or 17, further comprising: an evaluation circuit (3) which is connected to the temperature sensing circuit (2) and is configured to monitor at least one resistance of the temperature sensing circuit (2). Example 19. Transistor arrangement according to Example 18, wherein the temperature sensing resistor is one of a plurality of temperature sensing resistors (21a, 21b, 21c) connected in series, and wherein the evaluation circuit (3) is configured to monitor the resistance of at least one of the temperature sensing resistors (21a, 21b, 21c). Example 20. Transistor arrangement according to Example 18 or 19, further comprising: a control circuit (4) which is configured to control the transistor device (1) depending on a temperature signal (Sot) received by the evaluation circuit (3). Example 21. Transistor arrangement according to one of the preceding examples, wherein the IMT material is selected from the group consisting of: VO2; NiS 2-x See x ; RNiO3, where R is selected from Ho, Y, Er, Lu; BaCoS; BaCo 1-x Ni x S2; VO2-doped semiconductor material; VO2-doped metal; Sr2IrO4; and doped Sr2IrO4. Example 22. Transistor arrangement according to one of the preceding examples, wherein the MIT material is selected from the group consisting of: Cr-doped V2O3; V2O3-doped Ti2O3; Ca2RuO4. Example 23. Transistor arrangement, comprising: a transistor device (1); and a resistor (21) which is thermally and electrically coupled to the transistor device (1), wherein the resistance (21) comprises a material consisting of an insulator-to-metal transition (IMT) or a metal-to-insulator transition (MIT).

[0139] It should be noted that the methods and devices, including their preferred embodiments, as set forth in this document, may be used alone or in combination with the other methods and devices disclosed herein. Furthermore, the features described in connection with a device are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and devices described in this document may be combined in any way. In particular, the features of the claims may be combined with one another in any manner.

Claims

[1] Transistor arrangement comprising: a MOSFET (1), comprising: a semiconductor body (100), a gate pad (111) formed over a first surface (101) of the semiconductor body (100) and forming a gate node (11) or connected to the gate node (11), a source pad (112) formed over the first surface (101) of the semiconductor body (100) and forming a source node (12) or connected to the source node (12), a plurality of transistor cells (10), each comprising a gate electrode (15) connected to the gate pad (111) and a field electrode (17) connected to the source pad (112), wherein the gate electrode (15) and the field electrode (17) of each transistor cell (10) are arranged in a trench extending from the first surface (101) into the semiconductor body (100); and a temperature sensing circuit (2) which is thermally coupled to the MOSFET (1) and includes a temperature sensing resistor (21), wherein the temperature sensing resistor (21) comprises at least one insulator-to-metal junction, IMT, material layer (221) arranged between the gate electrode (15) and the field electrode (17) of at least one of the plurality of transistor cells (10). [2] Transistor arrangement according to claim 1, wherein the IMT material is configured to have the insulator-to-metal transition when the temperature rises and reaches a predefined temperature threshold. [3] Transistor arrangement according to claim 1, wherein each transistor cell (10) further comprises a source region (1011) and a body region (1012) which are connected to the source pad (112) and are dielectrically isolated from the gate electrode (15) by a gate dielectric (16). [4] Transistor arrangement according to one of claims 1 to 3, wherein the thickness of the IMT material layer (221) is in a range between 10 nanometers and 300 micrometers, in particular between 50 nanometers and 10 micrometers. [5] Transistor arrangement according to any one of claims 1 to 4, wherein the MOSFET (1) is a first transistor device (1a), and the transistor arrangement further comprises: a second transistor device (1b) with a load path connected in parallel to a load path of the first transistor device (1a). [6] Transistor arrangement according to claim 1, further comprising: an evaluation circuit (3) which is connected to the temperature sensing circuit (2) and is configured to monitor at least one resistance of the temperature sensing circuit (2). [7] Transistor arrangement according to claim 6, wherein the temperature sensing resistor is one of a plurality of temperature sensing resistors (21a, 21b, 21c) connected in series, and wherein the evaluation circuit (3) is configured to monitor the resistance of at least one of the temperature sensing resistors (21a, 21b, 21c). [8] Transistor arrangement according to claim 6 or 7, further comprising: a control circuit (4) which is set up to control the MOSFET (1) depending on a temperature signal (Sot) received by the evaluation circuit (3). [9] Transistor arrangement according to any one of the preceding claims, wherein the IMT material is selected from the group consisting of: VO2; NiS 2-x See x ; RNiO3, where R is selected from Ho, Y, Er, Lu; BaCoS; BaCo 1-x Ni x S2; VO2-doped semiconductor material; VO2-doped metal; Sr2IrO4; and doped Sr2IrO4. [10] Transistor arrangement comprising: a MOSFET (1), comprising: a semiconductor body (100), a gate pad (111) formed over a first surface (101) of the semiconductor body (100) and forming a gate node (11) or connected to the gate node (11), a source pad (112) formed over the first surface (101) of the semiconductor body (100) and forming a source node (12) or connected to the source node (12), a plurality of transistor cells (10), each comprising a gate electrode (15) connected to the gate pad (111), and a source region (1011) and a body region (1012) connected to the source pad (112), an insulating layer (114) formed between the semiconductor body (100) and the source pad (112), Source vias (112') extending through the insulating layer (114) to the source and body regions (1011, 1012) and connected to the source pad (112), and Gate vias (111') extending through the insulating layer (114) to the gate electrodes (15) and connected to the gate pad (111); and a temperature sensing circuit (2) which is thermally coupled to the MOSFET (1) and includes a temperature sensing resistor (21), wherein the temperature sensing resistor (21) comprises at least one IMT material layer (221) arranged in the insulating layer (114) and adjacent to at least one of the source vias (112') and at least one of the gate vias (111'). [11] Transistor arrangement according to claim 10, wherein the IMT material is configured to have the insulator-to-metal transition when the temperature rises and reaches a predefined temperature threshold. [12] Transistor arrangement according to claim 10, wherein each transistor cell (10) further comprises a source region (1011) and a body region (1012) which are connected to the source pad (112) and are dielectrically isolated from the gate electrode (15) by a gate dielectric (16). [13] Transistor arrangement according to one of claims 10 to 12, wherein the thickness of the IMT material layer (221) is in a range between 10 nanometers and 300 micrometers, in particular between 50 nanometers and 10 micrometers. [14] Transistor arrangement according to any one of claims 10 to 13, wherein the MOSFET (1) is a first transistor device (1a), and the transistor arrangement further comprises: a second transistor device (1b) with a load path connected in parallel to a load path of the first transistor device (1a). [15] Transistor arrangement according to claim 10, further comprising: an evaluation circuit (3) which is connected to the temperature sensing circuit (2) and is configured to monitor at least one resistance of the temperature sensing circuit (2). [16] Transistor arrangement according to claim 15, wherein the temperature sensing resistor is one of a plurality of temperature sensing resistors (21a, 21b, 21c) connected in series, and wherein the evaluation circuit (3) is configured to monitor the resistance of at least one of the temperature sensing resistors (21a, 21b, 21c). [17] Transistor arrangement according to claim 15 or 16, further comprising: a control circuit (4) which is set up to control the MOSFET (1) depending on a temperature signal (Sot) received by the evaluation circuit (3). [18] Transistor arrangement according to any one of claims 10 to 17, wherein the IMT material is selected from the group consisting of: VO2; NiS 2-x See x ; RNiO3, where R is selected from Ho, Y, Er, Lu; BaCoS; BaCo 1-x Ni x S2; VO2-doped semiconductor material; VO2-doped metal; Sr2IrO4; and doped Sr2IrO4.

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