DISPLAY DEVICE

Abstract

A display device is provided, wherein a sub-pixel includes a first light-emitting device receiving a first low-potential voltage and a second light-emitting device receiving a second low-potential voltage. Additionally, a display device is provided, wherein, in a sub-pixel, first electrodes of a first and a second light-emitting device are connected to one and the same thin-film transistor, and second electrodes of the first and second light-emitting devices are spaced apart.

Description

[0001] This application claims priority to Republic of Korea Patent Application No. 10-2024-0030223, filed on February 29, 2024, and Republic of Korea Patent Application No. 10-2024-0114056, filed on August 26, 2024. BACKGROUNDTechnical field

[0002] The present disclosure relates to a display device. Description of the related field

[0003] The display device is often used as a display screen of a notebook computer, a tablet computer, a smartphone, a portable display device, and a portable information device, in addition to a display screen of a television or a monitor. With the advancement of technology, a display device may provide photography functions or various sensing functions in addition to an image display device function. Accordingly, the display device may include an electronic device such as a camera or a sensor.

[0004] Among display devices, an organic light-emitting display (OLD) is a self-emitting type and has advantages such as superior viewing angles and contrast ratio. Compared with a liquid crystal display (LCD), it is lightweight and thin because it does not require a separate backlight, and its power consumption is advantageous. In addition, the OLD has advantages such as low-voltage DC drive capability, fast response speed, and exceptionally low manufacturing costs.

[0005] The description provided in the Background section should not be presumed to be prior art merely because it is mentioned or associated with the Background section. The Background section may contain information describing one or more aspects of the subject technology. SUMMARY

[0006] During the formation of a light-emitting device of an organic light-emitting display device, external particles may penetrate. Specifically, the light-emitting device may be formed by sequentially depositing an anode, a light-emitting layer, and a cathode. If a particle penetrating from the outside deposits on the anode, the light-emitting layer cannot be stably formed on the anode. Likewise, the cathode cannot be stably formed on the light-emitting layer. In this case, the cathode and the anode may touch each other, resulting in a short circuit. Since the light-emitting device in which the short circuit has occurred cannot emit light, a defective pixel containing a dark spot may occur.

[0007] Recently, an aging process has been used to remove dark spots to normalize defective pixels. However, dark spots can reappear in normalized pixels, and the problem of numerous dark spots still exists.

[0008] Accordingly, there is a need to provide a display device with a reduced probability of dark spots.

[0009] All of the problems described above, or a problem that a person skilled in the art will recognize from the present description, are solved by a display device incorporating the features of one of the independent claims. Further aspects of the respective display devices are defined in the respective dependent claims.

[0010] According to one aspect of the present disclosure, the above-described and other technical effects can be achieved by providing a display device comprising a display panel including a display surface on which a plurality of sub-pixels are arranged, and a low-potential voltage supply unit or circuit that supplies a first low-potential voltage and a second low-potential voltage to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a first light-emitting part or unit including a first light-emitting device, and a second light-emitting part or unit including a second light-emitting device.which includes a second light-emitting device, and the first light-emitting device receives the first low-potential voltage via a first low-potential voltage line and the second light-emitting device receives the second low-potential voltage via a second low-potential voltage line.

[0011] According to another aspect of the present disclosure, a display device is provided that includes a display panel having a display surface on which a plurality of sub-pixels are arranged, and a low-potential voltage supply circuit that supplies a first low-potential voltage and a second low-potential voltage to the plurality of sub-pixels, wherein each of the plurality of sub-pixels includes a first light-emitting part including a first light-emitting device and a second light-emitting part including a second light-emitting device, the first light-emitting device and the second light-emitting device share a pixel circuit, and the first light-emitting device is configured to receive the first low-potential voltage via a first low-potential voltage line, and the second light-emitting device is configured,to receive the second low-potential voltage via a second low-potential voltage line.,

[0012] According to a further aspect of the present disclosure, the above-described and other aspects can be achieved by providing a display device comprising a substrate including a plurality of low-potential lines and a plurality of sub-pixels, each of the plurality of sub-pixels including a thin-film transistor disposed on the substrate, a planarization layer disposed on the thin-film transistor, the planarization layer having an opening, and a first light-emitting device and a second light-emitting device disposed on the planarization layer,wherein a first electrode of the first light-emitting device and a first electrode of the second light-emitting device are connected to the same thin-film transistor, and a second electrode of the first light-emitting device and a second electrode of the second light-emitting device are spaced apart from each other.

[0013] The display devices according to the aspects described above may further comprise one or more of the following features:

[0014] The first low-potential voltage line and the second low-potential voltage line may be arranged alternately.

[0015] Each of the plurality of sub-pixels may further include an opening between the first light-emitting part and the second light-emitting part.

[0016] Each of the plurality of sub-pixels may overlap with one of the first low-potential voltage line and the second low-potential voltage line. Each of the plurality of sub-pixels need not overlap with the other of the first low-potential voltage line and the second low-potential voltage line.

[0017] The plurality of sub-pixels may include a plurality of first sub-pixels. The plurality of sub-pixels may include a plurality of second sub-pixels. The plurality of first sub-pixels and the plurality of second sub-pixels may be arranged adjacent to and spaced from each other in a first direction. Each of the plurality of first sub-pixels and the plurality of second sub-pixels may be arranged in a second direction that crosses the first direction. The first light-emitting part of the plurality of first sub-pixels may overlap with the first low-potential voltage line. The second light-emitting part of the plurality of first sub-pixels may not overlap with the first low-potential voltage line and the second low-potential voltage line. The first light-emitting part of the plurality of second sub-pixels may overlap with the second low-potential voltage line.The second light-emitting part of the plurality of second sub-pixels does not need to overlap with the first low-potential voltage line and the second low-potential voltage line.

[0018] The first light-emitting device may include a first cathode overlapping the first low-potential voltage line. The second light-emitting device may include a second cathode overlapping the second low-potential voltage line.

[0019] The first light-emitting device may include a first cathode electrically connected to the first low-potential voltage line. The second light-emitting device may include a second cathode electrically connected to the second low-potential voltage line.

[0020] Each of the plurality of sub-pixels may further include an opening between the first light-emitting portion and the second light-emitting portion. The first cathode and the second cathode may be spaced apart from each other, with the opening disposed therebetween.

[0021] The first cathode and the second cathode may be split, i.e., separated from each other, in a first direction. The first cathode and the second cathode may be provided with a gap in a first direction. The first direction may cross a second direction. The first low-potential voltage line and the second low-potential voltage line may extend in the second direction.

[0022] The plurality of sub-pixels may include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels spaced apart in a first direction. Each of the plurality of first sub-pixels, the plurality of second sub-pixels, and the plurality of third sub-pixels may be arranged in a second direction that crosses the first direction. The first light-emitting device of each of the plurality of first sub-pixels, the plurality of second sub-pixels, and the plurality of third sub-pixels may overlap with different cathodes. The first light-emitting device of the plurality of first sub-pixels may share a first cathode. The second light-emitting device of the plurality of first sub-pixels and the first light-emitting device of the plurality of second sub-pixels may share a second cathode that is different from the first cathode.The second light-emitting device of the plurality of second sub-pixels and the first light-emitting device of the plurality of third sub-pixels may share a third cathode different from the first cathode and the second cathode.

[0023] The first cathode, the second cathode, and the third cathode may be spaced apart from each other in the first direction. The first cathode, the second cathode, and the third cathode may extend in the second direction.

[0024] The low-potential voltage supply circuit may comprise a plurality of flexible printed circuit boards, each of which has an integrated drive circuit mounted thereon. The low-potential voltage supply circuit may comprise a first shorting bar connected to the first low-potential voltage line. The low-potential voltage supply circuit may comprise a second shorting bar connected to the second low-potential voltage line.

[0025] The first shorting bar may include a plurality of first connecting parts connected to the plurality of flexible circuit boards. The first shorting bar may include a second connecting part connected to the first low-potential voltage line. The second shorting bar may include a plurality of first connecting parts connected to the plurality of flexible circuit boards. The second shorting bar may include a second connecting part connected to the second low-potential voltage line.

[0026] Each of the plurality of sub-pixels may include a first sub-electrode and a second sub-electrode. One side of the first sub-electrode may be connected to the first light-emitting device. Another side of the first sub-electrode may be connected to the pixel circuit. One side of the second sub-electrode may be connected to the second light-emitting device. Another side of the second sub-electrode may be connected to the pixel circuit.

[0027] Each of the plurality of sub-pixels may include a first sub-contact hole. The first sub-electrode may be connected to a first electrode of the first light-emitting device through the first sub-contact hole. Each of the plurality of sub-pixels may include a second sub-contact hole. The second sub-electrode may be connected to the first electrode of the second light-emitting device through the second sub-contact hole.

[0028] Each of the plurality of sub-pixels may further include a third sub-contact hole. Each of the plurality of sub-pixels may further include a fourth sub-contact hole. The pixel circuit may include a thin-film transistor. The first sub-electrode may be connected to a source / drain electrode of the thin-film transistor through the third sub-contact hole. The second sub-electrode may be connected to the source / drain electrode of the thin-film transistor through the fourth sub-contact hole.

[0029] Each of the plurality of sub-pixels may further include an opening disposed between the first and second light-emitting portions. The source / drain electrode may overlap with the opening.

[0030] The first low potential voltage and the second low potential voltage may be configured to have the same voltage value or different voltage values.

[0031] The first light-emitting part and the second light-emitting part may be configured to emit light of the same color.

[0032] Each of the plurality of sub-pixels may further include a planarization layer on which the first light-emitting device and the second light-emitting device may be arranged. The planarization layer may be divided by the opening. The planarization layer may have an undercut in its side surface facing the opening.

[0033] The planarization layer may include a lower layer. The planarization layer may include an upper layer that protrudes from the lower layer toward the opening. A side surface of the lower layer facing the opening may have an inverted conical shape. A side surface of the upper layer facing the opening may have a conical shape.

[0034] The display device may further comprise a repair detector configured to apply the first low-potential voltage and the second low-potential voltage, respectively, to cathodes of the first light-emitting device and the second light-emitting device. The repair detector may further be configured to measure a voltage transmitted to a common node between anodes of the first light-emitting device and the second light-emitting device.

[0035] The planarization layer may include a first planarization layer and a second planarization layer spaced apart by the opening. The first light-emitting device may be disposed on the first planarization layer. The second light-emitting device may be disposed on the second planarization layer.

[0036] A side surface of the first planarization layer and a side surface of the second planarization layer adjacent to the opening may have an undercut shape. A side surface of the first planarization layer facing the opening and a side surface of the second planarization layer facing the opening may have an undercut shape.

[0037] A first placeholder layer and a second placeholder layer may be arranged in the opening. The second placeholder layer may be arranged on the first placeholder layer. A light-emitting layer of the first light-emitting device, a light-emitting layer of the second light-emitting device, and the first placeholder layer may contain the same material. The second electrode of the first light-emitting device, the second electrode of the second light-emitting device, and the second placeholder layer may contain the same material.

[0038] The first placeholder layer and the second placeholder layer may be spaced apart from the first light-emitting device. The first placeholder layer and the second placeholder layer may be spaced apart from the second light-emitting device.

[0039] The plurality of low-potential lines may include a first low-potential line and a second low-potential line. The second electrode of the first light-emitting device may be connected to the first low-potential line. A second electrode of the second light-emitting device may be connected to the second low-potential line.

[0040] The display device may further include a first passivation layer covering the first low-potential line. The display device may further include a connecting electrode on the first passivation layer. The display device may further include a second passivation layer on the connecting electrode. The connecting electrode and the first low-potential line may contact each other through a contact hole in the first passivation layer.

[0041] The second passivation layer may include a first contact portion exposing a portion of an upper surface of the connecting electrode. The connecting electrode and the second electrode of the first light-emitting device may contact each other via the first contact portion.

[0042] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concept as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principle of the disclosure; in the drawings: Fig. 1 is a schematic block diagram of a display device according to an embodiment of the present disclosure; Fig. 2 is a plan view of a display device according to an embodiment of the present disclosure; Fig. 3 is a plan view of a display panel according to an embodiment of the present disclosure; Fig. 4 is a cross-sectional view taken along the line AA' of Fig. 3, according to an embodiment of the present disclosure; Fig. 5 is a cross-sectional view taken along the line BB' of Fig. 3, according to an embodiment of the present disclosure; Fig. 6 is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure; Fig. 7 is a graph illustrating a voltage variation according to an embodiment of the present disclosure; Fig. 8 is a cross-sectional view illustrating a repair process according to an embodiment of the present disclosure; Fig. 9 is a diagram illustrating a portion of a display device according to an embodiment of the present disclosure; Fig. 10 is a view illustrating a surface I which is in Fig. 9, according to one embodiment of the present disclosure; Fig. 11 is a cross-sectional view taken along the line CC' of Fig. 10, according to an embodiment of the present disclosure; Fig. 12 and Fig. 13 cross-sectional views taken along line DD' of Fig. 10, according to a various embodiment of the present disclosure; Fig. 14 a view illustrating an area II which is in Fig. 10, according to one embodiment of the present disclosure; Fig. 15 is a cross-sectional view taken along the line EE' of Fig. 14, according to an embodiment of the present disclosure; Fig. 16 is a cross-sectional view taken along the line FF' of Fig. 14, according to an embodiment of the present disclosure; Fig. 17 is a diagram illustrating multiple pixels of a display device, according to an embodiment of the present disclosure; Fig. 18 is a diagram illustrating a subpixel and a repair detector of a display device, according to an embodiment of the present disclosure; and Fig. 19 is a diagram illustrating a voltage measured by a repair detector installed in Fig. 18, according to one embodiment of the present disclosure.

[0044] Throughout the drawings and detailed description, the same reference numerals should be understood to refer to the same elements, features, and structures unless otherwise described. The relative size and representation of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The sequence of processing steps and / or operations described is an example; however, the sequence of steps and / or operations is not limited to that set forth herein and may be changed, as is known in the art, except for steps and / or operations that necessarily occur in a particular order. Names of the respective elements used in the following explanations may be chosen merely to simplify the writing of the application text and may therefore be different from those used in actual products.

[0046] Advantages and features of the present disclosure and their methods of implementation will be more fully understood by the following embodiments, which are described with reference to the accompanying drawings. This disclosure may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0047] A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus the present disclosure is not limited to the illustrated details. Similar reference numerals refer to similar elements throughout the application text. In the following description, when it is determined that the detailed description of the relevant known function or configuration would unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. When 'comprise', 'have', and 'include' described in the present disclosure are used, another part may be added unless 'merely' is used. The terms of a singular form may include plural forms unless otherwise stated.

[0048] The word "exemplary" is used to mean serving as an example or illustrative. Aspects are exemplary aspects. "Embodiments," "examples," "aspects," and the like are not intended to be construed as preferred or advantageous over other implementations. An embodiment, example, exemplary embodiment, aspect, or the like may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, or the like, unless otherwise noted. Further, the term "could" includes all meanings of the term "may."

[0049] When designing an element, the element is interpreted as containing an error band even though there is no explicit description. Any implementation described herein as an "example" should not necessarily be interpreted as preferred or advantageous over other implementations.

[0050] For example, when describing a positional relationship, where the positional relationship is described as 'on top,' 'over,' 'under,' and 'next to,' one or more sections may be located between two other sections, unless 'exactly' or 'directly' is used. Terms such as 'under,' 'lower,' 'over,' 'upper,' and the like may be used herein to describe a relationship between one or more elements, as illustrated in the drawings. It is understood that the terms are spatially relative and use the orientation shown in the drawings as a basis.

[0051] It will be understood that although the terms "first," "second," "A," "B," "(a)," and "(b)," etc., may be used herein to describe various elements, the elements are not intended to be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present disclosure.

[0052] The term "at least one" should be understood to include all combinations of one or more of the associated listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" includes the combination of all three listed elements, combinations of any two of the three elements, as well as each of the first element, the second element, or the third element.

[0053] Features of various embodiments of the present disclosure may be partially or entirely coupled or combined with one another, and may interact and be technically controlled differently, as will be readily understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of one another or may be implemented together in an interdependent relationship.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one skilled in the art to which exemplary embodiments belong. It will further be understood that terms such as those defined in common dictionaries should be interpreted to have a meaning that is, for example, consistent with the meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless expressly defined so herein. For example, the term "part" or "unit" may, for example,apply to a separate circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform a described function, as understood by one of ordinary skill in the art.

[0055] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0056] Fig. 1 is a schematic plan view of a display device 1000 according to an embodiment of the present invention.

[0057] With reference to Fig. 1, the display device 1000 according to an embodiment of the present disclosure may include a display panel 100, a gate driver 200, a data driver 300, a high potential voltage driver 400, a low potential voltage driver 500, and a timing control unit 600.

[0058] The display panel 100 may include a display area DA and a non-display area NDA extending from the display area DA. As an example, the non-display area NDA may completely or partially surround the display area DA. The display area DA is an area in which an image can be displayed, and the non-display area NDA is an area in which no image is displayed.

[0059] A plurality of subpixels SP and a plurality of signal lines for driving the plurality of subpixels SP may be arranged in the display area DA. The plurality of signal lines may include a plurality of data lines DL and a plurality of gate lines GL.

[0060] The gate driver 200 is a circuit configured to drive the plurality of gate lines GL and can output sensing signals to the plurality of gate lines GL.

[0061] The data driver 300 is a circuit configured to drive the plurality of data lines DL and can output data signals to the plurality of data lines DL.

[0062] The high potential voltage driver 400 can supply a high potential voltage EVDD to the plurality of sub-pixels SP.

[0063] The low potential voltage driver 500 can supply the low potential voltage EVSS to the plurality of sub-pixels SP.

[0064] Timing control unit 600 may supply various control signals for controlling gate driver 200, data driver 300, high-potential voltage driver 400, and low-potential voltage driver 500. Embodiments are not limited thereto. As an example, at least one of the above-mentioned components may be omitted depending on the design. As an example, two or more of the above-mentioned components may be combined into one component. As an example, one or more additional components may be further included.

[0065] Fig. 2 is a top view of the display device 1000 according to an embodiment of the present disclosure.

[0066] With reference to Fig. 2, the display device 1000 may include a display panel 100 and a low potential voltage driver 500.

[0067] As described above, the display panel 100 may include the display area DA and the non-display area NDA surrounding the display area DA.

[0068] The low potential voltage driver 500 (e.g., a circuit) may include a plurality of driver ICs 510, a plurality of flexible printed circuit boards 520, a first shorting bar 530, and a second shorting bar 540.

[0069] Each of the plurality of drive ICs 510 may be mounted on the flexible circuit board 520. Furthermore, the flexible circuit board 520 may include a plurality of wirings and may electrically connect the plurality of drive ICs 510 to the display panel 100.

[0070] The first short-circuit bar 530 may include a plurality of first connecting parts 531 and a second connecting part 532.

[0071] One side of each of a plurality of first connecting parts 531 may be connected to the plurality of drive ICs 510, and the other side of the first connecting parts 531 may be connected to the second connecting parts 532. That is, the first shorting bar 530 may have a shape in which the plurality of first connecting parts 531 protrude from one side of the second connecting parts 532 toward the plurality of drive ICs 510. In addition, one side of the second connecting part 532 may be connected to the plurality of first connecting parts 531, and the other side of the second connecting part 532 may be connected to the plurality of first low-potential voltage lines EVSSL1.

[0072] Likewise, the second shorting bar 540 may include a plurality of first connecting parts 541 and a second connecting part 542. Furthermore, the second shorting bar 540 need not be electrically connected to the first shorting bar 530.

[0073] One side of each of the plurality of first connecting parts 541 may be connected to the plurality of drive ICs 510, and the other side of the first connecting parts 541 may be connected to the second connecting part 542. That is, the second shorting bar 540 may have a shape in which the plurality of first connecting parts 541 protrude from one side of the second connecting part 542 toward the plurality of drive ICs 510. Furthermore, one side of the second connecting part 542 may be connected to the plurality of first connecting parts 541, and the other side of the second connecting part 542 may be connected to a plurality of second low-potential voltage lines EVSSL2.

[0074] Several low-potential voltage lines EVSSL can be arranged in the display area DA of the display panel 100. Although it is not Fig. As shown in Figure 2, the plurality of low-potential voltage lines EVSSL may be connected to the plurality of sub-pixels SP arranged in the display area DA. Accordingly, the low-potential voltage driver 500 may supply the low-potential voltage EVSS to the plurality of sub-pixels SP via the plurality of low-potential voltage lines EVSSL.

[0075] The plurality of low-potential voltage lines EVSSL may include the plurality of first low-potential voltage lines EVSSL1 and the plurality of second low-potential voltage lines EVSSL2. Each of the plurality of sub-pixels SP may be electrically connected to both the first and second low-potential voltage lines EVSSL1 and EVSSL2.

[0076] In the display panel 100, the first and second low-potential voltage lines EVSSL1 and EVSSL2 may be arranged alternately. Specifically, the low-potential voltage line EVSSL arranged at an odd number from one end of the display panel 100 may be the first low-potential voltage line EVSSL1, and the low-potential voltage line EVSSL arranged at an even number from the end of the display panel 100 may be the second low-potential voltage line EVSSL2. Embodiments are not limited to this. For example, the low-potential voltage line EVSSL arranged at an even number from one end of the display panel 100 may be the first low-potential voltage line EVSSL1, and the low-potential voltage line EVSSL arranged at an odd number from the end of the display panel 100 may be the second low-potential voltage line EVSSL2, but this is not limited to this.

[0077] The low-potential voltage driver 500 may apply the first low-potential voltage EVSS1 to the first low-potential voltage line EVSSL1 via the first shorting bar 530. Furthermore, the low-potential voltage driver 500 may apply the second low-potential voltage EVSS2 to the second low-potential voltage line EVSSL2 via the second shorting bar 540. Furthermore, a magnitude of the first low-potential voltage EVSS1 may be the same as a magnitude of the second low-potential voltage EVSS2, but is not limited thereto.

[0078] Fig. 3 is a top view of the display panel 100 according to an embodiment of the present disclosure. Specifically, Fig. 3 shows an arrangement of the plurality of sub-pixels SP and the low-potential voltage line EVSSL arranged on the display panel 100.

[0079] With reference to Fig. 3, the display panel 100 according to an embodiment of the present invention may include the plurality of sub-pixels SP. The plurality of sub-pixels SP may be arranged in a matrix structure arranged in a first direction and a second direction X and Y. Each of the plurality of sub-pixels SP may emit one of red, green, blue, and white light, but is not limited thereto. As an example, at least one of the plurality of sub-pixels SP may emit light of a color other than red, green, blue, and white (e.g., cyan, magenta, or yellow, etc.). Although Fig. 3 illustrates that sub-pixels arranged in the first direction X emit light of the same color, but it is not limited to this. As an example, the sub-pixels arranged in the first direction X emit light of different colors.

[0080] A first low-potential voltage line and a second low-potential voltage line EVSSL1 and EVSSL2 are arranged under the plurality of sub-pixels SP, and the plurality of sub-pixels SP may overlap with the first and second low-potential voltage lines EVSSL1 and EVSSL2. Embodiments are not limited thereto. As an example, at least one or all of the plurality of sub-pixels SP may not overlap with at least one of the first and second low-potential voltage lines EVSSL1 and EVSSL2. Furthermore, each of the first and second low-potential voltage lines EVSSL1 and EVSSL2 may extend in the second direction Y. That is, one low-potential voltage line EVSSL may overlap with multiple sub-pixels SP.As an example, a low-potential voltage line EVSSL may overlap with the multiple sub-pixels SP emitting light of different colors, or may overlap with the multiple sub-pixels SP emitting light of the same color. Furthermore, although . Fig. 3 illustrates that the first and second low-potential voltage lines EVSSL1 and EVSSL2 are arranged adjacent to a left end of the sub-pixel SP, but are not limited thereto. For example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 may be arranged adjacent to a right end of the sub-pixel SP, may be arranged in the central portion of the sub-pixel SP, or may be arranged in an outer portion of the sub-pixel SP, but are not limited thereto.

[0081] A sub-pixel SP may include a first light-emitting part EM1, a second light-emitting part EM2, and an opening OP. Each of the first and second light-emitting parts EM1 and EM2 includes a light-emitting device and can emit light. Furthermore, the first and second light-emitting parts EM1 and EM2 can emit light of the same color. The opening OP may be arranged between the first and second light-emitting parts EM1 and EM2 and may separate the first light-emitting part EM1 and the second light-emitting part EM2. Furthermore, the opening OP does not need to include a light-emitting device.

[0082] A subpixel SP may receive first and second low-potential voltages EVSS1 and EVSS2 from the first and second low-potential voltage lines EVSSL1 and EVSSL2. Furthermore, a subpixel SP may overlap with one of the first and second low-potential voltage lines EVSSL1 and EVSSL2 and may be spaced apart from the other of the first and second low-potential voltage lines EVSSL1 and EVSSL2.

[0083] For example, the first sub-pixel SP1 may overlap with the first low-potential voltage line EVSSL1 and may be spaced apart from the second low-potential voltage line EVSSL2. For example, the first sub-pixel SP1 does not need to overlap with the second low-potential voltage line EVSSL2. Furthermore, the second sub-pixel SP2 may overlap with the second low-potential voltage line EVSSL2 and may be spaced apart from the first low-potential voltage line EVSSL1. For example, the second sub-pixel SP2 does not need to overlap with the first low-potential voltage line EVSSL1. Furthermore, the third sub-pixel SP3 may overlap with the first low-potential voltage line EVSSL1 and may be spaced apart from the second low-potential voltage line EVSSL2. For example, the third sub-pixel SP3 does not need to overlap with the second low-potential voltage line EVSSL2.That is, the sub-pixel SP overlapping with the first low-potential voltage line EVSSL1 and the sub-pixel SP overlapping with the second low-potential voltage line EVSSL2 may be arranged alternately.

[0084] The first light-emitting part EM1 of the first sub-pixel SP1 may overlap with the first low-potential voltage line EVSSL1, and the second light-emitting part EM2 of the first sub-pixel SP1 may be spaced apart from the first and second low-potential voltage lines EVSSL1 and EVSSL2. For example, the second light-emitting part EM2 of the first sub-pixel SP1 may not overlap with the first and second low-potential voltage lines EVSSL1 and EVSSL2. In addition, the first light-emitting part EM1 of the second sub-pixel SP2 may overlap with the second low-potential voltage line EVSSL2, and the second light-emitting part EM2 of the second sub-pixel SP2 may be spaced apart from the first and second low-potential voltage lines EVSSL1 and EVSSL2. For example, the second light-emitting part EM2 of the second sub-pixel SP2 does not need to overlap with the first and second low-potential voltage lines EVSSL1 and EVSSL2.

[0085] A cathode CAT may include a first cathode and a second cathode CAT1 and CAT2. The first cathode CAT1 may be disposed on the first low-potential voltage line EVSSL1. Furthermore, the second cathode CAT2 may be disposed on the second low-potential voltage line EVSSL2. The first and second cathodes CAT1 and CAT2 may be spaced apart from each other in an area that overlaps with the opening OP. That is, the first and second cathodes CAT1 and CAT2 do not need to be electrically connected to each other. Embodiments are not limited to this. As an example, the first cathode CAT1 may or may not overlap with the first low-potential voltage line EVSSL1, and the second cathode CAT2 may or may not overlap with the second low-potential voltage line EVSSL2, but are not limited to this.

[0086] The first low-potential voltage lines EVSSL1 may include a first contact portion CT1. As an example, the first contact portion CT1 may be formed to extend to one side of the first low-potential voltage lines EVSSL1, or may overlap with the first low-potential voltage lines EVSSL1, but is not limited thereto. The first low-potential voltage lines EVSSL1 may be electrically connected to the first cathode CAT1 through the first contact portion CT1. Furthermore, the second low-potential voltage line EVSSL2 may include a second contact portion CT2. As an example, the second contact portion CT2 may be formed to extend to one side of the second low-potential voltage line EVSSL2, or may overlap with the first low-potential voltage lines EVSSL1, but is not limited thereto.The second low-potential voltage line EVSSL2 may be electrically connected to the second cathode CAT2 through the second contact portion CT2.

[0087] That is, a sub-pixel SP may include both the first cathode CAT1, which receives the first low-potential voltage EVSS1 from the first low-potential voltage line EVSSL1, and the second cathode CAT2, which receives the second low-potential voltage from the second low-potential voltage line EVSSL2. That is, the first and second light-emitting parts EM1 and EM2 may receive the low-potential voltage from different lines.

[0088] Accordingly, the display panel 100 according to an embodiment of the present disclosure can automatically detect a repair target for a repair process by checking whether the light-emitting part emits light. Specifically, it is possible to check whether the light-emitting part driven by one of the first low-potential voltage line EVSSL1 and the second low-potential voltage line EVSSL2 emits light. For example, if the light-emitting part driven by the first low-potential voltage line EVSSL1 emits light normally and the light-emitting part driven by the second low-potential voltage line EVSSL2 does not emit light, it can be determined that the light-emitting part connected to the second low-potential voltage line EVSSL2 has a fault.

[0089] The first and second cathodes CAT1 and CAT2 may include a conductor material. As an example, the first and second cathodes CAT1 and CAT2 may include, but are not limited to, a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may include an opaque conductor material such as metal. Furthermore, the first and second cathodes CAT1 and CAT2 may include, but are not limited to, the same material.

[0090] Fig. 4 is a cross-sectional view taken along the line AA' of Fig. 3, according to one embodiment. That is, Fig. 4 is a cross-sectional view of a subpixel SP.

[0091] With reference to Fig. 4, a sub-pixel SP according to an embodiment of the present invention may include a substrate 110, an interlayer insulation layer 115, a thin film transistor 120, a passivation layer 130, a first connection electrode 141, a second connection electrode 142, a planarization layer 150, a first light-emitting device 160, and a second light-emitting device 170.

[0092] The substrate 110 may be made of, but is not limited to, glass, plastic, metal, or a flexible thin polymer film. The display device according to an embodiment of the present invention may be configured as a top emission type in which the emitted light is emitted upward, a bottom emission type in which the emitted light is emitted downward, or a dual emission type. Accordingly, not only a transparent material but also an opaque material may be used as the material of the substrate 110.

[0093] The thin-film transistor 120 may be arranged on the substrate 110. The thin-film transistor 120 may include a gate electrode 121, a semiconductor layer 122, a gate insulation layer 123, a source electrode 124, and a drain electrode 125. Although Fig. While FIG. 4 illustrates that the thin-film transistor 120 is disposed in the first light-emitting part EM1, the present invention is not limited thereto. As an example, the thin-film transistor 120 may be disposed in the opening OP or the second light-emitting part EM2, but is not limited thereto.

[0094] The gate electrode 121 of the thin-film transistor 120 may be disposed on the substrate 110. Furthermore, the semiconductor layer 122 may be disposed on the gate electrode 121. The semiconductor layer 122 may include, but is not limited to, a polysilicon semiconductor, an oxide semiconductor, an amorphous silicon semiconductor (a-Si semiconductor), a compound semiconductor, or an organic semiconductor. Additionally, when the semiconductor layer 122 includes an oxide semiconductor, it may include at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0095] To isolate the gate electrode 121 from the semiconductor layer 122, a gate insulation layer 123 may be disposed between the gate electrode 121 and the semiconductor layer 122. The gate insulation layer 123 may include a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Furthermore, Fig. 4 illustrates a bottom-gate structure in which a semiconductor layer 122 is disposed on a gate electrode 121, but is not limited thereto. For example, a top-gate structure in which the gate electrode 121 is disposed on the semiconductor layer 122 may be disclosed.

[0096] The source electrode 124 and the drain electrode 125 may be disposed on the semiconductor layer 122 while facing each other. Furthermore, the first low-potential voltage line EVSSL1 may be disposed on the same layer as the source electrode 124 and the drain electrode 125. The source electrode 124, the drain electrode 125, and the first low-potential voltage line EVSSL1 may be formed by the same process. Embodiments are not limited to this. As an example, the first low-potential voltage line EVSSL1 may be disposed on a different layer than the source electrode 124 and the drain electrode 125 and / or may be formed by a different process than the source electrode 124 and the drain electrode 125.

[0097] The interlayer insulation layer 115 may be disposed on the source electrode 124, the drain electrode 125, and the first low-potential voltage line EVSSL1. A contact hole exposing a portion of the drain electrode 125 may be formed in the interlayer insulation layer 115. Furthermore, the interlayer insulation layer 115 may be formed from an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

[0098] The passivation layer 130 may be disposed on the thin-film transistor 120 and may be disposed in the first and second light-emitting portions EM1 and EM2 and the opening OP. Furthermore, the passivation layer 130 may include a first passivation layer and a second passivation layer 131 and 132.

[0099] The first passivation layer 131 may be disposed on the thin-film transistor 120, and the second passivation layer 132 may be disposed on the first passivation layer 131. The first and second passivation layers 131 and 132 may compensate for a step difference caused by the thin-film transistor 120 to flatten the upper region of the thin-film transistor 120. Furthermore, the first and second passivation layers 131 and 132 may be formed of an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0100] The planarization layer 150 may be disposed on the second passivation layer 132. The planarization layer 150 may include a first planarization layer and a second planarization layer 151 and 152. The first planarization layer 151 may be disposed in the first light-emitting part EM1, and the second planarization layer 152 may be disposed in the second light-emitting part EM2. Furthermore, the first and second planarization layers 151 and 152 may be spaced apart from each other by the opening OP.

[0101] Each of the first and second planarization layers 151 and 152 may include a lower layer 151a and 152a and an upper layer 151b and 152b. The lower layer 151a and 152a may be disposed on the second passivation layer 132, and the upper layer 151b and 152b may be disposed on the lower layers 151a and 152a.

[0102] Each of the first and second planarization layers 151 and 152 may have an undercut UC in a side surface of each of the first and second planarization layers 151 and 152 adjacent to the opening OP. Specifically, an area of ​​an upper surface of the lower layers 151a and 152a may be smaller than an area of ​​a lower surface of the upper layers 151b and 152b. Furthermore, one side of the upper layers 151b and 152b protrudes from the lower layers 151a and 152a, and thus the lower surface of the upper layers 151b and 152b may be exposed to the outside. Furthermore, a side surface of the lower layers 151a and 152a may have an inverted conical shape, and a side surface of the upper layers 151b and 152b may have a conical shape.

[0103] The first and second planarization layers 151 and 152 may be formed of an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0104] The first light-emitting device 160 may be disposed on the first planarization layer 151. The first light-emitting device 160 may include a first electrode 161, a light-emitting layer 162, and a second electrode 163.

[0105] The first electrode 161 is disposed on the first planarization layer 151 and may function as an anode of the display device. The first electrode 161 may be electrically connected to the drain electrode 125 of the thin-film transistor 120. As an example, the first electrode 161 may be electrically connected to the drain electrode 125 of the thin-film transistor 120 through the first connection electrode 141 disposed on the first passivation layer 131. Embodiments are not limited to this. As an example, the first connection electrode 141 may be omitted depending on the design. In this case, the first electrode 161 may be directly connected to the drain electrode 125 of the thin-film transistor 120, but this is not limited to this.

[0106] The first electrode 161 may include a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first electrode 161 may include a metal material such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr), or an alloy thereof. Furthermore, although illustrated as a single layer, the first electrode 161 may be formed from multiple layers.

[0107] Bank 180 may be disposed on the first planarization layer 151 and the first electrode 161. Bank 180 may define a light-emitting area and a non-light-emitting area of ​​the first light-emitting part EM1. That is, an area where bank 180 is not disposed may be the light-emitting area, and an area where bank 180 is disposed may be a non-light-emitting area.

[0108] The bank 180 may contain an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. Alternatively, the bank 750 may contain an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy). Furthermore, the bank 180 may contain a black dye to absorb light incident from the outside.

[0109] The light-emitting layer 162 may be disposed on the first electrode 161. The light-emitting layer 162 may also be disposed on an upper surface of the bank 180. Furthermore, the light-emitting layer 162 may extend from the upper surface of the bank 180 and be disposed on a side surface of the bank 180 adjacent to the opening OP and a side surface of the upper layer 151b of the first planarization layer 151. In this case, since the first planarization layer 151 has the undercut UC, the light-emitting layer 162 need not be disposed on a side surface of the lower layer 151a.

[0110] The light-emitting layer 162 may include a hole-transport layer, an organic emission layer, and an electron-transport layer. In this case, when a voltage is applied to the first electrode 161 and the second electrode 163, holes and electrons move to the organic emission layer via the hole-transport layer and the electron-transport layer, respectively, and may combine with each other in the organic emission layer to emit light. Embodiments are not limited to this. As an example, the hole-transport layer and / or the electron-transport layer may be omitted depending on the design and / or one or more additional layers may be further included.

[0111] The second electrode 163 may be disposed on the light-emitting layer 162. The second electrode 163 may function as a cathode of the display device. Like the light-emitting layer 162, the second electrode 163 may also be disposed on the upper surface of the bank 180. Furthermore, the second electrode 163 may extend from the upper surface of the bank 180 and be disposed on the side surface of the bank 180 adjacent to the opening OP and the side surface of the upper layer 151b of the first planarization layer 151. In this case, since the first planarization layer 151 has the undercut UC, the second electrode 163 need not be disposed on the side surface of the lower layer 151a.

[0112] Since the display device according to an embodiment of the present invention is configured in the top-emitting type, the second electrode 163 may include a transparent conductor material such as an indium tin oxide (ITO) or an indium zinc oxide (IZO) to guide the light emitted from the light-emitting layer 162 to an upper portion of the display device.

[0113] The second light-emitting device 170 may be disposed on the second planarization layer 152. The second light-emitting device 170 may include a first electrode 171, a light-emitting layer 172, and a second electrode 173. Since the second light-emitting device 170 has the same structure as the first light-emitting device 160, its detailed description will be omitted. Furthermore, the first electrode 171 may be electrically connected to the drain electrode 125 of the thin-film transistor 120 through the second connection electrode 142 disposed on the first passivation layer 131. The second connection electrode 142 may be spaced apart from the first connection electrode 141, but is not limited thereto. As an example, the second connection electrode 142 may be connected to the first connection electrode 141 or may be integrated with it.

[0114] Meanwhile, the first electrodes 161 and 171 of the first and second light-emitting devices 160 and 170 may be electrically connected to the drain electrode 125 of the same thin-film transistor 120. On the other hand, the light-emitting layers 162 and 172 of the first and second light-emitting devices 160 and 170 may be spaced apart from each other by the opening OP. Furthermore, the second electrodes 163 and 173 of the first and second light-emitting devices 160 and 170 may be spaced apart from each other by the opening OP. Accordingly, the first electrodes 161 and 171 of the first and second light-emitting devices 160 and 170 may not be electrically connected to each other or may be electrically connected to each other, for example, via the first and second connection electrodes 141, 142 and the drain electrode 125 of the thin-film transistor 120, but are not limited thereto.

[0115] A placeholder layer D may be disposed on the second passivation layer 132 and disposed in the opening OP. Furthermore, the placeholder layer D may be spaced apart from the planarization layer 151 and need not overlap with the undercut UC. The placeholder layer D may include a first placeholder layer D1 and a second placeholder layer D2. The first placeholder layer D1 may be disposed on the second passivation layer 132, and the second placeholder layer D2 may be disposed on the first placeholder layer D1.

[0116] The first placeholder layer D1 may contain the same material as the light-emitting layers 162 and 172. Specifically, in the process of forming the light-emitting layers 162 and 172, a light-emitting material may be deposited on the substrate 110. In this case, due to the undercut UC and the opening OP, the light-emitting material does not need to be deposited on the entire surface of the substrate 110. Accordingly, the light-emitting material deposited in such a manner as to be spaced apart from the light-emitting layers 162 and 172 remains in the opening OP, and the light-emitting material remaining in the opening OP may become the first placeholder layer D1.

[0117] The second placeholder layer D2 may include the same material as the second electrodes 163 and 173. Specifically, in the process of forming the second electrodes 163 and 173, a conductor material may be deposited on the substrate 110. In this case, due to the undercut UC and the opening OP, the conductor material does not need to be deposited on the entire surface of the substrate 110. Accordingly, the conductor material deposited such that it is spaced apart from the second electrodes 163 and 173 remains in the opening OP, and the conductor material remaining in the opening OP may become the second placeholder layer D2.

[0118] Fig. 5 is a cross-sectional view taken along the line BB' of Fig. 3, according to one embodiment. That is, Fig. 5 is a cross-sectional view of a contact surface CA and the first light-emitting part EM1.

[0119] With reference to Fig. 5, a portion of the first low-potential line EVSSL1 or a portion extending from one side of the first low-potential line EVSSL1 may be disposed in the contact area CA. As described above, the first low-potential line EVSSL1 may be disposed at the same layer as the source electrode 124 and the drain electrode 125.

[0120] A third connection electrode 143 is disposed on the first passivation layer 131. As an example, the third connection electrode 143 may be formed by the same process as the first and second connection electrodes 141 and 142, or may be formed by a separate process from the first and second connection electrodes 141 and 142, but is not limited thereto. The third connection electrode 143 may be electrically connected to the first low-potential line EVSSL1 through a contact hole formed in the first passivation layer 131.

[0121] A first contact portion CT1 may be disposed in the second passivation layer 132. The first contact portion CT1 may expose a portion or the entirety of an upper surface of the third connection electrode 143.

[0122] A spacer 190 may be disposed on the third connection electrode 143. The spacer 190 may include a first spacer 191 and a second spacer 192. The first spacer 191 may be disposed on the third connection electrode 143, and the second spacer 192 may be disposed on the first spacer 191.

[0123] The first spacer 191 is disposed in the first contact portion CT1 and may be in contact with a portion of the upper surface of the third connection electrode 143. That is, an area of ​​a lower surface of the first spacer 191 may be smaller than an area of ​​the upper surface of the third connection electrode 143 exposed through the second passivation layer 132. Furthermore, an area of ​​a lower surface of the second spacer 192 may be larger than an area of ​​an upper surface of the first spacer 191. That is, an edge of the second spacer 192 may protrude from the first spacer 191, and a portion of the lower surface of the second spacer 192 may be exposed to the outside.

[0124] The light-emitting layer 162 and the second electrode 163 arranged in the first light-emitting part EM1 may extend to the contact area CA. The light-emitting layer 162 may cover side surfaces of the first planarization layer 151 and the second passivation layer 132 adjacent to the contact area CA. Furthermore, the light-emitting layer 162 may be arranged in the first contact part CT1. Furthermore, the light-emitting layer 162 may cover only a partial area of ​​the upper surface of the third connection electrode 143 exposed by the second passivation layer 132.

[0125] Likewise, the second electrode 163 may cover side surfaces of the first planarization layer 151 and the second passivation layer 132 adjacent to the contact area CA. Furthermore, the second electrode 163 may be arranged in the first contact portion CT1. Furthermore, the second electrode 163 may cover at least a portion or the entirety of the third connection electrode 143 exposed through the light-emitting layer 162. Accordingly, the second electrode 163 may be in contact with the third connection electrode 143 through the first contact portion CT1. That is, the second electrode 163 may be electrically connected to the first low-potential line EVSSL1 through the third connection electrode 143. Likewise, although Fig. 5 is not illustrated, the second electrode 173 of the second light-emitting device 170 may also be electrically connected to the second low-potential line EVSSL2 through a second contact portion CT2.

[0126] A light-emitting material layer 162a and a conductor material layer 163a may be disposed on the spacer 190. The light-emitting material layer 162a and the conductor material layer 163a may be disposed on a top surface and a side surface of the second spacer 192.

[0127] The light-emitting material layer 162a may contain the same material as the light-emitting layer 162. Specifically, in the process of forming the light-emitting layer 162, a light-emitting material may be deposited on the substrate 110. In this case, the light-emitting material does not need to be deposited on the entire surface of the substrate 110 through the spacer 190. Accordingly, the light-emitting material deposited in such a manner as to be spaced apart from the light-emitting layer 162 remains on the spacer 190, and the light-emitting material remaining on the spacer 190 may become the light-emitting material layer 162a.

[0128] The conductor material layer 163a may include the same material as the second electrode 163. Specifically, in the process of forming the second electrode 163, a conductor material may be deposited on the substrate 110. In this case, the conductor material does not need to be deposited on the entire surface of the substrate 110 through the spacer 190. Accordingly, the conductor material deposited to be spaced apart from the second electrode 163 may remain on the spacer 190, and the conductor material remaining on the spacer 190 may become the conductor material layer 163a.

[0129] Fig. 6 is a circuit diagram of a sub-pixel SP according to an embodiment of the present disclosure.

[0130] The sub-pixel SP may include a plurality of transistors ST1, ST2, and DT, a plurality of light-emitting devices LED1 and LED2, and a plurality of capacitors C1 and C2. A plurality of transistors ST1, ST2, and DT may include first and second switching transistors ST1 and ST2 and a driving transistor DT. Embodiments are not limited thereto. As an example, at least one of the above-mentioned components may be omitted, or one or more additional components may be further included. As an example, one or more transistors, light-emitting devices, and capacitors may be further included.

[0131] Each of the plurality of transistors ST1, ST2, and DT of the sub-pixel SP includes a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode are not fixed and can be changed according to the voltage and current directions applied to the gate electrode, one of the source electrode and the drain electrode can be expressed as the first electrode, and the other can be expressed as the second electrode.

[0132] The first and second switching transistors ST1 and ST2 may operate according to a scanning signal SCAN. When the scanning signal SCAN is the gate-on voltage, the first switching transistor ST1 may supply a data voltage Vdata to a first electrode of the first capacitor C1. Furthermore, when the scanning signal SCAN is the gate-on voltage, the second switching transistor ST2 may supply an initialization voltage Vref to a second electrode of the first capacitor C1. Although it is illustrated that the first and second switching transistors ST1 and ST2 may operate according to the same scanning signal SCAN, embodiments are not limited thereto. As an example, the first and second switching transistors ST1 and ST2 may operate according to different scanning signals and may operate at the same or different timings.

[0133] A high-potential voltage EVDD can be supplied to a first electrode of the drive transistor DT, and a second electrode of the drive transistor DT can be connected to the first and second light-emitting devices LED1 and LED2. The drive transistor DT can control the light intensity of the first and second light-emitting devices LED1 and LED2 by controlling a drive current Ids according to a drive voltage Vgs of the first capacitor C1.

[0134] The first capacitor C1 may be connected between the gate electrode and the first electrode of the drive transistor DT to charge the drive voltage Vgs corresponding to the data voltage Vdata. During the light emission period, the first capacitor C1 may maintain the charged drive voltage Vgs and supply the drive voltage Vgs to the drive transistor DT.

[0135] The first light-emitting device LED1 may include an anode connected to the driving transistor DT and a cathode supplied with the first low-potential voltage EVSS1. Furthermore, the second light-emitting device LED2 may include an anode connected to the driving transistor DT and a cathode supplied with the second low-potential voltage EVSS2. That is, the first and second light-emitting devices LED1 and LED2 may be controlled by the same driving transistor DT. Furthermore, the anodes of the first and second light-emitting devices LED1 and LED2 are connected at a second node n2, but the cathodes of the first and second light-emitting devices LED1 and LED2 need not be electrically connected to each other.

[0136] In this case, it is possible to check whether the first and second light-emitting devices LED1 and LED2 are operating normally through the first and second low-potential voltages EVSS1 and EVSS2.

[0137] Specifically, the first and second low-potential voltages EVSS1 and EVSS2 can be set to different voltage values. For example, the first low-potential voltage EVSS1 can be set to 10 V, and the second low-potential voltage EVSS2 can be set to 0 V. In this case, it is possible to check whether the first light-emitting device LED1 connected to the first low-potential voltage EVSS1 is operating normally.

[0138] In addition, the second node n2, to which the drive transistor DT and the first and second light-emitting devices LED1 and LED2 are connected, can be charged with an arbitrary voltage. That is, the source electrode of the drive transistor DT can be charged with the arbitrary voltage. And, after an arbitrary time has elapsed, a voltage change amount of the second node n2 can be detected by a sensing unit SENSE to check whether the first light-emitting device LED1 is normal or not.

[0139] Fig. 7 is a graph illustrating the amount of change in the voltage of the second node n2 according to one embodiment. Fig. 7 illustrates the amount of change in the voltage of the second node n2 after a test voltage V0 is applied to the source electrode of the drive transistor DT and then a test time t0 has elapsed.

[0140] A first graph G1 illustrates a case where the light-emitting device is driven normally. When the light-emitting device is driven normally, the test voltage V0 applied to the source electrode of the drive transistor DT can be maintained stably.

[0141] On the other hand, a second graph G2 and a third graph G3 illustrate a case where the light-emitting device is not driven normally. When the light-emitting device is not driven normally, the voltage applied to the source electrode of the driving transistor DT may be discharged. In this case, the smaller the resistance of the light-emitting device, the faster the voltage can be discharged. That is, the resistance of the light-emitting device may be relatively smaller in the third graph G3 than in the second graph G2.

[0142] Accordingly, by forming the first and second low-potential voltage lines EVSSL1 and EVSSL2 instead of one low-potential voltage line by applying the first and second low-potential voltages EVSS1 and EVSS2 to each of the first and second light-emitting devices LED1 and LED2, it is possible to check whether the sub-pixel is normal.

[0143] As described above, after checking whether the sub-pixel is normal, a repair process can be performed. Specifically, Fig. 8 shows the repair process when the first light-emitting device 160 is not driven normally. Referring to Fig. 8, the first connection electrode 141 can be separated by a laser process. Accordingly, the first electrode 161 of the first light-emitting device 160 does not need to be electrically connected to the drain electrode 125 of the thin-film transistor 120. Accordingly, the first light-emitting device 160 cannot emit light.

[0144] On the other hand, the second light-emitting device 170 may be electrically connected to the drain electrode 125 of the thin-film transistor 120 through the second connection electrode 142. Accordingly, the second light-emitting device 170 may emit light. That is, even if the first light-emitting device 160 does not emit light, the sub-pixel may emit light through the second light-emitting device 170. Accordingly, the sub-pixel may be driven normally.

[0145] Fig. 9 is a diagram illustrating a portion of a display device according to an embodiment of the present disclosure.

[0146] With reference to Fig. 9, the display device may include a transmissive surface TA and a non-transmissive surface NTA. The transmissive surface TA may be a surface that transmits most of the light incident from the outside, that is, external light, and the non-transmissive surface NTA may be a surface that does not transmit most of the light incident from the outside. For example, the transmissive surface TA may be a surface having a light transmittance greater than a%, and the non-transmissive surface NTA may be a surface having a light transmittance less than b%. In this case, a may be a value greater than b. The display device according to an embodiment of the present invention can view an object or background positioned on the back surface (or the bottom surface) of the display panel 100 through the transmissive surface TA.

[0147] The non-transparent area NTA may contain a plurality of pixels P, a first non-transparent area NTA1 and a second non-transparent area NTA2.

[0148] Each pixel P is located in each area where the first non-transmissive area NTA1 and the second non-transmissive area NTA2 intersect, and can emit light to display an image. Each pixel P can contain multiple sub-pixels SP1, SP2, SP3, and SP4.

[0149] The transmissive area TA may be adjacent to the pixel P in a first direction X. That is, the transmissive area TA may be adjacent to the plurality of sub-pixels SP1, SP2, SP3, and SP4 in the first direction X. Furthermore, the plurality of sub-pixels SP1, SP2, SP3, and SP4 in each pixel P may be adjacent to each other in a second direction Y.

[0150] Each pixel P may include a light-emitting area EM that emits light corresponding to the plurality of sub-pixels SP1, SP2, SP3, and SP4 that include a light-emitting device. The light-emitting area EM may be an area that emits light from the pixel P. Furthermore, the light-emitting area EM may overlap with a pixel circuit of the plurality of sub-pixels SP1, SP2, SP3, and SP4.

[0151] The light-emitting surfaces EM corresponding to the plurality of sub-pixels SP1, SP2, SP3, and SP4 may all emit light of different colors, or the light-emitting surfaces EM corresponding to two or more of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may emit light of the same color, but this is not limited to this. For example, the light-emitting surface EM of the first sub-pixel SP1 may emit green light, the light-emitting surface EM of the second sub-pixel SP2 may emit blue light, the light-emitting surface EM of the third sub-pixel SP3 may emit white light, and the light-emitting surface EM of the fourth sub-pixel SP4 may emit red light.

[0152] The plurality of sub-pixels SP1, SP2, SP3, and SP4 may be configured in a stripe type arranged in the second direction Y or a quadruple type arranged in the first and second directions X and Y, but are not limited thereto.

[0153] The first non-transmissive surface NTA1 may extend in the second direction Y in the display panel 100 and may be arranged to at least partially overlap the light-emitting surface EM of each of the sub-pixels SP1, SP2, SP3, and SP4. A plurality of first non-transmissive surfaces NTA1 may be configured. The plurality of first non-transmissive surfaces NTA1 may be arranged to be spaced apart from each other in the first direction X and may extend in the second direction Y. Two adjacent first non-transmissive surfaces NTA1 may be arranged to be spaced apart from each other, with the transmissive surface TA interposed therebetween. For example, the transmissive surface TA may be between two adjacent first non-transmissive surfaces NTA1.

[0154] At least one first signal line extending in the second direction Y may be arranged in the first non-transmissive area NTA1. Additionally, at least one first signal line may overlap with the first non-transmissive area NTA1. The at least one first signal line may include, but is not limited to, at least one of a high-potential power supply line, a low-potential power supply line, and a data line.

[0155] The second non-transmissive surface NTA2 may extend in the first direction X in the display panel 100 and may be arranged to at least partially overlap the light-emitting surface EM of each of the sub-pixels SP1, SP2, SP3, and SP4, or may be arranged to not overlap the light-emitting surface EM of each of the sub-pixels SP1, SP2, SP3, and SP4, but is not limited thereto. A plurality of second non-transmissive surfaces NTA2 may be configured. The plurality of second non-transmissive surfaces NTA2 may extend in the first direction X and may be arranged to be spaced apart from each other in the second direction Y. Two adjacent second non-transmissive surfaces NTA2 may be arranged to be spaced apart from each other with the transmissive surface TA interposed therebetween.For example, the permeable area TA between two adjacent second non-permeable areas NTA2 may be.

[0156] At least one second signal line extending in the first direction X may be arranged in the second non-transmissive area NTA2. Furthermore, at least one second signal line may include, but is not limited to, a scan line SL (or a gate line).

[0157] Fig. 10 is a view showing a surface I, which in Fig. 9, according to an embodiment of the present disclosure.

[0158] With reference to Fig. 10, the display device according to an embodiment of the present invention may include a plurality of sub-pixels SP1, SP2, SP3 and SP4, a first low-potential voltage line EVSSL1 and a second low-potential voltage line EVSSL2.

[0159] As an example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 are arranged under the plurality of sub-pixels SP1, SP2, SP3, and SP4, and the plurality of sub-pixels SP may overlap with the first and second low-potential voltage lines EVSSL1 and EVSSL2. Additionally, each of the first and second low-potential voltage lines EVSSL1 and EVSSL2 may extend in the second direction Y. That is, one low-potential voltage line EVSSL may overlap with the plurality of sub-pixels SP1, SP2, SP3, and SP4 that emit light of different colors. Furthermore, Fig. 10, the first and second low-potential voltage lines EVSSL1 and EVSSL2 are adjacent to a left end of the sub-pixel SP, but are not limited thereto. For example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 may be adjacent to a right end of the sub-pixel SP or the center portion of the sub-pixel SP, but are not limited thereto. As an example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 do not need to overlap with the sub-pixel SP. As an example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 may overlap with the transmissive area TA. As an example, the first and second low-potential voltage lines EVSSL1 and EVSSL2 may comprise, but are not limited to, a transparent conductor material or an opaque conductor material.

[0160] Each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first light-emitting part EM11, EM21, EM31, or EM41, a second light-emitting part EM12, EM22, EM32, or EM42, or an opening OP. Each of the first light-emitting parts EM11, EM21, EM31, or EM41 or the second light-emitting parts EM12, EM22, EM32, or EM42 includes a light-emitting device and can emit light. In addition, the first light-emitting parts EM11, EM21, EM31, or EM41 and the second light-emitting parts EM12, EM22, EM32, or EM42 of a sub-pixel SP may emit light of the same color. In a sub-pixel SP, the opening OP is arranged between the first light-emitting parts EM11, EM21, EM31 or EM41 and the second light-emitting parts EM12, EM22, EM32 or EM42 to separate the first light-emitting parts EM11, EM21, EM31 or EM41 and the second light-emitting parts EM12, EM22, EM32 or EM42.Furthermore, the opening OP does not need to contain a light-emitting device.

[0161] A subpixel SP may receive the first and second low-potential voltages EVSS1 and EVSS2 from the first and second low-potential voltage lines EVSSL1 and EVSSL2. Additionally, a subpixel SP may overlap with one of the first and second low-potential voltage lines EVSSL1 and EVSSL2 and may be spaced apart from the other.

[0162] For example, the first sub-pixel SP1 may overlap with the first low-potential voltage line EVSSL1 and may be spaced apart from the second low-potential power supply line EVSSL2. Additionally, the second sub-pixel SP2 may overlap with the second low-potential voltage line EVSSL2 and may be spaced apart from the first low-potential voltage line EVSSL1. Additionally, the third sub-pixel SP3 may overlap with the first low-potential voltage line EVSSL1 and may be spaced apart from the second low-potential voltage line EVSSL2. That is, the sub-pixel SP that overlaps with the first low-potential voltage line EVSSL1 and the sub-pixel SP that overlaps with the second low-potential voltage line EVSSL2 may be arranged alternately.

[0163] The first light-emitting part EM11 of the first sub-pixel SP1 overlaps with the first low-potential voltage line EVSSL1, and the second light-emitting part EM12 of the first sub-pixel SP1 may be spaced apart from the first and second low-potential voltage lines EVSSL1 and EVSSL2. Furthermore, the first light-emitting part EM21 of the second sub-pixel SP2 overlaps with the second low-potential voltage line EVSSL2, and the second light-emitting part EM22 of the second sub-pixel SP2 may be spaced apart from the first and second low-potential voltage lines EVSSL1 and EVSSL2.

[0164] Each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first anode ANO1 and a second anode ANO2. In each of the plurality of sub-pixels SP1, SP2, SP3, and SP4, the first anode ANO1 may be disposed in the first light-emitting portions EM11, EM21, EM31, and EM41, and the second anode ANO2 may be disposed in the second light-emitting portions EM12, EM22, EM32, and EM42. The first anode ANO1 and the second anode ANO2 may be spaced apart from each other, with the opening OP disposed therebetween.

[0165] Each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a sub-electrode SE. The sub-electrode SE may include a first sub-electrode SE1 and a second sub-electrode SE2.

[0166] The first sub-electrode SE1 can electrically connect the first anode ANO1 to the source / drain electrode S / D of the drive transistor. Specifically, one side of the first sub-electrode SE1 can be electrically connected to the first anode ANO1 through a first sub-contact hole SCNT1, and the other side of the first sub-electrode SE1 can be electrically connected to the source / drain electrode S / D of the drive transistor.

[0167] The second sub-electrode SE2 may electrically connect the second anode ANO2 to the source / drain electrode S / D of the drive transistor. Specifically, one side of the second sub-electrode SE2 may be electrically connected to the second anode ANO2 through a second sub-contact hole SCNT2, and the other side of the second sub-electrode SE2 may be electrically connected to the source / drain electrode S / D of the drive transistor.

[0168] When a particle is formed in one of the first anode ANO1 and the second anode ANO2, the sub-electrode SE can separate or break an electrical connection between the anode where the particle is formed and the source / drain electrode S / D of the drive transistor.

[0169] Specifically, one of the first anode ANO1 and the second anode ANO2 in which the particle is formed may be electrically separated or interrupted from the sub-electrode SE, and the other anode of the first anode ANO1 and the second anode ANO2 in which the particle is not formed may be electrically connected to the source / drain electrode S / D of the drive transistor through the sub-electrode SE.

[0170] Accordingly, one of the first anode ANO1 and the second anode ANO2 in which the particle is formed can be darkened, and the other anode can be driven normally. Accordingly, the sub-pixel in which the particle is formed can be repaired by the sub-electrode SE.

[0171] The cathode CAT may include a first cathode CAT1 and a second cathode CAT2. The first cathode CAT1 may be arranged on the first low-potential voltage line EVSSL1. Furthermore, the second cathode CAT2 may be arranged on the second low-potential voltage line EVSSL2. The first and second cathodes CAT1 and CAT2 may be spaced apart from each other by an area that overlaps the opening OP.

[0172] The first low-potential voltage line EVSSL1 may include a first contact portion CT1 formed to extend to one side of the first low-potential voltage line EVSSL1. The first low-potential voltage line EVSSL1 may be electrically connected to the first cathode CAT1 through the first contact portion CT1. Furthermore, the second low-potential voltage line EVSSL2 may include a second contact portion CT2 formed to extend to one side of the second low-potential voltage line EVSSL2. The second low-potential voltage line EVSSL2 may be electrically connected to the second cathode CAT2 through the second contact portion CT2.

[0173] As an example, a sub-pixel SP may include both the first cathode CAT1, which receives the first low-potential voltage EVSS1 from the first low-potential voltage line EVSSL1, and the second cathode CAT2, which receives the second low-potential voltage EVSS2 from the second low-potential voltage line EVSSL2. As an example, the first and second light-emitting parts EM1 and EM2 of a sub-pixel may receive the low-potential voltage from different lines.

[0174] Accordingly, the display panel 100 according to an embodiment of the present invention can automatically detect a repair target for a repair process by checking whether the light-emitting part emits light. Specifically, it is possible to check whether the light-emitting part driven by one of the first low-potential voltage line EVSSL1 and the second low-potential voltage line EVSSL2 emits light. For example, if the light-emitting part driven by the first low-potential voltage line EVSSL1 emits light normally and the light-emitting part driven by the second low-potential voltage line EVSSL2 does not emit light, it can be determined that the light-emitting part connected to the second low-potential voltage line EVSSL2 has a fault.

[0175] The first and second cathodes CAT1 and CAT2 may contain a transparent conductor material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Furthermore, the first and second cathodes CAT1 and CAT2 may contain the same material, but are not limited to this.

[0176] Fig. 11 is a cross-sectional view taken along the line CC' of Fig. 10, according to one embodiment. Specifically, Fig. 11 a cross-sectional view of the first subpixel SP1.

[0177] With reference to Fig. 11, the first sub-pixel SP1 may include a substrate SUB, a buffer layer BUF, an interlayer insulation layer ILD, a first passivation layer PAS1, a second passivation layer PAS2, a planarization layer OC, a bank BNK, a first light-emitting device ED1, and a second light-emitting device ED2.

[0178] The buffer layer BUF, the intermediate insulation layer ILD, the first passivation layer PAS1, the second passivation layer PAS2, and the planarization layer OC can be arranged sequentially on the substrate SUB. Each of the buffer layer BUF, the intermediate insulation layer ILD, the first passivation layer PAS1, the second passivation layer PAS2, and the planarization layer OC can be formed from an inorganic insulating material or an organic insulating material.

[0179] In this case, an undercut UC may be formed by the second passivation layer PAS2 and the planarization layer OC. Specifically, an area of ​​an upper surface of the second passivation layer PAS2 may be smaller than an area of ​​a lower surface of the planarization layer OC. Furthermore, one side of the planarization layer OC protrudes from the second passivation layer PAS2, such that the lower surface of the planarization layer OC may be exposed to the outside. Furthermore, a side surface of the second passivation layer PAS2 may have an inverted cone shape, and a side surface of the planarization layer OC may have a cone shape.

[0180] The first light-emitting device ED1 and the second light-emitting device ED2 may be arranged on the planarization layer OC. The first light-emitting device ED1 may include a first anode ANO1, a light-emitting layer EL, and a first cathode CAT1. Furthermore, the second light-emitting device ED2 may include a second anode ANO2, a light-emitting layer EL, and a second cathode CAT2.

[0181] The light-emitting layer EL may extend from a top surface of the bank BNK and may also be formed on a side surface of the bank BNK and a side surface of the planarization layer OC adjacent to the opening OP. Furthermore, the light-emitting layer EL need not be formed on a side surface of the second passivation layer PAS2 due to the undercut UC.

[0182] Similar to the light-emitting layer EL, the first cathode CAT1 and the second cathode CAT2 may extend from the top surface of the bank BNK and may also be formed on the side surface of the bank BNK and the side surface of the planarization layer OC adjacent to the opening OP. Furthermore, the first cathode CAT1 and the second cathode CAT2 do not need to be formed on the side surface of the second passivation layer PAS2 due to the undercut UC.

[0183] The placeholder layer D can be arranged on the first passivation layer PAS1 and can be arranged in the opening OP. Furthermore, the placeholder layer D can be spaced apart from the second passivation layer PAS2 and does not have to overlap with the undercut UC. The placeholder layer D can include a first and a second placeholder layer D1 and D2. The first placeholder layer D1 can be arranged on the first passivation layer PAS1, and the second placeholder layer D2 can be arranged on the first placeholder layer D1.

[0184] The first placeholder layer D1 may contain the same material as the light-emitting layer EL. Specifically, during the process of forming the light-emitting layer EL, a light-emitting material may be deposited on the substrate SUB. In this case, due to the undercut UC and the opening OP, the light-emitting material does not need to be deposited on the entire surface of the substrate SUB. Accordingly, the light-emitting material deposited in such a manner that it is spaced apart from the light-emitting layer EL remains in the opening OP, and the light-emitting material remaining in the opening OP may become the first placeholder layer D1.

[0185] The second placeholder layer D2 may contain the same material as the first cathode CAT1 and the second cathode CAT2. Specifically, during the process of forming the first cathode CAT1 and the second cathode CAT2, a conductor material may be deposited on the substrate SUB. In this case, due to the undercut UC and the opening OP, the conductor material does not need to be deposited on the entire surface of the substrate SUB. Accordingly, the conductor material deposited in such a way that it is spaced apart from the first cathode CAT1 and the second cathode CAT2 remains in the opening OP, and the conductor material remaining in the opening OP may become the second placeholder layer D2.

[0186] Fig. 12 and Fig. 13 are cross-sectional views taken along the line DD' of Fig. 10, according to various embodiments. Specifically, Fig. 12 and Fig. 13 a cross-sectional view of the first contact portion CT1.

[0187] With reference to Fig. 12 and Fig. 13, a contact electrode CTE may be arranged on the insulation interlayer ILD. The contact electrode CTE may be electrically connected to the first low-potential voltage line EVSSL1 via a connecting electrode CE. Fig. 12 shows that the contact electrode CTE, the connection electrode CE and the first low-potential voltage line EVSSL1 are formed on the same layer, but they are not limited to this.

[0188] A first contact portion CT1 may be arranged on the first passivation layer PAS1. The first contact portion CT1 may expose a portion of an upper surface of the contact electrode CTE.

[0189] With reference to Fig. 12, a coating CLD may be disposed on the contact electrode CTE exposed by the first contact part CT1. The coating CLD reduces or prevents, or at least reduces, damage to the contact electrode CTE and may stably connect the contact electrode CTE to the first cathode CAT1. As an example, the coating CLD may cover the entire upper surface of the contact electrode CTE exposed by the first contact part CT1. As an example, the coating CLD may extend to an upper surface of the first passivation layer PAS1 and may be disposed between the first passivation layer PAS1 and the second passivation layer PAS2, but is not limited thereto. As an example, the coating CLD may comprise a conductor material. Alternatively, as in Fig. 13, the structure of the CLD coating may be omitted.

[0190] A spacer SPC can be arranged on the coating CLD. Alternatively, as shown in Fig. 13, when the coating structure CLD is omitted, the spacer SPC may be arranged on the contact electrode CTE.

[0191] The spacer SPC may include a first spacer SPC1 and a second spacer SPC2. The first spacer SPC1 is formed in the first contact part CT1 and may be in contact with a portion of an upper surface of the coating CLD or a portion of the contact electrode CTE. An area of ​​a lower surface of the first spacer SPC1 may be smaller than an area of ​​the upper surface of the coating CLD exposed by the second passivation layer PAS2 or an area of ​​the upper surface of the contact electrode CTE exposed by the first contact part CT1. Furthermore, an area of ​​a lower surface of the second spacer SPC2 may be larger than an area of ​​an upper surface of the first spacer SPC1.For example, an edge of the second spacer SPC2 may protrude from the first spacer SPC1 and a part of the lower surface of the second spacer SPC2 may be exposed to the outside.

[0192] The light-emitting layer EL and the first cathode CAT formed in the first light-emitting part EM1 may extend to the first contact part CT1. The light-emitting layer EL covers only a partial area of ​​the coating CLD, and the first cathode CAT may cover the coating CLD exposed by the light-emitting layer EL. Alternatively, the light-emitting layer EL covers only a partial area of ​​the upper surface of the contact electrode CTE exposed by the first contact part CT1, and the first cathode CAT may cover the upper surface of the contact electrode CTE exposed by the light-emitting layer EL.

[0193] Accordingly, the first cathode CAT1 can be in contact with the coating CLD through the first contact part CT1. Alternatively, as shown in Fig. As shown in Figure 13, when the coating structure CLD is omitted, the first cathode CAT1 may be in contact with the contact electrode CTE. Accordingly, the first cathode CAT1 may be electrically connected to the first low-potential voltage line EVSSL1 through the contact electrode CTE and the connecting electrode CE.

[0194] A light-emitting material layer ELa and a conductor material layer CATa may be disposed on the spacer SPC. The light-emitting material layer ELa and the conductor material layer CATa may be disposed on the top and side surfaces of the second spacer SPC2.

[0195] The light-emitting material layer ELa may contain the same material as the light-emitting layer EL. Specifically, in the process of forming the light-emitting layer EL, a light-emitting material may be deposited on the substrate SUB. In this case, due to the spacer SPC, the light-emitting material does not need to be deposited on the entire surface of the substrate SUB. Accordingly, the light-emitting material deposited in such a way that it is spaced apart from the light-emitting layer EL remains on the spacer SPC, and the light-emitting material remaining on the spacer SPC may become the light-emitting material layer ELa.

[0196] The conductor material layer CATa may contain the same material as the first cathode CAT1. Specifically, during the process of forming the first cathode CAT1, a conductor material may be deposited on the substrate SUB. In this case, due to the spacer SPC, the conductor material does not need to be deposited on the entire surface of the substrate SUB. Accordingly, the conductor material deposited in such a way that it is spaced apart from the first cathode CAT1 remains on the spacer SPC, and the conductor material remaining on the spacer SPC may become the conductor material layer CATa.

[0197] Fig. 14 is a view showing an area II located in Fig. 10, according to an embodiment of the present disclosure. Specifically, Fig. 14 is a plan view of a subpixel SP and configurations of the first and second cathodes CAT1 and CAT2 are omitted. Fig. 15 is a cross-sectional view taken along the line EE' of Fig. 14, according to one embodiment and is Fig. 16 is a cross-sectional view taken along the line FF' of Fig. 14, according to one embodiment.

[0198] As described above, in Fig. 10 the first sub-electrode SE1 electrically connects the first anode ANO1 to the source / drain electrode S / D of the drive transistor.

[0199] With reference to Fig. 15, the first sub-electrode SE1 may be arranged on the first passivation layer PAS1. The first sub-electrode SE1 may be electrically connected to the first anode ANO1 through the first sub-contact hole SCNT1 formed in the second passivation layer PAS2 and the planarization layer OC.

[0200] With reference to Fig. 16, the source / drain electrode S / D may be arranged on the interlayer insulation layer ILD. The first sub-electrode SE1 may be electrically connected to the source / drain electrode S / D through the third sub-contact hole SCNT3 formed in the first passivation layer PAS1. Furthermore, the second sub-electrode SE2 may be electrically connected to the source / drain electrode S / D through the fourth sub-contact hole SCNT4 formed in the first passivation layer PAS1. Furthermore, the fourth sub-contact hole SCNT4 is spaced apart from the third sub-contact hole SCNT3.

[0201] Consequently, the source / drain electrode S / D of the drive transistor may be electrically connected to the first anode ANO1 and the second anode ANO2 through the sub-electrode SE.

[0202] Fig. 17 is a diagram illustrating multiple pixels of a display device according to an embodiment of the present disclosure.

[0203] With reference to Fig. 17, each of the plurality of pixels P may include a plurality of sub-pixels SP1, SP2, SP3, and SP4. In this case, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first light-emitting part EM11, EM21, EM31, or EM41 and a second light-emitting part EM12, EM22, EM32, or EM42 arranged in the first direction X.

[0204] As in Fig. As described in Figure 10, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first anode ANO1 arranged to correspond to the first light-emitting parts EM11, EM21, EM31, or EM41, and a second anode ANO2 arranged to correspond to the second light-emitting parts EM12, EM22, EM32, or EM42. As an example, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 discloses the first anode ANO1 and the second anode electrode ANO2 arranged in the first direction X.

[0205] In this case, the present invention discloses a plurality of first cathodes CAT1 arranged to correspond to the first anode ANO1, and a plurality of second cathodes CAT2 arranged to correspond to the second anode ANO2. As an example, the present invention discloses that the cathode has a plurality of divided regions corresponding to the arrangement structure of the divided anode electrodes, rather than a single shape covering the entire display panel. As an example, the first anode ANO1 and the second first anode ANO2 are divided in the first direction X, which crosses or intersects the second direction Y in which the first low-potential voltage line EVSSL1 and the second low-potential voltage line EVSSL2 extend. As an example, the first cathode CAT1 and the second cathode CAT2 are also divided in the first direction X.

[0206] Fig. 18 is a diagram illustrating a sub-pixel and a repair detector of a display device according to an embodiment of the present disclosure.

[0207] With reference to Fig. 18, the display device according to an embodiment of the present invention may include a repair detector RD electrically connected to a second node N2, which is a common node between the first light-emitting device ED1 and the second light-emitting device ED2.

[0208] As described above, the cathode CAT may include the first cathode CAT1 and the second cathode CAT2, which are separated to correspond to the first anode ANO1 and the second anode ANO2, respectively. As an example, the first anode ANO1 and the first cathode CAT1 may form the first light-emitting device ED1, and the second anode ANO2 and the second cathode CAT2 may form the second light-emitting device ED2.

[0209] The first low-potential voltage line EVSS1 can apply the first low-potential voltage EVSS1 to the first cathode CAT1 corresponding to the first anode ANO1, and the second low-potential voltage line EVSS2 can apply the second low-potential voltage EVSS2 to the second cathode CAT2 corresponding to the second anode ANO2.

[0210] The repair detector RD can simultaneously apply the first low-potential voltage EVSS1 and the second low-potential voltage EVSS2 to the first cathode CAT1 and the second cathode CAT2, respectively. In this case, the first low-potential voltage line EVSS1 can apply the first low-potential voltage EVSS1 to the first cathode CAT1, and the second low-potential voltage line EVSS2 can apply the second low-potential voltage EVSS2 to the second cathode CAT2.

[0211] Additionally, the repair detector RD can measure a voltage transmitted to the second node N2 (or the common node) between the first anode ANO1 and the second anode ANO2 via the first cathode CAT1 and the second cathode CAT2. Based on the measured voltage of the second node N2, the repair detector RD can detect whether one of the first anode ANO1 and the second anode ANO2 is faulty or short-circuited. Accordingly, the repair detector RD can detect whether one of the first light-emitting device ED1 and the second light-emitting device ED2 is faulty or short-circuited.

[0212] In this case, a resistance difference may occur between the first cathode CAT1, the first low-potential voltage line EVSSL1 and the first anode ANO1 and the second cathode CAT2, the second low-potential voltage line EVSSL2 and the second anode ANO2.

[0213] For example, a first resistor R1 may be formed between the first light-emitting device ED1 and the first low-potential voltage line EVSSL1, and a second resistor R2 may be formed between the second light-emitting device ED2 and the second low-potential voltage line EVSSL2.

[0214] The first resistor R1 may be a resistor between the first anode ANO1 and the first low-potential voltage line EVSSL1. Alternatively, the first resistor R1 may be a resistor from the first contact portion CT1, where the first low-potential voltage line EVSSL1 is electrically connected to the cathode CAT, to the first cathode CAT1, which overlaps the first anode ANO1.

[0215] The second resistor R2 may be a resistor between the second anode ANO2 and the second low-potential voltage line EVSSL2. Alternatively, the second resistor R2 may be a resistor from the second contact part CT2, where the second low-potential voltage line EVSSL2 is electrically connected to the cathode CAT, to the second cathode CAT2, which overlaps the second anode ANO2.

[0216] Therefore, based on the value of a measured voltage of the second node N2 (or the common node) between the first anode ANO1 and the second anode ANO2, which is changed by the first low-potential voltage EVSS1 and the second low-potential voltage EVSS2 applied at different voltage levels, the repair detector RD can detect whether one of the first anode ANO1 and the second anode ANO2 is faulty or short-circuited using the resistance difference described above. Accordingly, the repair detector RD can detect whether one of the first light-emitting device ED1 and the second light-emitting device ED2 is faulty or short-circuited.

[0217] Fig. Figure 19 is a diagram illustrating a voltage detected by a repair detector installed in Fig. 18, according to one embodiment of the present disclosure.

[0218] With reference to Fig. 19, when the first low-potential voltage EVSS1 is applied to 0 V and the second low-potential voltage EVSS2 is applied to 10 V, no fault occurs in either the first anode ANO1 or the second anode ANO2, and the value of the measured voltage of the second node N2 detected by the repair detector RD may be 10 V.

[0219] In addition, when a fault occurs in either the first anode ANO1 or the second anode ANO2, the value of the measured voltage of the second node N2 detected by the repair detector RD can be determined according to a location where the fault occurred based on 5 V.

[0220] For example, the value of a measured voltage of the second node N2 detected by the repair detector RD may be in the range of 10 V to 5 V or in the range of 5 V to 0 V. Specifically, when a fault occurs in the first anode ANO1, a voltage in the range of 0 V may be detected, and when a fault occurs in the second anode ANO2, a voltage in the range of 10 V may be detected, but the present invention is not limited thereto.

[0221] When a fault or short circuit occurs in the first anode ANO1, the repair detector RD can detect a measured voltage value of the second node N2 as 5 V or less, which is the reference BL, and as the value that is in the range of 0 V. Accordingly, the repair detector RD can determine that the fault or short circuit occurs in the first anode ANO1. That is, the repair detector RD can determine that the fault or short circuit occurs in the first light-emitting device ED1.

[0222] When a fault or short circuit occurs in the second anode ANO2, the repair detector RD can detect a measured voltage value of the second node N2 of 5 V, which is the reference BL, or higher than the value in the range of 10 V. Accordingly, the repair detector RD can determine that a fault or short circuit occurs in the second anode ANO2. That is, the repair detector RD can determine that the fault or short circuit occurs in the second light-emitting device ED2.

[0223] According to the present disclosure, the above-described advantageous effects can be obtained. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0030223

[0001] KR 10-2024-0114056

[0001]

Claims

[1] Display device (1000) comprising: a display panel (100) including a display surface (DA) on which a plurality of sub-pixels (SP) are arranged, and a low-potential voltage supply circuit (500) supplying a first low-potential voltage (EVSS1) and a second low-potential voltage (EVSS2) to the plurality of sub-pixels (SP), wherein each of the plurality of sub-pixels (SP) includes a first light-emitting part (EM1) including a first light-emitting device and a second light-emitting part (EM2) including a second light-emitting device, and the first light-emitting device (160) and the second light-emitting device (170) share a pixel circuit, and the first light-emitting device (160) is configured to receive the first low-potential voltage (EVSS1) via a first low-potential voltage line (EVSSL1) and the second light-emitting device (170) is configured to receive the second low-potential voltage (EVSS2) via a second low-potential voltage line (EVSSL2). [2] A display device according to claim 1, wherein the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2) are arranged alternately and / or the first low-potential voltage (EVSS1) and the second low-potential voltage (EVSS2) are configured to have the same voltage value or different voltage values; and / or each of the plurality of sub-pixels (SP) overlaps with one of the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2) and does not overlap with the other of the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2). [3] The display device (1000) according to claim 1, wherein each of the plurality of sub-pixels (SP) further includes an opening (OP) between the first light-emitting part (EM1) and the second light-emitting part (EM2) and / or the first light-emitting part (EM1) and the second light-emitting part (EM2) are configured to emit light of the same color. [4] The display device (1000) according to claim 2, wherein the plurality of sub-pixels (SP) includes a plurality of first sub-pixels (SP1) and a plurality of second sub-pixels (SP2) that are adjacent to each other and spaced apart from each other in a first direction (X), each of the plurality of first sub-pixels (SP1) and the plurality of second sub-pixels (SP2) is arranged in a second direction (Y) crossing the first direction (X), the first light-emitting part (EM11) of the plurality of first sub-pixels (SP1) overlaps with the first low-potential voltage line (EVSSL1) and the second light-emitting part (EM12) of the plurality of first sub-pixels (SP1) does not overlap with the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2), and the first light-emitting part (EM21) of the plurality of second sub-pixels (SP2) overlaps with the second low-potential voltage line (EVSSL2) and the second light-emitting part (EM22) of the plurality of second sub-pixels (SP2) does not overlap with the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2). [5] The display device (1000) according to claim 1, wherein the first light-emitting device (160) includes a first cathode (CAT1) overlapping with the first low-potential voltage line (EVSSL1), and the second light-emitting device (170) includes a second cathode (CAT2) overlapping with the second low-potential voltage line (EVSSL2); and / or the first light-emitting device (160) includes a first cathode (CAT1) electrically connected to the first low-potential voltage line (EVSSL1), and the second light-emitting device (170) includes a second cathode (CAT2) electrically connected to the second low-potential voltage line (EVSSL2). [6] The display device (1000) according to claim 5, wherein each of the plurality of sub-pixels (SP) further includes an opening (OP) between the first light-emitting part (EM1) and the second light-emitting part (EM2), and the first cathode (CAT1) and the second cathode (CAT2) are spaced apart from each other with the opening (OP) interposed therebetween; and / or the first cathode (CAT1) and the second cathode (CAT2) are divided in a first direction (X) crossing a second direction (Y), the first low-potential voltage line (EVSSL1) and the second low-potential voltage line (EVSSL2) extending in the second direction (Y). [7] The display device (1000) according to claim 1, wherein the plurality of sub-pixels (SP) includes a plurality of first sub-pixels (SP1), a plurality of second sub-pixels (SP2), and a plurality of third sub-pixels (SP3) spaced apart in a first direction (X), all of the plurality of first sub-pixels (SP1), the plurality of second sub-pixels (SP2) and the plurality of third sub-pixels (SP3) are arranged in a second direction (Y) which crosses the first direction (X), the first light-emitting device (160) overlaps each of the plurality of first sub-pixels (SP1), the plurality of second sub-pixels (SP2) and the plurality of third sub-pixels (SP3) with different cathodes (CAT1, CAT2, CAT3), the first light-emitting device (160) of the plurality of first sub-pixels (SP1) uses a first cathode (CAT1) in common, the second light-emitting device (170) of the plurality of first sub-pixels (SP1) and the first light-emitting device (160) of the plurality of second sub-pixels (SP2) share a second cathode (CAT2) that is different from the first cathode (CAT1), and the second light-emitting device (170) of the plurality of second sub-pixels (SP2) and the first light-emitting device (160) of the plurality of third sub-pixels (SP3) share a third cathode (CAT3) that is different from the first cathode (CAT1) and the second cathode (CAT2), wherein preferably the first cathode (CAT1), the second cathode (CAT2) and the third cathode (CAT3) are spaced apart from each other in the first direction (X) and extend in the second direction (Y). [8] The display device (1000) according to claim 1, wherein the low-potential voltage supply circuit (500) comprises: a plurality of flexible printed circuit boards (520), each of which has an integrated control circuit (510) mounted thereon, a first short-circuit bar (530) connected to the first low-potential voltage line (EVSSL1), and a second short-circuit bar (540) connected to the second low-potential voltage line (EVSSL2). [9] The display device (1000) according to claim 8, wherein the first short-circuit bar (530) includes a plurality of first connecting parts (531) connected to the plurality of flexible circuit boards (520) and a second connecting part (532) connected to the first low-potential voltage line (EVSSL1), and / or the second short-circuit bar (540) includes a plurality of first connecting parts (541) connected to the plurality of flexible circuit boards (520) and a second connecting part (542) connected to the second low-potential voltage line (EVSSL2). [10] The display device (1000) according to claim 1, wherein each of the plurality of sub-pixels (SP) includes a first sub-electrode (SE1) and a second sub-electrode (SE2), one side of the first sub-electrode (SE1) is connected to the first light-emitting device (160) and another side of the first sub-electrode (SE1) is connected to the pixel circuit and one side of the second sub-electrode (SE2) is connected to the second light-emitting device (170) and another side of the second sub-electrode (SE2) is connected to the pixel circuit. [11] The display device (1000) according to claim 10, wherein each of the plurality of sub-pixels (SP) includes a first sub-contact hole (SCNT1) and a second sub-contact hole (SCNT2), and the first sub-electrode (SE1) is connected to a first electrode (161) of the first light-emitting device (160) through the first sub-contact hole (SCNT1), and the second sub-electrode (SE2) is connected to the first electrode (161) of the second light-emitting device (170) through the second sub-contact hole (SCNT2). [12] The display device (1000) according to claim 11, wherein each of the plurality of sub-pixels (SP) further includes a third sub-contact hole (SCNT3) and a fourth sub-contact hole (SCNT4), and the pixel circuit includes a thin film transistor (120), and the first sub-electrode (SE1) is connected to a source / drain electrode (S / D) of the thin film transistor (120) through the third sub-contact hole (SCNT3), and the second sub-electrode (SE2) is connected to the source / drain electrode (S / D) of the thin film transistor (120) through the fourth sub-contact hole (SCNT4). [13] The display device (1000) according to claim 12, wherein each of the plurality of sub-pixels (SP) further includes an opening (OP) disposed between the first and second light-emitting parts (EM1, EM2), and the source / drain electrode (S / D) overlaps with the opening (OP). [14] The display device (1000) according to claim 3, wherein each of the plurality of sub-pixels (SP) further includes a planarization layer (150) on which the first light-emitting device (160) and the second light-emitting device (170) are arranged, the planarization layer (150) being divided by the opening (OP), and the planarization layer (150) having an undercut (UC) in its side surface facing the opening (OP). [15] The display device (1000) according to claim 14, wherein the planarization layer (150) includes a lower layer (151a, 152a) and an upper layer (151b, 152b) protrudes from the lower layer (151a, 152a) toward the opening (OP), and a side surface of the lower layer (151a, 152a) facing the opening (OP) has an inverted conical shape, and a side surface of the upper layer (151b, 152b) facing the opening (OP) has a conical shape. [16] Display device (1000) comprising: a substrate (110) including a plurality of low potential lines (EVSSL) and a plurality of sub-pixels (SP), each of the plurality of sub-pixels (SP) including: a thin-film transistor (120) on the substrate (110), a planarization layer (150) on the thin-film transistor (120), wherein the planarization layer (150) has an opening (OP), and a first light-emitting device (160) and a second light-emitting device (170) on the planarization layer (150), wherein a first electrode (161) of the first light-emitting device (160) and a first electrode (171) of the second light-emitting device (170) are connected to the same thin-film transistor (120), and a second electrode (163) of the first light-emitting device (160) and a second electrode (173) of the second light-emitting device (170) are spaced apart from each other. [17] The display device (1000) of claim 16, wherein the planarization layer (150) includes a first planarization layer (151) and a second planarization layer (152) spaced apart from each other by the opening (OP), the first light-emitting device (160) is on the first planarization layer (151) and the second light-emitting device (170) is on the second planarization layer (152) and Preferably, a side surface of the first planarization layer (151) and a side surface of the second planarization layer (152) adjacent to the opening (OP) have an undercut shape (UC). [18] The display device (1000) according to claim 16, wherein a first placeholder layer (D1) and a second placeholder layer (D2) are in the opening (OP) and the second placeholder layer (D2) is on the first placeholder layer (d1), wherein the first placeholder layer (D1) and the second placeholder layer (D2) are spaced apart from the first light-emitting device (160) and are spaced apart from the second light-emitting device (170); and / or a light-emitting layer (162) of the first light-emitting device (160), a light-emitting layer (172) of the second light-emitting device (170) and the first placeholder layer (D1) contain the same material and the second electrode (163) of the first light-emitting device (160), the second electrode (173) of the second light-emitting device (170) and the second placeholder layer (D2) contain the same material. [19] The display device (1000) according to claim 16, wherein the plurality of low-potential lines (EVSSL) include a first low-potential line (EVSSL1) and a second low-potential line (EVSSL2), and the second electrode (163) of the first light-emitting device (160) is connected to the first low-potential line (EVSSL1), and a second electrode (173) of the second light-emitting device (170) is connected to the second low-potential line (EVSSL2). [20] The display device (1000) of claim 19, further comprising: a first passivation layer (131) covering the first low-potential line (EVSSL1); a connection electrode (141) on the first passivation layer (131) and a second passivation layer (132) on the connecting electrode (141), wherein the connecting electrode (141) and the first low-potential line (EVSSL1) contact each other through a contact hole in the first passivation layer (131) and / or the second passivation layer (132) includes a first contact portion (CT1) exposing a part of an upper surface of the connection electrode (141), and the connection electrode (141) and the second electrode (163) of the first light-emitting device (160) are in contact with each other via the first contact portion (CT1).

Images