INTEGRATED CIRCUIT WITH GALVANIC INSULATION STRUCTURE AND GATE DRIVER CIRCUIT

Abstract

An integrated circuit (500) comprises a semiconductor layer (130) with a first section (131) in a first device area (310) and a second section (132) in a second device area (320). A galvanic isolation structure (330) is formed between the first section (131) and the second section (132) of the semiconductor layer (130). A capacitive coupling element (200) is formed on a first surface (139) of the semiconductor layer (130). The capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310) and a capacitor dielectric (250) that separates the first lower electrode (210) from an upper electrode (290) extending over the galvanic isolation structure (330). The first lower electrode (210) is signal-connected to a first circuit element (315) in the first device area (310).The upper electrode (290) is operatively connected to a second circuit element (325) in the second device area (320).

Description

TECHNICAL AREA

[0001] The present disclosure relates to integrated high-voltage circuits with separate device areas and to gate driver circuits. BACKGROUND

[0002] Integrated high-voltage circuits in CMOS (complementary metal-oxide-semiconductor) technology typically comprise a low-voltage region for interconnection with low-voltage CMOS control and / or sensor circuits and a high-voltage region for controlling high-voltage switches or analyzing high-voltage signals. Up to application voltages of several hundred volts, lightly doped semiconducting voltage junctions can separate the high-voltage region from the low-voltage region, and internal high-voltage semiconductor elements can transfer electrical signals between the two. At higher application voltages, such semiconducting voltage junctions require a considerably large chip area, and it becomes increasingly difficult to prevent unwanted voltage breakdown between the high-voltage and low-voltage regions.

[0003] A CMOS image sensor is known from US 2020 / 058 688 A1.

[0004] From DE 10 2010 011 258 A1 a semiconductor device is disclosed, comprising an N-type impurity region provided in a substrate, wherein a P-type RESURF layer is provided on a top side of the substrate in the N-type impurity region.

[0005] DE 10 2008 012 858 A1 discloses semiconductor devices with at least two semiconductor regions. In one embodiment, the semiconductor regions of the semiconductor device are electrically isolated from each other by an insulator, and a deposited, structured metal layer extends over the semiconductor regions and over the insulator.

[0006] DE 10 2021 103 424 A1 discloses a microelectronic device comprising a first electrode, a second electrode arranged vertically below the first electrode and separated by a dielectric material, and a connecting wire electrically connected to the second electrode, wherein the first electrode comprises a notch arranged vertically above the connecting wire.

[0007] There is a constant need to provide integrated high-voltage circuits with high-voltage breakdown capability and reliable internal data transmission. SUMMARY

[0008] An integrated circuit comprises a semiconductor layer with a first section in a first device area and a second section in a second device area. A galvanic isolation structure is formed between the first and second sections of the semiconductor layer. A capacitive coupling element is formed on a first surface of the semiconductor layer. The capacitive coupling element comprises a first lower electrode in the first device area and a capacitor dielectric that separates the first lower electrode from an upper electrode extending across the galvanic isolation structure. The first lower electrode is signal-connected to a first circuit element in the first device area. The upper electrode is functionally connected to a second circuit element in the second device area.

[0009] The galvanic isolation structure provides an area-efficient isolation structure for high nominal breakdown voltages. The capacitive coupling element ensures reliable signal transmission across the galvanic isolation with predictable transmission parameters, without compromising the galvanic isolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. Figures 1A-1B illustrate a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a galvanic isolation structure and a capacitive coupling element for signal transmission over the galvanic isolation structure according to an embodiment relating to a capacitive coupling element having an upper electrode and a lower electrode. Fig. Figures 2A-2B illustrate a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a galvanic isolation structure and a capacitive coupling element for signal transmission over the galvanic isolation structure according to an embodiment relating to a capacitive coupling element having an upper electrode and two lower electrodes on both sides of the galvanic isolation structure. Fig. Figure 3 illustrates a schematic top view of an integrated circuit with a galvanic isolation structure between a first device area and a second device area and with capacitive coupling elements for signal transmission between the first device area and the second device area according to one embodiment. Fig. Figure 4 illustrates a schematic vertical cross-sectional view of a section of an integrated circuit with an upper electrode of a capacitive coupling element formed in a top metal layer, according to one embodiment. Fig. Figure 5 illustrates a schematic top view of a section of an integrated circuit with a capacitive coupling element comprising an upper electrode with two electrode sections and a narrow connecting section linking the two electrode sections, according to one embodiment. Fig. Figures 6A-6B illustrate a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a capacitive coupling element and with trench isolation structures that laterally surround embedded areas of a semiconductor layer directly below the lower electrodes of the capacitive coupling element, according to one embodiment. Fig. Figures 7A-7B illustrate a schematic vertical cross-sectional view and a corresponding horizontal cross-sectional view of a section of an integrated circuit with a capacitive coupling element and protective leads that partially surround the lower electrodes of the capacitive coupling element, according to one embodiment. Fig. Figure 8 illustrates a schematic top view of a section of an integrated circuit with capacitive coupling elements and protective conductors according to another embodiment. Fig. Figure 9 is a schematic block diagram of a gate driver circuit with capacitive coupling elements for routing differential data signals from a high-side part to a low-side part and from the low-side part to the high-side part according to one embodiment. DETAILED DESCRIPTION

[0011] The terms "have," "contain," "include," "include," and the like are open-ended, indicating the presence of certain structures, elements, or features, but not excluding the presence of additional elements or features. The articles "a," "an," and "the" include both the plural and the singular unless the context clearly indicates otherwise.

[0012] The terms "electrically connected," "signal-connected," and "functionally connected" can include a direct connection or a connection through other electronic elements that are provided and suitable for permanent signal transmission, temporary signal transmission, and / or energy transmission. Electronic elements can be electrically connected, signal-connected, and functionally connected via resistors, capacitors, semiconductor diodes, electronic switches such as field-effect transistors, transistor circuits such as transmission gates, buffers and amplifiers, logic gates, inverters, optocouplers, transformers, and others. At least one electrical signal in a second electrical circuit, which is signal-connected or functionally connected to a first electrical circuit, responds in a predictable, intended manner to a change in an electrical signal in the first electrical circuit.Directly electrically connected electronic elements are connected by low-resistance wiring, an ohmic contact and / or a unipolar semiconductor junction.

[0013] An ohmic contact describes a non-rectifying electrical junction between two conductors, e.g., between a semiconductor material and a metal. The ohmic contact exhibits a linear or nearly linear current-voltage curve (IV curve) in the first and third quadrants of the IV diagram, as described by Ohm's law.

[0014] Ranges specified for physical dimensions include the limit values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit value such as "at most" and "at least".

[0015] The term "on" should not be interpreted as meaning only "directly on". Rather, if one element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) can be positioned between the two elements (e.g., another layer can be positioned between a layer and a substrate if the layer is "on" the substrate).

[0016] The examples described herein provide an integrated circuit that may comprise a semiconductor layer, which may include a first section in a first device region and a second section in a second device region. A galvanic isolation structure may be formed between the first and second sections of the semiconductor layer. A capacitive coupling element may be formed on a first surface of the semiconductor layer. The capacitive coupling element may comprise a first lower electrode in the first device region and an upper electrode extending across the galvanic isolation structure. A capacitor dielectric may separate the first lower electrode from the upper electrode. The first lower electrode may be signal-connected to a first circuit element formed in the first device region.The upper electrode can be operatively connected to a second circuit element that is formed in the second device area.

[0017] For example, a wiring connection can directly electrically connect an output of the first circuit element in the first device area to the first lower electrode. The first lower electrode is capacitively coupled to the upper electrode. The upper electrode is operatively connected to the second circuit element in the second device area.

[0018] The integrated circuit can be, for example, a high-voltage integrated circuit (HVIC), such as a power factor correction controller, a gate driver circuit, an intelligent power conversion circuit including driver circuits for controlling high-voltage switches, or an intelligent motor control circuit. The semiconductor layer can be a single-crystal silicon layer of uniform thickness or comprise several layers. A planar or nearly planar first surface of the semiconductor layer extends in a horizontal plane and defines a front face of the semiconductor layer and the integrated circuit. The thickness of the semiconductor layer in a vertical direction orthogonal to the horizontal plane is uniform or nearly uniform.

[0019] The first and second device areas of the integrated circuit are adjacent to each other in the horizontal (lateral) direction. One of the device areas can partially or completely enclose the other device area laterally, or the two device areas can be arranged side by side. For example, the first and second device areas can be approximately rectangular and are arranged side by side at a uniform distance from each other.

[0020] The lateral extents of the first and second device regions define the first and second sections of the semiconductor layer. The first section of the semiconductor layer can be formed exclusively within the first device region. The second section of the semiconductor layer can be formed exclusively within the second device region. The semiconductor layer can also include a third section outside the first and second device regions.

[0021] The galvanic isolation structure can be capable of withstanding a voltage of at least 200 V, e.g., at least 600 V, at least 900 V, at least 1200 V, or at least 1700 V, without breakdown. The rated breakdown voltage can be at least 600 V, at least 900 V, at least 1200 V, or at least 1700 V. The galvanic isolation structure can extend from the first surface of the semiconductor layer into and through the semiconductor layer down to a dielectric structure or a buried insulating layer formed on the back side of the semiconductor layer. The galvanic isolation structure can comprise a single trench structure containing pressed-in doped or undoped glass or deposited dielectric material. Alternatively, the galvanic isolation structure can comprise multiple trench structures running parallel to one another.Vertical fins of the semiconductor layer or of another material can laterally separate adjacent trench structures. Each trench structure can have a homogeneous dielectric filling, comprising, for example, deposited silicon oxide and / or silicon oxynitride. Alternatively, each trench structure can comprise a dielectric lining covering one side wall of a trench formed in the semiconductor layer and a dielectric or semiconducting filler material deposited on the dielectric lining.

[0022] The galvanic isolation structure can laterally separate the first section of the semiconductor layer in the first device area from the second section of the semiconductor layer in the second device area. The galvanic isolation structure can be a linear structure extending from one side of the semiconductor layer to the opposite side, dividing the semiconductor layer into the first section and the second section on opposite sides of the galvanic isolation structure. Alternatively, the galvanic isolation structure can form two closed loops, each laterally enclosing one of the first and second sections of the semiconductor layer.

[0023] An interlayer dielectric can separate the first lower electrode from the semiconductor layer. The interlayer dielectric can be a homogeneous layer or it can comprise two or more sublayers, with directly adjacent sublayers having different material compositions and / or densities. For example, the interlayer dielectric can comprise a stack of layers consisting of thermally grown silicon oxide, one or more layers of deposited silicon oxide, and / or one or more layers of silicon nitride or silicon oxynitride.

[0024] The first lower electrode can be a thin-film structure extending parallel to the first surface. The thickness of the first lower electrode can range from 50 nm to 5 µm, e.g., from 0.1 µm to 1 µm. The first lower electrode can comprise an elemental transition metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or tantalum (Ta), a metal alloy, or a transition metal nitride, e.g., titanium nitride (TiN) or tantalum (TaN).

[0025] The first lower electrode can be located in the lowest metal layer closest to the first surface of the semiconductor layer, in the second metal layer counting from the first surface, or in another metal layer between the lowest metal layer and an uppermost metal layer. The first lower electrode can be a continuous structure without openings or it can be lattice-shaped.

[0026] The upper electrode comprises a section directly above the first lower electrode and extends across the galvanic insulation structure. The upper electrode may be the same thickness as the first lower electrode or significantly thicker. The upper electrode may be made of an elemental metal, a metal compound, or a metal alloy different from that of the first lower electrode.

[0027] The capacitor dielectric can separate the first lower electrode from the upper electrode of the capacitive coupling element. The capacitor dielectric can be a homogeneous layer or it can comprise two or more sublayers, with directly adjacent sublayers having different material compositions and / or densities. For example, the capacitor dielectric can comprise a stack of layers including one or more layers of deposited silicon oxide and / or one or more layers of silicon nitride. The capacitor dielectric can have a rated breakdown voltage that is not lower than the rated breakdown voltage of the galvanic isolation structure.

[0028] The first circuit element, which is signal-connected to the first lower electrode, can be a driver stage of an asymmetric driver or one of the two output stages of a differential driver. This first circuit element can drive a signal on a line that directly connects the output of the first circuit element and the first lower electrode, and charge / discharge the first lower electrode sufficiently quickly for a predetermined signal transfer rate. The second circuit element, which is functionally connected to the upper electrode, can be a receiver stage for an asymmetric driver or one of two input stages of a differential signal receiver stage. This second circuit element can process a signal received via a line that directly connects the upper electrode to a receiver input of the second circuit element.Alternatively, the first circuit element may be able to process a signal received via a line that directly connects the upper electrode to a receiver input of the first circuit element.

[0029] The galvanic isolation structure enables high nominal breakdown voltages on the chip, and the capacitive coupling element allows for reliable signal transmission between device areas on the chip at high data rates. Implementing the capacitive coupling element requires only moderate modifications to the integrated circuit manufacturing process. Component parameters of the capacitive coupling element, which determine the signal transmission characteristics, can be defined relatively precisely with limited effort.

[0030] According to one embodiment, the upper electrode and the second circuit element, which is formed in the second device area, can be directly electrically connected. For example, a combination of metal wiring leads and vias can form a direct electrical connection from the upper electrode to an input of the second circuit element.

[0031] According to another embodiment, the capacitive coupling element can further comprise a second lower electrode formed in the second device area. The capacitor dielectric can further separate the second lower electrode from the upper electrode. The second lower electrode is signal-connected to the second circuit element formed in the second device area.

[0032] The interlayer dielectric can separate both the first and second lower electrodes from the semiconductor layer. The interlayer dielectric can be a homogeneous layer or it can comprise two or more sublayers, with directly adjacent sublayers having different material compositions and / or densities. For example, the interlayer dielectric can comprise a stack of layers consisting of thermally grown silicon oxide, one or more layers of deposited silicon oxide, and / or one or more layers of silicon nitride or silicon oxynitride.

[0033] The first and second lower electrodes can be thin-film structures extending parallel to the first surface and can be formed in the same metal layer. The thickness of the first and second lower electrodes can range from 50 nm to 5 µm, e.g., from 0.1 µm to 1 µm. The first and second lower electrodes can have the same or different lateral dimensions and can comprise an elemental transition metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or tantalum (Ta), a metal alloy, or a transition metal nitride, e.g., titanium nitride (TiN) or tantalum (TaN).

[0034] The first and second lower electrodes are laterally separated by a section of the interlayer dielectric, the section of the interlayer dielectric between the first and second lower electrodes having a rated breakdown voltage not lower than the rated breakdown voltage of the galvanic isolation structure. The lateral distance between the first and second lower electrodes can be greater than the lateral width of the galvanic isolation structure along the same direction.

[0035] The vertical distance between the first lower electrode and the first surface of the semiconductor layer and the vertical distance between the second lower electrode and the first surface of the semiconductor layer can be equal. The first and second lower electrodes can be located in the lowest metal layer closest to the first surface of the semiconductor layer, in the second metal layer counting from the first surface, or in another metal layer between the lowest metal layer and an uppermost metal layer. The first and second lower electrodes can be continuous structures without openings or they can be lattice-like.

[0036] The upper electrode comprises sections directly above the first and second lower electrodes and extends across the galvanic insulation structure. The upper electrode may be the same thickness as the lower electrodes or significantly thicker. It may be made of an elemental metal, a metal compound, or a metal alloy different from that of the first and second lower electrodes.

[0037] The capacitor dielectric can separate the first lower electrode and the second lower electrode from the upper electrode of the capacitive coupling element. The capacitor dielectric can be a homogeneous layer or it can comprise two or more sublayers, with directly adjacent sublayers having different material compositions and / or densities. For example, the capacitor dielectric can comprise a stack of layers including one or more layers of deposited silicon oxide and / or one or more layers of silicon nitride. The capacitor dielectric can have a rated breakdown voltage that is not lower than the rated breakdown voltage of the galvanic isolation structure.

[0038] The first circuit element connected to the first lower electrode can be a driver stage of an asymmetric driver or one of the two output stages of a differential driver. This first circuit element can drive a signal on a line directly connecting its output to the first lower electrode, charging / discharging the first lower electrode sufficiently quickly for a predetermined signal transfer rate. The second circuit element connected to the second lower electrode can be a receiver stage for an asymmetric driver or one of two input stages of a differential signal receiver stage. This second circuit element can process a signal received via a line directly connecting the second lower electrode to a receiver input of the second circuit element.Alternatively, the first circuit element connected to the first lower electrode can be a receiver stage for an asymmetrical signal or one of two input stages of a differential signal receiver stage. The first circuit element can be capable of processing a signal received via a line that directly connects the first lower electrode to a receiver input of the first circuit element.

[0039] The galvanic isolation structure enables high nominal breakdown voltages on the chip, and the capacitive coupling element allows for reliable signal transmission between device areas on the chip at high data rates. Implementing the capacitive coupling element requires only moderate modifications to the integrated circuit manufacturing process. Component parameters of the capacitive coupling element, which determine the signal transmission characteristics, can be defined relatively precisely with limited effort.

[0040] According to one embodiment, the galvanic isolation structure can extend from a first surface of the semiconductor layer into the semiconductor layer and isolate the first section and the second section of the semiconductor layer from each other up to a nominal breakdown voltage or alternatively a specified nominal maximum operating voltage of at least 300 V.

[0041] For example, the nominal breakdown voltage of the galvanic isolation structure can be at least 750 V or 1200 V. The galvanic isolation structure can structurally and electrically separate the first section of the semiconductor layer in the first device area from the second section of the semiconductor layer in the second device area in one or more lateral directions. In the vertical direction, the galvanic isolation structure can extend to or into an insulating layer formed on the back side of the semiconductor layer, with the first section of the semiconductor layer in the first device area being completely electrically separated from the second section of the semiconductor layer in the second device area.

[0042] According to one embodiment, the upper electrode can comprise a section of an uppermost metal layer of the integrated circuit.

[0043] The top metal layer can be made of an elemental metal such as copper (Cu), a metal compound, or a metal alloy, e.g., a copper alloy such as aluminum-copper (AlCu) or aluminum-silicon-copper (AlSiCu). Sections of the top metal layer, excluding the top electrode, can form contact pads, e.g., for bond wires. The top metal layer can include a nucleation layer and an electroplated section.

[0044] According to one embodiment, a polyimide layer can cover the top electrode. The polyimide layer can completely cover the top electrode, partially cover other sections of the top metal layer, and fill gaps between laterally separated sections of the top metal layer. Openings in the polyimide layer can expose other sections of the top metal layer. The polyimide layer can be formed directly on the top electrode, for example, directly on the top metal layer and on sections of the capacitor dielectric exposed through the openings in the top metal layer. Alternatively, a dielectric or high-resistance auxiliary layer can be formed directly on the top metal layer and on the sections of the capacitor dielectric exposed through the openings in the top metal layer, and the polyimide layer can be formed on the auxiliary layer.The auxiliary layer can be a homogeneous layer or it can comprise two or more sublayers made of different materials and / or structures. For example, the auxiliary layer can include a silicon nitride layer. The polyimide layer can contain additives that fine-tune its mechanical and / or electrical properties.

[0045] According to one embodiment, the upper electrode can comprise a first electrode section in the first device area, a second electrode section in the second device area, and a narrow connecting section that connects the first electrode section and the second electrode section.

[0046] The junction can be narrower than the first and second electrode sections and can extend across the galvanic isolation structure. Along a direction orthogonal to a shortest path between the first and second electrode sections of the semiconductor layer, the junction is narrower than either the first or second electrode section. The reduced width of the upper electrode between the first and second electrode sections reduces parasitic capacitances and increases signal transmission efficiency. A comparatively small junction width may be sufficient for the small displacement currents that occur in the upper electrode during signal transmission.

[0047] According to one embodiment, the connecting section has a length along a direction that directly connects the first electrode section and the second electrode section in a horizontal plane parallel to the first surface of the semiconductor layer, and a width w3 in the horizontal plane orthogonal to the length, wherein the width w3 is smaller than the first lateral extensions of the first electrode section and the second electrode section parallel to the width w3 of the connecting section.

[0048] In the case of a linear galvanic isolation structure that includes a straight section directly between the first and second sections of the semiconductor layer, the first electrode section has a first lateral extent w11 along a first direction parallel to the straight section of the linear galvanic isolation structure, the second electrode section has a first lateral extent w21 along the first direction, and the width w3 of the interconnection section is smaller than the first lateral extents w11 and w21 of the first and second electrode sections, respectively. For example, the width w3 of the interconnection structure is at most 30% or at most 20% of the mean of the first lateral extents w11 and w21 of the first and second electrode sections, respectively.Narrowing the connection section that links the first and second electrode sections reduces parasitic capacitances and increases signal transmission efficiency.

[0049] According to one embodiment, the first electrode section of the upper electrode can extend laterally beyond the first lower electrode and / or the second electrode section of the upper electrode can extend laterally beyond the second lower electrode.

[0050] The first electrode section can extend laterally beyond the first lower electrode on all sides. The second electrode section can also extend laterally beyond the second lower electrode on all sides. The nominal lateral projection can be sufficiently large to compensate for process-related misalignments between the lower electrodes and the electrode sections of the upper electrode.

[0051] For example, the first lower electrode and the first electrode segment of the upper electrode can be geometrically similar in the horizontal plane, and / or the second lower electrode and the second electrode segment of the upper electrode can be geometrically similar in the horizontal plane. The horizontal shape of the first electrode segment can be obtained by scaling the horizontal shape of the first lower electrode with a scaling factor greater than 1, and / or the horizontal shape of the second electrode segment can be obtained by scaling the horizontal shape of the second lower electrode with a scaling factor greater than 1. Additionally, the centers of the first lower electrode and the first electrode segment of the upper electrode can be concentric, i.e., on the same vertical axis. The centers of the second lower electrode and the second electrode segment of the upper electrode can also be concentric, i.e., on the same vertical axis.on the same vertical axis.

[0052] The larger electrode sections of the upper electrode can compensate for process-related alignment errors between the lower electrodes and the electrode sections of the upper electrode, so that the range of the actual capacitance values ​​of the capacitive coupling element is comparatively narrow and the data transmission rate via the capacitive coupling element is robust against manufacturing variations in the formation of the upper electrode.

[0053] According to one embodiment, the first electrode section has a horizontal shape parallel to the first surface and / or the second electrode section of the upper electrode is rounded with a radius of at least 5 µm.

[0054] For example, the horizontal shape of the first electrode segment and / or the second electrode segment forms a circle, an oval, or an ellipse. Alternatively, the horizontal shape of the first electrode segment and / or the second electrode segment is a polygon with rounded corners, e.g., a regular polygon with rounded corners. For example, the horizontal shape of the first electrode segment and / or the second electrode segment is a rectangle with rounded corners.

[0055] The absence of sharp corners and / or the rounding of corners reduces the electric field in both the polyimide layer and the capacitor dielectric and can contribute to higher reliability of the integrated circuit.

[0056] According to one embodiment, the integrated circuit may further comprise a first trench insulation structure extending from the first surface into the semiconductor layer and laterally surrounding a first embedded region of the semiconductor layer directly below the first lower electrode, and / or a second trench insulation structure extending from the first surface into the semiconductor layer and laterally surrounding a second embedded region of the semiconductor layer directly below the second lower electrode.

[0057] The first trench isolation structure can form a closed lateral frame around the first embedded region, and / or the second trench isolation structure can form a closed lateral frame around the second embedded region. The first trench isolation structure can extend from the first surface through the semiconductor layer down to an insulating layer on the back side of the semiconductor layer to completely electrically isolate the first embedded region from other regions of the first section of the semiconductor layer outside the first embedded region. Alternatively or additionally, the second trench isolation structure can extend from the first surface through the semiconductor layer down to the insulating layer to completely electrically isolate the second embedded region from other regions of the second section of the semiconductor layer outside the second embedded region.

[0058] Each trench isolation structure can have a homogeneous dielectric filling, such as deposited silicon oxide or silicon oxynitride. Alternatively, each trench isolation structure can comprise a dielectric lining covering one side wall of a trench formed in the semiconductor layer and a filling material deposited on the dielectric lining. The filling material can be an insulator, such as an oxide or nitride, or a semiconducting material, such as doped or undoped polysilicon. Trench structures of a multi-part galvanic isolation structure and the trench isolation structures can have a similar configuration and can be formed using the same processes.

[0059] The inner edge of the first trench insulation structure may be displaced outwards relative to the outer edge of the first lower electrode, and / or the inner edge of the second trench insulation structure may be displaced outwards relative to the outer edge of the second lower electrode in the horizontal direction. Accordingly, the horizontal cross-sectional area of ​​the first embedded area may be larger than the horizontal cross-sectional area of ​​the first lower electrode, and / or the horizontal cross-sectional area of ​​the second embedded area may be larger than the horizontal cross-sectional area of ​​the second lower electrode.

[0060] According to one embodiment, a first protective conductor can be formed along an edge of the first lower electrode and / or a second protective conductor can be formed along an edge of the second lower electrode.

[0061] The first protective conductor can be formed at a lateral distance from the first lower electrode, with the lateral distance between the first protective conductor and the first lower electrode being largely uniform. The second protective conductor can be formed at a lateral distance from the second lower electrode, with the lateral distance between the second protective conductor and the second lower electrode being largely uniform. The first protective conductor and the first lower electrode can be formed in the same metal layer. The second protective conductor and the second lower electrode can be formed in the same metal layer.

[0062] The first protective conductor can extend along the entire circumference of the first lower electrode. Alternatively, the first protective conductor can extend along all sections of the edge of the first lower electrode, except for the section of the edge directly facing the galvanic isolation structure. The second protective conductor can extend along the entire circumference of the second lower electrode. Alternatively, the second protective conductor can extend along all sections of the edge of the second lower electrode, except for the section of the edge directly facing the galvanic isolation structure. The protective conductors can reduce the electric field outside the capacitive coupling element.

[0063] According to one embodiment, the first protective conductor can be electrically connected to the first section of the semiconductor layer at a lateral distance from the first lower electrode and / or the second protective conductor can be electrically connected to the second section of the semiconductor layer at a lateral distance from the second lower electrode.

[0064] An ohmic contact between the first protective conductor and the semiconductor layer can be formed outside the first trench insulation structure, which laterally surrounds the first embedded region directly below the lower electrode. An ohmic contact between the second protective conductor and the semiconductor layer can be formed outside the second trench insulation structure, which laterally surrounds the second embedded region directly below the lower electrode.

[0065] Connecting the protective conductors to a fixed potential facilitates the discharge of the displacement currents of the capacitive coupling element.

[0066] According to one embodiment, the first conductive protective conductor and the first lower electrode can be formed from different sections of a lower electrode metal layer and / or the second conductive protective conductor and the second lower electrode can be formed from different sections of the lower electrode metal layer.

[0067] The lower electrode metal layer can be the first or second metal layer, counted from the first surface of the semiconductor layer.

[0068] According to one embodiment, the integrated circuit can further comprise a first feed line connecting the first circuit element and the first lower electrode, wherein the first protective conductor and a through-pass section of the first feed line crossing the first protective conductor are formed in different metal layers. Alternatively or additionally, the integrated circuit can further comprise a second feed line connecting the second circuit element and the second lower electrode, wherein the second protective conductor and a through-pass section of the second feed line crossing the second protective conductor are formed in different metal layers.

[0069] According to one embodiment, the integrated circuit may further comprise an insulating layer formed on one side of the semiconductor layer opposite the first surface.

[0070] In particular, the integrated circuit can be a semiconductor-on-insulator device. The insulating layer can be a silicon oxide layer with a thickness between 2 µm and 10 µm. The galvanic isolation structure can extend from the first surface of the semiconductor layer to or into the insulating layer. The first and second trench isolation structures can extend from the first surface of the semiconductor layer to or into the insulating layer.

[0071] In the absence of an insulating layer, the first embedded region can include a deep counter-doped region extending across the entire cross-sectional area of ​​the first embedded region at a distance from a first surface at the front of the semiconductor layer. Alternatively or additionally, the second embedded region can include a deep counter-doped region extending across the entire cross-sectional area of ​​the second embedded region at a distance from the first surface at the front of the semiconductor layer. The counter-doped regions can be n-type for a p-type semiconductor layer. The first trench insulation structure can then extend downwards from the first surface to or into the counter-doped region to separate the first embedded region from other regions of the first section of the semiconductor layer outside the first embedded region.Alternatively or additionally, the second trench isolation structure can extend downwards from the first surface to or into the counter-doped region to separate the second embedded region from further regions of the second section of the semiconductor layer outside the second embedded region.

[0072] The integrated circuit may include one or more additional layers on the insulating layer side opposite the semiconductor layer. A tape and / or a handling substrate may be applied or formed on the insulating layer side opposite the semiconductor layer.

[0073] Other examples described herein provide a gate driver circuit that may comprise a semiconductor layer, which may include a first section in a first device area and a second section in a second device area. A galvanic isolation structure may be formed between the first and second sections of the semiconductor layer. A capacitive coupling element may be formed on a first surface of the semiconductor layer. The capacitive coupling element may include a first lower electrode in the first device area, a second lower electrode in the second device area, and an upper electrode. A capacitor dielectric may separate the first lower electrode and the second lower electrode from the upper electrode. The first lower electrode may be signal-connected to a first circuit element formed in the first device area.The second lower electrode can be signal-connected to a second circuit element formed in the second device area.

[0074] Fig. 1A and Fig. Figure 1B shows an integrated circuit 500 with a first device area 310 and a second device area 320 on opposite sides of an intermediate galvanic isolation structure 330 formed in a semiconductor layer 130. A first surface 139 on the front face of the semiconductor layer 130 defines a horizontal plane. A vertical direction is orthogonal to the horizontal plane.

[0075] The galvanic isolation structure 330 laterally separates the semiconductor layer 130 into a first section 131 in the first device area 310 and a second section 132 in the second device area 320. A first circuit element 315 in the first device area 310 comprises doped regions formed in the first section 131 of the semiconductor layer 130. A second circuit element 325 in the second device area 320 comprises doped regions formed in the second section 132 of the semiconductor layer 130. The semiconductor layer 130 is a single-crystal silicon layer. An interlayer dielectric 140 is formed directly on the first surface 139. The interlayer dielectric 140 is a homogeneous layer or a stack of layers comprising two or more dielectric layers, e.g., silicon oxide, silicon nitride, and / or silicon oxynitride.

[0076] A capacitive coupling element 200 is formed on the interlayer dielectric 140. A first lower electrode 210 of the capacitive coupling element 200 is formed on a section of the interlayer dielectric 140 in the first device area 310. A capacitor dielectric 250 of the capacitive coupling element 200 is formed on the first lower electrode 210. The capacitor dielectric 250 can extend laterally beyond the outer edge of the first lower electrode 210, facing away from the galvanic isolation structure 330. The capacitor dielectric 250 can be a homogeneous layer of a single dielectric material or a stack of layers comprising layers of different dielectric materials such as silicon oxide and silicon nitride.The thickness of the capacitor dielectric 250 can range from 800 nm to 2 µm for a nominal breakdown voltage of 300 V to 5 µm to 10 µm for a nominal breakdown voltage of 1200 V. An upper electrode 290 of the capacitive coupling element 200 is formed on the capacitor dielectric 250.

[0077] In the illustrated example, the shape of the first lower electrode 210 in the horizontal cross-section is a rectangle, and the shape of the upper electrode 290 in the horizontal cross-section is a rectangle with an area larger than the total area of ​​the first lower electrode 210. At least 90%, e.g., 100%, of the vertical projection of a section of the upper electrode 290 in the first device area 310 into the plane of the first lower electrode 210 overlaps with the first lower electrode 210.

[0078] The first circuit element 315 is a driver circuit for a digital signal. A conductor connects a driver output of the first circuit element 315 to the first lower electrode 210 of the capacitive coupling element 200. The second circuit element 325 is a receiver circuit for a digital signal. A conductor connects the upper electrode 290 of the capacitive coupling element 200 to a receiver input of the second circuit element 325.

[0079] The capacitive coupling element 200 is located in the transmission path from the first circuit element 315 to the second circuit element 325 and can have a capacitance in the range of 50 fF to 400 fF. The nominal breakdown voltage of the section of the interlayer dielectric between the first and second lower electrodes 210, 220 and the capacitor dielectric 250, and the nominal breakdown voltage of the galvanic isolation structure 330 are of the same order of magnitude and greater than 300 V, 750 V, or 1200 V.

[0080] Fig. 2A and Fig. Figure 2B shows an integrated circuit 500 with a first device area 310 and a second device area 320 on opposite sides of an intermediate galvanic isolation structure 330 formed in a semiconductor layer 130. A first surface 139 on the front face of the semiconductor layer 130 defines a horizontal plane. A vertical direction is orthogonal to the horizontal plane.

[0081] The galvanic isolation structure 330 laterally separates the semiconductor layer 130 into a first section 131 in the first device area 310 and a second section 132 in the second device area 320. A first circuit element 315 in the first device area 310 comprises doped regions formed in the first section 131 of the semiconductor layer 130. A second circuit element 325 in the second device area 320 comprises doped regions formed in the second section 132 of the semiconductor layer 130. The semiconductor layer 130 is a single-crystal silicon layer. An interlayer dielectric 140 is formed directly on the first surface 139. The interlayer dielectric 140 is a homogeneous layer or a stack of layers comprising two or more dielectric layers, e.g., silicon oxide, silicon nitride, and / or silicon oxynitride.

[0082] A capacitive coupling element 200 is formed on the interlayer dielectric 140. A first lower electrode 210 of the capacitive coupling element 200 is formed on a section of the interlayer dielectric 140 in the first device area 310. A second lower electrode 220 of the capacitive coupling element 200 is formed on a section of the interlayer dielectric 140 in the second device area 310. Another section of the interlayer dielectric 140 separates the first lower electrode 210 from the second lower electrode 220 laterally. The first and second lower electrodes 210, 220 are formed at the same distance from the first surface 139.A capacitor dielectric 250 of the capacitive coupling element 200 is formed on the first lower electrode 210, the second lower electrode 220, and the section of the interlayer dielectric 140 that laterally separates the first lower electrode 210 from the second lower electrode 220. The capacitor dielectric 250 can extend laterally beyond the outer edges of the first and second lower electrodes 210, 220, facing away from the galvanic isolation structure 330. The capacitor dielectric 250 can be a homogeneous layer of a single dielectric material or a stack of layers comprising layers of different dielectric materials such as silicon oxide and silicon nitride. The thickness of the capacitor dielectric 250 can range from 800 nm to 2 µm for a nominal breakdown voltage of 300 V to a range of 5 µm to 10 µm for a nominal breakdown voltage of 1200 V.An upper electrode 290 of the capacitive coupling element 200 is formed on the capacitor dielectric 250.

[0083] In the illustrated example, the shape of the first and second lower electrodes 210, 220 in the horizontal cross-section is a rectangle, and the shape of the upper electrode 290 in the horizontal cross-section is a rectangle with an area larger than the combined area of ​​the first and second lower electrodes 210, 220. At least 90%, e.g., 100%, of the vertical projection of the upper electrode 290 into the plane of the lower electrodes 210, 220 overlaps with the first and second lower electrodes 210, 220.

[0084] The first circuit element 315 is a driver circuit for a digital signal. A conductor connects a driver output of the first circuit element 315 to the first lower electrode 210 of the capacitive coupling element 200. The second circuit element 325 is a receiver circuit for a digital signal. A conductor connects the second lower electrode 210 of the capacitive coupling element 200 to a receiver input of the second circuit element 325.

[0085] The capacitive coupling element 200 is located in the transmission path from the first circuit element 315 to the second circuit element 325 and can have a capacitance in the range of 50 fF to 400 fF. The nominal breakdown voltage of the section of the interlayer dielectric between the first and second lower electrodes 210, 220 and the capacitor dielectric 250, and the nominal breakdown voltage of the galvanic isolation structure 330 are of the same order of magnitude and greater than 300 V, 750 V, or 1200 V.

[0086] The in Fig. Figure 3 illustrates the integrated circuit 500 comprising a galvanic isolation structure 330 forming two closed loops, each loop laterally surrounding one of the first and second sections 131, 132 of the semiconductor layer 130. A straight line section 331 of the galvanic isolation structure 330 laterally separates the first and second sections 131, 132 and defines a first and a second device area 310, 320 on opposite sides of the straight line section 331. A frame section 332 forms a single frame around the first section 131 and the second section 132 and laterally separates the first and second sections 131, 132 from a third section 138 of the semiconductor layer 130 located between the frame section 332 and an outer lateral surface 103 of the integrated circuit 500.The integrated circuit 500 comprises two capacitive coupling elements 200 with upper electrodes 290, which bridge the straight line section 331 of the galvanic isolation structure 330.

[0087] As in Fig. As shown in Figure 4, the galvanic isolation structure 330 can extend from the first surface 139 through the semiconductor layer 130 downwards to an insulating layer 120, which is formed on the back side of the semiconductor layer 130 opposite the first surface 139. The insulating layer 120 separates the semiconductor layer 130 from a substrate layer 110. An interlayer dielectric 140 is formed on the first surface 139. A second lower electrode 220 of a capacitive coupling element 200 is formed on the interlayer dielectric 140. A capacitor dielectric 250 of the capacitive coupling element 200 is formed on the second lower electrode 220.

[0088] An upper electrode 290 of the capacitive coupling element 200 is formed on the capacitor dielectric 250.

[0089] A metal contact 229 extends from a metal conductor 225 through the interlayer dielectric 140 to a doping contact area 137 in the second section 132 of the semiconductor layer 130. The metal conductor 225 and the second lower electrode 220 are formed in the same metal layer 150 of the lower electrode. A further metal contact 299 extends from a metal contact pad 295 formed on the capacitor dielectric 250 through the capacitor dielectric 250 to the metal conductor 225. The contact pad 295 and the upper electrode 290 are formed in the same uppermost metal layer 180. A polyimide layer 190 covers the upper electrode 290, side walls of the contact pad 295, and a section of the capacitor dielectric 250 between the upper electrode 290 and the contact pad 295. An opening in the polyimide layer 190 exposes an upper surface of the contact pad 295.

[0090] In Fig. 5 comprises an upper electrode 290 of a capacitive coupling element 200, a first electrode section 291 directly above the first lower electrode 210, a second electrode section 292 directly above the second lower electrode 220, and a connecting section 293 that connects the first electrode section 291 and the second electrode section 292.

[0091] The horizontal shapes of the first lower electrode 210 and the first electrode section 291 are geometrically similar, with the horizontal shape of the first electrode section 291 being obtained by scaling the horizontal shape of the first lower electrode 210 by a scaling factor greater than 1 and shifting the shape along the vertical axis. The horizontal shapes of the second lower electrode 220 and the second electrode section 292 are geometrically similar, with the horizontal shape of the second electrode section 292 being obtained by scaling the horizontal shape of the second lower electrode 220 by a scaling factor greater than 1 and shifting the shape along the vertical axis. Both scaling factors are the same. The shapes of the first lower electrode 210, the second lower electrode 220, the first electrode section 291, and the second electrode section 292 are rectangles with rounded corners.The radius of curvature r1 of the corners of the first and second electrode sections 291, 292 can be in the range of 1 µm to 20 µm. The radius of curvature r2 of the corners of the first and second lower electrodes 210, 220 can be in the range of 1 µm to 20 µm. The electrode sections 291, 292 of the upper electrode 290 project beyond the lower electrodes 210, 220 to the same extent on all sides.

[0092] The connecting section 293 extends over a multi-part galvanic isolation structure 300. Along a direction orthogonal to a shortest connection between the first electrode section 291 and the second electrode section 292 of the upper electrode 290, the connecting section 293 is narrower than either the first electrode section 291 or the second electrode section 292. The width of the connecting section 293 is less than 20% of the corresponding widths of the first and second electrode sections 291 and 292.

[0093] The straight line segment of the multi-part galvanic isolation structure 300 comprises four parallel trench structures 333, which are laterally separated by semiconductor fins 334 formed from sections of the semiconductor layer 130. The trench structures 333 have identical widths and extend parallel to each other. Any two of the trench structures 333 can form one of the Fig. Form 3 illustrated loops.

[0094] Fig. Figure 6A further shows a first trench insulation structure 261 extending from the first surface 139 through the semiconductor layer 130 downwards to the insulator layer 120 and laterally surrounding a first embedded region 133 of the semiconductor layer 130 directly below the first lower electrode 210. A second trench insulation structure 262 extends from the first surface 139 through the semiconductor layer 130 to the insulator layer 120 and laterally surrounding a second embedded region 134 of the semiconductor layer 130 directly below the second lower electrode 220.

[0095] As in Fig. As illustrated in Figure 6B, the first trench isolation structure 261 forms a closed frame around the first embedded area 133. The second trench isolation structure 262 forms a closed frame around the second embedded area 134. For further details, refer to the description of Fig. 2A and Fig. Reference is made to 2B.

[0096] Fig. Figure 7A shows a multi-part galvanic isolation structure 330 comprising three parallel trench structures 333 in a straight line segment 331 between the first segment 131 and the second segment 132 of the semiconductor layer 130. The different trench structures 333 have the same lateral and vertical dimensions and the same configuration. Each trench structure 333 comprises a dielectric lining 335, which lines at least the side walls of a trench extending from the first surface 139 into the semiconductor layer 130, and a filling 336. The dielectric lining 335 may comprise a silicon oxide. The filling 336 may comprise a dielectric or semiconducting material, e.g., polycrystalline silicon, deposited on the dielectric lining 335. The trench structures 333 and the isolation structures 261, 262 may have the same width and configuration.

[0097] A first protective conductor 281 is formed along an edge of the first lower electrode 210. The first protective conductor 281 is formed in the lower electrode metal layer 150 at a lateral distance from the first lower electrode 210, the lateral distance between the first protective conductor 281 and the first lower electrode 210 being at least largely uniform. The first protective conductor 281 extends along all sides of the first lower electrode 210 except for the side directly facing the galvanic insulation structure 330.

[0098] A second protective conductor 282 is formed along an edge of the second lower electrode 220. The second protective conductor 282 is formed in the lower electrode metal layer 150 at a lateral distance from the second lower electrode 220, the lateral distance between the second protective conductor 282 and the second lower electrode 220 being at least largely uniform. The second protective conductor 282 extends along all sides of the second lower electrode 220 except for the side directly facing the galvanic insulation structure 330.

[0099] A first protective conductor contact 283 connects the first protective conductor 281 to a doped first protective conductor contact area 135, which is formed in a region of the first section 131 of the semiconductor layer 130 outside the first embedded region 133. The first protective conductor contact 283 and the first protective conductor contact area 135 form a resistive contact.

[0100] A second protective conductor contact 284 connects the second protective conductor 282 to a doped second protective conductor contact area 136, which is formed in a region of the second section 132 of the semiconductor layer 130 outside the second embedded region 134. The second protective conductor contact 284 and the second protective conductor contact area 136 form a resistive contact.

[0101] A first feed line 316, which in Fig. Figure 7A illustrates the connection between the first circuit element 315 and the first lower electrode 210. The connection comprises a main section formed in the metal layer 150 of the lower electrode and a through section 317 formed in an auxiliary metal layer 151. The through section 317 of the first feed line 316 and the first protective conductor 281 intersect in different metal layers. A first feed line contact connects the main section of the first feed line 316 to the through section 317, and a second feed line contact connects the first lower electrode 210 to the through section 317.

[0102] A second feed line 326, which in Fig. Figure 7A illustrates the connection between the second circuit element 325 and the second lower electrode 220. This element comprises a main section formed in the metal layer 150 of the lower electrode and a through section 327 formed in the auxiliary metal layer 151. The through section 327 of the second feed line 326 and the second protective conductor 282 intersect in different metal layers. A second feed line contact connects the main section of the second feed line 326 to the through section 327 of the second feed line 326, and a second feed line contact connects the second lower electrode 220 to the through section 327 of the second feed line 326.

[0103] Fig. 8 combines protective conductors 281, 282, as in Fig. 7A and Fig. Figure 7B illustrates, with capacitive coupling elements 200, as in Fig. Figure 5 illustrates this. A single first protective conductor 281 and a single second protective conductor 282 can be provided for electrode sections of a plurality of capacitive coupling elements 200 that are formed side by side along the straight line section of the galvanic isolation structure 330. Protective conductors with sections formed directly between adjacent electrode sections of the same device area can reduce crosstalk between signals transmitted via the adjacent capacitive coupling elements 200.

[0104] Fig.Figure 9 shows an integrated circuit 500 configured as a gate driver circuit in silicon-on-isolator technology. The integrated circuit 500 includes a high-side part 620 configured to drive a gate of a high-side switch 922 of a half-bridge, and a low-side part 610 configured to drive a gate of a low-side switch 921 of the half-bridge. A galvanic isolation structure 330, as described above, galvanically isolates the high-side part 620 from the low-side part. The integrated circuit 500 includes a high-side power supply circuit 621 to provide a positive power supply voltage VB for the high-side part 620 (high-side supply potential VB). The positive power supply voltage VB for the high-side part 620 is referenced to a high-side reference potential VS, which can correspond to the potential of the switching node of a half-bridge 920.

[0105] A high-side desaturation detection circuit 622 is connected to the supply potential VA of the half-bridge 920, detects desaturation of the high-side switch 922 of the half-bridge 920, and outputs a high-side desaturation signal indicating whether a desaturation condition exists. A high-side receiver circuit 623 includes second circuit elements 325, as described above, for receiving a differential gate control signal via two first capacitive coupling elements 201, as described above, and outputs an asymmetric high-side gate control signal. A logic circuit 624 in the high-side part 620 receives the high-side desaturation signal and the high-side gate control signal. The logic circuit 624 in the high-side part 620 outputs a second gate driver signal Gout2 in response to the high-side gate control signal, provided that the high-side desaturation signal does not specify a desaturation condition.A high-side driver stage 625 can drive the second gate driver signal Gout2.

[0106] The logic circuit 624 in the high-side section further includes first circuit elements 315, as described above, for outputting a differential high-side data signal. Two second capacitive coupling elements 202, as described above, transmit the differential high-side data signal from the high-side section 620 to a low-side receiver circuit 613 in the low-side section 610.

[0107] The low-side section 610 of the gate driver circuit includes a low-side power supply circuit 611 to provide a positive power supply voltage VDD for the low-side section 610. The positive power supply voltage VDD for the low-side section 610 is referenced to the first reference potential VSS.

[0108] A low-side desaturation detection circuit 612 is connected to the output node of the half-bridge 920, detects desaturation of the low-side switch 921, and outputs a low-side desaturation signal indicating whether a desaturation condition exists. The low-side receiver circuit 613 includes second circuit elements 325, as described above, for receiving a differential low-side data signal from the two second capacitive coupling elements 202 and outputs an asymmetric low-side data signal. A logic circuit 614 in the low-side section 610 receives the low-side data signal, the low-side desaturation signal, and a low-side gate control signal from an external source such as a processor 990.The logic circuit 614 in the low-side section 610 outputs a first gate driver signal Gout1 in response to the low-side gate control signal, provided that neither the low-side desaturation signal nor the low-side data signal specifies a desaturation condition. A low-side driver stage 615 drives the first gate driver signal Gout1.

[0109] The logic circuit 614 in the low-side section 610 further includes initial circuit elements 315, as described above, which output a differential gate control signal. The first two capacitive coupling elements 201 transmit the differential gate control signal from the low-side section 610 to the high-side section 620. An inductive load 930 is electrically connected between the switching nodes of two half-bridges 920.

[0110] The first and second capacitive coupling elements 201, 202, which have any of the configurations of the present embodiments, enable signal transmission between the low-side part 610 and the high-side part 620 and can be designed in such a way that the transmission parameters are robust against process variations.

[0111] It should be noted that the integrated circuit, including its preferred embodiments, as set forth in this document, can be used alone or in combination with the other integrated circuits disclosed herein. Furthermore, the features set forth in the context of an integrated circuit are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the integrated circuits set forth in this document can be combined in any way. In particular, the features of the claims can be combined with one another in any manner.

Claims

[1] Integrated circuit comprising: a semiconductor layer (130) comprising a first section (131) in a first device area (310) and a second section (132) in a second device area (320); a galvanic isolation structure (330) formed between the first section (131) and the second section (132) of the semiconductor layer (130); and a capacitive coupling element (200) formed on a first surface (139) of the semiconductor layer (130), wherein the capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310) and a capacitor dielectric (250) separating the first lower electrode (210) from an upper electrode (290) extending over the galvanic isolation structure (330), wherein the first lower electrode (210) is signal-connected to a first circuit element (315) formed in the first device area (310) and the upper electrode (290) is functionally connected to a second circuit element (325) formed in the second device area (320). [2] Integrated circuit according to claim 1, wherein the upper electrode (290) and the second circuit element (325) formed in the second device area (320) are directly electrically connected. [3] Integrated circuit according to claim 1, wherein the capacitive coupling element (200) further comprises a second lower electrode (220) in the second device area (320), the capacitor dielectric (250) further separates the second lower electrode (220) from the upper electrode (290) and the second lower electrode (220) is signal-connected to the second circuit element (325) formed in the second device area (320). [4] Integrated circuit according to one of the preceding claims, wherein the galvanic isolation structure (330) extends from a first surface (139) of the semiconductor layer (130) into the semiconductor layer (130) and isolates the first section (131) and the second section (132) of the semiconductor layer (130) from each other up to a breakdown voltage of at least 200 V. [5] Integrated circuit according to one of the preceding claims, wherein the upper electrode (290) comprises a section of an uppermost metal layer (180) of the integrated circuit (500). [6] Integrated circuit according to any one of the preceding claims, further comprising: a polyimide layer (190) covering the upper electrode (290). [7] Integrated circuit according to one of the preceding claims, wherein the upper electrode (290) comprises a first electrode section (291) in the first device area (310), a second electrode section (292) in the second device area (320) and a narrow connecting section (293) connecting the first electrode section (291) and the second electrode section (292). [8] Integrated circuit according to claim 7, wherein the connecting section (293) has a length along a direction that directly connects the first electrode section (291) and the second electrode section (292) in a horizontal plane parallel to the first surface (139) of the semiconductor layer (130), and a width (w3) in the horizontal plane orthogonal to the length extent, wherein the width extent (w3) is smaller than horizontal extents of the first electrode section (291) and the second electrode section (292) parallel to the width extent (w3) of the connecting section (293). [9] Integrated circuit according to one of claims 7 or 8, wherein the first electrode section (291) of the upper electrode (290) extends laterally beyond the first lower electrode (210) and / or the second electrode section (292) of the upper electrode (290) extends laterally beyond the second lower electrode (220). [10] Integrated circuit according to one of claims 7 to 9, wherein a horizontal shape of the first electrode section (291) parallel to the first surface (139) and / or the second electrode section (292) of the upper electrode (290) are rounded with a radius of at least 5 µm. [11] Integrated circuit according to any one of the preceding claims, further comprising: a first trench insulation structure (261) extending from the first surface (139) into the semiconductor layer (130) and laterally surrounding a first embedded region (133) of the semiconductor layer (130) directly below the first lower electrode (210), and / or a second trench insulation structure (262) extending from the first surface (139) into the semiconductor layer (130) and laterally surrounding a second embedded area (134) of the semiconductor layer (130) directly below the second lower electrode (220). [12] Integrated circuit according to any one of the preceding claims, further comprising: a first protective conductor (281) formed along an edge of the first lower electrode (210), and / or a second protective conductor (282) formed along an edge of the second lower electrode (220). [13] Integrated circuit according to claim 12, wherein the first protective conductor (281) is electrically connected to the first section (131) of the semiconductor layer (130) at a lateral distance from the first lower electrode (210) and / or the second protective conductor (282) is electrically connected to the second section (132) of the semiconductor layer (130) at a lateral distance from the second lower electrode (220). [14] Integrated circuit according to claim 13, wherein the first conductive protective conductor (281) and the first lower electrode (210) are formed from different sections of a lower electrode metal layer, and / or wherein the second conductive protective conductor (282) and the second lower electrode (220) are formed from different sections of a lower electrode metal layer. [15] Integrated circuit according to claim 14, further comprising: a first feed line (316) connecting the first circuit element (315) and the first lower electrode (210), wherein the first protective conductor (281) and a through section (317) of the first feed line (316) crossing the first protective conductor (281) are formed in different metal layers; and / or a second feed line (326) connecting the second circuit element (325) and the second lower electrode (220), wherein the second protective line (282) and a through section (327) of the second feed line (326) crossing the second protective line (282) are formed in different metal layers. [16] Integrated circuit according to any one of the preceding claims, further comprising: an insulating layer (120) which is formed on one side of the semiconductor layer (130) opposite the first surface (131). [17] Gate driver circuit, comprising: a semiconductor layer (130) comprising a first section (131) in a first device area (310) and a second section (132) in a second device area (320); a galvanic isolation structure (330) formed between the first section (131) and the second section (132) of the semiconductor layer (130); and a capacitive coupling element (200) formed on a first surface (139) of the semiconductor layer (130), wherein the capacitive coupling element (200) comprises a first lower electrode (210) in the first device area (310), a second lower electrode (220) in the second device area (320) and a capacitor dielectric (250) separating the first lower electrode (210) and the second lower electrode (220) from an upper electrode (290), wherein the first lower electrode (210) is signal-connected to a first circuit element (315) formed in the first device area (310) and the second lower electrode (220) is signal-connected to a second circuit element (325) formed in the second device area (320).

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