Semiconductor packages and methods for forming them

Abstract

A device comprises a substrate package including component substrates and a first encapsulating means around and between the component substrates. A wafer package is attached to a first side of the substrate package and includes integrated circuit devices and a second encapsulating means around and between the integrated circuit devices. Voltage regulators are attached to a second side of the substrate package, the component substrates electrically connecting the voltage regulators to the integrated circuit devices. External connectors are also attached to the second side of the substrate package, the component substrates electrically connecting the external connectors to the integrated circuit devices.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over preliminary U.S. application No. 63 / 735,658 filed on December 18, 2024, which is hereby incorporated by reference herein. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to an iterative reduction in the minimum feature size, enabling the integration of more components into a given area. As the demand for shrinkable electronic devices has increased, a need has arisen for smaller and more innovative packaging techniques for semiconductor dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in combination with the accompanying figures. It should be noted that, in accordance with standard industry practice, various structures are not drawn to scale. In fact, the dimensions of the various structures may have been enlarged or reduced arbitrarily for the clarity of the discussion. Fig. Figure 1 is a cross-sectional view of an integrated circuit die. Fig. 2A-2B are cross-sectional views of die stacks. Fig. Figures 3-8 are cross-sectional views of intermediate stages in the manufacture of a wafer package according to some embodiments. Fig. Figure 9 is a cross-sectional view of a wafer package according to some embodiments. Fig. Figures 10-19 are cross-sectional views of intermediate stages in the manufacture of a component substrate according to some embodiments. Fig. Figures 20-25 show intermediate stages in the manufacture of a substrate package according to some embodiments. Fig. Figure 26 is a cross-sectional view of a system-on-wafer arrangement according to some embodiments. Fig. Figures 27-28 show views of intermediate stages in the manufacture of a substrate package according to some embodiments. Fig. Figure 29 is a cross-sectional view of a system-on-wafer arrangement according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structure above or on top of a second structure in the following description may include embodiments in which the first and second structures are in direct contact, and may also include embodiments in which additional structures may be formed between the first and second structures, so that the first and second structures may not be in direct contact. Additionally, the present disclosure may repeat reference numerals in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or structure to another element(s) or structure(s), as shown in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] According to various embodiments, a system package comprises a wafer package attached to a substrate package. The substrate package includes several component substrates encapsulated in a first encapsulation means, while the wafer package includes several integrated circuit devices encapsulated in a second encapsulation means. The wafer package is attached to a first side of the substrate package. Voltage regulators and external connectors are attached to a second side of the substrate package, with the component substrates electrically connecting these components to the integrated circuit devices.

[0007] The substrate package can contain separate component substrates for power distribution and external interconnection. These component substrates can be individually tested and verified as known good substrates before integration into the substrate package, potentially improving overall yield and reliability. Furthermore, different types of component substrates can be used within the same package; for example, some component substrates can have passive devices, while others can be coreless, allowing for customization based on the specific power, signal, or space requirements of different regions within the system package.

[0008] Fig. Figure 1 is a cross-sectional view of an integrated circuit die 50. Several integrated circuit dies 50 are packaged in a subsequent processing step. Each 50-inch integrated circuit die can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC) die, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a high-frequency (HF) die, an interface die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g.,The integrated circuit die 50 can be a digital signal processing (DSP) die, a front-end die (e.g., analog front-end dies (AFE dies)), the like, or combinations thereof. The integrated circuit die 50 can be formed on a wafer, which may have different die regions that are subsequently separated to form a plurality of integrated circuit dies 50. The integrated circuit die 50 comprises a semiconductor substrate 52, an interconnect structure 54, die connectors 56, and a dielectric layer 58.

[0009] The semiconductor substrate 52 can be a silicon substrate, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active surface (e.g., the surface that is in Fig. 1 points upwards) and an inactive surface (e.g., the surface that is in Fig. 1 points downwards). Devices (not shown separately) are located on the active surface of the semiconductor substrate 52. The devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface can be free of devices.

[0010] The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 can have one or more dielectric layer(s) and corresponding metallization layer(s) within the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide, nitrides such as silicon nitride, combinations thereof such as silicon oxynitride, or the like. Other dielectric materials can also be used, such as polymers such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB)-based polymer, or the like.The metallization layer(s) may include conductive vias and / or conductive traces to connect the devices of the semiconductor substrate 52. The metallization layer(s) may be formed from a conductive material such as a metal like copper, cobalt, aluminum, gold, combinations thereof, or the like. The metallization layer(s) of the interconnect structure 54 may be formed by a Damascene process such as a single-Damascene process, a dual-Damascene process, or the like.

[0011] The die connectors 56 are located on the front face 50F of the integrated circuit die 50. The die connectors 56 can be conductive pillars, pads, or the like, used to establish external connections. The die connectors 56 can be located in and / or on the interconnect structure 54. For example, the die connectors 56 can be part of an upper metallization layer of the interconnect structure 54. The die connectors 56 can be made of a metal such as copper, aluminum, or the like, and can be formed, for example, by plating or the like.

[0012] Optionally, solder pads (not shown separately) can be placed on the die connectors 56 during the formation of the integrated circuit die 50. These solder pads can be used to perform a chip probe (CP) test on the integrated circuit die 50. For example, the solder pads can be solder balls, solder bumps, or the like, used to attach a chip probe to the die connectors 56. The chip probe test can be performed on the integrated circuit die 50 to determine if it is a known good die (KGD). Thus, only KGDs are packaged for subsequent processing, and dies that fail the chip probe test are not packaged. After testing, the solder pads can be removed.

[0013] A dielectric layer 58 is located on the front face 50F of the integrated circuit die 50. The dielectric layer 58 can be located within and / or on the interconnect structure 54. For example, the dielectric layer 58 can be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 can be an oxide, a nitride, a polymer, the like, or a combination thereof, which can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. The dielectric layer 58 can laterally encapsulate the die interconnects 56. The front faces of the die interconnects 56 and the dielectric layer 58 can be substantially coplanar (within process variations) on the front face 50F of the integrated circuit die 50.

[0014] Fig. Figures 2A-2B are cross-sectional views of die stacks 60A and 60B, respectively. Die stacks 60A and 60B can each have a single function (e.g., a logic device, a memory die, etc.) or they can each have multiple functions. In some embodiments, die stack 60A is a logic device, such as a system-on-integrated-chip (SoIC) device, and die stack 60B is a memory device, such as a high-bandwidth-memory (HBM) device.

[0015] As in Fig. As shown in Figure 2A, the die stack 60A comprises two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die and the second integrated circuit die 50B is an interface die. An interface die forms a bridge from a logic die to memory dies and translates instructions between the logic die and the memory dies. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded such that their active surfaces face each other (e.g., they are bonded "face-to-face"). Conductive vias 62 can be formed through one of the integrated circuit dies 50, allowing external connections to be made to the die stack 60A.The conductive vias 62 can be through-substrate vias (TSVs), such as through-silicon vias or the like. In the illustrated embodiment, the conductive vias 62 are formed in the second integrated circuit die 50B (e.g., the interface die). The conductive vias 62 extend through the semiconductor substrate 52 of the respective integrated circuit die 50 to be physically and electrically connected to the metallization layer(s) of the interconnect structure 54.

[0016] As in Fig. As shown in Figure 2B, the die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, the die stack 60B can be a stacked memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) device, a high-bandwidth memory cube (HBM) device, or the like. Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected by conductive vias 62, such as TSVs.

[0017] As described below, a system package is formed by packaging integrated circuit devices. The integrated circuit devices can be integrated circuit dies (similar to the integrated circuit die 50, which is used for Fig. 1 is described) or can be die stacks (similar to die stacks 60A, 60B, which are for Fig. (described in sections 2A-2B). The system package has multiple compute sites and multiple interconnects. Each integrated circuit device in the system package can have, for example, logic functions, memory functions, or the like, and the system package can be a single computing system that includes the compute sites and interconnects, such as a system-on-wafer (SoW). For example, the system package can be an artificial intelligence accelerator, and each compute site can be a neural network node for the AI ​​accelerator. The interconnects can include external connectors for connecting the compute sites to an external system. Example external systems that can implement the system package include AI servers, high-performance computing (HPC) systems, high-performance computing devices, cloud computing systems, edge computing systems, and the like.

[0018] Fig. Figures 3-8 are cross-sectional views of intermediate stages in the production of a 100A wafer package (see Fig. 8) according to some embodiments. The wafer package 100A is a reconstituted wafer comprising integrated circuit devices in an encapsulation medium. The wafer package 100A is subsequently attached to a substrate package to form a system package.

[0019] In Fig. Step 3 provides a support substrate 102 and forms a separation layer 104 on the support substrate 102. The support substrate 102 can be a glass substrate, a ceramic substrate, or the like. The support substrate 102 can be a wafer.

[0020] The release layer 104 can be made of a polymer-based material that, together with the support substrate 102, can be removed from the overlying structure formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 104 can be dispersed and cured as a liquid, be a laminate film laminated onto the support substrate 102, or the like. The upper surface of the release layer 104 can be leveled and may exhibit a high degree of planarity.

[0021] A rear-side redistribution structure 110 is formed on the separating layer 104. The rear-side redistribution structure 110 has dielectric layers 112 and metallization layers 114 (sometimes referred to as redistribution layers or redistribution lines) amidst the dielectric layers 112. Thus, the rear-side redistribution structure 110 has metallization layers 114 that are separated from each other by corresponding dielectric layers 112.

[0022] The dielectric layers 112 can each be formed from a suitable dielectric material. In some embodiments, the dielectric layers 112 are formed from silicon oxide, silicon nitride, silicon oxynitride, or the like, which can be formed by a suitable deposition process such as CVD, ALD, or the like. In some embodiments, the dielectric layers 112 are formed from a polymer, which can be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, which can be structured using a lithography mask formed by spin coating, lamination, CVD, or the like. In some embodiments, the dielectric layers 112 are formed from a molding compound, which can include a resin with fillers arranged therein. Examples of resins include epoxy-, acrylic-, or polyimide-based materials.Examples of fillers include silicon dioxide or similar materials. The molding compound can be applied by compression molding, transfer molding, or similar processes, and can be applied in liquid or semi-liquid form and then subsequently cured.

[0023] The metallization layers 114 each feature conductive vias and / or conductive traces. The conductive vias extend through respective dielectric layers 112, and the conductive traces extend along respective dielectric layers 112. The metallization layers 114 can be formed from a conductive material. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The metallization layers 114 can be composite layers comprising a multitude of sublayers formed from different materials.

[0024] As an example of forming a layer of the backside redistribution structure 110, a dielectric layer 112 can be formed from a polymer. After the dielectric layer 112 has formed, it can be patterned to expose underlying conductive features (if any), such as an underlying metallization layer. The patterning can be performed by any acceptable process, such as exposing the dielectric layers to light if the dielectric layers 112 are a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layers 112 are photosensitive materials, they can be developed after exposure. This forms a metallization layer 114.For example, a seed layer (not shown separately) can be formed over the respective underlying features. The seed layer can be formed on the dielectric layer 112 and in any openings through the dielectric layer 112. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using a deposition process such as physical vapor deposition (PVD) or the like. Then, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to a metallization layer 114. The patterning creates openings through the photoresist to expose the seed layer.A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating or electroplating, from the seed layer or the like. Then, the photoresist and portions of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layer 114.

[0025] As another example of forming a layer of the backside redistribution structure 110, a metallization layer 114 can be formed. For example, a seed layer (not shown separately) can be formed over the respective underlying features, such as an underlying dielectric layer. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using a deposition process such as physical vapor deposition (PVD) or the like. Then, a first photoresist is formed and patterned on the seed layer. The first photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the first photoresist corresponds to conductive traces for the metallization layer 114.The structuring process creates openings through the first photoresist to expose the seed layer. A conductive material is formed in the openings of the first photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating or electroplating, from the seed layer, or similar processes. The first photoresist is then removed. The first photoresist can be removed by an acceptable ashing or peeling process, such as using an oxygen plasma, or similar methods. A second photoresist is then formed and structured on the seed layer and the conductive traces. The second photoresist can be formed by spin coating or similar processes and can be exposed to light for structuring. The pattern of the second photoresist corresponds to conductive vias for the metallization layer 114.The structuring process creates openings through the second photoresist to expose the conductive traces. Additional conductive material is formed in the openings of the second photoresist and on the exposed portions of the conductive traces. The conductive material can be formed by plating, such as electroless plating or electroplating, onto the conductive traces, or by the like. In some embodiments, no seed layers are formed between the conductive traces and the conductive vias. In this case, the second photoresist and portions of the seed layer where the conductive material is not formed are removed. The second photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like.After the second photoresist is removed, exposed portions of the seed layer are removed, for example, using an acceptable etching process such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization layer 114. A dielectric layer 112 is formed around the metallization layer 114. The dielectric layer 112 can be formed from a molding compound. The dielectric layer 112 can be formed over the metallization layer 114, so that the metallization layer 114 is buried or covered. A planarization process can then be performed on the dielectric layer 112 to expose the conductive vias of the metallization layer 114. The top surfaces of the dielectric layer 112 and the metallization layer 114 are essentially coplanar after the planarization process (within process variations).The planarization process can, for example, be chemical-mechanical polishing (CMP).

[0026] The rear-side redistribution structure 110 can comprise a combination of different types of dielectric layers 112. In some embodiments, certain dielectric layers 112 can be formed from polymer (as previously described), while other dielectric layers 112 within the same structure can be formed from molding compound (as previously described). This hybrid approach can enable tailored properties in different regions of the redistribution structure. For example, polymer-based dielectric layers can be used in regions where precise structuring is performed by lithography, while molding compound layers can be used in regions that benefit from their specific mechanical or electrical properties.

[0027] The rear-side redistribution structure 110 is shown as an example. More or fewer dielectric layers 112 and metallization layers 114 than shown can be formed by repeating the previously described steps any desired number of times.

[0028] Under-bump metallization layers (UBMLs) 116 are formed for subsequent connection with the backside redistribution structure 110. The UBMLs 116 have bump sections and extend along the main surface of the upper dielectric layer 112 of the backside redistribution structure 110 and have via sections that extend through the upper dielectric layer 112 of the backside redistribution structure 110 to physically and electrically couple the upper metallization layer 114 of the backside redistribution structure 110. The UBMLs 116 can be formed from the same material as the metallization layers 114 and can be formed by a similar process. In some embodiments, the UBMLs 116 have a different size than the metallization layers 114.

[0029] In Fig. Four vias 118 are formed on a first subset of the UBMLs 116. Additionally, interconnection dies 120 are attached to a second subset of the UBMLs 116. The second subset of the UBMLs 116 remains free of the vias 118. The first subset of the UBMLs 116 and the vias 118 are subsequently used for communication with higher layers of the wafer package. The second subset of the UBMLs 116 and the interconnection dies 120 are subsequently used for direct communication between integrated circuit devices of the resulting wafer package.

[0030] As an example of forming the vias 118, a photoresist is formed and patterned on the UBMLs 116 and the backside redistribution structure 110. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the vias 118. The patterning creates openings through the photoresist to expose the UBMLs 116. A conductive material is formed in the openings of the photoresist and on the exposed sections of the UBMLs 116. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material of the vias 118 can be plated directly from a conductive material of the UBMLs 116. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist is then removed.The photoresist can be removed by an acceptable ashing or removal process, such as using an oxygen plasma or the like. The remaining sections of conductive material form the vias 118.

[0031] Each interconnect die 120 can be a local silicon interconnect (LSI), a large-format integration package, an interposer die, or the like. Each interconnect die 120 has a substrate 122, wherein conductive structures are formed in and / or on the substrate 122. The substrates 122 can be a semiconductor substrate, one or more dielectric layers, or the like. Additionally, each interconnect die 120 can have through-silicon vias (TSVs) 124 extending into or through the substrate 122, which can be coupled to the conductive features of the interconnect die 120. An interconnect die 120 is attached to the UBMLs 116 using die connectors 126 located on the back side of the interconnect die 120. Some of the die connectors 126 can be electrically coupled to the front of the connecting die 120 via the TSVs 124.As described in more detail below, the TSVs 124 are small, for example smaller than the vias 118. Because the TSVs 124 are small, they can have a higher density, which increases the number of connections to the connection dies 120.

[0032] In embodiments where the interconnect dies 120 are LSIs, the interconnect dies 120 can be bridge structures comprising die bridges 128. The die bridges 128 can be metallization layers formed in and / or on, for example, the substrate 122, and serve to connect overlying integrated circuit devices (described below). The die bridges 128 are located on the front face of the interconnect dies 120. Thus, the LSIs can be used to directly connect the integrated circuit devices and enable communication between them. In such embodiments, the interconnect dies 120 can be placed in regions located between the downstream integrated circuit devices, so that each interconnect die 120 overlaps several overlying integrated circuit devices.In some embodiments, the connecting dies 120 may further include logic devices and / or memory devices. In some embodiments, the connecting dies 120 may be free of logic devices and / or memory devices. The connecting dies 120 are attached to the UBMLs 116 such that the die bridges 128 face away from the rear redistribution structure 110.

[0033] In the illustrated embodiment, the connection dies 120 are attached to the rear redistribution structure 110 (via the UBMLs 116) by solder connections, such as conductive connectors 130. The conductive connectors 130 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection bumps (C4 bumps), micro-bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG), or the like. The conductive connectors 130 can comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connectors 130 may be made of a conductive material such as copper, aluminium, gold, nickel, silver, palladium, tin or the like.In some embodiments, the conductive connectors 130 are formed by initially forming a layer of solder by evaporation, electroplating, printing, solder transfer, bead placement, or the like. Once a layer of solder has formed, melting can be performed to shape the material into the desired bump shapes. Attaching the connecting die 120 to the UBMLs 116 can involve placing the connecting die 120 onto the UBMLs 116 (e.g., using a pick-and-place process) and melting the conductive connectors 130 to physically and electrically couple the die connectors 126 to the UBMLs 116. In another embodiment, the connecting dies 120 are attached to the rear redistribution structure 110 with direct connections using the die connectors 126.

[0034] In some embodiments, an underfill 132 is formed around the conductive connectors 130 and between the rear redistribution structure 110 and the connection dies 120. The underfill 132 can reduce the stress and protect the connection points resulting from the melting of the conductive connectors 130. The underfill 132 can also be used to securely connect the connection dies 120 to the rear redistribution structure 110, providing structural support and environmental protection. The underfill 132 can be formed from a molding compound, epoxy, or the like. The underfill 132 can be formed by a capillary flow process after the connection dies 120 have been applied, or it can be formed by a suitable deposition process before the connection dies 120 are applied.The underfill 132 can be applied in liquid or semi-liquid form and then subsequently hardened.

[0035] Optionally, the connecting dies 120 can have die connectors 134 arranged on the front of the connecting die 120. The die connectors 134 can be electrically coupled to the die bridges 128.

[0036] The interconnect dies 120 can be optional components in the wafer package. The inclusion or exclusion of interconnect dies 120 may depend on specific design requirements, performance targets, or manufacturing considerations. While interconnect dies 120 can be implemented as local silicon interconnects (LSIs) in some cases, alternative components such as integrated voltage regulators (IVRs) or integrated passive devices (IPDs) can be used instead of LSIs. These alternative components can provide different functionalities or advantages depending on the specific requirements of the wafer package. For example, IVRs can offer improved power management capabilities, while IPDs can provide improved integration of passive components within the wafer package.

[0037] In Fig. 5. An encapsulating agent 136 is formed on and around the various components. After formation, the encapsulating agent 136 encapsulates the UBMLs 116, the vias 118, the interconnect dies 120, and / or the underfill 132. The encapsulating agent 136 can be a molding compound, epoxy, or the like. The encapsulating agent 136 can be applied by compression molding, transfer molding, or the like and can be formed over the support substrate 102 such that the vias 118 and / or the interconnect dies 120 are buried or covered. The encapsulating agent 136 is also formed in gap regions between the interconnect dies 120 and the vias 118. The encapsulating agent 136 can be applied in liquid or semi-liquid form and then subsequently cured.

[0038] A planarization process can optionally be performed on the encapsulating medium 136 to expose the vias 118 and the connecting dies 120 (e.g., the die connectors 134). The planarization process can remove material from the vias 118, the connecting dies 120, and / or the encapsulating medium 136 until the connecting dies 120 and the vias 118 are exposed. The top surfaces of the vias 118, the die connectors 134, and the encapsulating medium 136 are substantially coplanar (within process variations) after the planarization process. The planarization process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, the planarization can be omitted, for example, if the vias 118 and / or the die connectors 134 are already exposed.After the planarization process, the through-hole vias 118 extend through the encapsulating medium 136. As such, the through-hole vias 118 can be referred to as through-mold vias (TMVs).

[0039] In Fig. 6 A front-side redistribution structure 140 is formed on the front surfaces of the encapsulating medium 136, the interconnecting dies 120 (e.g., the die connectors 134), and the vias 118. The front-side redistribution structure 140 has dielectric layers 142 and metallization layer(s) 144 (sometimes referred to as redistribution layers or redistribution lines) beneath the dielectric layers 142. Thus, the front-side redistribution structure 140 has metallization layer(s) 144 that are separated from each other by corresponding dielectric layers 142. The metallization layer(s) 144 of the front-side redistribution structure 140 are connected to the vias 118 and to the interconnecting dies 120 (e.g., the die connectors 134).

[0040] In some embodiments, the dielectric layers 142 are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers 142 are formed from a nitride such as silicon nitride, an oxide such as silicon oxide, or the like. The dielectric layers 142 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. Once a dielectric layer 142 has been formed, it can be patterned to expose underlying conductive structures such as sections of the vias 118, the die connectors 134, and / or the metallization layer(s) 144.The structuring can be carried out by any acceptable process, such as by exposing the dielectric layers 142 to light if they are formed from photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layers 142 are formed from a photosensitive material, they can be developed after exposure.

[0041] The metallization layer(s) 144 each have conductive vias and / or conductive traces. The conductive vias extend through the respective dielectric layers 142, and the conductive traces extend along the respective dielectric layers 142. As an example of forming a metallization layer 144, a seed layer (not shown separately) is formed over the respective underlying structures. For example, the seed layer can be formed on the respective dielectric layer 142 and in any openings through the respective dielectric layer 142. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using a deposition process such as PVD or the like. Then, a photoresist is formed and patterned on the seed layer.The photoresist can be formed by spin coating or similar processes and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 144. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating or electroplating, of the seed layer or similar processes. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or similar materials, or combinations thereof. The photoresist and portions of the seed layer where the conductive material is not formed are then removed.The photoresist can be removed by an acceptable ashing or removal process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, for example, by an acceptable etching process such as wet or dry etching. The remaining portions of the seed layer and the conductive material form a metallization layer 144 of the front-side redistribution structure 140.

[0042] The front-side redistribution structure 140 is shown as an example. More or fewer dielectric layers 142 and metallization layer(s) 144 than shown can be formed by repeating the previously described steps any desired number of times.

[0043] Other variations of the front-side redistribution structure 140 are considered. For example, some of the dielectric layers 142 can be formed from an encapsulating material such as a molding compound, epoxy, or the like. A metallization layer 144 can be formed by plating a conductive via from a conductive conductor. A dielectric layer 142 can be formed by encapsulating this metallization layer 144. Any desired stack of materials can be used for the dielectric layers 142.

[0044] Under-bump metallizations (UBMs) 146 can be formed through the upper dielectric layer 142 of the front-side redistribution structure 140. The UBMs 146 are physically and electrically coupled to the upper metallization layer 144 of the front-side redistribution structure 140. The UBMs 146 each have conductive vias and conductive bumps. The conductive vias extend through the upper dielectric layer 142, and the conductive bumps extend along the upper dielectric layer 142. The UBMs 146 can be formed from the same material(s) as the metallization layer(s) 144. In some embodiments, the UBMs 146 have a different size than the metallization layer(s) 144.

[0045] In Fig. 7 Integrated circuit devices 70 are attached to the front-side redistribution structure 140. A desired type and number of integrated circuit devices 70 are adjacent to one another. In some embodiments, the integrated circuit devices 70 comprise a first type of integrated circuit device (such as computing devices 70A) and a second type of integrated circuit device (such as interface devices 70B). The computing devices 70A and the interface devices 70B can be implemented in processes of the same technology node or in processes of different technology nodes. For example, the computing devices 70A can be implemented by a more advanced process node than the interface devices 70B.

[0046] Each 70A computing device can include a logic die, a memory die, and / or the like. The 70A computing devices can be integrated circuit dies (similar to the 50 integrated circuit die, which is used for Fig. 1 is described) or can be die stacks (similar to die stacks 60A, 60B, which are for Fig. (described in 2A-2B). In some embodiments, the computing devices 70A are system-on-a-chip dies (SoC dies). In some embodiments, the computing devices 70A are die stacks, such as system-on-integrated-chip devices (SoIC devices). Each die stack may include one system-on-a-chip die (SoC die) and one or more HBM dies. In some embodiments, the computing device 70A includes various combinations of logic components, such as system-on-chip dies (SoC dies) or I / O dies, along with other specialized components. These combinations may include memory modules, photonic silicon elements, or integrated passive devices (IPDs).

[0047] Each 70B interface device can have input / output interfaces, memory controllers, network interfaces, or other types of interface circuitry to provide a bridge for communication between the 70A computing devices and external components. The 70B interface devices can translate commands and data between protocols used by the 70A computing devices and protocols used by the external components. The 70B interface devices can be integrated circuit dies (similar to the 50 integrated circuit die used for Fig. 1 is described) or can be die stacks (similar to die stacks 60A, 60B, which are for Fig. 2A-2B are described). In some embodiments, the interface devices are 70B I / O dies.

[0048] The interface devices 70B can be arranged around the computing devices 70A to facilitate connections to external systems. In particular, the interface devices 70B can surround the computing devices 70A in a top view (described below). This arrangement can enable shorter electrical paths between the interface devices 70B and external connectors (described below) attached to the system package.

[0049] In the illustrated embodiment, the integrated circuit devices 70 are attached to the front-side redistribution structure 140 by soldered connections, such as conductive connectors 152. The conductive connectors 152 can be made of a meltable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connectors 152 are formed by initially forming a layer of solder by processes such as evaporation, electroplating, printing, solder transfer, bead placement, or the like. Once a layer of solder has been formed, melting can be carried out to shape the conductive connectors 152 into desired bump shapes.Attaching the integrated circuit devices 70 to the front-side redistribution structure 140 can involve placing the integrated circuit devices 70 onto the front-side redistribution structure 140 and melting the conductive connectors 152. For example, the integrated circuit devices 70 can be placed onto the front-side redistribution structure 140 using a pick-and-place tool. The conductive connectors 152 are melted to attach die connectors 154 to the front faces of the integrated circuit devices 70 at the UBMs 146 of the front-side redistribution structure 140, thereby electrically connecting the front-side redistribution structure 140 to the integrated circuit devices 70. In another embodiment, the integrated circuit devices 70 are attached to the front-side redistribution structure 140 by direct connections using the die connectors 154.

[0050] In some embodiments, an underfill 160 is formed around the conductive connectors 152 and between the front redistribution structure 140 and the integrated circuit devices 70. The underfill 160 can reduce the stress and protect the connection points resulting from the melting of the conductive connectors 152. The underfill 160 can be formed from an underfill material such as a molding compound, epoxy, or the like. The underfill 160 can be formed by a capillary flow process after the integrated circuit devices 70 have been attached to the front redistribution structure 140, or it can be formed by a suitable deposition process before the integrated circuit devices 70 are attached to the front redistribution structure 140.The underfill 160 can be applied in liquid or semi-liquid form and then subsequently hardened.

[0051] An encapsulating agent 162 is formed around the various components. Once formed, the encapsulating agent 162 laterally encapsulates the underfill 160 (if present) and the integrated circuit devices 70. The encapsulating agent 162 can be a molding compound, epoxy, or the like. The encapsulating agent 162 can be applied by compression molding, transfer molding, or the like, and can be formed over the front redistribution structure 140 so that the integrated circuit devices 70 are buried or covered. The encapsulating agent 162 is also formed in gap regions between the underfill 160 (if present) and / or the integrated circuit devices 70. The encapsulating agent 162 can be applied in liquid or semi-liquid form and then subsequently cured.

[0052] An optional removal process can be performed on the encapsulating medium 162 to expose the integrated circuit devices 70. The removal process can include, for example, a planarization process such as chemical-mechanical polishing (CMP), grinding, or the like. The top surfaces of the encapsulating medium 162 and the integrated circuit devices 70 can be substantially coplanar (within process variations) after the planarization process. Planarization can be omitted, for example, if the integrated circuit devices 70 are already exposed.

[0053] In Fig. 8. A support substrate debonding process can be performed to separate (or “debond”) the support substrate 102 from the rear-side redistribution structure 110. According to some embodiments, the debonding involves projecting light, such as UV light, onto the release layer 104, causing the release layer 104 to decompose under the heat of the light and allowing the support substrate 102 to be removed. The remaining structure is a wafer package 100A, which is subsequently attached to a substrate package. The wafer package 100A can be placed on a tape, a support substrate, or another suitable support structure (not shown separately) for subsequent processing.

[0054] UBMs 164 can be configured for subsequent connection with the rear-side redistribution structure 110. The UBMs 164 have ridged sections located on and extending along the main surface of the lower dielectric layer 112 of the rear-side redistribution structure 110, and have via-hole sections extending through the lower dielectric layer 112 of the rear-side redistribution structure 110 to physically and electrically couple the lower metallization layer 114 of the rear-side redistribution structure 110. The UBMs 164 can be formed from the same material as the metallization layers 114 and can be formed by a similar process. In some embodiments, the UBMs 164 can have a different size than the metallization layers 114.

[0055] Fig. Figure 9 is a cross-sectional view of a wafer package 100B according to some embodiments. In this embodiment, the integrated circuit devices 70 are encapsulated in the encapsulation medium 162, potentially while the integrated circuit devices 70 are arranged on a support substrate. The redistribution structure 110 is then formed on the encapsulation medium 162, wherein the metallization layers 114 of the redistribution structure 110 are electrically coupled to the integrated circuit devices 70. The UBMs 164 are configured for the redistribution structure 110, for example by an upper dielectric layer 112 of the redistribution structure 110.

[0056] Fig. Figures 10-19 are cross-sectional views of intermediate stages in the production of a component substrate 200 (see Fig. 19) according to some embodiments. Several component substrates 200 are packaged in a subsequent processing step. Each component substrate 200 can be used to connect voltage regulator modules (VRMs) or external connectors to integrated circuit devices. In some aspects, a component substrate 200 can be a power distribution board or a connector board. The component substrates 200 can enable direct communication between integrated circuit devices (such as computing devices, interface devices, or the like) and external connectors or VRMs. The component substrate 200 can have an organic core or it can be coreless. In some aspects, the component substrate 200 can contain devices, such as passive devices. In other aspects, the component substrate 200 can be free of devices.

[0057] While the formation of a single component substrate 200 is described, it is understood that several component substrates 200 can be produced simultaneously, for example on a larger panel or wafer. After the production steps are completed, the component substrates 200 can be separated or singulated from the larger panel.

[0058] In Fig. 10. A substrate core 202 with seed layers 204 on opposite sides is provided. The substrate core 202 can be an FR-4 or BT resin core. The substrate core 202 can be formed from a pre-impregnated composite fiber (“prepreg”), an insulating film or build-up film, paper, glass fiber, non-woven glass fabric, silicon, or the like. In some embodiments, the substrate core 202 is an organic core formed from organic material or materials. In some embodiments, the substrate core 202 is formed from a prepreg comprising glass fiber and a resin. The seed layers 204 can be one or more layers of copper, titanium, nickel, aluminum, combinations thereof, or the like, and can be deposited or laminated on opposite sides of the substrate core 202.In some embodiments, the substrate core 202 and the nucleation layers 204 are part of a double-sided copper-clad laminate substrate (CCL substrate), such as a copper-clad epoxy-impregnated glass fabric laminate, a copper-clad polyimide-impregnated glass fabric laminate, or the like.

[0059] In Fig. 11 Openings 206 are formed in the substrate core 202 and the nucleation layers 204. In some embodiments, the openings 206 are formed by laser drilling. Other processes, such as mechanical drilling, can also be used to form the openings 206. The openings 206 can have any top-view shape, such as a polygon, a circle, or the like. A cleaning process can then be carried out to clean areas near the openings 206 that may have been smeared with removed material from the substrate core 202. The cleaning process can be a desmearing process. Desmearing can be achieved mechanically (e.g., blasting with a fine abrasive in a wet slurry), chemically (e.g., rinsing with a combination of organic solvents, permanganates, and the like), or by a combination of mechanical and chemical processes.

[0060] In Fig. 12. Conductive vias 208 are formed in the openings 206, and conductive traces 210 are formed on opposite sides of the substrate core 202. The conductive vias 208 and conductive traces 210 can be formed from a conductive material such as copper, titanium, tungsten, aluminum, or the like. The conductive vias 208 and conductive traces 210 can be formed from the same material or different materials and can be formed by the same process or different processes. In some embodiments, the conductive vias 208 are formed by a first process, and the conductive traces 210 are formed by a second process.For example, a first plating process, such as electroless plating, can be used to deposit a conductive material in the openings 206, thereby forming the conductive vias 208. In embodiments where electroless plating is used, seed layers can be formed in the openings 206. A second plating process, such as electroplating, electroless plating, or the like, can be performed using the seed layers 204. A photoresist is formed and patterned on the seed layers 204. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive traces 210. The patterning creates openings through the photoresist to expose the seed layer.A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The photoresist and portions of the seed layers 204 where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or removal process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layers 204 are removed, such as by using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layers 204 and the conductive material form the conductive traces 210.

[0061] In Fig. 13. An adhesive 212 can be applied to one side of the substrate core 202 and over the conductive lines 210. The adhesive 212 can be applied using various techniques such as lamination, spin coating, or spray coating. In some cases, the adhesive 212 can be an adhesive tape laminated to the surface. The adhesive 212 can cover the surface of the substrate core 202 and the conductive lines 210 on one side, or it can be applied selectively to specific areas. In some cases, the adhesive 212 can be applied temporarily to provide support during subsequent processing steps and can be removed later.

[0062] In Fig. Optionally, an opening 214 can be formed by removing sections of the substrate core 202 and the adhesive 212. Material removal to form the opening 214 can be achieved through various processes, such as computer numerical control (CNC) drilling, laser cutting, or laser drilling. In embodiments using CNC drilling, a mechanical drill, controlled by a computer or controller, removes material from the desired locations. Laser-based processes can also be used for more precise or complex opening shapes. The size and shape of the opening 214 can be customized to accommodate specific components or achieve desired mechanical properties. The opening 214 can extend through both the substrate core 202 and the adhesive 212.The remaining sections of the material form a frame-like structure around the opening 214. The opening 214 can accommodate a passive device, if present, enabling efficient integration of these components within the component substrate 200.

[0063] In Fig. In step 15, a support substrate 222 is provided and a separation layer 224 is formed on the support substrate 222. The support substrate 222 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 222 can be a wafer.

[0064] The release layer 224 can be formed from a polymer-based material that, together with the support substrate 222, can be removed from the overlying structure formed in subsequent steps. In some embodiments, the release layer 224 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 224 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 224 can be dispensed as a liquid and cured, be a laminate film that is laminated onto the support substrate 222, or the like. The upper surface of the release layer 224 can be leveled and may exhibit a high degree of planarity.

[0065] A dielectric layer 226 is formed on the separating layer 224. The dielectric layer 226 can be formed from a suitable dielectric material. In some embodiments, the dielectric layer 226 is formed from silicon oxide, silicon nitride, silicon oxynitride, or the like, which can be formed by a suitable deposition process such as CVD, ALD, or the like. In some embodiments, the dielectric layer 226 is formed from a polymer, which can be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, which can be structured using a lithography mask formed by spin coating, lamination, CVD, or the like.

[0066] The substrate core 202 can be bonded to the dielectric layer 226 using the adhesive 212. The adhesive 212 can be activated by applying pressure, heat, or a combination thereof to bond the substrate core 202 to the dielectric layer 226. In some embodiments, the adhesive 212 can be a thermosetting adhesive that hardens and forms a strong bond when exposed to elevated temperatures. The bonding process can be carried out using equipment such as a laminating press or a vacuum laminator to ensure a uniform pressure and temperature distribution across the bond interface.

[0067] In some embodiments, if the substrate core 202 has an opening 214, UBMs 228 can be formed through the dielectric layer 226. The UBMs 228 can be formed before the substrate core 202 is bonded to the dielectric layer 226. Initially, openings in the dielectric layer 226 can be patterned using photolithography and / or etching techniques. Then, a seed layer can be deposited covering the openings and the surface of the dielectric layer 226. A photoresist can be applied and patterned to define the shape and size of the UBMs 228. Electroplating or electroless plating processes can be used to form a conductive material (such as copper) in the openings through the photoresist to create the UBMs 228. After plating, the photoresist can be removed, and the excess seed layer can be etched away.In some cases, additional metal layers can be formed on the UBMs 228 to improve their properties or to facilitate bonding with subsequent components. The resulting UBMs 228 can extend through the dielectric layer 226. During the bonding of the substrate core 202 to the dielectric layer 226, the opening 214 in the substrate core 202 can be aligned with the UBMs 228.

[0068] In Fig. In Figure 16, a passive device 230 is attached to the underlying structure. The passive device 230 will be contained within the component substrate 200 to provide specific electrical properties, improve signal integrity, perform power distribution within the substrate, or the like. The passive device 230 can be placed, for example, through the substrate core 202 in the opening 214 using a pick-and-place tool, but any other method for placing the passive device 230 can also be used. The type and placement of the passive device 230 can be determined by factors such as the intended application of the substrate, performance targets, or space constraints. Although a single passive device 230 is shown and described, it is understood that some embodiments may have multiple passive devices 230 within the component substrate 200.

[0069] The passive device 230 can be formed or processed according to applicable manufacturing processes. For example, the passive device 230 can be an IPD comprising one or more passive devices in a main structure. The main structure can include a substrate and / or an encapsulating agent. In embodiments comprising a substrate, the substrate can be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of an SOI substrate. The semiconductor substrate can comprise another semiconductor material, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.The passive devices may comprise a capacitor, resistor, inductor, or the like, or a combination thereof. In some embodiments, the passive device 230 is a completely passive device (e.g., the substrate is free of active or doped regions, so that it has no active devices), such as an integrated voltage regulator (IVR). In some embodiments, the passive device 230 may be partially passive, e.g., it may include some active devices. The passive devices may be formed in and / or on the semiconductor substrate and / or within the encapsulation medium and may be interconnected by interconnection structures formed, for example, by metallization patterns in one or more dielectric layers on the main structure to form the passive device 230.

[0070] The passive device 230 further comprises device connectors 232, which are mechanically and electrically connected to the structures of the passive device 230. The device connectors 232 can be, for example, microbumps, UBMs, or the like, and can be made of a conductive material such as copper, aluminum, tungsten, nickel, or alloys thereof, which may be formed by plating or the like. A dielectric material can laterally encapsulate the device connectors 232.

[0071] The passive device 230 may further comprise device connectors 234, which are formed on a side opposite the passive device 230, similar to the device connectors 232. The device connectors 234 may be similar to the device connectors 232 and may be made of a similar material. The device connectors 234 are mechanically and electrically connected to the features of the passive device 230. The device connectors 234 may be formed, for example, by plating or the like. A dielectric material may laterally encapsulate the device connectors 234.

[0072] The passive device 230 may further comprise through-substrate vias (TSVs) 236. The TSVs 236 extend through the substrate of the passive device 230 and connect the device connectors 234 to the device connectors 232. It is understood that each of the device connectors 232 may not be connected to a specific connector 234. For example, some of the device connectors 232 (e.g., a first subset) may be connected to the passive components of the passive device 230, and others of the device connectors 232 (e.g., a second subset) may be connected to their respective device connectors 234 via the TSVs 236. Furthermore, some of the device connectors 232 may be connected to both the passive components of the passive device 230 and to a specific connector 234.

[0073] The TSVs 236 can be formed by applying and developing a suitable photoresist onto the substrate of the passive device 230 and then etching the substrate to form TSV openings. The TSV openings can be filled, for example, with a lining (not shown), a barrier layer (also not shown), and a conductive material. In one embodiment, the lining can be a dielectric material such as silicon nitride, silicon oxide, a dielectric polymer, combinations thereof, or the like, formed by a process such as chemical vapor deposition, oxidation, physical vapor deposition, atomic layer deposition, or the like. The barrier layer can be a conductive material such as titanium nitride, although alternatively other materials such as tantalum nitride, titanium, another dielectric, or the like can be used.The barrier layer can be formed using a CVD process such as PECVD. The barrier layer can be shaped to conform to the underlying shape of the TSV openings. The conductive material can be copper, although other suitable materials such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, and the like can be used. The conductive material can be formed by depositing a seed layer and then electroplating copper onto the seed layer, filling (and possibly overfilling) the TSV openings. Once the TSV openings are filled, excess barrier layer and excess conductive material outside the TSV openings can be removed by a planarization process such as CMP or grinding, although any suitable removal process can be used.

[0074] Conductive connectors 238 are formed at the ends of the fixture connectors 232 of the passive fixture 230. The conductive connectors 238 can be, for example, solder balls and form soldered connections between the fixture connectors 232 and the UBMs 228. Attaching the passive fixture 230 to the underlying structure includes forming the conductive connectors 238. Forming the conductive connectors 238 can include forming solder balls and melting the solder balls to create connections between the fixture connectors 232 and the UBMs 228.

[0075] An underfill 240 can be filled into the gap between the passive device 230 and the dielectric layer 226, and around the device connectors 232 and the conductive connectors 238. The underfill 240 can be a molding compound, an epoxy, a filler, a resin, or the like. The underfill 240 provides structural support for the passive device 230 and can be distributed by capillary action after the passive device 230 has been attached to the UBMs 228. Other processes can be used, such as lamination, compression molding, transfer molding, or the like. A curing step can then be performed to harden and solidify the underfill 240.

[0076] In some embodiments, the passive device 230 can be provided on a substrate (not shown separately). The substrate can be made of a semiconductor material or other suitable materials. After the passive device 230 has been placed in the opening 214, the substrate can optionally be subjected to a thinning process. This thinning process can include techniques such as back-side grinding, chemical-mechanical polishing (CMP), or wet setting to reduce (or possibly remove) the thickness of the substrate.

[0077] In Fig. 17. A dielectric material 242 is formed over the substrate core 202 and in the opening 214, for example, around the passive device 230 and the underfill 240. The dielectric material 242 can be formed from Ajinomoto build-up film (ABF), an epoxy, a molding compound, an epoxy molding compound, glass fiber-reinforced resin materials, silicon dioxide filler, polymer materials, polyimide materials, other build-up materials, other laminates, or the like, or combinations thereof. In some cases, the dielectric material 242 can be formed by lamination, whereby a pre-formed dielectric film is applied using heat and pressure. For example, ABF can be laminated onto the structure using a vacuum lamination process. In other cases, the dielectric material 242 can be applied by spin coating, such as when using liquid epoxy or polyimide materials.Molding compounds or epoxy molding compounds can be applied using compression molding or transfer molding techniques. In some embodiments, the dielectric material 242 can be deposited using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD), particularly for certain polymer materials. After application, the dielectric material 242 can be subjected to curing processes, which, depending on the specific material used, may include heat treatment, UV exposure, or a combination thereof.

[0078] After the formation of the dielectric material 242, it can optionally be subjected to a thinning process to expose the passive device 230. This thinning process can include techniques such as chemical-mechanical polishing (CMP), grinding, or etching. In some embodiments, a planarization process can be performed to remove excess material and produce a substantially planar surface. The thinning process can be controlled to expose the top surface of the passive device 230. In some cases, a combination of thinning methods can be employed, such as an initial grinding step followed by a CMP process for improved surface quality. After thinning, the exposed surface of the passive device 230 can be substantially coplanar (within process variations) with the surrounding dielectric material 242.

[0079] In Fig. 18. A support substrate debonding can be performed to separate (or “debond”) the support substrate 222 from the overlying structure. According to some embodiments, the debonding involves projecting light, such as UV light, onto the separating layer 224, so that the separating layer 224 decomposes under the heat of the light and the support substrate 222 can be removed.

[0080] Following substrate debonding, openings 244 can be formed through the dielectric material 242, and openings 246 can be formed through the dielectric layer 226 and the adhesive 212. The openings 244 and 246 can be formed using various techniques such as photolithography followed by etching, laser drilling, mechanical drilling, or the like. In some cases, a combination of methods can be used for different layers. The openings 244 and 246 expose the conductive traces 210, thus providing access to these underlying features. Furthermore, a cleaning process can be performed to remove any deposits or residues, such as those resulting from the formation of the opening.This cleaning step may include techniques such as plasma cleaning, wet chemical cleaning, or mechanical scrubbing to ensure that the openings are free of contaminants that could affect subsequent processing or device performance.

[0081] In Fig. 19 A first routing structure 250 is formed on one side of the substrate core 202. Furthermore, a second routing structure 252 is formed on the other side of the substrate core 202.

[0082] The first routing structure 250 can have multiple routing layers, which may include conductive traces, conductive vias, conductive pads, metallization patterns, or redistribution layers. The first routing structure 250 can have a variety of routing layers embedded within multiple insulating layers. The routing layers may have one or more layers of conductive materials such as copper, nickel, aluminum, or combinations thereof. The insulating layers may be made of materials such as build-up material, ABF, prepreg material, laminate material, oxides, nitrides, or polymers. In some cases, the outermost routing layer of the first routing structure 250 may include bonding pads to provide physical and electrical connections to other package components. These bonding pads may include conductive pads, conductive pillars, solder bumps, or under-bump metallizations (UBMs).

[0083] The second routing structure 252 can have multiple routing layers that include conductive traces, conductive vias, conductive pads, metallization patterns, or redistribution layers. The second routing structure 252 can have a variety of routing layers embedded within multiple insulating layers. The routing layers can have one or more layers of conductive materials such as copper, nickel, aluminum, or combinations thereof. The insulating layers can be made of materials such as build-up material, ABF, prepreg material, laminate material, oxides, nitrides, or polymers. In some cases, the outermost routing layer of the second routing structure 252 can have bonding pads to provide physical and electrical connections to other package components. These bonding pads can include conductive pads, conductive pillars, solder bumps, or under-bump metallizations (UBMs).

[0084] The first routing structure 250 and the second routing structure 252 can be coupled to the conductive lines 210 via vias formed in the openings 244 and 246, respectively. In this way, the conductive vias 208 in the substrate core 202 can electrically connect the first routing structure 250 to the second routing structure 252. Additionally, in some embodiments, the first routing structure 250 and the second routing structure 252 can be electrically coupled to the passive device 230. This configuration can enable efficient routing of electrical signals between different layers of the package and to various components, including the passive device 230.

[0085] The first routing structure 250 and the second routing structure 252 can be formed using similar processes. These processes can involve building alternating layers of dielectric material and conductive structures. Conductive structures, including traces, vias, and pads, can be formed within and between dielectric layers using techniques such as photolithography, etching, and plating. Each layer can be formed sequentially, with vias providing electrical connections between different metal layers. The process can be repeated multiple times to produce the desired number of routing layers.

[0086] A solder resist layer 254 can be formed on the outer surface of the first routing structure 250. The solder resist layer 254 can be applied as a liquid or dry film using techniques such as screen printing, spray coating, or lamination. After application, the solder resist layer 254 can be patterned using photolithography to create openings that expose underlying conductive pads or features where electrical connections are desired. The patterned solder resist layer 254 can then be subjected to curing processes, which, depending on the specific material used, may include heat treatment, UV exposure, or a combination thereof. This solder resist layer 254 helps to protect the underlying circuit from environmental factors and prevents solder bridges during subsequent assembly processes.

[0087] Subsequently, the component substrate 200 can be separated from adjacent component substrates. The separation process can involve sawing, laser cutting, or mechanical separation to divide a larger substrate into smaller, discrete component substrates. The resulting individual component substrate 200 can be contained within a substrate package, where it can be combined with other components to form a more complex assembly.

[0088] Once its individual processing is complete, testing can be performed on the component substrate 200. For example, probe testing can be performed on the component substrate 200 to determine if it is a known good substrate. This testing may involve the use of an automated tester with probe cards to establish temporary electrical connections to test pads or terminals on the component substrate 200. The testing may include electrical continuity tests, resistance measurements, capacitance measurements, and functional tests to verify the integrity of conductive paths, insulation between layers, and the proper operation of embedded passive components. In some cases, the testing may also include thermal cycling or stress tests to ensure reliability under various operating conditions.Therefore, only component substrates 200 that are known to be good substrates will be subjected to subsequent processing, and substrates that do not pass the probe test will not be packaged.

[0089] Other variations of the component substrates 200 are considered. In some embodiments, devices (including passive devices) can be omitted from a component substrate 200. Such a component substrate 200 may have a substrate core 202 without any devices mounted on it. This configuration can provide a simpler structure that can still function as part of an overall package arrangement. In some embodiments, a component substrate 200 may be a coreless substrate. A coreless substrate may refer to a substrate that does not have a solid substrate core, such as an FR-4 or BT resin core. Instead, it is built up from alternating dielectric and conductive layers. Coreless substrates can be formed by successively forming and structuring dielectric and conductive materials on a temporary support that is subsequently removed.This type of substrate can offer advantages such as reduced thickness and improved electrical performance in certain applications. The coreless design can enable finer-spaced connections and facilitate easier integration with other package components. Additionally, coreless substrates can provide better thermal management due to the absence of a thick core layer.

[0090] Fig. Figures 20-25 are cross-sectional views of intermediate stages in the production of a System Package 300 (see Fig. 24-25) according to some embodiments. Fig. Figures 20-24 are cross-sectional views, showing only one section (e.g. half) of the system package 300 for clarity of illustration. Fig. Figure 25 is a top view.

[0091] In Fig. In step 20, a support substrate 302 is provided and a separation layer 304 is formed on the support substrate 302. The support substrate 302 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 302 can be a wafer.

[0092] The release layer 304 can be made of a polymer-based material that, together with the support substrate 302, can be removed from the overlying structure formed in subsequent steps. In some embodiments, the release layer 304 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 304 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 304 can be dispersed and cured as a liquid, can be a laminate film laminated onto the support substrate 302, or the like. The upper surface of the release layer 304 can be leveled and exhibit a high degree of planarity.

[0093] A multitude of component substrates 200 are then applied to the separating layer 304. A desired type and number of component substrates 200 are placed adjacent to one another. In some embodiments, the component substrates 200 include one or more power distribution substrates and one or more connector substrates. The component substrates 200 can be placed on the separating layer 304, for example, using a pick-and-place tool. In some embodiments, the component substrates 200 are positioned such that their solder resist layers 254 face the carrier substrate 302.

[0094] Although not shown separately, it is understood that some or all of the component substrates are 200 passive devices (previously for Fig. 16) may have fixtures. Furthermore, a subset of the component substrates 200 (such as power distribution substrates) may have fixtures, while another subset of the component substrates 200 (such as connector substrates) may be free of fixtures.

[0095] In Fig. In embodiment 21, an encapsulating agent 306 is formed on and around the various components. After formation, the encapsulating agent 306 can encapsulate the component substrates 200. The encapsulating agent 306 can be a molding compound, epoxy, or the like, and can be applied by compression molding, transfer molding, or the like. The encapsulating agent 306 can be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulating agent 306 is formed over the support substrate 302, so that the component substrates 200 are buried or covered, and a planarization process can then be carried out on the encapsulating agent 306 to expose the component substrates 200. The planarization process can be, for example, chemical-mechanical polishing (CMP), grinding, or the like.The upper surfaces of the encapsulating agent 306 and the component substrates 200 can be essentially coplanar (within process variations) after the planarization process.

[0096] In Fig. 22 A redistribution structure 310 is formed above the encapsulating medium 306 and the component substrates 200. The redistribution structure 310 has dielectric layers 312 and metallization layer(s) 314 (sometimes referred to as redistribution layers or redistribution lines) beneath the dielectric layers 312. Thus, the redistribution structure 310 has metallization layer(s) 314 that are separated from each other by corresponding dielectric layers 312. The metallization layer(s) 314 of the redistribution structure 310 are connected to the conductive features of the upper routing structures of the component substrates 200.

[0097] In some embodiments, the dielectric layers 312 are formed from a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, and which can be patterned using a lithography mask. In other embodiments, the dielectric layers 312 are formed from a nitride such as silicon nitride, an oxide such as silicon oxide, or the like. The dielectric layers 312 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. Once a dielectric layer 312 is formed, it can be patterned to expose underlying conductive features of the component substrates 200 and / or the metallization layer(s) 314.The structuring can be carried out by any acceptable process, such as by exposing the dielectric layers 312 to light if they are formed from photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layers 312 are formed from a photosensitive material, they can be developed after exposure.

[0098] The metallization layer(s) 314 each have conductive vias and / or conductive traces. The conductive vias extend through the respective dielectric layers 312, and the conductive traces extend along the respective dielectric layers 312. As an example of forming a metallization layer 314, a seed layer (not shown separately) is formed over the respective underlying structures. For example, the seed layer can be formed on the respective dielectric layer 312 and in any openings through the respective dielectric layer 312. In some embodiments, the seed layer has a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using a deposition process such as PVD or the like. Then, a photoresist is formed and patterned on the seed layer.The photoresist can be formed by spin coating or similar processes and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 314. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating or electroplating, of the seed layer or similar processes. The conductive material can be a metal or metal alloy such as copper, titanium, tungsten, aluminum, or similar materials, or combinations thereof. The photoresist and portions of the seed layer where the conductive material is not formed are then removed.The photoresist can be removed by an acceptable ashing or removal process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, for example, by an acceptable etching process such as wet or dry etching. The remaining portions of the seed layer and the conductive material form a metallization layer 314 of the redistribution structure 310.

[0099] The redistribution structure 310 is shown as an example. More or fewer dielectric layers 312 and metallization layer(s) 314 than shown can be formed by repeating the steps described above any desired number of times.

[0100] Other variations of the redistribution structure 310 are considered. For example, some of the dielectric layers 312 can be formed from an encapsulating material such as a molding compound, epoxy, or the like. A metallization layer 314 can be formed by plating a conductive via with a conductive conductor. A dielectric layer 312 can be formed by encapsulating this metallization layer 314. Any desired stack of materials can be used for the dielectric layers 312.

[0101] Under-bump metallizations (UBMs) 316 can be formed through the upper dielectric layer 312 of the redistribution structure 310. The UBMs 316 are physically and electrically coupled to the upper metallization layer 314 of the redistribution structure 310. The UBMs 316 each have conductive vias and conductive bumps. The conductive vias extend through the upper dielectric layer 312, and the conductive bumps extend along the upper dielectric layer 312. The UBMs 316 can be formed from the same material(s) as the metallization layer(s) 314. In some embodiments, the UBMs 316 have a different size than the metallization layer(s) 314.

[0102] The structure formed over the support substrate 302 during this processing step is a substrate package 320. The substrate package 320 is a reconstituted wafer containing the multiple component substrates 200 in the encapsulation agent 306, with the redistribution structure 310 arranged on it.

[0103] In Fig. 23 A wafer package 100 is attached to the redistribution structure 310 of the substrate package 320. In this example, this is for Fig. The wafer package described in section 8 is attached. Alternatively, this can be used for Fig. The wafer package described in section 9, or another wafer package, may be attached to the redistribution structure 310.

[0104] In the illustrated embodiment, the wafer package 100 is attached to the substrate package 320 by solder joints, such as conductive connectors 322. The conductive connectors 322 can be made of a meltable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connectors 322 are formed by initially forming a layer of solder by processes such as evaporation, electroplating, printing, solder transfer, bead placement, or the like. Once a layer of solder has been formed, melting can be performed to shape the conductive connectors 322 into desired bump shapes.Attaching the wafer package 100 to the redistribution structure 310 can involve placing the wafer package 100 onto the redistribution structure 310 and melting the conductive connectors 322. For example, the wafer package 100 can be placed onto the redistribution structure 310 using a pick-and-place tool. The conductive connectors 322 are melted to attach the UBMs 164 of the wafer package 100 to the UBMs 316 of the redistribution structure 310, thereby electrically connecting the redistribution structure 310 to the wafer package 100. In another embodiment, the wafer package 100 is attached to the substrate package 320 via direct connections.

[0105] After the wafer package 100 is attached to the substrate package 320, a support substrate debonding process can be performed to separate (or "debond") the support substrate 302 from the substrate package 320. According to some embodiments, the debonding process involves projecting light, such as UV light, onto the release liner 304, causing the release liner 304 to degrade under the heat of the light and allowing the support substrate 302 to be removed. Removing the support substrate 302 can expose the lower surfaces of the component substrates 200 (of the substrate package 320) for subsequent attachment of additional components to the substrate package 320.

[0106] In Fig. Voltage regulators 324 and external connectors 326 are mounted on the side of the substrate package 320 opposite the wafer package 100. These components enable efficient power distribution and external connectivity to the resulting system package. Placing these components on the opposite side of the substrate package 320 from the wafer package 100 facilitates easier system maintenance or upgrades.

[0107] The voltage regulators 324 can be power management devices for maintaining stable voltage levels for the various components in the wafer package 100. These regulators can be implemented in various forms, such as integrated circuit dies, discrete components on circuit boards, multi-chip modules, or the like. In some embodiments, the voltage regulators 324 can be system-in-package (SiP) devices that incorporate multiple functions, including power regulation, current sensing, and thermal management. The voltage regulators 324 can also be implemented as switching regulators, linear regulators, or a combination of both, depending on the specific power requirements of the system.

[0108] The external connectors 326 can serve as interfaces for connecting system components (e.g., the wafer package 100) to external systems or components. These connectors can be implemented as ribbon cable receivers, flexible printed circuit receivers, or other types of high-density connections. In some embodiments, the external connectors 326 can support various communication protocols, such as PCI Express, USB, InfiniBand, custom high-speed interfaces, or the like. The design of these connectors allows for easy attachment and removal of external cables or modules, facilitating the integration of the resulting system package with an external system.

[0109] The component substrates 200 electrically connect the voltage regulators 324 to the integrated circuit devices in the wafer package 100. Similarly, the component substrates 200 electrically connect the external connectors 326 to the integrated circuit devices in the wafer package 100, enabling communication between the integrated circuit devices and external systems.

[0110] The voltage regulators 324 and external connectors 326 can be attached to the substrate package 320 using fusible connectors that connect the components to the lower routing structures of the component substrates 200. The fusible connectors can be made of a conductive material such as solder, copper, aluminum, gold, nickel, silver, tin, or combinations thereof. In some embodiments, the fusible connectors can be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, or the like. The fusible connectors can be formed by initially creating openings in the solder resist layers 254 of the component substrates 200. Next, a conductive material can be formed in the openings by processes such as evaporation, electroplating, printing, solder transfer, or bead placement.After the conductive material has been formed, a melting process can be carried out to shape the material into the desired connector structures.

[0111] Attaching the voltage regulators 324 and external connectors 326 to the substrate package 320 can involve placing the components on the substrate package 320 (e.g., the remeltable connectors extending through the solder resist layers 254) using a pick-and-place technique, followed by a melting process to create reliable electrical and mechanical connections with the lower routing structures of the component substrates 200. In some embodiments, a clamping device can be used to facilitate the attachment process. The clamping device can have adjustable sections that can be positioned to support the substrate package 320 and attached components during placement and melting. After the voltage regulators 324 and external connectors 326 are attached, the clamping device can be removed. The remaining structure is a system package 300, which can be a system of work (SoW).The SoW is a complete computing system comprising computing units (including the wafer package 100 devices and associated voltage regulators 324) and connection points (including the external connectors 326).

[0112] In some embodiments, the voltage regulators 324 and external connectors 326 can have a one-to-one correspondence with the component substrates 200, with each component substrate 200 being associated with a single voltage regulator 324 or external connector 326. In other embodiments, multiple voltage regulators 324 or external connectors 326 can be attached to a single component substrate 200, allowing for more flexible power distribution and connectivity options. For example, multiple voltage regulators 324 can be attached to a power distribution substrate, while multiple external connectors 326 can be attached to a connector substrate.

[0113] The component substrates 200 can include dedicated power distribution substrates for the voltage regulators 324 and separate, dedicated connector substrates for the external connectors 326. These different types of component substrates 200 can have different structures, functionalities, and integrated devices tailored to their specific roles. For example, power distribution substrates can include features optimized for efficient power delivery, while connector substrates can be designed with high-speed signal routing and impedance matching considerations. The power distribution substrates can have different structures compared to the connector substrates. In some aspects, the power distribution substrates can include devices, while the connector substrates can be device-free.

[0114] The substrate package 320 can contain any number of component substrates 200. For example, the substrate package 320 can have four component substrates 200 arranged in a 2x2 grid configuration. The number of component substrates 200 can be selected based on factors such as the desired functionality, performance requirements, and connectivity requirements of the system package 300. This modular approach can provide flexibility in system design and allow the substrate package 320 to be adapted to meet various application requirements.

[0115] While each component substrate 200 can be smaller than the wafer package 100, the substrate package 320 (including the multiple component substrates 200) is larger than the wafer package 100. The outer perimeter of the substrate package 320 extends beyond the outer perimeter of the wafer package 100. In other words, the width of the substrate package 320 can be greater than the width of the wafer package 100 in a cross-sectional view, while the width of each component substrate 200 can be less than the width of the wafer package 100 in a cross-sectional view. The larger size of the substrate package 320 relative to the wafer package 100 allows for additional routing features and external connections around the perimeter of the wafer package 100, including those that would overhang the edge of the wafer package 100 if attached directly to it.

[0116] The sections of the substrate package 320 that extend beyond the perimeter of the wafer package 100 can be used to mount the external connectors 326. These extended regions can provide dedicated areas for high-density connections, such as ribbon cable receivers, flexible printed circuit receivers, or other types of connectors that facilitate communication with external systems or components. Meanwhile, the internal sections of the substrate package 320 that overlap with the wafer package 100 can be used to mount the voltage regulators 324. This arrangement can enable efficient power distribution to the components within the wafer package 100, as the voltage regulators 324 can be positioned in close proximity to the devices they support.

[0117] With reference to Fig. The system package 300 is shown in more detail in section 25. While all the components discussed below are in Fig. Figure 25 is shown for clarity of illustration; it is understood that the wafer package 100 can be positioned below the substrate package 320 (e.g. going into the sheet) and the voltage regulators 324 and external connectors 326 can be positioned above the wafer package 100 (e.g. coming out of the sheet).

[0118] The voltage regulators 324 can be positioned directly above the wafer package 100, with each voltage regulator 324 corresponding to a computing device 70A (e.g., a logic die, a memory die, a combination thereof, etc.) of the wafer package 100. Each voltage regulator 324 can provide power to the wafer package 100 through the routing structures in the substrate package 320. Positioning the voltage regulators 324 close to the devices of the wafer package 100 can reduce power losses and / or voltage drops.

[0119] The external connectors 326 can be located around the perimeter of the substrate package 320, positioned along its edges. This placement can facilitate simpler connections to external components or systems, as the external connectors 326 are easily accessible at the outer boundaries of the system package 300.

[0120] The interface devices 70B are located at the edge of the wafer package 100, possibly in close proximity to the external connectors 326. In the top view, the interface devices 70B are positioned between the external connectors 326 and the array of voltage regulators 324 and computing devices 70A. The interface devices 70B may be positioned to reduce signal path lengths to the external connectors 326. The interface devices 70B can mediate communication between the external connectors 326 and the computing devices 70A, thereby performing signal routing and data transfer within the system package 300.

[0121] The layout of components within the system package 300 can be arranged, in plan view, with respect to the perimeter of the wafer package 100. The voltage regulators 324 can be positioned within the perimeter of the wafer package 100. Meanwhile, the external connectors 326 can be positioned outside the perimeter of the wafer package 100. Other variations are possible.

[0122] The substrate package 320 and the wafer package 100 can have different shapes when viewed from above. The wafer package 100 can be circular (truncated or untruncated), while the substrate package 320 can be square.

[0123] Furthermore, in the example of Fig. 25 The components of the system package 300 are arranged symmetrically. In another embodiment, an asymmetrical layout can be used. The layout of the system package 300 can be determined based on specific application requirements.

[0124] Fig. Figure 26 is a cross-sectional view of a system-on-wafer assembly 400 according to some embodiments. The system-on-wafer assembly 400 is formed by attaching the system package 300 of Fig. 24-25 between a thermal module 402 and a frame 404. Distortion of the system package 300 can be reduced by fastening the system package 300 between the thermal module 402 and the frame 404. In this embodiment, the width of the wafer package 100 is smaller than the width of the substrate package 320.

[0125] The thermal module 402 can be attached to the underside of the system package 300 on the same side as the wafer package 100. The thermal module 402 is in thermal contact with the wafer package 100. The thermal module 402 can be a heat sink, a heat distributor, a cold plate, or a similar device designed to manage heat dissipation from the components within the system-on-wafer assembly 400. In some embodiments, the thermal module 402 may have a recess to accommodate the wafer package 100. The recesses may allow the thermal module 402 to make closer contact with heat-generating components of the wafer package 100 while providing space for other protruding elements.

[0126] The frame 404 is attached to the top of the system package 300 and provides structural support and protection for the internal components, such as the voltage regulators 324 and external connectors 326. The frame 404 is a rigid support that may be made of a material with high stiffness, such as a metal, e.g., steel, titanium, cobalt, or the like. In some embodiments, the system-on-wafer assembly 400 may include a spacer (not shown separately) between the frame 404 and the substrate package 320. The frame 404 (or spacer, if present) physically engages sections of the substrate package 320. The frame 404 has recesses and / or openings that accommodate the voltage regulators 324 and external connectors 326 on this side of the substrate package 320. The frame 404 may also have openings for connectors (e.g., wires, cables, etc.).) from external systems to the external connectors 326.

[0127] Bolts 406 can be used to fasten the system package 300 between the thermal module 402 and the frame 404. The bolts 406 can extend into or through the thermal module 402 and / or the frame 404. In particular, the thermal module 402 and the frame 404 can have corresponding bolt holes, which may be threaded or unthreaded. During the assembly process, bolt holes can be drilled into the substrate package 320 and the wafer package 100 to accommodate the bolts 406. If the bolt holes are threaded, the bolts 406 can be screwed directly into the threaded holes. If the bolt holes are unthreaded, the bolts 406 can be secured with fasteners (not shown separately), such as nuts, washers, or the like. The bolts 406 fasten the components of the system-on-wafer assembly 400 together and provide structural integrity.The bolts 406 (or fasteners attached to them) can be tightened to a specific torque to apply a desired clamping force over the system-on-wafer assembly 400, which can reduce distortion of the assembly.

[0128] In some embodiments, a thermal interface material 408 can be applied between the thermal module 402 and the wafer package 100. The thermal interface material 408 improves the thermal conductivity between the wafer package 100 and the thermal module 402 and improves the overall heat dissipation in the system-on-wafer assembly 400. The thermal interface material 408 can be a film comprising materials such as indium or other thermally conductive substances.

[0129] In some embodiments, a cooling system 410 can be attached to the frame 404 of the system-on-wafer assembly 400. The cooling system 410 can be part of an external system designed to improve the thermal management of the assembly. This cooling system can take various forms, such as a liquid cooling system that circulates coolant through channels or tubes integrated into or attached to the frame 404. For example, the cooling system 410 can include a water cooling setup with a pump, a radiator, and a reservoir. Alternatively, the cooling system 410 can be an air cooling system with fans or blowers that force air through heat sinks or fins attached to the frame 404. The integration of the cooling system 410 can enable more efficient heat dissipation from the components within the system-on-wafer assembly 400, potentially allowing for higher performance or more compact designs.

[0130] Other structures and processes may also be provided. For example, test structures may be provided to assist in the verification testing of the 3D packaging or 3DIC devices. These test structures may, for example, include test pads formed in a redistribution layer or on a substrate, enabling the testing of the 3D packaging or 3DIC device, the use of probes and / or probe cards, and the like. The verification testing can be performed on both intermediate and final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that include intermediate verification of known good dies to increase yield and reduce costs.

[0131] Fig. Figures 27-28 show intermediate stages in the production of a substrate package according to some embodiments. This embodiment is similar to the embodiment of Fig. 20-25, except that the wafer package 100 is formed after (and above) the substrate package 320. Fig. Figures 27-28 are cross-sectional views, showing only one section (e.g. half) of the System Package 300 for clarity of illustration.

[0132] In Fig. 27 will describe the structure of Fig. 22 are trained or received, except that the UBMs 316 can be omitted. Instead, the wafer package 100 is trained on the redistribution structure 310. The wafer package 100 can, for example, be trained by a similar process to the one for Fig. The components described in Figures 3-8 can be formed, except that the back-side redistribution structure 110 can be built over the redistribution structure 310 instead of a separate support substrate. This can reduce warping caused by the formation of the back-side redistribution structure 110. Furthermore, UBMs can be omitted from the back-side redistribution structure 110; instead, the metallization layers 114 of the back-side redistribution structure 110 can be directly connected to the metallization layers 314 of the redistribution structure 310. This direct connection between redistribution structures can, in some cases, enable a more compact overall package structure.

[0133] In some embodiments, the wafer package 100 may include dummy dies 166 in addition to functional integrated circuit devices. These dummy dies 166 may be positioned within the wafer package 100 at desired locations, which may overlap with areas where the external connectors 326 are attached to the substrate package 320. The inclusion of the dummy dies 166 may serve various purposes, such as maintaining structural uniformity, improving thermal distribution, reducing warpage, or improving the overall mechanical stability of the wafer package 100. In cases where the dummy dies 166 overlap with the external connectors 326 and / or connector substrates, they may provide additional support or act as spacers, potentially facilitating more reliable connections between the wafer package 100 and the substrate package 320.

[0134] In Fig. 28. After the wafer package 100 has been formed, the support substrate 302 can be removed. A similar processing procedure as described previously can be performed to complete the system package 300.

[0135] In this embodiment, the wafer package 100 and the substrate package 320 can have essentially the same width. This configuration can enable efficient use of space within the system package 300. Both the voltage regulators 324 and the external connectors 326 can be arranged within the perimeter of the wafer package 100 in a top view. However, the external connectors 326 can still be positioned beyond the integrated circuit devices of the wafer package 100. The dummy dies 166 contained in the wafer package 100 overlap with the external connectors 326, potentially providing additional mechanical support or acting as spacers.

[0136] Fig. Figure 29 is a cross-sectional view of a system-on-wafer assembly 400 according to some embodiments. The system-on-wafer assembly 400 is mounted by attaching the system package 300. Fig. 28 between a thermal module 402 and a frame 404 similar to the embodiment of Fig. 26. In this embodiment, the width of the wafer package 100 is equal to the width of the substrate package 320.

[0137] Embodiments can achieve advantages. By implementing the substrate package 320 with component substrates 200, the peripheral regions of the substrate package 320 can be effectively used for attaching the external connector 326. This approach allows the wafer package 100 to accommodate a larger number of computing devices 70A and interface devices 70B, since the previously unused peripheral regions of the wafer package 100 become available for device placement. As a result, the overall system density and functionality can be increased without necessarily increasing the footprint of the wafer package 100. In addition, this configuration can lead to improved power output, improved signal integrity, and more efficient thermal management due to the strategic placement of voltage regulators 324 and external connectors 326 in close proximity to the computing devices 70A and 70B, respectively.Interface devices 70B lead.

[0138] One embodiment of a device comprises: a substrate package having a plurality of component substrates and a first encapsulating means located around and between the component substrates; a wafer package attached to a first side of the substrate package, wherein the wafer package has a plurality of integrated circuit devices and a second encapsulating means located around and between the integrated circuit devices; a plurality of voltage regulators attached to a second side of the substrate package, wherein the component substrates electrically connect the voltage regulators to the integrated circuit devices; and a plurality of external connectors attached to the second side of the substrate package, wherein the component substrates electrically connect the external connectors to the integrated circuit devices.In some embodiments of the device, the substrate package further comprises a first redistribution structure, the wafer package further comprises a second redistribution structure, and the first redistribution structure is attached to the second redistribution structure. In some embodiments of the device, the component substrates are arranged in a grid within the substrate package in a top view. In some embodiments of the device, the component substrates comprise power distribution substrates and connector substrates; the voltage regulators are attached to the power distribution substrates, and the external connectors are attached to the connector substrates. In some embodiments of the device, the voltage regulators are arranged within a perimeter of the wafer package in a top view, and the external connectors are arranged outside the perimeter of the wafer package in a top view.In some embodiments of the device, the voltage regulators are arranged within a circumference of the wafer package in a top view, and the external connectors are also arranged within the circumference of the wafer package in a top view. In some embodiments of the device, the external connectors are flat ribbon cable receivers. In some embodiments of the device, the wafer package is circular and the substrate package is square. In some embodiments of the device, it further comprises: a thermal module; a frame with openings that expose the external connectors, the substrate package and the wafer package being arranged between the frame and the thermal module; and a plurality of bolts extending through the thermal module and the frame.

[0139] One embodiment of a device comprises: a thermal module; a frame with openings; and a system package between the thermal module and the frame, wherein the system package comprises: a substrate package having a plurality of connector substrates, an encapsulating means located around and between the connector substrates, and a redistribution structure on the encapsulating means; a wafer package attached to the redistribution structure of the substrate package, wherein a width of the substrate package is greater than a width of the wafer package, the wafer package having integrated circuit devices; and a plurality of external connectors attached to the connector substrates of the substrate package, the connector substrates electrically connecting the external connectors to the integrated circuit devices, the openings of the frame exposing the external connectors.In some embodiments of the device, it further comprises a plurality of bolts extending through the thermal module and the frame. In some embodiments of the device, an upper surface of the encapsulating means is coplanar with the upper surfaces of the connector substrates, and the redistribution structure is located on the upper surface of the encapsulating means and the upper surfaces of the connector substrates. In some embodiments of the device, at least one of the connector substrates has a substrate core and a passive device within the substrate core. In some embodiments of the device, at least one of the connector substrates is a coreless substrate.

[0140] One embodiment of a method comprises: forming a substrate package by: encapsulating a connector substrate and a power distribution substrate with a molding compound; planarizing the molding compound until an upper surface of the molding compound is coplanar with an upper surface of the connector substrate and an upper surface of the power distribution substrate; and forming a redistribution structure on the molding compound, wherein the redistribution structure has redistribution lines that are electrically connected to the connector substrate and the power distribution substrate; attaching a wafer package to the redistribution structure of the substrate package; and attaching an external connector and a voltage regulator to a lower surface of the connector substrate and a lower surface of the power distribution substrate, respectively.In some embodiments of the method, the substrate package is formed on a support substrate, and the formation of the substrate package further comprises removing the support substrate to expose the lower surface of the connector substrate and the lower surface of the power distribution substrate. In some embodiments of the method, it further comprises forming the power distribution substrate by: forming an opening in a substrate core; and placing a passive device in the opening. In some embodiments of the method, the width of the connector substrate is smaller than the width of the wafer package, the width of the power distribution substrate is smaller than the width of the wafer package, and the width of the substrate package is larger than the width of the wafer package.In some embodiments of the method, it further comprises drilling bolt holes into the substrate package and the wafer package; and fastening the substrate package and the wafer package between a thermal module and a frame with bolts extending through the bolt holes. In some embodiments of the method, the voltage regulator is arranged in a top view within a circumference of the wafer package, and the external connector is arranged in a top view outside the circumference of the wafer package.

[0141] The foregoing outlines features of several embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. The person skilled in the art should recognize that he can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that he can make various changes, substitutions, and modifications therein without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 735,658

[0001]

Claims

[1] Device comprising: a substrate package comprising a variety of component substrates and a first encapsulating agent located around and between the component substrates; a wafer package attached to a first side of the substrate package, wherein the wafer package comprises a plurality of integrated circuit devices and a second encapsulation means located around and between the integrated circuit devices; a plurality of voltage regulators attached to a second side of the substrate package, wherein the component substrates electrically connect the voltage regulators to the integrated circuit devices; and a multitude of external connectors attached to the second side of the substrate package, wherein the component substrates electrically connect the external connectors to the integrated circuit devices. [2] Device according to claim 1, wherein the substrate package further comprises a first redistribution structure, the wafer package further comprises a second redistribution structure and the first redistribution structure is attached to the second redistribution structure. [3] Device according to claim 1 or 2, wherein the component substrates are arranged in a grid within the substrate package in a top view. [4] Device according to one of the preceding claims, wherein the component substrates comprise power distribution substrates and connector substrates, the voltage regulators are attached to the power distribution substrates, and the external connectors are attached to the connector substrates. [5] Device according to one of the preceding claims, wherein the voltage regulators are arranged in a top view within a circumference of the wafer package and the external connectors are arranged in a top view outside the circumference of the wafer package. [6] Device according to one of the preceding claims, wherein the voltage regulators are arranged in a top view within a circumference of the wafer package and the external connectors are arranged in a top view within the circumference of the wafer package. [7] Device according to one of the preceding claims, wherein the external connectors are flat ribbon cable receivers. [8] Device according to one of the preceding claims, wherein the wafer package is circular and the substrate package is square. [9] Device according to any one of the preceding claims, further comprising: a thermal module; a frame with openings that expose the external connectors, wherein the substrate package and the wafer package are arranged between the frame and the thermal module; and a multitude of bolts extending through the thermal module and the frame. [10] Device comprising: a thermal module; a frame that includes openings; and a system package between the thermal module and the frame, wherein the system package includes: a substrate package comprising a variety of connector substrates, an encapsulating agent located around and between the connector substrates, and a redistribution structure on the encapsulating agent; a wafer package attached to the redistribution structure of the substrate package, wherein a width of the substrate package is greater than a width of the wafer package, and wherein the wafer package comprises integrated circuit devices; and a plurality of external connectors attached to the connector substrates of the substrate package, the connector substrates electrically connecting the external connectors to the integrated circuit devices, the openings of the frame exposing the external connectors. [11] Device according to claim 10, further comprising: a multitude of bolts extending through the thermal module and the frame. [12] Device according to claim 10 or 11, wherein an upper surface of the encapsulating means is coplanar with upper surfaces of the connector substrates and the redistribution structure is on the upper surface of the encapsulating means and the upper surfaces of the connector substrates. [13] Device according to one of claims 10 to 12, wherein at least one of the connector substrates comprises a substrate core and a passive device in the substrate core. [14] Device according to any one of claims 10 to 13, wherein at least one of the connector substrates is a coreless substrate. [15] Procedure, encompassing: Forming a substrate package by: Encapsulation of a connector substrate and a power distribution substrate with a molding compound; Planarize the molding compound until an upper surface of the molding compound is coplanar with an upper surface of the connector substrate and an upper surface of the power distribution substrate; and Forming a redistribution structure on the molding compound, wherein the redistribution structure comprises redistribution lines that are electrically connected to the connector substrate and the power distribution substrate; Attaching a wafer package to the substrate package redistribution structure; and Attaching an external connector and a voltage regulator to a lower surface of the connector substrate or a lower surface of the power distribution substrate. [16] Method according to claim 15, wherein the substrate package is formed on a support substrate and the formation of the substrate package further comprises: Removing the support substrate to expose the lower surface of the connector substrate and the lower surface of the power distribution substrate. [17] Method according to claim 15 or 16, further comprising forming the power distribution substrate by: Forming an opening in a substrate core; and Placing a passive device in the opening. [18] Method according to any one of claims 15 to 17, wherein a width of the connector substrate is smaller than a width of the wafer package, a width of the power distribution substrate is smaller than the width of the wafer package and a width of the substrate package is larger than the width of the wafer package. [19] Method according to any one of claims 15 to 18, further comprising: Drilling bolt holes into the substrate package and the wafer package; and Securing the substrate package and the wafer package between a thermal module and a frame with bolts extending through the bolt holes. [20] Method according to any one of claims 15 to 19, wherein the voltage regulator is arranged in a top view within a circumference of the wafer package and the external connector is arranged in a top view outside the circumference of the wafer package.

Images