Method of forming a semiconductor package structure

Abstract

This invention provides a method for forming a semiconductor package structure, comprising: placing a chip with its active surface facing upwards; forming an alignment structure on a carrier; flipping the chip and placing it on the carrier while tilting the carrier, such that the active surface of the chip contacts the carrier and the sidewalls of the chip contacts the alignment structure. The purpose of this invention is to at least improve the precision of the semiconductor package structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically, to a method for forming a semiconductor package structure. Background Technology

[0002] In the design and manufacture of semiconductor integrated circuits, it is necessary to package several chips containing semiconductor devices (e.g., semiconductor chips) in a package structure with precise spatial relative positions. Chips are typically manufactured separately in advance. During packaging, it is necessary to first align the different chips within the package structure before encapsulation. This invention relates to a novel alignment method.

[0003] In existing alignment techniques, a carrier is typically used, and several chips are then transferred to a predetermined position on the carrier. This can lead to a discrepancy between the actual and predetermined positions of the chips. Summary of the Invention

[0004] In view of the problems existing in related technologies, the purpose of this invention is to provide a method for forming a semiconductor package structure, so as to at least improve the accuracy of the semiconductor package structure.

[0005] To achieve the above objectives, the present invention provides a method for forming a semiconductor package structure, comprising: setting the active surface of a chip facing upward; forming an alignment structure on a carrier; flipping the chip and placing it on the carrier and tilting the carrier such that the active surface of the chip contacts the carrier and the sidewalls of the chip contacts the alignment structure.

[0006] According to an embodiment of the present invention, the step of setting the active side of the chip facing upward includes: providing a tray with a limiting structure, placing the chip in the tray with the active side of the chip facing upward, wherein the alignment structure corresponds to the limiting structure.

[0007] According to an embodiment of the present invention, the step of flipping and placing the chip on the carrier includes: rotating the tray on which the chip is placed in a first direction at a first angle, wherein the first angle is an acute angle; placing the carrier with the alignment structure on top of the tray and aligning the alignment structure and the limiting structure facing each other; continuing to rotate the carrier in the first direction until the angle rotated is an obtuse angle, thereby transferring the chip from the tray to the carrier, and the active surface of the chip contacts the carrier and the sidewall of the chip contacts the alignment structure; and detaching the tray from the carrier.

[0008] According to an embodiment of the present invention, after the chip is transferred onto the carrier, the chip and the alignment structure located on the carrier are encapsulated using a molding material.

[0009] According to an embodiment of the present invention, after encapsulating the chip using a molding material, the carrier is separated from the chip, the alignment structure, and the molding material; a redistribution layer is formed that is attached to the active surface of the chip, and the vias in the redistribution layer are electrically connected to the active surface.

[0010] According to an embodiment of the present invention, the molding material is also located above the alignment structure.

[0011] According to an embodiment of the invention, the method further includes: performing a planarization process to partially remove the molding material to expose the alignment structure.

[0012] According to an embodiment of the present invention, the method further includes performing a planarization process to partially remove the molding material to expose the back side of the chip.

[0013] According to an embodiment of the present invention, the alignment structure has a bottom adjacent to the carrier and a top located on the bottom, the lateral dimension of the bottom being constant and the lateral dimension of the top gradually decreasing from bottom to top.

[0014] According to an embodiment of the present invention, the height of the bottom is greater than the height of the chip.

[0015] According to an embodiment of the present invention, in a top view, the alignment structure is constructed in a grid shape, and two adjacent sidewalls of the chip simultaneously contact the alignment structure.

[0016] Another aspect of the present invention provides a semiconductor packaging structure, comprising: a redistribution layer; a chip located on the redistribution layer, the active surface of the chip being directly connected to the redistribution layer; and an alignment structure surrounding the chip, the sidewalls of the chip being in contact with the alignment structure.

[0017] According to an embodiment of the present invention, there are no other connecting structures between the active surface and the redistribution layer.

[0018] According to an embodiment of the present invention, the vias in the redistribution layer directly contact the active surface.

[0019] According to an embodiment of the present invention, the alignment structure includes a bottom that contacts the redistribution layer and a top located on the bottom, wherein the lateral dimension of the bottom is constant and the lateral dimension of the top decreases as the distance from the redistribution layer increases.

[0020] According to an embodiment of the present invention, it further includes: a molding material, an encapsulating chip and an alignment structure in contact with the redistribution layer, the molding material being located on top of the layer.

[0021] According to an embodiment of the present invention, it further includes: a molding material, an encapsulating chip and an alignment structure in contact with the redistribution layer, wherein the top surface of the molding material is flush with the top surface of the top layer.

[0022] According to an embodiment of the present invention, the height of the bottom is greater than the height of the chip.

[0023] According to embodiments of the present invention, the molding material and the alignment structure are made of different materials.

[0024] According to an embodiment of the present invention, in a top view, the alignment structure is grid-like, and two adjacent sidewalls of the chip simultaneously contact the alignment structure.

[0025] According to an embodiment of the present invention, the other two sidewalls of the chip, which are disposed opposite to the two adjacent sidewalls, are separated from the alignment structure.

[0026] The beneficial technical effects of this invention are as follows:

[0027] This application provides a new alignment method for semiconductor packaging structures, which improves the accuracy of chip alignment in semiconductor packaging structures. Attached Figure Description

[0028] Figure 1 and Figure 2 A schematic diagram of semiconductor structure formation using existing technology is shown.

[0029] Figures 3 to 26C A schematic diagram of a semiconductor package structure formed according to an embodiment of this application is shown.

[0030] Figures 27 to 30B A schematic diagram of a semiconductor package structure according to other embodiments of this application is shown.

[0031] Figure 31 A schematic diagram showing the dimensions of a semiconductor package structure according to an embodiment of this application is provided. Detailed Implementation

[0032] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0033] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0034] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0035] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0036] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0037] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0038] like Figure 1 The top view shown and Figure 2The cross-sectional view shown illustrates that a conventional semiconductor cell (e.g., a chip) exhibits displacements Δx and Δy in the x and y directions relative to a substrate material 13, and has a void 15 between itself and the substrate material 13. In the prior art, Δx and Δy are typically greater than 2 μm, while the void is typically greater than 1 μm.

[0039] The aforementioned displacement issue will prevent the semiconductor cell 11 from being accurately positioned as expected, leading to a decrease in product yield. When the packaging structure involves high-precision and high-density input / output devices (e.g., fan-out structures), and / or when manufacturing large-area integrated circuits, the yield will not meet requirements, thus increasing manufacturing costs.

[0040] One method to solve the aforementioned displacement problem is to use a laser to detect the degree of displacement of the semiconductor cell 11 after alignment. Based on the detected actual position of the semiconductor cell, adjustments are made accordingly (e.g., shifting or rotating the semiconductor cell). However, this method will result in an increase in conductor area or breakage of bridging, forming an open circuit, making it unsuitable for the manufacture of large-area (e.g., wafers or flat panels) integrated circuits, and will also increase manufacturing costs and time.

[0041] The first embodiment of this application is by Figures 3 to 26C As shown. In Figure 3 In this process, a compound (CPD) powder layer 103 is sprayed onto a release layer 102 on a carrier 100 through a nozzle 280.

[0042] exist Figure 4 In this process, a mold 300 is provided. The lower surface 400 of the mold 300 has a concave-convex shape and includes the alignment structure 104 to be formed (see reference). Figure 5 The pattern is formed by extruding the CPD powder layer 103 through the mold 300 to form the alignment structure 104.

[0043] exist Figure 5 In the middle, the mold 300 is removed. The alignment structure 104 formed by the CPD powder layer 103, which is complementary to the lower surface 400 of the mold, remains on the carrier 100. Figures 3 to 5 The fabrication of a carrier 100 containing alignment structures 104 is illustrated. It is equally feasible to fabricate using other methods, not limited to those described in the embodiments.

[0044] Figures 6A to 6DA method for manufacturing tray 206 is illustrated. Tray 206 is based on a silicon wafer 200. First, a photoresist layer 201 is formed on the silicon wafer 200. Then, the photoresist layer 201 is patterned using a chemical etching process 1001 to form a limiting structure 208 and channels 600, 602. The limiting structure 208 corresponds to the alignment structure 104 on the carrier 100. A capping layer 202 is formed on the silicon wafer 200 with channels 600 and 602 to form tray 206. In this embodiment, the capping layer 202 has a smooth surface.

[0045] exist Figure 7 In this process, chip 210 is transferred from wafer A to channel 600 of tray 206. In an embodiment, a vacuum port 282 is used to select chip 210 on wafer A and move and place it into channel 600. After the transfer, the active side 402 of chip 210 faces upward. During the transfer process, testing may be included to determine if the moved chip 210 is qualified.

[0046] and Figure 7 Similarly, such as Figure 8 As shown, chip 212 is transferred from wafer B to another channel 602 of tray 206. The active side 403 of chip 212 also faces upward. Figure 7 and Figure 8 The process can be repeated several times, and during this process, it can also include testing whether the moved chip is qualified. Repeat Figure 7 and Figure 8 Subsequently, several identical or different chips can be disposed in several channels of the tray 206. For clarity, only two channels 600 and 602 and the corresponding chips 210 and 212 are shown in the attached drawings.

[0047] exist Figure 9A In this embodiment, the tilted tray 206 and the tray plane 406 on which the chips 210 and 212 are placed form an angle of inclination θ1 with the horizontal plane 404. In this embodiment, the angle of inclination θ1 is less than 90 degrees. At this time, since the direction of gravity G is no longer perpendicular to the tray plane 406 and the active surfaces 402 and 404 of the chips 210 and 212, the chips 210 and 212 placed on the tray 206 slide on the tray 206 due to their own gravity and the reaction force of the tray 206. Because the tray 206 has several channels, the chips 210 and 212 are placed in the channels 600 and 602, thus restricting the sliding of the chips 210 and 212 within the channels 600 and 602. During this process, ultrasonic waves 700 can be used to treat the tray 206 and the chips 210 and 212 thereon to promote the sliding of the chips 210 and 212.

[0048] Figure 9BThe diagram shows a view of tray 206 and chips 210 and 212 thereon from another angle. In this embodiment, the channels and chips are square. For chip 210, the two sidewalls 500 and 502 of the channel 600 it occupies are at approximately a 45-degree angle to the horizontal plane. The sliding force on chip 210 will then point towards one of the apex corners of the square, i.e., the angle between sidewalls 500 and 502. This results in the two sidewalls 504 and 506 of the chip being in close contact with the two sidewalls 500 and 502 of the channel 600 after the sliding is complete. Since the positions of the channels on tray 206 are accurate and pre-set, this step completes the alignment of chip 210 in the tray along its channel 600. For chip 212 and the other chips, the same principle applies when the tray is pressed... Figure 9A and Figure 9B When the chip is lifted, alignment will occur as shown in chip 210.

[0049] exist Figure 10 In the middle, the tray 206 remains partially raised, and at the same time, according to Figures 3-5 The manufactured carrier 100 and its alignment structure 104 are placed on the tray 206. The surface of the alignment structure 104 on the carrier 100 is opposite to the surfaces of the chips 210 and 212 on the tray 206. Furthermore, the carrier plane 408 is raised to be parallel to the tray plane 406, aligning the alignment structure 104 on the carrier 100 with several channels on the tray 206. Then, the carrier 100 and the tray 206 are overlapped. At this point, the channels on the tray 206 and the recessed portions of the alignment structure 104 on the carrier 100 form several cavities, confining the chips 210 and 212, which were originally on the tray 206, within these cavities.

[0050] Figures 6A to 10 The purpose is to transfer several chips onto a carrier, with the active side of the chips facing the carrier and in contact with it. It is equally feasible to use other methods to manufacture the chips, and this is not limited to the cases described in the embodiments.

[0051] exist Figure 11 In the process, the entire pallet and carrier 211, while remaining overlapped and aligned, is further lifted, causing planes 406 and 408 to rotate to a 90-degree angle with the horizontal plane 404. At this point, the pallet 206 and carrier 100 still retain their original positions. Figure 9B The state shown is such that the two sidewalls of the square channels are at approximately a 45-degree angle to the horizontal plane. Because the channels in the tray 206 are aligned and in contact with the alignment structure 104 on the carrier 100, the chips 210 and 212 will not fall out of the cavity.

[0052] exist Figure 12In the middle, the entire pallet and carrier 211 is further lifted, causing planes 406 and 408 to rotate to an angle greater than 90 degrees with the horizontal plane 404 (along... Figure 9A (The angle is continuously calculated from the direction in which the cylinder begins to lift). At this time, in the direction of gravity, since the carrier 100 containing the alignment structure 104 is below and the tray 206 is above, the chips 210 and 212 in the cavity will be supported by the carrier 100 and the alignment structure 104, but not by the tray 206. At this time, the tray 206 can be removed from above the carrier 100 and the alignment structure 104, leaving the chips 210 and 212 on the carrier 100 and the alignment structure 104, completing the transfer of chips 210 and 212 from the tray 206 to the carrier 100. When the chips 210 and 212 were originally on the tray 206, their active surfaces 402 and 403 faced the channels 600 and 602. After the transfer, the active surfaces 402 and 403 will face the carrier 100 and be in contact with the carrier 100. At this time, the tray 206 and the carrier 100 still retain the same position as before. Figure 9B The state shown is such that the two sidewalls of the square channels form approximately a 45-degree angle with the horizontal plane 404. Since chips 210 and 212 were already aligned on tray 206, and the channels on tray 206 are aligned with the alignment structure 104 on carrier 100, chips 210 and 212 remain aligned after transfer. Even if misalignment exists, the carrier 100 remains in the same position as shown in the diagram. Figure 9B The structure shown still allows chips 210 and 212 to be subjected to a sliding force pointing to one of the apex corners of the square in the alignment structure 104, thus enabling them to be further aligned.

[0053] exist Figure 13A The raised carrier 100 is placed with its plane 406 parallel to the horizontal plane 404 (i.e., tilted at an angle of 180 degrees, along...). Figure 9A (The angle is continuously calculated from the direction in which the chip begins to lift). At this point, although the sliding force no longer exists, chips 210 and 212 will not experience new displacement due to gravity, thus maintaining their original alignment. Then, molding material 220 is applied to the carrier 100, the alignment structure 104, and chips 210 and 212. In this embodiment, molding material 220 is composed of a compound material (CPD). The application of molding material 220 prevents any relative movement between chips 210 and 212 and the alignment structure 104, thus fixing the original alignment. Figure 13B Observing from another perspective Figure 13AThe carrier 100, alignment structure 104, and chips 210 and 212 are included. Maintaining the alignment state ensures that the sidewalls 504 and 506 of chip 210 are in contact with the two sidewalls 508 and 510 of alignment structure 104, respectively. In embodiments, different portions of alignment structure 104 may have different heights and different widths, or the same height but different widths, or the same height and width. Chips 210 and 212, etc., may have different heights and different widths, or the same height but different widths, or the same height and width.

[0054] exist Figure 14 This process allows the carrier 100 to separate from the alignment structure 104, chips 210 and 212, and molding material 220. The separation process involves detaching the carrier 100 from the substrate 100 via a release layer 102. At this point, the active surfaces 402 and 403 of chips 210 and 212 are exposed.

[0055] exist Figure 15 In this process, a first dielectric layer 222 is formed on the active surfaces 402 and 403 of the chip 210, as well as on the surfaces of the alignment structure 104 and the molding material 220 that are in contact with the active semiconductor surfaces 402 and 403, and an exposure process is performed to cure the first dielectric layer 222. In this embodiment, the first dielectric layer 222 is made of polyamide (PA) material. Then, a certain pattern is etched in the first dielectric layer 222. In this embodiment, the etching method is photolithography.

[0056] exist Figure 16 In this process, a channel 604 is etched into the first dielectric layer 222, extending to expose the active semiconductor surfaces 402 and 403 or the surfaces of the alignment structure 104 and the molding material 220 adjacent to them. A first seed layer 224 is formed above the first dielectric layer 222 and on the inner surface of the etched channel 604. In this embodiment, the first seed layer 224 is formed by physical vapor deposition.

[0057] exist Figure 17 In this process, a photoresist layer (PR) 226 is disposed above the first seed layer 224 and cured using an exposure process. Then, a specific pattern is etched onto the photoresist layer 226. In this embodiment, the etching method is photolithography.

[0058] exist Figure 18In the process, after the photoresist layer 226 is etched, a channel 606 is formed. A first seed layer 224 is exposed on the bottom surface of the channel 606. Then, a first metal layer 228 is formed on the inner surface of the channel 606 above the exposed first seed layer 224. At this time, the first seed layer 224 and the first metal layer 228 are formed on the inner surface of the channel 604 in the first dielectric layer 222, so that the portion of the first metal layer 228 located in the channel 604 can be used as a via for connecting the chip. The first seed layer 224 and the first metal layer 228 are also formed above the first dielectric layer 222, and these two conductive layers together constitute the redistribution layer above the via.

[0059] exist Figure 19 In the process, the remaining photoresist layer 226 is removed, and the first seed layer 224 below it is etched at the location of the remaining photoresist layer 226 until the first dielectric layer 222 is exposed. At this time, a channel 608 is formed in the first metal layer 228 and the first seed layer 224.

[0060] exist Figure 20 In this embodiment, a second dielectric layer 230 is disposed above the first metal layer 228 and within the channel 608 in the first metal layer 228 and the first seed layer 224, and the second dielectric layer 230 is cured by an exposure process 2001. In this embodiment, the second dielectric layer 230 is made of polyamide (PA) material. Then, a certain pattern is etched on the second dielectric layer 230. In this embodiment, the etching method is photolithography. The materials of the first dielectric layer 222 and the second dielectric layer 230, the alignment structure 104, and the molding material 220 can be one or more organic or inorganic materials: polyamide (PA), polyimide (PI), epoxy, polybenzoxazole (PBO), and FR4; Si, glass, ceramic, and oxides such as SiOx, SiN, TaOx, etc. The processing methods for the first dielectric layer 222 and the second dielectric layer 230, the alignment structure 104, and the molding material 220 can be one or more of the following: printing, lamination, potting, coating, and molding.

[0061] exist Figure 21 In this process, a channel 610 is etched in the second dielectric layer 230 until the first metal layer 228 is exposed within the channel 610. A second seed layer 232 is disposed above the second dielectric layer 230 and on the inner surface of the etched channel 610. In an embodiment, the second seed layer 232 is disposed by physical vapor deposition.

[0062] exist Figure 22In this process, a second photoresist layer 234 is disposed above the second seed layer 232, and the second photoresist layer 234 is cured using an exposure process 2201. A certain pattern is etched into the second photoresist layer 234. In this embodiment, the etching method is photolithography.

[0063] exist Figure 23 In the second photoresist layer 234, a channel 612 is etched. A second seed layer 232 is exposed on the bottom surface of the channel 612. A second metal layer 236 is formed along the exposed second seed layer 232 on the inner surface of the channel 612. At this time, the second seed layer 232 and the second metal layer 236 are formed on the inner surface of the channel 610 in the second dielectric layer 230, such that the portion of the second metal layer 236 located in the channel 610 can be used as a via connecting the redistribution layer. A second seed layer 232 and the second metal layer 236 are also formed above the second dielectric layer 230; these two conductive layers together constitute the redistribution layer above the via.

[0064] exist Figure 24 In the process, the remaining photoresist in the second photoresist layer 234 is removed, and etching continues at the location of the remaining photoresist in the second photoresist layer 234 until the second dielectric layer 230 is exposed, forming a redistribution layer 221.

[0065] exist Figure 25 At this point, the inner surface of the channel 610 in the second dielectric layer 230 has been covered by the second seed layer 232 and the second metal layer 236. Several ball- or bump-shaped solder connectors 238 are disposed above several portions of the channel 610 in the second dielectric layer 230, and above the second seed layer 232 and the second metal layer 236 on the inner surface of the channel 610. The semiconductor integrated circuit manufactured according to the above method is then individualized to form... Figure 26A The semiconductor packaging structure 2061 in the redistribution layer 221. The materials of the metal layer and seed layer in the redistribution layer 221, as well as the welding connector, can be one or more of the following: Cu, Ag, Au, Ni, and Pd, etc. The processing methods of the metal layer and seed layer in the redistribution layer 221, as well as the welding connector, can be one or more of the following: sputtering, plating, electroless plating, printing, lamination, and potting, etc.

[0066] In this embodiment, the redistribution layer may be located on both sides of the chip, as shown in the reference. Figure 27 As shown, it also includes a second redistribution layer 223.

[0067] Figures 15 to 25Vias and redistribution layers are fabricated on the active surface of the chip. Other methods can also be used for fabrication, and are not limited to those described in the embodiments.

[0068] Based on the above description, the present invention... Figures 11 to 12 The alignment scheme involves a carrier that is not fixedly connected to the active surface of the chip, and an alignment structure on the carrier. By tilting the carrier and the alignment structure, the chip slides on the carrier under the influence of gravity, aligning itself with the alignment structure.

[0069] Implementation Figures 11 to 12 The alignment scheme described herein requires several additional steps, including first fabricating the alignment structure on the carrier, fixing the aligned chip, and then further fabricating structures such as vias and redistribution layers on the fixed chip, and finally performing the monomerization of the semiconductor integrated circuit, as described in Example 1. These additional steps are intended to complement the alignment scheme proposed in this invention and to completely manufacture the semiconductor integrated circuit product. Additional steps to achieve the same purpose can also be used, and are not limited to the steps described in the examples.

[0070] In an embodiment, such as Figures 28A to 28B As shown, the alignment structure 104 can have trapezoidal, arc, planar and other irregular shapes in the cross-sectional view.

[0071] In this embodiment, the redistribution layer 221 may be as follows: Figure 29A The single shown, or as shown Figure 29B The multi-layered structure shown may further include wire connections 290 in the redistribution layer 221.

[0072] In an embodiment, such as Figure 30A The chip shown can be multi-layered, meaning it includes another chip 302. For example... Figure 30B As shown, bumps 304 and 306 are also included at the locations where chips 210 and 211 connect to the redistribution layer 221.

[0073] This invention provides a method for forming a semiconductor package structure, comprising: setting the active surfaces of chips facing upwards; forming an alignment structure 104 on a carrier 100; flipping and placing chips 210 and 212 on the carrier 100 and tilting the carrier 100 such that the active surfaces 402 and 403 of chips 210 and 212 contact the carrier 100, and the sidewalls of chips 210 and 212 contact the alignment structure 104. In an embodiment, the step of setting the active surfaces 402 and 403 of the chips facing upwards includes: providing a tray 206 with a limiting structure 208, placing chips 210 and 212 in the tray 206 with the active surfaces 402 and 403 of chips 210 and 212 facing upwards, wherein the alignment structure 104 corresponds to the limiting structure 208. In this embodiment, the step of flipping and placing chips 210 and 212 on the carrier 100 includes: rotating the tray 206 on which chips 210 and 212 are placed at a first angle θ1 along a first direction (e.g., clockwise), where the first angle θ1 is an acute angle; placing the carrier 100, which is provided with the alignment structure 104, on top of the tray 206, and aligning the alignment structure 104 and the limiting structure 208 facing each other; continuing to rotate the carrier 100 along the first direction (e.g., clockwise) until the angle θ3 rotated is an obtuse angle, thereby transferring chips 210 and 212 from the tray 206 to the carrier 100, and the active surfaces 402 and 403 of chips 210 and 212 contact the carrier 100, and the sidewalls of chips 210 and 212 contact the alignment structure 104; and detaching the tray 206 from the carrier 100. In this embodiment, after transferring chips 210 and 212 onto the carrier 100, the chips 210 and 212 and the alignment structure 104 located on the carrier 100 are encapsulated using molding material 220. In this embodiment, after encapsulating chips 210 and 212 using molding material 220, the carrier 100 is separated from chips 210 and 212, the alignment structure 104, and the molding material 220; a redistribution layer 221 is formed that adheres to the active surfaces 402 and 403 of chips 210 and 212, and the vias (parts of the first metal layer 228) in the redistribution layer 221 are electrically connected to the active surfaces 402 and 403. In this embodiment, as... Figure 26A As shown, the molding material 220 of the semiconductor package structure 2601 is also located above the alignment structure 104. In an embodiment, as... Figure 26B As shown, it also includes: performing a planarization process to partially remove the molding material 220 to expose the alignment structure 104, forming a semiconductor package structure 2602. In an embodiment, as... Figure 26C As shown, it also includes: performing a planarization process to partially remove the molding material 220 to expose the back side of the chip 210, forming a semiconductor package structure 2603. In an embodiment, as... Figure 31As shown, the alignment structure 104 has a bottom 1041 adjacent to the carrier 100 and a top 1042 located on the bottom 1041. The lateral dimension Fw2 of the bottom is constant, and the lateral dimension Fw1 of the top 1042 gradually decreases from bottom to top. This makes the upper dimension TO of the gap between the alignment structures 104 greater than the lower dimension BO. The lower dimension BO is less than twice the width Cs of the chip 212, meaning the distance between the chip 212 and its opposite alignment structure 104 is less than the width Cs of the chip 212 itself. In this embodiment, the height Ft2 of the bottom 1041 is greater than the height Ct of the chips 210 and 212. In this embodiment, in the top view, as shown... Figure 13B As shown, the alignment structure 104 is constructed in a grid shape, and the two adjacent sidewalls 504 and 506 of the chip 210 simultaneously contact the alignment structure 104.

[0074] Another aspect of the present invention provides a semiconductor packaging structure 2601, such as... Figure 26A As shown, it includes: a redistribution layer 221; chips 210 and 212 located on the redistribution layer 221, with active surfaces 402 and 403 of chips 210 and 212 directly connected to the redistribution layer 221; and an alignment structure 104 surrounding chips 210 and 212, with the sidewalls of chips 210 and 212 contacting the alignment structure 104. In this embodiment, there are no other connecting structures between the active surfaces 402 and 403 and the redistribution layer 221. In this embodiment, vias (parts of the first metal layer 228) in the redistribution layer 221 directly contact the active surfaces 402 and 403. In this embodiment, as... Figure 31 As shown, the alignment structure 104 includes a bottom 1041 in contact with the redistribution layer 221 and a top 1042 located on the bottom 1041. The lateral dimension Fw2 of the bottom 1041 is constant, and the lateral dimension Fw1 of the top 1042 decreases as the distance from the redistribution layer 221 increases. The lateral dimension Fw1 of the top 1042 is Fw2 – 2×Ft1×Tanθ, where θ is the tilt angle of the sidewall of the top 1042. The special shape of the alignment structure 104 makes the transfer of chips 210 and 212 smoother. For example, if the chips 210 and 212 are right-angled, they may be reversed 180° during transfer. In the embodiment, it also includes a molding material 220, which encapsulates the chips 210 and 212 and the alignment structure 104 and contacts the redistribution layer 221. In the embodiment, as shown... Figure 26A and Figure 31 As shown, the molding material 220 is located above the top 1042, and the height Mt of the molding material 220 is greater than the height Ft of the alignment structure 104. In the embodiment, as... Figure 26B As shown, the top surface of the molding material 220 is flush with the top surface of the top 1042. In an embodiment, as... Figure 26CAs shown, the top surface of the molding material 220 is flush with the top surface of the chip 210. In an embodiment, the height of the bottom 1041 is greater than the height of the adjacent chips 210 / 212. In an embodiment, the molding material 220 and the alignment structure 104 are made of different materials. In an embodiment, in a top view, as shown... Figure 13B As shown, the alignment structure 104 is grid-shaped, and two adjacent sidewalls 504 and 506 of the chip 210 simultaneously contact the alignment structure 104. In this embodiment, the other two sidewalls of the chip 210, which are opposite to the two adjacent sidewalls 504 and 506, are separated from the alignment structure 104.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor package structure, characterized in that, include: A tray with a limiting structure is provided, the limiting structure defining a channel, a cover layer being formed on the channel, and the cover layer having a smooth surface, wherein a chip is placed on the smooth surface of the cover layer with the active side of the chip facing upward; An alignment structure is formed on the carrier, the alignment structure corresponding to the limiting structure; The chip is flipped and placed on the carrier, and the carrier is tilted such that the active surface of the chip contacts the carrier and a pair of adjacent sidewalls of the chip contacts a pair of adjacent sidewalls of the alignment structure. The step of flipping the chip onto the carrier includes: rotating the tray on which the chip is placed at a first angle of an acute angle along a first direction, such that the chip slides on the smooth surface of the cover layer and is restricted by the limiting structure, thereby engaging the corners defined by the pair of adjacent sidewalls of the chip in the included angle defined by the pair of adjacent sidewalls of the limiting structure; and placing the carrier with the alignment structure on top of the tray, and aligning the alignment structure and the limiting structure facing each other. Continue rotating the carrier along the first direction until the angle rotated is obtuse, thereby transferring the chip from the tray to the carrier, and the active surface of the chip directly contacts the carrier, and the corners defined by the pair of adjacent sidewalls of the chip engage in the included angle defined by the pair of adjacent sidewalls of the alignment structure; detach the tray from the carrier.

2. The method for forming a semiconductor package structure according to claim 1, characterized in that, After the chip is transferred onto the carrier, the chip and the alignment structure located on the carrier are encapsulated using molding material.

3. The method for forming a semiconductor package structure according to claim 2, characterized in that, After encapsulating the chip using the molding material, the carrier is separated from the chip, the alignment structure, and the molding material; A redistribution layer is formed on the active surface of the chip, and vias in the redistribution layer are electrically connected to the active surface.

4. The method for forming a semiconductor package structure according to claim 2, characterized in that, The molding material is also located above the alignment structure.

5. The method for forming a semiconductor package structure according to claim 4, characterized in that, Also includes: A planarization process is performed to partially remove the molding material, thereby exposing the alignment structure.

6. The method for forming a semiconductor package structure according to claim 4, characterized in that, Also includes: A planarization process is performed to partially remove the molding material, thereby exposing the back side of the chip.

7. The method for forming a semiconductor package structure according to claim 1, characterized in that, The alignment structure has a bottom adjacent to the carrier and a top located on the bottom, the lateral dimension of the bottom being constant and the lateral dimension of the top gradually decreasing from bottom to top.

8. The method for forming a semiconductor package structure according to claim 7, characterized in that, The height of the bottom is greater than the height of the chip.

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