ATS endpoint optimization for storage workloads

Abstract

Instead of simply deploying an Address Translation Cache (ATC) with a global approach that ignores client requests, or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance and limits the performance of individual clients when necessary. With the dynamic approach, it is determined periodically or strategically whether the currently used ATC allocation is delivering the desired performance. Dynamic ATC reallocation maximizes ATC efficiency and benefit by achieving maximum performance results for the application and / or workload.

Description

BACKGROUND OF REVELATION Area of ​​Revelation

[0001] Embodiments of the present disclosure generally relate to an improved address translation. Description of the state of the art

[0002] One use case for a multi-tenancy device is when the solid-state drive (SSD) is shared by multiple tenants (i.e., virtual machines (VMs)) without a hypervisor layer between the SSD and the VM. A variety of storage utilization optimizations are possible when the host operating system (host OS) (e.g., Windows Server) implements page-shifting capabilities. These capabilities require the Address Translation Service (ATS) and Page Request Interface (PRI) functionality in each Peripheral Component Interconnect Express (PCIe) device that guest VMs directly access. Moving storage pages implies that the device receives PCIe addresses that must be translated.

[0003] When using ATS + PRI, translated addresses can be stored in an address translation cache (ATC). The ATC function is very expensive because it requires a huge amount of memory (on the order of several megabytes (MB)) to be used as the cache buffer and powerful lookup operations. ATC significantly increases the device's footprint, cost, and power consumption.

[0004] One approach to effectively utilizing ATC is a global ATC, where all clients are served globally without regard to client identification (ID). Another approach uses static ATC attributes, allocating the same amount of cached memory to each client. Both approaches face the challenge of achieving optimal performance.

[0005] In the field of technology, there is a need for improved address translation. SUMMARY OF THE REVELATION

[0006] Instead of simply deploying an Address Translation Cache (ATC) with a global approach that ignores client requests, or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance and limits the performance of individual clients when necessary. With the dynamic approach, it is determined periodically or strategically whether the currently used ATC allocation is delivering the desired performance. Dynamic ATC reallocation maximizes ATC efficiency and benefit by achieving maximum performance results for the application and / or workload.

[0007] In one embodiment, a data storage device comprises: a storage device; and a controller coupled to the storage device, the controller being configured to: select a configuration for address translation cache (ATC) attributes for operating the data storage device; operate the data storage device using the configuration; measure the performance of the data storage device using the configuration; switch from one configuration to another for the ATC attributes based on measurement and repeat the operation, measurement, and switching process.

[0008] In another embodiment, a data storage device comprises: a storage device; and a controller coupled to the storage device, the controller comprising a host interface module (HIM) comprising: a calibration logic module configured to adjust cache configurations, measure the performance of the data storage device, and intelligently select optimal cache configurations; a performance monitoring module configured to monitor the performance of the data storage device; and an address translation cache configuration module (ATC configuration module) configured to retain one or more cache configuration(s) to be used for adjustment by the calibration logic module.

[0009] In another embodiment, a data storage device comprises: storage means and a controller coupled to the storage means, wherein the controller is configured to: measure the performance of the data storage device; modify the address translation cache attributes (ATC attributes) based on the measurement; operate the data storage device using the modified ATC attributes; store the ATC attributes; repeat the measuring, modifying, operating, and storing one or more times; select optimal ATC attributes and operate the data storage device using the selected optimal ATC attributes. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to understand in detail the nature of the aforementioned features of the present disclosure, a more precise description of the disclosure, which has been briefly summarized above, can be given with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate typical embodiments of this disclosure and are therefore not to be considered as limiting in its scope of protection, since the disclosure also permits other, equally effective embodiments. Fig. Figure 1 is a schematic block diagram illustrating a storage system in which a data storage device can function as a storage device for a host device according to certain embodiments. Fig. Figure 2 is a schematic diagram illustrating a multi-tenancy system supporting ATS functionality according to certain embodiments. Fig. Figure 3 is a schematic illustration of an ATC attribute calibration according to one embodiment. Fig. Figure 4 is a flowchart illustrating an ATC attribute calibration according to one embodiment. Fig. Figure 5 is a schematic illustration of a system block diagram according to one embodiment. Fig. Figure 6 is a flowchart illustrating a dynamic ATC assignment according to one embodiment.

[0011] To facilitate understanding, identical reference numerals have been used wherever possible to denote identical elements present in all figures. It is intended that elements disclosed in one embodiment may also be used effectively in other embodiments without specific mention. DETAILED DESCRIPTION

[0012] The following refers to embodiments of the disclosure. However, it is understood that the disclosure is not limited to specifically described embodiments. Instead, any combination of the following features and elements, regardless of whether they relate to different embodiments or not, is intended for the implementation and practical application of the disclosure. Furthermore, although embodiments of the disclosure may offer advantages over other possible solutions and / or over the prior art, the fact that a particular embodiment achieves a specific advantage or not does not constitute a limitation of the disclosure.Therefore, the following aspects, features, embodiments, and advantages serve only for illustration and are not considered elements or limitations of the accompanying claims unless expressly stated in one or more claims. Likewise, a reference to "the disclosure" is not to be construed as a generalization of any inventive subject matter disclosed herein and is not to be considered an element or limitation of the accompanying claims unless expressly stated in one or more claims.

[0013] Instead of simply deploying an Address Translation Cache (ATC) with a global approach that ignores client requests, or a static ATC that ignores performance changes, ATC allocation can be dynamically adjusted. Dynamic allocation optimizes overall system performance and limits the performance of individual clients when necessary. With the dynamic approach, it is determined periodically or strategically whether the currently used ATC allocation is delivering the desired performance. Dynamic ATC reallocation maximizes ATC efficiency and benefit by achieving maximum performance results for the application and / or workload.

[0014] Fig. Figure 1 is a schematic block diagram illustrating a storage system 100 comprising a data storage device 106, which, according to certain embodiments, can function as a storage device for a host device 104. For example, the host device 104 can use non-volatile memory (NVM) 110 enclosed in the data storage device 106 for storing and retrieving data. The host device 104 includes dynamic random-access memory (DRAM) 138. In some examples, the storage system 100 can include a variety of storage devices, such as the data storage device 106, which can function as a storage array.For example, the storage system 100 can include a variety of data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) and acting collectively as a mass storage device for the host device 104.

[0015] The host device 104 can store data on and / or retrieve data from one or more storage devices, such as the data storage device 106. As described in Fig. As illustrated in Figure 1, the host device 104 can communicate with the data storage device 106 via an interface 114. The host device 104 can include a wide range of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebooks (i.e., laptops), tablet computers, set-top boxes, mobile phones such as smartphones or smart tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices that can send data to or receive data from a data storage device.

[0016] The host DRAM 138 can optionally include a host memory buffer (HMB) 150. The HMB 150 is a section of the host DRAM 138 allocated to the data storage device 106 for the exclusive use of a controller 108 of the data storage device 106. For example, the controller 108 can store mapping data, buffered instructions, logic-physical (L2P) tables, metadata, and the like in the HMB 150. In other words, the HMB 150 can be used by the controller 108 to store data that would normally be stored in volatile memory 112, a buffer 116, internal memory of the controller 108 such as static random-access memory (SRAM), and the like. In examples where the data storage device 106 does not include DRAM (i.e., optional DRAM 118), the controller 108 can use the HMB 150 as the DRAM of the data storage device 106.

[0017] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components, which for clarity are shown in Fig. Figure 1 is not shown. For example, the data storage device 106 may include a printed circuit board (PCB) to which components of the data storage device 106 are mechanically attached and which includes electrically conductive traces that electrically connect components of the data storage device 106 or the like. In some examples, the physical dimensions and connection configurations of the data storage device 106 may conform to one or more standard form factors. Some examples of standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., an HDD or SSD), 2.5-inch data storage devices, 1.8-inch data storage devices, Peripheral Component Interconnect (PCI), PCI-Extended (PCI-X), and PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.).In some examples, the data storage device 106 can be directly coupled to a mainboard of the host device 104 (e.g., directly soldered or plugged into a connector).

[0018] Interface 114 can include a data bus for data exchange with the host device 104 and / or a control bus for exchanging commands with the host device 104. Interface 114 can operate according to any suitable protocol. For example, interface 114 can operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serially Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface 114 (e.g.,The data bus, the control bus, or both) is electrically connected to the controller 108 and provides an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 can also allow the data storage device 106 to receive power from the host device 104. For example, in... Fig. As illustrated in Figure 1, the power supply 111 can receive power from the host device 104 via the interface 114.

[0019] The NVM 110 can include a variety of storage devices or storage units. The NVM 110 can be configured to store and / or retrieve data. For example, a storage unit of the NVM 110 can receive data and a message from the controller 108 instructing the storage unit to store the data. Likewise, the storage unit can receive a message from the controller 108 instructing the storage unit to retrieve data. In some examples, each of the storage units can be referred to as a chip. In some examples, the NVM 110 can include a variety of chips (i.e., a variety of storage units). In some examples, each storage unit can be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0020] In some examples, each storage unit can include any type of non-volatile storage device, such as flash memory devices, phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), holographic storage devices, and any other type of non-volatile storage device.

[0021] The NVM 110 can incorporate a variety of flash memory devices or storage units. NVM flash memory devices can include NAND- or NOR-based flash memory devices and can store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device can be subdivided into a variety of dies, with each die containing a variety of physical or logical blocks, which can be further subdivided into a variety of pages. Each block within a given memory device can contain a variety of NVM cells. Rows of NVM cells can be electrically connected using a word line to define a page within a variety of pages.The individual cells in each of the multitude of pages can be electrically connected to the respective bit lines. Furthermore, NVM flash storage devices can be 2D or 3D devices and can be of the single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) type. The controller 108 can write and read data to and from NVM flash storage devices at the page level and erase data from NVM flash storage devices at the block level.

[0022] The power supply 111 can power one or more components of the data storage device 106. In standard mode, the power supply 111 can power one or more components by drawing power from an external device, such as the host device 104. For example, the power supply 111 can power the one or more components by using power received from the host device 104 via interface 114. In some examples, the power supply 111 can include one or more power storage components configured to power the one or more components when they are in shutdown mode, such as when no power is being received from the external device. In this way, the power supply 111 can function as an integrated backup power source.Examples of one or more energy storage components include capacitors, supercapacitors, batteries, and the like. In some cases, the amount of electricity that can be stored by one or more energy storage components may depend on the cost and / or size (e.g., area / volume) of the one or more energy storage components. In other words, as the amount of electricity stored by one or more energy storage components increases, so do the cost and / or size of the one or more energy storage components.

[0023] The volatile memory 112 can be used by the controller 108 to store information. The volatile memory 112 can include one or more volatile storage devices. In some examples, the controller 108 can use the volatile memory 112 as a cache. For example, the controller 108 can store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As in Fig. As illustrated in Figure 1, the volatile memory 112 can consume power received from the power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)). Likewise, the optional DRAM 118 can be used to store mapping data, buffered instructions, logic-physical (L2P) tables, metadata, cached data, and the like. In some examples, the data storage device 106 does not include the optional DRAM 118, so the data storage device 106 has no DRAM. In other examples, the data storage device 106 includes the optional DRAM 118.

[0024] The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data in the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating property of the storage system 100 and store at least one operating property in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in internal memory or write buffer 116 before sending the data to the NVM 110.The controller 108 can include switching logic or processors configured to run programs to operate the data storage device 106.

[0025] The controller 108 can include an optional second volatile memory 120. The optional second volatile memory 120 can be similar to the volatile memory 112. For example, the optional second volatile memory 120 can be SRAM. The controller 108 can allocate a portion of the optional second volatile memory to the host device 104 as a control memory buffer (CMB) 122. The CMB 122 can be accessed directly by the host device 104. For example, instead of managing one or more transmission queues in the host device 104, the host device 104 can use the CMB 122 to store the one or more transmission queues that are normally managed in the host device 104.In other words, the host device 104 can generate commands and store the generated commands with or without the associated data in the CMB 122, with the controller 108 accessing the CMB 122 to retrieve the stored generated commands and / or the associated data.

[0026] ATC is a feature in PCIe where the data storage device receives untranslated addresses from a host device, and these addresses must be translated by a translation agent (TA) before use. The TA maintains a table of translated addresses and their corresponding untranslated addresses. For example, the host device sends a command to the endpoint (i.e., the data storage device), and the command contains an untranslated address. Before the address can be used, the endpoint must first retrieve the translated address. The endpoint interacts with the TA to obtain the translated address. After receiving the translated address from the TA, the endpoint can use the translated address and store it in the ATC.

[0027] To improve performance and reduce connection overhead, the data storage device negotiates with the Transaction Access (TA) to obtain the translated address. Before negotiating with the TA, the endpoint first checks if the translated address exists in the Address Transfer Center (ATC). If the translated address is in the ATC, the endpoint uses the translated address stored there. Otherwise, the endpoint begins interacting with the TA.

[0028] In a multi-host or multi-tenancy setup, such as when the system contains multiple functions, multiple physical functions, multiple virtual functions, or multiple hosts, the system uses only a single ATC for all hosts or functions, so that all hosts or functions have access to the same ATC. This disclosure includes the method of optimizing the system from a quality of service (QoS) perspective. In other words, the disclosure includes how to improve performance in managing the ATC.

[0029] As stated above, with a global ATC, all functions can use the ATC without any specific policy. For example, data might be removed from the ATC based on the longest unused data (LRU) or other criteria. However, no space is reserved for a specific function within a global ATC. The other approach mentioned above is the static ATC attribute, where the ATC is allocated to functions / hosts at the outset, such as when one function requires higher QoS compared to others. For the function requiring higher QoS, half of the ATC might be allocated to that function, and the remainder to the other functions, allowing that function to provide better performance compared to the others. With the static ATC attribute, the ATC distribution remains unchanged. The focus of the disclosure is on the dynamic allocation of the ATC to improve performance.

[0030] Fig. Figure 2 is a schematic diagram illustrating a Multi-Tenancy System 200 supporting ATS functionality, according to certain embodiments. A TA handles memory translation requests. The ATC within the TA is referred to as the Translation Look-Aside Buffer (TLB). When the ATS-enabled SSD accesses system memory, the SSD must cache translated addresses in an internal ATC. This ATC is distinct from the TLB translation cache used by the host. The ATS-enabled SSD must implement and manage a specific ATC to minimize performance dependencies on the TA and reduce pressure on TA resources.

[0031] Examples of PCIe addresses to be translated include: caching of transmit queue (SQ) and completion queue (CQ) address ranges; SQ entry decoding, including standard data pointer decoding for read or write operations that immediately transmit translation requests; PRPs and SGLs that decode data pointers and follow linked lists; and the upper limit of translations per large instruction is equal to a rate that matches PRI translations with Gen5 bandwidth maxima (Gen5 BW maxima); and DIX translation requests for metadata pointers and associated linked address lists.

[0032] The ATC serves as a global resource shared by multiple clients and encompasses PCIe functions and applications. The performance and QoS of the storage device depend on the chosen attributes of the shared resource. Employing an algorithm that can identify the optimal ATC attributes for the best performance is therefore highly advantageous.

[0033] As discussed herein, a facility is designed to calibrate the ATC attributes in detail, with the goal of optimizing overall system performance while limiting the performance of each individual client as needed. The dynamic calibration process can be run at regular intervals or triggered otherwise to ensure that the current ATC attributes seamlessly match the current set of workloads, configurations, system conditions, and operational constraints.

[0034] The algorithm not only considers the immediate environment but also analyzes historical data to gain a comprehensive understanding of the system's performance trends over time. In this way, the algorithm effectively adapts to varying conditions, ensuring the continuous optimization of ATC attributes.

[0035] The core of the setup lies in the algorithm's ability to determine and recommend the optimal ATC size and removal policy for each PCIe function or application. This approach ensures that the individual characteristics and requirements of each client are taken into account, contributing to maximizing overall system performance. The main benefit is maximizing the utility and efficiency of the ATC by selecting optimal cache attributes, thereby achieving maximum performance for the current application or workload.

[0036] As discussed herein, the ATC can be used dynamically by finding the right attributes for each individual host or function from the ATC's perspective to maximize performance and QoS. The dynamic calibration approach involves experimenting with the ATC's configuration to obtain the optimal configuration, regardless of whether the ATC starts with a global configuration, static ATC attributes, or something else. For example, consideration can be given to the size of the ATC for each individual host or function and the removal policy for each. For instance, one host might have one removal policy, while another host might have a different removal policy.Optimization involves experimenting with configurations to find the best configuration for the specific system, where "best" means achieving the best performance and QoS results.

[0037] Fig. Figure 3 is a schematic illustration of an ATC attribute calibration according to one embodiment. Fig. There are several phases that repeat themselves.

[0038] First, the system, specifically the ATC, is configured based on the distance policy for each individual host, and the size to be allocated to each host is determined. This is followed by operation using the configuration, measurement of the results, and, after some time, adjustment of the configuration. The entirety of configuration, operation, measurement, and adjustment constitutes the calibration process. The calibration process is repeated until a level of accuracy sufficient for the specific system is reached. Additionally, the calibration is repeated periodically to recalibrate the system.

[0039] To perform the calibration, several parameters must be taken into account, such as the maximum permissible bandwidth for each client in the system, the namespaces used for each individual client, the priority, the performance QoS requirements for each host, the utilization, the capacity, the frequency, and the historical data collected for a specific host.

[0040] As mentioned above, the system can be calibrated periodically to determine the optimal ATC attributes. First, the ATC attributes are configured using a set of default parameters. Then, the system is activated while transmissions are taking place over the link. During this time, performance is measured, the results are analyzed, and the configured ATC attributes are adjusted. This process is repeated until the optimal configuration is found.

[0041] If the default ATC configuration is a global ATC, all clients are initially granted unrestricted access by ignoring their client ID. This initial configuration is evaluated as a baseline. Subsequently, the configuration is systematically adjusted and measured multiple times to identify potential improvements. Finally, the configuration that delivers optimal results is selected.

[0042] When defining an optimal cache configuration, several parameters are taken into account, including: maximum permissible bandwidth for each client; assigned namespaces for each client; client priority; client utilization (e.g., capacity, frequency, etc.) and collection of historical data on the clients.

[0043] It should be noted that a client can be either a physical or virtual PCIe function. Additionally, a client can be a specific process address space identifier (process address space ID) (PASID), which is used in a paravirtualized environment to identify a specific application. For disclosure purposes, depending on the use case and host configuration, a virtual function ID, a physical function ID, or a process address space ID can be used.

[0044] Fig. Figure 4 illustrates a Flowchart 400 that summarizes the procedure for calibrating ATC attributes according to one embodiment. At a high level, the process begins by measuring the performance results of the default configuration, which does not consider the client ID during ATC management. The configuration is then adjusted and re-evaluated based on the results. This iterative process continues until the optimal configuration is identified and selected for use. To maintain optimal performance over time, periodic recalibration may be performed.

[0045] More precisely, the process begins with initialization in block 402. The system then operates with the default configuration for the ATC attributes in block 404. The default setting could, for example, be global ATC. Next, in block 406, the system measures performance based on data traffic, such as read / write commands over the bus. After a certain period, and based on the measurements, the ATC attribute configuration is adjusted in block 408, and the performance is then measured again in block 410. Block 412 then checks whether the last experiment has taken place. If not, the process returns to block 408, where the system adjusts and modifies the configuration and then measures the result until the last experiment is complete. Once the last experiment is finished, the optimal ATC configuration is selected in block 414 based on the measured results.The system continues operating in the selected mode and then checks whether recalibration is beneficial. Recalibration can be performed periodically, such as hourly, or if the results are inefficient or performance drops. Based on the decision to recalibrate, the process is repeated.

[0046] Fig. Figure 5 is a schematic illustration of a system block diagram 500 according to one embodiment. Fig. 5 is the System Block Diagram 500, which includes the Host Interface Module (HIM), which in turn includes performance monitoring of the calibration logic to measure results and QoS performance. The HIM also contains the ATC attribute configuration, and this is being modified.

[0047] The HIM integrates the ATC and a dynamic calibration logic module. This module actively adjusts cache configurations, measures performance, and intelligently selects the optimal cache configuration. The goal is to achieve the best possible performance results, tailored to the specific characteristics of the system, workload, and configurations.

[0048] The results of the optimal ATC configuration can depend on the workload. Changes in workload may necessitate reconfiguration, as the results of the optimal ATC configuration are dependent on the workload. There are also some static configurations that can impact the results, such as the namespaces associated with a function. Namespaces that are more prone to latency, for example, would require more cache size allocation for those specific functions. For instance, whether the namespace is SLC or linked to SLC typically offers higher performance compared to TLC or QLC and therefore requires more allocation. The cache size can also adjust the removal policy based on the specific namespace. Finally, the frequency of calibration triggers can depend on several attributes.For example, if the system detects a drop in performance or a change in workload, or simply from time to time even if nothing is detected, the system can be recalibrated.

[0049] In one embodiment, the function cache allocation is controlled by the historically analyzed workload. Such an allocation is particularly valuable in enterprise data processing use cases, where the benefit of ATS in a specific function can be derived by analyzing previous I / O transactions.

[0050] In another embodiment, function cache allocation is influenced by a static configuration. For example, specific namespaces assigned to a function might indicate greater latency susceptibility and a higher allocation of ATS resources. Specific use cases include a multi-host automotive environment where some tenants might be preconfigured to use an SLC namespace. In this automotive multi-host example, ATS resource allocation would be weighted with respect to predefined functions requiring higher responsiveness.

[0051] In another embodiment, the trigger frequency of the presented calibration scheme can be modified according to various factors. For example, the calibration can be triggered at a higher rate when the measured power is relatively low, while it can be triggered at a lower rate when the measured power is relatively high. Threshold values ​​can be specified to determine low / high power. The value can also be continuous.

[0052] The frequency of calibration triggers can also depend on external conditions and the type of workload. If the workload is very intensive and system resources are needed to manage it, the calibration frequency may be lower, while with a less intensive workload, calibration can be performed more frequently.

[0053] Fig.Figure 6 is a flowchart 600 illustrating a dynamic ATC assignment according to one embodiment. First, in block 602, the initial ATC attributes are selected or set. The initial ATC attributes can be any ATC attribute distribution, such as a global ATC, a static ATC, or simply the last ATC attribute setting used by the system, to name a few. Once the initial ATC attributes are set, in block 604, the system is operated using these ATC attributes. "Operating" refers to any general operation, such as the actual processing of read / write commands or system-generated dummy commands to test the ATC attribute setting. The performance of the system operation using the ATC attribute settings is measured.

[0054] Block 606 then determines the system efficiency. Essentially, it determines whether the system is operating as efficiently as possible. If the system is not operating as efficiently as possible, the ATC attributes are changed in Block 608, and the system then operates with the new ATC attributes in Block 606.

[0055] If the system is operated as efficiently as possible, its operation continues in block 610 using the same ATC attributes. The system logs any changes that may occur and / or whether a time threshold has been exceeded. If a system parameter has changed in block 612, the process returns to block 606. However, if no parameters have changed, the process continues with block 614 to determine whether a time threshold has been exceeded. If a time threshold has been exceeded, the process returns to block 606, but continues in block 610 if the time threshold has not been exceeded. Note that blocks 612 and 614 can occur in any order and do not both need to be present.

[0056] By dynamically allocating the ATC through the selection of optimal cache attributes, the ATC achieves maximum performance results for the current application or workload. Efficiency can be measured by performance, assuming the same ATC size.

[0057] In one embodiment, a data storage device comprises: a storage device; and a controller coupled to the storage device, the controller being configured to: select a configuration for address translation cache (ATC) attributes to operate the data storage device; operate the data storage device using the configuration; measure the performance of the data storage device using the configuration; switch from one configuration to another for the ATC attributes based on measurement, and repeat the operation, measurement, and switching process. The configuration is a global ATC configuration. The configuration is a static ATC attribute configuration.The controller is configured to: select a working ATC configuration; operate the data storage device using the working configuration; and determine whether recalibration is required after operating the data storage device using the working ATC configuration. After determining that recalibration is required, the controller is configured to: switch from the working ATC configuration to a new configuration for the ATC attributes; operate the data storage device using the new configuration; measure the performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and operate the data storage device using the selected new working ATC configuration.The controller is configured to repeat the switch to a new configuration, operate using the new configuration, and measure performance using the new configuration. The controller includes a host interface module (HIM), with the ATC located within the HIM. The HIM includes an ATC attribute configuration module, a performance monitoring module, and a calibration logic module. The controller is configured to interact with one or more of the following: a virtual function; a physical function; a process address space identifier (PASID); and combinations thereof. The configuration is weighted with respect to functions requiring higher responsiveness compared to others.

[0058] In another embodiment, a data storage device comprises: a storage device; and a controller coupled to the storage device, the controller comprising a host interface module (HIM) that includes: a calibration logic module configured to adjust cache configurations, measure the performance of the data storage device, and intelligently select optimal cache configurations; a performance monitoring module configured to monitor the performance of the data storage device; and an address translation cache configuration module (ATC configuration module) configured to retain one or more cache configurations to be used for adjustment by the calibration logic module. The calibration logic module is configured to adjust cache configurations based on historically analyzed workloads.The calibration logic module is configured to adjust cache configurations with a pre-configured weighting for functions requiring higher responsiveness compared to other functions requiring lower responsiveness. Calibration performed by the calibration logic module is triggered more frequently when the measured power is below a threshold than when the measured power is equal to or greater than the threshold. Calibration is triggered based on external conditions and function workloads. As the workload increases, the calibration frequency decreases. The modules operate dynamically.

[0059] In another embodiment, a data storage device comprises storage means and a controller coupled to the storage means, the controller being configured to: measure the performance of the data storage device; modify the address translation cache attributes (ATC attributes) based on the measurement; operate the data storage device using the modified ATC attributes; store the ATC attributes; repeat the measuring, modifying, operating, and storing one or more times; select optimal ATC attributes and operate the data storage device using the selected optimal ATC attributes. The controller is configured to determine whether recalibration of the ATC attributes is necessary, the determination being made after operating the data storage device using the selected optimal ATC attributes.Measuring, changing, selecting and saving takes place in a host interface module (HIM) of the controller.

[0060] While the foregoing relates to embodiments of the present disclosure, other and further embodiments of the disclosure may be conceived without deviating from its basic scope, the scope of which is determined by the following claims.

Claims

Data storage device, comprising: a storage device; and a controller coupled to the storage device, the controller being configured to: select a configuration for address translation cache attributes (ATC attributes) for operating the data storage device; operate the data storage device using the configuration; measure the performance of the data storage device using the configuration; switch from one configuration to another for the ATC attributes based on measurement and repeat the operation, measurement and switching process. Data storage device according to claim 1, wherein the configuration is a configuration of a global ATC. Data storage device according to claim 1, wherein the configuration is a configuration of a static ATC attribute. Data storage device according to claim 1, wherein the controller is configured to: select a working ATC configuration; operate the data storage device using the working configuration; and determine whether recalibration should be performed after operating the data storage device using the working ATC configuration. Data storage device according to claim 4, wherein the controller, after determining that recalibration should be performed, is configured to: switch from the working ATC configuration to a new configuration for the ATC attributes; operate the data storage device using the new configuration; measure the performance of the data storage device using the new configuration; select a new working ATC configuration for the data storage device; and operate the data storage device using the selected new working ATC configuration. Data storage device according to claim 5, wherein the controller is configured to repeat the switching to a new configuration, the operation using the new configuration and the measurement of performance using the new configuration. Data storage device according to claim 1, wherein the controller comprises a host interface module (HIM) and wherein the ATC is arranged in the HIM. Data storage device according to claim 7, wherein the HIM comprises an ATC attribute configuration module, a power monitoring module and a calibration logic module. Data storage device according to claim 1, wherein the controller is configured to interact with one or more of the following: a virtual function; a physical function; a process address space identifier (ID) (PASID) and combinations thereof. Data storage device according to claim 1, wherein the configuration is weighted with respect to functions that require a higher responsiveness compared to other functions. Data storage device, comprising: a storage device; and a controller coupled to the storage device, the controller comprising a host interface module (HIM), comprising: a calibration logic module configured to adjust cache configurations, measure the performance of the data storage device, and intelligently select optimal cache configurations; a performance monitoring module configured to monitor the performance of the data storage device; and an address translation cache configuration module (ATC configuration module) configured to retain one or more cache configuration(s) to be used for adjustment by the calibration logic module. Data storage device according to claim 11, wherein the calibration logic module is configured to adjust cache configurations based on a historically analyzed workload. Data storage device according to claim 11, wherein the calibration logic module is configured to adapt cache configurations with a preconfigured weighting with respect to functions that require higher responsiveness compared to other functions that require lower responsiveness. Data storage device according to claim 11, wherein the calibration performed by the calibration logic module is triggered at a higher rate when the measured power is lower than a threshold than when the measured power is equal to or greater than the threshold. Data storage device according to claim 11, wherein the calibration performed by the calibration logic module is triggered based on external conditions and workloads of functions. Data storage device according to claim 15, wherein the calibration frequency is reduced as the workload increases. Data storage device according to claim 11, wherein the module is operated dynamically. Data storage device comprising: storage means and a controller coupled to the storage means, the controller being configured to: measure the performance of the data storage device; modify the address translation cache attributes (ATC attributes) based on the measurement; operate the data storage device using the modified ATC attributes; store the ATC attributes; repeat the measuring, modifying, operating, and storing one or more times; select optimal ATC attributes and operate the data storage device using the selected optimal ATC attributes. Data storage device according to claim 18, wherein the control is configured to determine whether a recalibration of the ATC attributes should be performed, wherein the determination is performed after operation of the data storage device using the selected optimal ATC attributes. Data storage device according to claim 18, wherein the measuring, changing, selecting and storing takes place in a host interface module (HIM) of the controller.

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