PROCESSING UNIT ARRANGEMENT AND A METHOD FOR DATA TRANSFER FOR A PROCESSING UNIT ARRANGEMENT

Abstract

Processing unit arrangement comprising a data source unit (10), a processing unit (20), and an actuation unit (30). The data source unit (10) is configured to provide the processing unit (20) with direct input data (D). DI ) to provide, wherein the data source unit (10) and the processing unit (20) are directly connected to each other via first data lines (W1). The processing unit (20) includes an arithmetic unit (22) configured to process direct actuation data (D DA ) to determine by performing arithmetic operations on the direct input data (D DI ) performs. The processing unit (20) is configured to process the direct actuation data (D DA) to provide the actuation unit (30), wherein the processing unit (20) and the actuation unit (30) are directly connected to each other via second data lines (W2). The actuation unit (30) is configured to operate an application using the direct actuation data (D DA ) to control.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a processing unit arrangement and a method for data transmission to a processing unit arrangement. TECHNICAL BACKGROUND

[0002] Common architectures form subsystems with a data source unit, e.g. an analog-to-digital converter (ADC), a processing unit and an actuation unit, e.g. a timer module, which are connected to each other via a bus structure.

[0003] The bus structure connecting the processing unit to the other modules introduces latency. For example, time is required before a read transaction is submitted to the data source unit, and time is needed before the data is forwarded to the processing unit and is ready for processing. The same applies to data communication between the processing unit and the actuator unit. This time limits the control loop speed. The control loop speed is determined by the time required for signal acquisition, processing, and activation or actuation. Software-based control loops are therefore limited by currently available microcontroller architectures. The speed of a control loop also hinders efficiency improvements.In other words, faster control circuits enable efficiency gains.

[0004] Consequently, there is a need for an improved processing unit arrangement, especially in power conversion applications, which are essential, for example, in the electrification of vehicles.

[0005] DE 10 2007 014 132 A1 describes a processor system with directly connected ports. The processor system comprises a first processor with at least one output and at least one second processor with at least one input. A switching device allows the output of the first processor to be directly connected to the input of the second processor. Due to the direct connection of the processors' outputs and inputs, no processing power is required for communication between the processors, resulting in significant energy savings.

[0006] EP 0 062 431 A1 describes a single-chip microcomputer comprising a central processing unit (CPU) having arithmetic, logic, and control units; a random-access memory for storing intermediate data with instructions to be processed by the CPU; means for transporting first data to be processed by the CPU; a random-access memory controller, controlled by the CPU, to provide a readout of second data stored in a predetermined area of ​​the random-access memory; means for transferring the second data stored in the predetermined area of ​​the random-access memory; and a port coupled to the means for transferring the first and second data to provide an output for the first data during a CPU operating mode and an output for the second data during a random-access memory operating mode.and time-division multiplexing means, controlled by the random access controller, to transfer the first or second data to the port. This has the advantage that direct transfer between the random access memory and the outside world can take place without providing additional ports. SUMMARY

[0007] According to one aspect, a processing unit arrangement comprises a data source unit, a processing unit, and an actuation unit. The data source unit is configured to provide direct input data to the processing unit, with the data source unit and the processing unit being directly connected via first data lines. The processing unit includes an arithmetic unit configured to determine direct actuation data by performing arithmetic operations on the direct input data. The processing unit is configured to provide the direct actuation data to the actuation unit, with the processing unit and the actuation unit being directly connected via second data lines.The actuation unit is designed to control an application using direct actuation data.

[0008] In other words, the direct connection between the processing unit, the data source unit, and the actuator unit allows for closer coupling of the processing unit's arithmetic unit to the data source and actuator unit. Eliminating an intermediate connection, such as a bus unit for data communication, enables a fast control circuit for applications, thereby reducing data transmission latency and resulting in faster control circuit execution. Consequently, the processing unit can support more sophisticated, or in other words, more complex, control algorithms.

[0009] The term "direct input data," as used here, refers to source data, or initial data or origin data, provided by the data source unit. This data is intended to be transmitted between the data source unit, the processing unit, and the actuator unit via the first and second data lines, specifically instead of using a data bus. In other words, direct input data defines the source data of the data source unit that is not transmitted via the data bus but instead directly to the respective unit via the first or second data line. Consequently, source data can be differentiated into input data and direct input data. Direct input data may be relevant to time-critical applications, such as applications with fast controllers or applications with a high-speed control circuit.

[0010] The first data lines can form a dedicated connection between the data source unit and the processing unit. In other words, no other component of the processing unit assembly is connected to the first data lines. The second data lines can form a dedicated connection between the processing unit and the actuation unit. In other words, no other component of the processing unit assembly is connected to the second data lines.

[0011] The application can include a power conversion or energy conversion application, particularly in electric vehicles. In the power conversion application, the processing unit arrangement thus provides improved response time to changing load conditions, increased precision for power electronics settings, and enables real-time algorithm optimization for dynamic / adaptive power conversion settings.

[0012] The application performed by the actuating unit can be a real-time application.

[0013] Consequently, the direct connection between the respective components, instead of a bus connection, enables the integration of real-time applications. A real-time application might include, for example, control applications on the microsecond scale. This real-time application could be a power conversion application in an electric vehicle. The processing unit might be configured to control an inverter that converts electrical power, specifically direct current (DC) power from the electric vehicle's battery, into alternating current (AC) power for the vehicle's electric motor, particularly from kilohertz to hundreds of kilohertz. Therefore, control applications on the microsecond scale per control circuit may be required.

[0014] The first data lines and the second data lines extend the generally known processing unit arrangement by providing a direct connection between the data source unit, the processing unit and the actuation unit, in addition to the generally used data bus.

[0015] This provides an improved processing unit arrangement, particularly with regard to response time.

[0016] In a preferred embodiment, the processing unit comprises an extension register unit. The extension register unit includes an extension register file configured to temporarily store the direct input data and the direct actuation data.

[0017] In other words, the extension register file is a dedicated register file used solely for direct input and direct actuation data. The extension register file is therefore an additional register file to the processing unit's standard arithmetic register file. The arithmetic register file is configured to temporarily store input and actuation data transmitted via a data bus connecting the processing unit, the data source unit, and the actuation unit. Consequently, the processing unit includes an extension register file that is separate from the arithmetic register file. The extension register file can be linked to the arithmetic register file.Thus, the arithmetic register file is set up to temporarily store the direct input data and the direct actuation data, as well as the input data and the actuation data, and is further set up to provide the corresponding data to the arithmetic unit.

[0018] A register file refers to a collection of registers configured for temporary data storage and / or manipulation, particularly during application execution. A register is a storage location containing data that the processing unit, especially an arithmetic unit, needs to access.

[0019] The extension register file enables the arithmetic unit to quickly access the direct input data. Furthermore, the extension register file enables the arithmetic unit to quickly access the actuation unit.

[0020] Thus, an improved processing unit arrangement is provided, particularly with regard to response time.

[0021] In a preferred embodiment, the processing unit comprises an arithmetic register file configured to receive direct input data from the extension register unit and to provide direct input data to the arithmetic unit. The extension register unit further comprises an extension pipeline configured to transfer direct input data and direct actuation data between the extension register file and the arithmetic register file.

[0022] The extension pipeline is configured to execute virtual load / save instructions, which are dedicated instructions for moving data to and from the arithmetic register file. The arithmetic register file can be connected to the arithmetic unit and is configured to transfer data to and receive data from the arithmetic unit.In other words, the arithmetic register file is configured to temporarily store the input data from the data source unit via the data bus, to temporarily store the direct actuation data from the data source via the first data lines, to temporarily store the direct actuation data from the arithmetic unit that is to be sent to the actuation unit via the second data lines, and to temporarily store the actuation data from the arithmetic unit that is to be sent to the actuation unit via the data bus. Consequently, the extension register unit is configured to send the direct input data from the extension register file to the arithmetic register file and to send the direct actuation data from the arithmetic register file to the extension register unit.

[0023] Consequently, the arithmetic register file can be accessed by the standard processor's load / store pipeline for storing data read from the normal data bus and by the extension pipeline for storing direct-input data from the extension register file. In other words, both an input data register file of the data source unit, which stores the input data, and a direct-input data register file of the data source, which stores the direct-input data, can access the arithmetic register file simultaneously. The input data register and the direct-input data register are thus configured to apply read and write restrictions to prevent data inconsistencies. This ensures that no simultaneous access to the arithmetic register file by different register files is possible.

[0024] The extension register unit, in particular the extension register file and the extension pipeline, extend the generally known processing unit arrangement, in particular the processing unit, so that the arithmetic unit can process the direct input data and provide the direct actuation data to the actuation unit.

[0025] In RISC-V technology, i.e., when the processing unit is a RISC-V processing unit, the arithmetic register file is referred to as the standard register file.

[0026] This provides an improved processing unit arrangement, particularly with regard to response time.

[0027] In a preferred embodiment, the extension register unit comprises a control / status register, CSR, extension unit configured to configure the extension register file.

[0028] The CSR extension unit allows the extension register file to be dynamically adjusted in at least one parameter.

[0029] This provides an improved processing unit arrangement, particularly with regard to response time.

[0030] In a preferred embodiment, configuring the extension register file includes determining a size and / or an input / output mode of registers of the extension register file.

[0031] In other words, the CSR extension unit is configured to determine parameters, such as how much of the direct input data in the direct input register file is transferred from the data source unit to the processing unit. This is referred to as determining the register size.

[0032] In particular, the CSR extension unit is configured to determine which register entries of the extension register file are used for input and output, respectively. Furthermore, the CSR extension unit is configured to determine when a data transfer between the extension register file and the direct input register file should occur. Thus, new direct input data is only accepted by the data source unit when sufficient direct input data is written from the extension register file to the arithmetic register file. This is referred to as determining a register input / output mode.

[0033] This provides an improved processing unit arrangement, particularly with regard to response time.

[0034] In a preferred embodiment, the data source unit comprises a direct input data register unit, wherein the direct input data register unit comprises a selection unit and a direct input data register file, wherein the direct input data register file is configured to temporarily store the direct input data, and wherein the selection unit is configured to select the direct input data from available source data of the data source unit.

[0035] The selection unit can apply a predefined selection rule to the source data to determine the direct input data. The selection rule can be dynamically configurable. The predefined selection rule can reflect the application for which the source data is used. The selection rule can determine the direct input data from the source data relating to time-critical applications, such as fast control circuit applications.

[0036] The direct input data register unit, in particular the selection unit and the direct input data register file, extend the generally known processing unit arrangement, in particular the data source unit, to enable a direct connection between the data source unit and the processing unit.

[0037] The direct input data register unit can be an extension of the generally known processing unit arrangement.

[0038] The data source unit automatically determines the direct input data from the source data.

[0039] In other words, the selection unit is set up to determine how much of the source data should be considered direct input data.

[0040] This provides an improved processing unit arrangement, particularly with regard to response time.

[0041] In a preferred embodiment, the direct input data register file includes a ring buffer configured to provide the direct input data to the processing unit in a ring model method, or a round-robin fashion.

[0042] The round-robin method provides a first-in, first-out algorithm for direct input data. This ensures that only the oldest direct input data in the direct input data register file is transferred to the processing unit.

[0043] The ring buffer also allows the direct input data register unit to collect some of the source data that should be provided directly to the processing unit via the first lines before the source data is actually transmitted.

[0044] This provides an improved processing unit arrangement, particularly with regard to response time.

[0045] In a preferred embodiment, the size of the direct input data register file is less than or equal to 12 register entries.

[0046] In power conversion applications, particularly in electric vehicles, limiting the direct input data register file to 12 register entries is sufficient to run the applications. Consequently, the size of the extension register file can also be relatively small, especially up to 32 entries.

[0047] Thus, an improved processing unit arrangement is provided, particularly with regard to response time.

[0048] In a preferred embodiment, the first data lines include a first feedback line to indicate that new direct input data can be accepted by the processing unit; and / or wherein the second data lines include a second feedback line to indicate that new direct actuation data can be accepted by the actuation unit.

[0049] The first and second feedback lines provide a stable data flow between the components of the processing unit arrangement.

[0050] In other words, the first data line and the second data line are set up to transmit a data vector, in particular a 16-bit word or a 32-bit word, and due to the feedback lines, they are set up to transmit a single bit of information.

[0051] This provides an improved processing unit arrangement, particularly with regard to response time.

[0052] In a preferred embodiment, the first data lines and the second data lines each comprise up to 32 data lines.

[0053] Consequently, the first data lines and the second data lines can each transmit thirty-two data bits. Thus, the first data lines and the second data lines each comprise a plurality of data lines, in particular thirty-two data lines, and the feedback line.

[0054] This provides an improved processing unit arrangement, particularly with regard to response time.

[0055] In a preferred embodiment, the data source comprises an analog-to-digital converter, ADC converter, and / or a sensor interface unit.

[0056] In a preferred embodiment, the processing unit arrangement further comprises a data bus that connects the data source unit, the processing unit, and the actuating unit, wherein the data bus is configured to exchange input data between the data source unit and the processing unit and to exchange actuating data between the processing unit and the actuating unit. The input data is the source data excluding the direct input data.

[0057] In other words, the data source unit provides source data from at least one data source. The data source can include a result handling unit and / or a digital signal processing unit. The source data can be stored temporarily in at least one input data register file. From this input data register file, the selection unit chooses the source data to be transmitted directly to the processing unit via the first data lines. This selected data is called direct input data and is stored temporarily in the direct input data register file. The source data to be transmitted to the processing unit via the data bus remains in the input data register file and is referred to as input data.

[0058] In a preferred embodiment, the arithmetic register file is configured to receive the input data from the data bus and to provide the input data to the arithmetic unit.

[0059] The arithmetic register file is therefore configured to receive input data from the data bus and direct input data from the extension register file. Furthermore, the arithmetic register file is configured to receive actuation data and direct actuation data from the arithmetic unit. In other words, the arithmetic register file is a central register file for all input and actuation data transmitted via the first and second data lines and the data bus.

[0060] This provides an improved processing unit arrangement, particularly with regard to response time.

[0061] In a preferred embodiment, the data bus is an axi interconnect.

[0062] According to one aspect, a data transmission method for a processing unit arrangement comprises a data source unit, a processing unit, and an actuation unit, wherein the processing unit includes an arithmetic unit, wherein the data source unit and the processing unit are directly connected to each other by first data lines, and wherein the processing unit and the actuation unit are directly connected to each other by second data lines, and wherein the method comprises: providing direct input data to the processing unit by the data source unit; determining direct actuation data by the arithmetic unit by performing arithmetic operations on the direct input data; providing the direct actuation data to the actuation unit by the processing unit; and controlling an application by the actuation unit using the direct actuation data.

[0063] The person skilled in the art will recognize additional features and advantages when reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements in the drawings are not necessarily to scale with one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. Figure 1 illustrates a processing unit arrangement according to an embodiment of the invention; and Fig. Figure 2 illustrates a method for data transmission for a processing unit arrangement according to an embodiment of the invention. DETAILED DESCRIPTION

[0065] Fig. Figure 1 illustrates a processing unit arrangement comprising a data source unit 10, a processing unit 20, and an actuation unit 30. In this case, the data source unit 10 is an analog-to-digital converter (ADC), the processing unit 20 is a RISC-V central processing unit (CPU), and the actuation unit 30 is a timer.

[0066] Data source unit 10 is configured to receive input data D I and direct input data D DI to be provided for processing unit 20. Processing unit 20 is configured to process data based on input data D. I Confirmation data D A to determine, and is set up to do so based on the direct input data D DI Direct actuation data D AI to determine. Processing unit 20 is further configured to determine the operating data D. A and the direct actuation data DAI to provide the actuating unit 30.

[0067] The processing unit arrangement comprises a data bus 40 that connects the data source unit 10, the processing unit 20, and the actuation unit 30. The data bus 40, the data source unit 10, and the processing unit 20 are configured to receive the input data D I from data source unit 10 via data bus 40 to processing unit 20. Furthermore, data bus 40, processing unit 20, and actuation unit 30 are configured to transmit the actuation data D A from the processing unit 20 to the actuation unit 30. In addition, the data bus 40 also serves for data transmission between other components besides the data source unit 10, the processing unit 20 and the actuation unit 30.

[0068] The processing unit also includes first data lines W1, which directly connect the data source unit 10 to the processing unit 20. The first data lines W1, the data source unit 10, and the processing unit 20 are configured to transmit the direct input data D. DI to transfer from data source unit 10 to processing unit 20.

[0069] The processing unit also includes second data lines W2, which connect the processing unit 20 directly to the actuating unit 30. The second data lines W2, the processing unit 20, and the actuating unit 30 are configured to transmit the direct actuating data D. AI to be transferred from processing unit 20 to actuation unit 30.

[0070] The processing unit arrangement thus allows data to be exchanged between the data source unit 10, the processing unit 20, and the actuator unit 30 via the data bus 40, which is the generally known approach. However, the processing unit arrangement also enables data exchange between the data source unit 10, the processing unit 20, and the actuator unit 30 via the first data lines W1 and the second data lines W2, thereby providing a direct connection between the respective components. This results in an improved processing unit arrangement, particularly with regard to response time.

[0071] The data source unit 10 comprises a result processing unit 12 and a digital signal processing unit 13, both of which process source data D SThe data source unit 10 comprises an initial input data register file 14a, which is configured to provide the source data D supplied by the result processing unit 12. S to temporarily store. The data source unit 10 includes a second input data register file 14b, which is configured to store the source data D provided by the digital signals processing unit 13. S to be stored temporarily. The first input data register file 14a is represented by the register entries RAW R0 to RAW Rx. The second data register file 14b is represented by the register entries DSP R0 to DSP Rx.

[0072] The data source unit 10 comprises a direct input data register unit 11. The direct input data register unit 11 comprises a selection unit 11a, a direct input data register file 11b, and a direct input data output control unit 11c.

[0073] The direct input data selection unit 11a is set up to process direct input data D DI from the available source data D S to select the data source unit 10, in other words, from the data provided by the result processing unit 12 and a digital signal processing unit 13. The selection unit 11a is thus configured to select the source data D S to select the direct input data D DI The data should be transmitted directly to the processing unit 20 via the first data lines W1.

[0074] The direct entry data register file 11b is set up to store the direct entry data D DI to be stored temporarily. The direct input data register file 11b can include a ring buffer. In this way, the direct input data D DIThe processing unit is provided in a round-robin procedure. In this case, the processing unit arrangement is configured for a power conversion application in an electric vehicle. The size of the direct input data register file 11b is therefore twelve. In other words, the direct input data register file 11b comprises twelve register entries, specified by the register entries Ri1 to Rix shown.

[0075] The direct input data output control unit 11c is configured to control the transfer of direct input data (DDI) from the data source unit 10, in particular the direct input data register file 11b, to the data processing unit 20. The first data lines W1 include a first feedback line to indicate to the direct input data output control unit 11c that new direct input data D DI can be accepted by processing unit 20.

[0076] Thus, the data source unit represents 10 source data D S , ready, with part of the source data D S via the first data lines W1 as direct input data D DI is transferred directly to processing unit 20, while the rest of the source data D S via data bus 40 as input data D I is transferred to processing unit 20.

[0077] The processing unit 20 comprises an extension register unit 21, an arithmetic unit 22, an arithmetic register unit 23, an instruction retrieval unit 24 and a write-back unit 25.

[0078] The extension register unit 21 comprises an extension register file 21a, an extension pipeline 21b, a control / status register extension unit 21c, a direct input data input control unit 21d and a direct actuation data output control unit 21e.

[0079] The extension register file 21a is set up to store the direct input data D DI to temporarily store data from the data source input unit 10, in particular the input data register file 11b. The extension register file 21a is represented by the register entries Re1 to Rex.

[0080] The extension pipeline 21b is configured to execute virtual load / store instructions, which are dedicated instructions for moving the direct input data D. DI into the arithmetic register unit 23, in particular into an arithmetic register file 23a.

[0081] The arithmetic register unit 23 is configured to process the direct input data D DIto receive from the extension register file 21a via the extension pipeline 21b, and is configured to receive the input data DI from the first input data register file 14a and the second input data register file 14b via the data bus 40.

[0082] The arithmetic register unit 23 comprises a RISC-V register file, designated as arithmetic register file 23a, a floating-point register file 23b, and a vector register file 23c. For simplicity, only arithmetic register file 23a is used here, especially since in this scenario the data source unit 10 is an ADC.

[0083] In other words, the arithmetic register file 23a is set up to store the input data D I and / or the direct input data D DI to store temporarily.

[0084] Arithmetic unit 22 is set up to process the input data D I the activation data D Ato determine and is set up for this purpose with the direct input data D DI the direct actuation data D DA to determine.

[0085] The write-back unit 25 is connected to the arithmetic unit 22 and is configured to record the actuation data D A and the direct actuation data D DA to write back to the arithmetic register file 23a.

[0086] In other words, the arithmetic register file 23a is set up to store the input data D I , the direct input data D DI , the activation data D A and / or the direct actuation data D DA to store temporarily.

[0087] The extension pipeline 21b is configured to execute virtual load / save instructions, which are dedicated instructions for moving the direct actuation data D. DI from the arithmetic register file 23a to the extension register file 21a.

[0088] The activation data D A are provided to the actuation unit 30, in particular an actuation register file 32, by the arithmetic register file 23a.

[0089] The control / status register expansion unit 21c is configured to configure the expansion register file 21a, as well as the direct input data input control unit 21d and the direct actuation data output control unit 21e. The direct input data input control unit 21d is connected to the direct input data output control unit 11c via the first data lines W1 and controls the data transmission of direct input data between the data source unit 10 and the processing unit 20. The direct actuation data output control unit 21e is connected to a direct actuation data input control unit 31 of the actuation unit 30 via the second data lines W2 and controls the data transmission of direct actuation data between the processing unit 20 and the actuation unit 30.

[0090] The direct actuation data D DAare provided to the actuation unit 30, in particular the actuation register file 32, from the extension register file 21a.

[0091] In other words, the actuation register file 32, represented by the register entries Ra1 to Rax, is set up to store the actuation data D A and / or the direct actuation data D DA to store temporarily.

[0092] The instruction retrieval unit 24 is configured to provide the arithmetic register file unit 23 with RISC-V instructions for performing the correct arithmetic operation or calculation operations.

[0093] The actuation unit 30 comprises the direct actuation data input control unit 31, the actuation register file 32, a direct actuation data selection unit 33 and an actuation unit output unit 34, which is also referred to as the time output unit.

[0094] The direct actuation data selection unit 33 is configured to control the direct actuation data input control unit 31. This prevents data inconsistencies in the actuation register file 32, since the actuation register file 32 is configured to store the actuation data D A and / or the direct actuation data D DA to temporarily store. The actuation output unit 34 is connected to the actuation register file 32 and configured to use the actuation data D. A and / or the direct actuation data D DA to determine an activity expenditure.

[0095] The direct actuation data output control unit 21e is configured to transmit the direct actuation data D DAfrom the processing unit 10, in particular the extension register file 21a, to the actuation unit 30. The second data lines W2 include a second feedback line to indicate to the direct actuation data output control unit 21e that new direct actuation data D DA can be assumed from the actuation unit 30.

[0096] The described processing unit arrangement thus makes it possible for some of the source data to be exchanged between the components of the processing unit arrangement in a more direct way without using the data bus, in order to provide shorter access times and lower latency in data communication between the components.

[0097] This provides an improved processing unit arrangement, particularly with regard to response time.

[0098] Fig.Figure 2 illustrates a data transmission method for a processing unit arrangement comprising a data source unit 10, a processing unit 20, and an actuation unit 30. The processing unit 20 includes an arithmetic unit 22. The data source unit 10 and the processing unit 20 are directly connected to each other via first data lines W1. The processing unit 20 and the actuation unit 30 are directly connected to each other via second data lines W2. The method comprises the following steps: Providing S10 with direct input data D DI to processing unit 20 by data source unit 10. Determine S20, by arithmetic unit 22, of direct actuation data D DA , by performing arithmetic operations on the direct input data D DI be carried out. Provide S30 the direct actuation data D DAthrough processing unit 20 to actuation unit 30. Control S40 of an application using direct actuation data D DA through the control unit 30.

[0099] Although certain examples have been illustrated and described herein, the person skilled in the art will recognize that a multitude of alternative and / or equivalent implementations can be used instead of the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover all adaptations or variations of the specific examples described herein.

[0100] Therefore, the present invention shall be limited only by the claims and their equivalents.

[0101] It should be noted that the methods and arrangements, including their preferred embodiments, as described in this document, can be used alone or in combination with the other methods and arrangements disclosed herein. Furthermore, the features described in connection with an arrangement are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and arrangements described in this document can be combined with one another as desired. In particular, the features of the claims can be combined with one another in any way desired. List of reference symbols 10 Data source unit 11 Direct Input Data Register Unit 11a Selection Unit 11b Direct input data register file 11c Direct Input Data Output Control Unit 12 Result processing unit 13 Digital signal processing unit 14a first input data register file 14b second input data register file 20 processing units 21 Extension Register 21a Extension Register File 21b Expansion pipeline 21c Control / Status Register Expansion Unit 21d Direct Input Data Input Control Unit 21e Direct Actuation Data Output Control Unit 22 Arithmetic units 23 Arithmetic Register File Unit 23a Arithmetic Register File 23b Floating-point register file 23c vector register file 24 Command Retrieval Unit 25 write-back unit 30 Actuating unit 31 Actuation data output control unit 32 Activity register file 33 Direct Actuation Data Selection Unit 34 Actuating unit-dispensing unit 40 Data bus D DI Direct input data D DA Direct actuation data D I Input data D A Actuation data D S Source data W1 first data lines W2 second data lines

Claims

[1] Processing unit arrangement, with: a data source unit (10); a processing unit (20); and an actuating unit (30); wherein the data source unit (10) is configured to receive direct input data (D DI ) to provide the processing unit (20), wherein the data source unit (10) and the processing unit (20) are directly connected to each other via first data lines (W1); wherein the processing unit (20) comprises an arithmetic unit (22) configured to process direct actuation data (D DA ) to determine by performing arithmetic operations on the direct input data (D DI ) carries out; wherein the processing unit (20) is configured to process the direct actuation data (D DA) to provide the actuation unit (30), wherein the processing unit (20) and the actuation unit (30) are directly connected to each other via second data lines (W2); wherein the actuating unit (30) is configured to execute an application using the direct actuating data (D DA ) to control. [2] Processing unit arrangement according to claim 1, wherein the processing unit (20) comprises an extension register unit (21), wherein the extension register unit (21) comprises an extension register file (21a) configured to store the direct input data (D DI ) and the direct actuation data (D DA ) to store temporarily. [3] Processing unit arrangement according to claim 2, wherein the processing unit (20) comprises an arithmetic register file (23) configured to process the direct input data (D DI) to receive from the extension register unit (21) and the direct input data (D DI ) to provide the arithmetic unit (22); wherein the extension register unit (21) further comprises an extension pipeline (21b) configured to receive the direct input data (D DI ) and the direct actuation data (D DA ) between the extension register file (21a) and the arithmetic register file (23). [4] Processing unit arrangement according to one of claims 2 or 3, wherein the extension register unit (21) comprises a control / status register, CSR, extension unit (21c) configured to configure the extension register file (21a). [5] Processing unit arrangement according to claim 4, wherein configuring the extension register file (21a) includes determining a size and / or an input / output mode of registers of the extension register file (21a). [6] Processing unit arrangement according to one of the preceding claims, wherein the data source unit (10) comprises a direct input data register unit (11), wherein the direct input data register unit (11) comprises a selection unit (11a) and a direct input data register file (11b), wherein the direct input data register file (11b) is configured to store the direct input data (D DI ) to temporarily store, wherein the selection unit (11a) is configured to store the direct input data (D DI ) from available source data (D S ) to select the data source unit (10). [7] Processing unit arrangement according to claim 6, wherein the direct input data register file (11b) comprises a ring buffer configured to supply the processing unit (20) with the direct input data (D DI ) to provide in a round-robin format. [8] Processing unit arrangement according to one of claims 6 or 7, wherein the size of the direct input data register file (11b) is less than or equal to 12 register entries. [9] Processing unit arrangement according to any one of the preceding claims, wherein the first data lines (W1) include a first feedback line to indicate that new direct input data (D DI ) can be accepted by the processing unit (20); and / or wherein the second data lines (W2) include a second feedback line to indicate that new direct actuation data (D DA ) can be accepted by the actuating unit (30). [10] Processing unit arrangement according to claim 9, wherein the first data lines (W1) and the second data lines (W2) each comprise up to 32 data lines. [11] Processing unit arrangement according to one of the preceding claims, wherein the data source (10) comprises an analog-to-digital converter, ADC converter, and / or a sensor interface unit. [12] Processing unit arrangement according to one of the preceding claims, further comprising a data bus (40) connecting the data source unit (10), the processing unit (20) and the actuation unit (30), wherein the data bus is configured to transmit input data (D I ) between the data source unit (10) and the processing unit (20), and is configured to exchange the actuation data between the processing unit (20) and the actuation unit (30), wherein the input data (D I ) the source data (D S ) without the direct input data (D DI ) are. [13] Processing unit arrangement according to claim 12, wherein the arithmetic register file (23) is configured to store the input data (D I ) from the data bus (40) and the input data (D I ) to provide the arithmetic unit (22). [14] Processing unit arrangement according to one of claims 12 or 13, wherein the data bus (40) is an Axi connection. [15] Data transmission method for a processing unit arrangement comprising a data source unit (10), a processing unit (20) and an actuation unit (30), wherein the processing unit (20) comprises an arithmetic unit (22), wherein the data source unit (10) and the processing unit (20) are directly connected to each other via first data lines (W1), wherein the processing unit (20) and the actuation unit (30) are directly connected to each other via second data lines (W2), the method comprising: Providing (S10) direct input data (D DI ) to the processing unit (20) by the data source unit (10); Determine (S20), by the arithmetic unit (22), of direct actuation data (D DA ) by performing arithmetic operations on the direct input data (D DI ); Providing (S30), through the processing unit (20), the direct actuation data (D DA ) to the actuating unit (30); and Control (S40), by the actuation unit (30), an application using the direct actuation data (D DA ).

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