GATE CONTROL SYSTEM

Abstract

A gate drive system for controlling a switching operation of a first switch, wherein the gate drive system is configured to receive a control signal, provide a gate drive voltage signal at a gate terminal of the first switch to control the switching operation of the first switch, detect a first voltage at a first terminal of the first switch, and adjust the gate drive voltage signal based on the detected first voltage.

Description

AREA

[0001] This disclosure relates to a gate control system. In particular, this disclosure relates to a gate control system for controlling the switching operation of a switch. BACKGROUND

[0002] Switches, such as power switches, are ubiquitous in electronic circuits. The opening and closing of the switches can be controlled by a gate drive voltage applied to one of the switch terminals. A switch can be implemented using a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0003] Selecting the correct drive voltage for a MOSFET is crucial, as it directly affects the functionality, safety, and overall performance of the circuit. The optimal drive voltage depends on various factors, such as the MOSFET type, its threshold voltage, the application requirements, the balance between switching-speed-related EMI and power loss, and the capabilities of the gate drive circuit.

[0004] The selected drive voltage is preferably within the nominal parameters of the MOSFET, such as the maximum gate voltage limit (VG). gs_max ), and simultaneously meets the performance requirements of the application. SUMMARY

[0005] It is desirable to provide an improved gate control system for controlling the switching operation of a switch.

[0006] According to a first aspect of the disclosure, a gate drive system is provided for controlling a switching operation of a first switch, wherein the gate drive system is configured to receive a control signal, provide a gate drive voltage signal to a gate terminal of the first switch to control the switching operation of the first switch, detect a first voltage at a first terminal of the first switch, and adjust the gate drive voltage signal based on the detected first voltage.

[0007] Optionally, the gate drive system is configured to provide the gate drive voltage signal with a first gate drive voltage when the control signal is in a first state, and to provide the gate drive voltage signal with a second gate drive voltage when the control signal is in a second state.

[0008] Optionally, the gate drive system is configured to adjust the first gate drive voltage using the detected first voltage to maintain an essentially constant difference between the first gate drive voltage and the first voltage while the control signal is in the first state, and / or to adjust the second gate drive voltage using the detected first voltage to maintain an essentially constant difference between the second gate drive voltage and the first voltage while the control signal is in the second state.

[0009] Optionally, the first switch is a metal oxide semiconductor field-effect transistor (MOSFET).

[0010] Optionally, the first switch is an insulated-gate bipolar transistor (IGBT).

[0011] Optionally, the MOSFET can be a silicon MOSFET, a silicon carbide MOSFET, or a gallium nitride MOSFET.

[0012] Optionally, the MOSFET is an N-channel enrichment mode MOSFET.

[0013] Optionally, the first voltage is a source voltage and the first connection is a source connection.

[0014] Optionally, the first switch is coupled to a detection resistor at the first terminal and / or the first switch is coupled to an additional circuit at the second terminal.

[0015] Optionally, the control signal is a pulse width modulation (PWM) signal.

[0016] Optionally, the gate drive system includes a gate drive circuit configured to receive the control signal and provide the gate drive voltage signal to the gate terminal of the first switch to drive the switching operation of the first switch, and a compensation circuit configured to detect the first voltage at the first terminal of the first switch and provide an adjustment signal to the gate drive circuit that depends on the detected first voltage, with the gate drive circuit being configured to adjust the gate drive voltage signal based on the received adjustment signal.

[0017] Optionally, the compensation circuit is configured to receive a supply voltage and generate an adapted supply voltage based on the detected first voltage, with the adaptation signal depending on the adapted supply voltage.

[0018] Optionally, the adaptation signal is the adapted supply voltage.

[0019] Optionally, the gate drive system is configured to provide the gate drive voltage signal with a first gate drive voltage when the control signal is in a first state, to provide the gate drive voltage signal with a second gate drive voltage when the control signal is in a second state, and to provide the first gate drive voltage using a matched supply voltage, thereby matching the gate drive voltage signal based on the first voltage, and / or to provide the second gate drive voltage using a matched supply voltage, thereby matching the gate drive voltage signal based on the first voltage.

[0020] Optionally, the compensation circuit includes an add-in circuit configured to generate the adjusted supply voltage by adding the supply voltage and the detected first voltage.

[0021] Optionally, the add-in circuit is configured to successively generate the adjusted supply voltage during operation at discrete time intervals.

[0022] According to a second aspect of the disclosure, a device is provided which includes a control device for controlling a power converter for receiving an input voltage and generating an output voltage, wherein the power converter includes one or more power switches, wherein the control device includes a gate drive system for controlling a switching operation of each of the one or more power switches, wherein the gate drive system is configured to receive a control signal and to provide a gate drive voltage signal to a gate terminal of each of the one or more power switches in order to control the switching operation of the power switch, to detect a first voltage at a first terminal of the power switch and to adjust the gate drive voltage signal based on the detected first voltage.

[0023] The device optionally includes the power converter.

[0024] Optionally, the control device is configured to provide a discontinuous conduction mode (DCM) or a continuous conduction mode (CCM) for the power converter.

[0025] Optionally, the power converter can be a buck converter, a boost converter, or a buck-boost converter.

[0026] Optionally, the power converter is a step-down converter, a step-up converter, or a step-down / step-up converter, such as a flyback, forward, or Cuk converter, etc. Optionally, the source of the power switch is connected to ground via an impedance-inducing device, such as a sensing resistor.

[0027] It is obvious that the device of the second aspect may include the features described in the first aspect and may include further features described here.

[0028] According to a third aspect of the disclosure, a method for controlling a switching operation of a first switch using a gate control system is provided, comprising receiving a control signal, providing a gate control voltage signal to a gate terminal of the first switch to control the switching operation of the first switch, detecting a first voltage at a first terminal of the first switch, and adjusting the gate control voltage signal based on the detected first voltage.

[0029] It is evident that the procedure of the third aspect may include the use and / or provision of the features described in the first aspect and / or the second aspect, and may include further features described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The disclosure is described in more detail below using examples and with reference to the attached drawings, in which: Fig. 1A is a diagram showing the relationship between gate-source voltage and drain-source on-resistance of an N-channel enhancement mode MOSFET; Fig. 1B is a diagram showing the relationship between temperature and drain current of an N-channel enrichment mode MOSFET; Fig. 2A is a schematic representation of a device with a control device, Fig. 2B is a schematic representation of a device with an isolated driver; Fig. 3A is a diagram showing the waveforms of an operation of a practical implementation of the device of Fig. 2A in a discontinuous line mode (DCM) indicates, Fig. 3B is a diagram showing the waveforms of an operation of a practical implementation of the device of Fig. 2A in continuous conduction mode (CCM) indicates, Fig. 3C is a diagram that shows the waveforms of an operation of a practical implementation of the device of Fig. 2B in discontinuous conduction mode (DCM) shows, Fig. 3D is a diagram that shows the waveforms of an operation of a practical implementation of the device of Fig. 2B shows in continuous conduction mode (CCM); Fig. 4A is a schematic representation of a gate control system for controlling a switching operation of a switch according to a first embodiment of the present disclosure, Fig. 4B a schematic representation of a specific embodiment of the gate control system of Fig. 4A according to a second embodiment of the present disclosure is, Fig. 4C is a diagram showing waveforms associated with the operation of a practical implementation of the gate drive system of Fig. are associated with 4B; Fig. 5A a schematic representation of a specific embodiment of the gate control system of Fig. 4A according to a third embodiment of the present disclosure is, Fig. 5B is a schematic representation of the gate control system with a specific embodiment of the compensation circuit according to a fourth embodiment of the present disclosure, Fig. 5C is a schematic representation of the gate control system with a specific embodiment of the compensation circuit according to a fifth embodiment of the present disclosure; Fig. 6A is a diagram showing waveforms associated with the operation of a practical implementation of the gate drive system of Fig. 5B are associated with the linear adaptive MOSFET drive approach with DCM, Fig. Figure 6B is a diagram showing waveforms associated with the operation of a practical implementation of the gate drive system of Fig. 5B are associated with the linear adaptive MOSFET drive approach with CCM, Fig. 6C is a diagram showing waveforms associated with the operation of a practical implementation of the gate drive system of Fig. 5B are associated with the non-linear adaptive MOSFET drive approach with DCM, Fig. 6D is a diagram showing waveforms associated with the operation of a practical implementation of the gate drive system of Fig. 5B is associated with the non-linear adaptive MOSFET drive approach using CCM; and Fig. 7 is a schematic representation of a device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Various parameters are taken into account when selecting a drive voltage for a MOSFET.

[0032] The higher the drive voltage, the lower the drain-source on-resistance R. ds_on The higher the drive voltage, the lower the conduction loss and the lower the switching loss, as the MOSFET turn-on speed is faster. However, a higher drive voltage increases the likelihood of electromagnetic interference (EMI) due to the faster turn-on, and the charging loss of the MOSFET gate also increases. Additionally, a certain margin must be maintained between the drive voltage and the maximum gate voltage limit (VG). gs_max These limits must be adhered to in order to ensure that even in worst-case scenarios – including gate voltage oscillations due to parasitic inductance in the drive circuit – the drive voltage does not exceed the gate voltage limit V. gs_max does not exceed.

[0033] Taking the above factors into account, developers can choose a suitable drive voltage that ensures the MOSFET operates efficiently and reliably for the specific application.

[0034] The embodiments described in this disclosure are primarily presented for an N-channel enhancement-mode MOSFET. However, it is obvious that other switch types can also be used for further embodiments, according to the understanding of those skilled in the art.

[0035] Fig. 1A is a diagram 100 that shows the relationship between the gate-source voltage V GS and the drain-source on-resistance R Dson represents an N-channel enrichment mode MOSFET. Fig. 1B is a diagram 102 showing the relationship between temperature and drain current I D for an N-channel enrichment mode MOSFET.

[0036] As in Fig. 1A and Fig. Figure 1B shows that the higher the gate-source voltage Vgs, the lower the drain-source on-resistance R. Dson This reduces conduction losses. This is particularly important in high-current applications. If the gate-source voltage Vgs is too low, the drain-source on-resistance R increases. Dson This leads to higher line losses, significant heating of the components and reduced current carrying capacity, which can lead to circuit malfunctions.

[0037] In the development of power converters, measuring the current through a MOSFET is often necessary for current control or protection. To keep costs down, a sensing resistor is typically used between the MOSFET's source and ground (GND). The power converter can, for example, be a boost converter.

[0038] There are typically two conventional gate control methods: non-isolated and isolated. The following sections describe each method along with its respective advantages and disadvantages.

[0039] Fig. Figure 2A is a schematic representation of a device 200 with a control device 202 with a gate driver 204 for controlling a MOSFET 206. The MOSFET 206 is coupled to a detection resistor 208 and an additional circuit 210. Fig. Figure 2A shows a known non-isolated control method. Fig. Figure 2B is a schematic representation of a device 212 with an isolated driver 214 for controlling the MOSFET 206.

[0040] Fig. 3A is a diagram 300 showing the waveforms in relation to the operation of a practical implementation of the device 200 in a discontinuous line mode (DCM). Fig. 3B is a diagram 302 showing the waveforms in relation to the operation of a practical implementation of the device 200 in a continuous line mode (CCM).

[0041] Fig. 3C is a diagram 304 showing the waveforms relating to the operation of a practical implementation of the device 212 in a discontinuous line mode (DCM). Fig. 3D is a diagram 306 showing the waveforms in relation to the operation of a practical implementation of the device 212 in a continuous line mode (CCM).

[0042] The conventional gate drive method, a non-isolated solution for driving MOSFET 206, as in Fig. 2A is shown, and the relevant waveform for this method is in Fig. 3A and Fig. Figure 3B shows this method. This method sets the gate voltage to a fixed value that is optimized with respect to efficiency, electromagnetic interference (EMI) and Vgs rating of the MOSFET.

[0043] However, if the current ID through the detection resistor 208 increases, the source voltage V also increases. s of MOSFET 206, which in turn reduces the gate-source voltage Vgs. As a result, Vgs deviates from its optimized value, leading to an increase in R. ds_on This leads to increased heat dissipation, reduces the current carrying capacity of the MOSFET, and in severe cases can lead to circuit failure.

[0044] A developer could counteract the drop in Vgs voltage caused by an increase in MOSFET current ID by increasing the gate voltage V. g compensate. However, this approach would bring the Vgs voltage closer to its maximum value (V). gs_max) when the MOSFET current ID is low, which may lead to problems such as increased electromagnetic interference (EMI) and additional drive losses due to the increasing gate charge (Q). gs ).

[0045] An alternative conventional approach, the isolated solution for controlling MOSFET 206, as in Fig. Figure 2B shows the use of the isolated driver 214. The relevant waveforms for this method are shown in Fig. 3C and Fig. 3D representation. The reference mass of this isolated driver 214 is defined by the Source V. s of the MOSFET, ensuring that Vgs is independent of changes in V s This method remains stable. However, it increases costs and requires additional wiring. Since isolated drivers are still difficult to integrate into a chip, this method not only increases costs but also the overall size of the final design.

[0046] In summary, while the conventional non-isolated method for driving a MOSFET is cost-effective, the gate-source voltage (Vgs) fluctuates with changes in the source voltage (V). s ) and deviates from its originally optimized value. As the current increases, the Vgs voltage decreases, leading to a higher R ds_on This leads to a reduction in efficiency and power density. The conventional isolated method with an isolated driver solves this problem, but incurs additional costs, complexity due to extra wiring, and increases the size.

[0047] Fig. Figure 4A is a schematic representation of a gate control system 400 for controlling a switching operation of a switch 402 according to a first embodiment of the present disclosure.

[0048] The gate control system 400 is configured to receive a control signal 404 and to provide a gate drive voltage signal Vg to a gate terminal 406 of the switch 402 in order to control the switching operation of the switch 402. The control signal 404 can be a pulse width modulation (PWM) signal. The gate drive voltage signal Vg can be dependent on the control signal 404.

[0049] The gate drive system 400 is further configured to apply a voltage V s to detect at a terminal 408 of the switch 402 and to generate the gate drive voltage signal Vg based on the detected voltage V s to adapt.

[0050] Fig. Figure 4B is a schematic representation of a specific embodiment of the gate control system 400 from Fig. 4A according to a second embodiment of the present disclosure. In the present embodiment, the switch 402 is a MOSFET. The MOSFET 402 can be, for example, a silicon MOSFET, a silicon carbide MOSFET, or a gallium nitride MOSFET. The MOSFET 402 can be, for example, an N-channel enhancement-mode MOSFET. In the present embodiment, the voltage V s A source voltage is applied, and terminal 408 is a source terminal. In another embodiment, switch 402 can be an insulated-gate bipolar transistor (IGBT).

[0051] In the present embodiment, the switch 402 is coupled to a detection resistor 410 at terminal 408 and the switch 402 is coupled to an additional circuit 411 at terminal 412.

[0052] Fig. 4C is a diagram 414 showing waveforms associated with the operation of a practical implementation of the gate drive system 400. Fig. 4B are associated. In the present example, the waveforms are represented as time-varying voltages.

[0053] Line 416 is the control signal 404. In the present embodiment, the control signal is a PWM signal, which is a digital signal that switches between a first state and a second state. In this example, the first state is a high state and the second state is a low state. Examples of the high and low states are shown in Fig. Designated 4C.

[0054] Line 418 is the gate drive voltage signal Vg. In operation, the gate drive system 400 sets the gate drive voltage signal Vg to a first gate drive voltage Vg1 when the control signal 404 is in the first state, which is the high state, and sets the gate drive voltage signal Vg to a second gate drive voltage Vg2 when the control signal 404 is in the second state, which is the low state.

[0055] When the gate drive voltage Vg1 is applied to switch 402, switch 402 can be in a closed state (which can be referred to as the "on state") if current can flow through switch 402. When the gate drive voltage Vg2 is applied to switch 402, the switch can be in an open state (which can be referred to as the "off state") if no current can flow through switch 402.

[0056] In another embodiment, the gate control voltage Vg1 provided to the switch 402 can put the switch 402 into an open state, and the gate control voltage Vg2 provided to the switch 402 can put the switch 402 into a closed state.

[0057] In the present embodiment, the value of the first gate drive voltage Vg1 varies linearly. In further embodiments, the value of the first gate drive voltage Vg1 can vary non-linearly. In further embodiments, the value of the second gate drive voltage Vg2 can additionally or alternatively vary linearly or non-linearly.

[0058] Line 420 shows the change in source voltage Vs over time, and line 422 shows the change in gate-to-source voltage Vgs over time.

[0059] In the present embodiment, the gate drive system 400 is configured to set the gate drive voltage Vg1 using the detected voltage V s to adjust to maintain a substantially constant difference between the gate drive voltage Vg1 and the voltage V s to maintain the gate-source voltage while the control signal 404 is in the first state (the high state). The difference between Vg1 and Vs is the gate-source voltage Vgs while the control signal 404 is in the first state (high state).

[0060] In another embodiment, the gate drive system can be additionally or alternatively configured to adjust the gate drive voltage Vg2 using the detected voltage Vs in order to maintain a substantially constant difference between the gate drive voltage Vg2 and the voltage V2 while the control signal 404 is in the second state (the low state). The difference between Vg2 and Vs is the gate-source voltage Vgs while the control signal 404 is in the second state (the low state).

[0061] In further embodiments, the gate control system 400 can be configured to control Vgs to follow the desired waveforms, for example a constant difference between Vg and Vs; or other shapes to maintain the balance between R ds_on and to optimize EMI, etc.

[0062] It should be noted that embodiments of the Gate Drive System 400 may incorporate an adaptive MOSFET drive method to optimize MOSFET drive and maintain Vgs at its optimal value to balance efficiency and EMI behavior.

[0063] Exemplary embodiments of this disclosure allow the gate voltage Vg to follow the source voltage Vs during the conduction phase of the MOSFET 402 to ensure that the gate-source voltage Vgs remains at an optimized value. This helps to balance efficiency and EMI at a preset equilibrium value, thereby improving overall performance.

[0064] During the turn-on phase of the MOSFET 402, the gate voltage Vg can also follow the source voltage Vs, thus keeping the gate-source voltage Vgs stable and at a lower level to ensure efficient turn-off.

[0065] Fig. 5A is a schematic representation of a specific embodiment of the gate control system 400 from Fig. 4A according to a third embodiment of the present disclosure.

[0066] In the present embodiment, the gate drive system 400 comprises a gate drive circuit 500 configured to receive the control signal 404 and to supply the gate drive voltage signal Vg to the gate terminal 406 of the switch 402 to control the switching operation of the switch 402. In another embodiment, the switch 402 can be a MOSFET, for example as described in relation to Fig. 4B described. Furthermore, the switch 402 can be coupled with the detection resistor 410 and / or an additional circuit 411, as described in relation to Fig. 4B described.

[0067] The gate drive system 400 further includes a compensation circuit 502, which is configured to detect the voltage Vs and provide an adjustment signal 504 to the gate drive circuit 500. The adjustment signal 504 depends on the detected voltage Vs. In operation, the gate drive circuit 500 adjusts the gate drive voltage signal Vg based on the adjustment signal 504.

[0068] In a specific embodiment, the compensation circuit 502 can be configured to receive a supply voltage Vsupply1 and generate an adapted supply voltage Vsupply2, which depends on the voltage Vs and the received supply voltage Vsupply1, as detected.

[0069] The adaptation signal 504 can depend on the adapted supply voltage Vsupply2 and in a specific embodiment the adaptation signal 504 can be the adapted supply voltage Vsupply2.

[0070] In a specific embodiment, the gate drive voltage Vg1 can be provided using the adapted supply voltage Vsupply2 and can, for example, correspond to the adapted supply voltage Vsupply2. Alternatively or additionally, the gate drive voltage Vg2 can be provided using the adapted supply voltage Vsupply2 and can, for example, correspond to the adapted supply voltage Vsupply2. It should be noted that the add-in circuit is only one of many forms of compensation circuits.

[0071] Fig. Figure 5B is a schematic representation of the gate drive system 400 with a specific embodiment of the compensation circuit 502 according to a fourth embodiment of the present disclosure. In this embodiment, the compensation circuit 502 comprises an add-in circuit 506 configured to generate the adjusted supply voltage Vsupply2 by adding the supply voltage Vsupply1 and the voltage Vs.

[0072] Fig. Figure 5C is a schematic representation of the gate drive system 400 with a specific embodiment of the compensation circuit 502 according to a fifth embodiment of the present disclosure. In this embodiment, the add-in circuit 506 is configured to successively generate the adjusted supply voltage Vsupply2 during operation at discrete time intervals.

[0073] The in the Fig. 5B and Fig. The embodiments shown in 5C represent two approaches to compensating for Vg due to the change in Vs. In particular, the one shown in Fig. The embodiment shown in 5B is a linear approach and the one described in Fig. The embodiment shown in Figure 5C is a non-linear approach.

[0074] Fig. 6A is a diagram 600 showing waveforms associated with the operation of a practical implementation of the gate drive system 400. Fig. 5B is associated with the linear adaptive MOSFET drive approach using DCM. In the present example, the MOSFET 402 is part of a boost converter.

[0075] Shown are: the control signal 404, referred to as “PWM” (line 602), the drain current ID (line 604), the gate drive voltage signal Vg (line 606), the source voltage Vs (line 608) and the gate-source voltage Vgs (line 610).

[0076] Fig. Figure 6B is a diagram 611 showing waveforms associated with the operation of a practical implementation of the Gate Drive System 400. Fig. 5B is associated with the linear adaptive MOSFET drive approach using CCM. In the present example, the MOSFET 402 is part of a boost converter.

[0077] Shown are: the control signal 404, referred to as “PWM” (line 612), the drain current ID (line 614), the gate drive voltage signal Vg (line 616), the source voltage Vs (line 618) and the gate-source voltage Vgs (line 620).

[0078] Fig. 6C is a diagram 621 showing the waveforms that occur with the operation of a practical implementation of the Gate Drive System 400. Fig. 5B is associated with the non-linear adaptive MOSFET drive approach using DCM. In the present example, the MOSFET 402 is part of a boost converter.

[0079] Shown are: the control signal 404, referred to as “PWM” (line 622), the drain current ID (line 624), the gate drive voltage signal Vg (line 626), the source voltage Vs (line 628) and the gate source voltage Vgs (line 630).

[0080] Fig. 6D is a diagram 631 showing waveforms associated with the operation of a practical implementation of the Gate Drive System 400 by Fig. 5B is associated with the non-linear adaptive MOSFET drive approach using CCM. In the present example, the MOSFET 402 is part of a boost converter.

[0081] Shown are: the control signal 404, referred to as “PWM” (line 632), the drain current ID (line 634), the gate drive voltage signal Vg (line 636), the source voltage Vs (line 638) and the gate source voltage Vgs (line 640).

[0082] In the examples presented, the waveforms are represented as time-varying voltages. The drain current ID can alternatively be referred to as the "drive current".

[0083] The embodiment of the gate control system 400, which is in Fig. The linear compensation method shown in Figure 5B is used. In the present embodiment, the linear method is implemented using analog methods, for example, by an analog implementation of the add-in circuit 506. Other embodiments can be implemented digitally, for example, by a digital add-in circuit.

[0084] In one specific embodiment, the voltage level Vg corresponds to the voltage level at the power pin of the gate drive circuit 500.

[0085] The gate drive system 400 can be implemented as part of a control device 508 of a power converter, where the power converter in this example is a boost converter. When the control device 508 samples the Vs voltage for current sensing or protection purposes, it can use this available Vs voltage information to dynamically adjust the Vg voltage level in real time to achieve Vg = V(gs_desired) + Vs referenced to GND. V(gs_desired) is the target gate-source voltage Vgs with optimized switching.

[0086] Since the gate control system 400 can be implemented as part of the control device 508, costs and design size can be reduced compared to an embodiment that provides the gate control system 400 with external circuitry.

[0087] Fig. 6A and Fig. Figure 6B shows the waveforms of the adaptive MOSFET drive method. As shown in Fig. 6A and Fig. As shown in Figure 6B, the gate-source voltage remains constant close to an optimized value despite fluctuations in the source voltage Vs due to changes in the current ID. Exemplary embodiments of this disclosure, which implement the linearly according to the exemplary embodiment of Fig. Using 5B, a similar performance to the isolated control method according to Fig. 2B can be achieved, but without an additional isolated driver, which significantly simplifies integration into a chip.

[0088] The in Fig. The embodiment of the gate control system 400 shown in Figure 5C uses the non-linear compensation method. In this embodiment, the non-linear method is implemented using digital methods, for example, by a digital implementation of the add-in circuit 506. Other embodiments can be implemented using analog methods, for example, by using an analog add-in circuit.

[0089] In contrast to the linear method of Fig. 5B, which can compensate in real time, compensates for the non-linear method of Fig. 5C in N steps, where N is an integer greater than or equal to two. In operation, the add-in circuit 506 successively generates the adjusted supply voltage Vsupply2 in discrete time intervals. This results in the stepped waveform of the gate drive voltage signal Vg, as shown by lines 626 and 636. In the example waveforms of Fig. 6C and Fig. 6D is N equal to four.

[0090] The non-linear approach of Fig. 5C may be easier to implement digitally than with analog circuits and can be compared to the linear method of Fig. 5B leads to a reduced chip size and lower costs.

[0091] It should be noted that as N increases, the compensation effect comes closer to that of the linear approach, but this also requires more computing resources. Conversely, a smaller N results in less effective compensation compared to the linear approach, but consumes fewer computing resources. This is a trade-off, and in a specific implementation, N can be set as an adjustable parameter, allowing users to choose a suitable value based on their design requirements and the desired balance between performance and computing resources.

[0092] Fig. Figure 7 is a schematic representation of a device 700 according to a sixth embodiment of the present disclosure. The device 700 comprises the control device 702 for a power converter 704. The power converter 704 is a switching converter with one or more switches. In operation, the power converter 704 receives an input voltage Vin and generates an output voltage Vout. The power converter 704 can be, for example, a buck converter, a boost converter, or a buck-boost converter. The control device 702 can be configured to provide a discontinuous line mode (DCM) or a continuous line mode (CCM) for the power converter 704.

[0093] The control device 702 comprises the gate control system 400, which can be implemented with any of the embodiments of the gate control system 400 described herein. In the present embodiment, the switch 402 is one of the power switches of the power converter 704 and can be implemented with any of the embodiments of the switch 402 described herein. The gate control system 400 and the switch 402 function essentially as described above.

[0094] It is evident that in further embodiments the power converter 704 can comprise two or more circuit breakers, wherein the gate drive system 400 is configured to control the switching operation of each of the additional circuit breakers as described for the breaker 402, according to the understanding of those skilled in the art. In particular, the gate drive system 400 can be configured for each of the additional circuit breakers to provide a gate drive voltage signal to a gate terminal of the circuit breaker to control the switching operation of the circuit breaker, to detect a voltage at a terminal of the circuit breaker (e.g., the source voltage of the circuit breaker at its source terminal), and to adjust the gate drive voltage signal based on the detected voltage.

[0095] Exemplary embodiments of this disclosure provide a novel adaptive method for driving a MOSFET that overcomes the limitations of previous approaches. This method provides a cost-effective solution to compensate for the drop in gate-source voltage Vgs caused by an increase in MOSFET current, thereby avoiding the need for oversizing to account for worst-case scenarios, and thus reducing R dson and operational efficiency is optimized during the line phase.

[0096] Exemplary embodiments of the present disclosure can achieve an optimal balance between the known non-isolated method, which is described in Fig. 2A is shown, and the known isolated method described in Fig. As shown in 2B, the embodiments of this disclosure can provide a cost-effective solution to the problem of increased R dsondue to increasing electricity, thereby improving efficiency, power density and reliability.

[0097] Exemplary embodiments of the present disclosure provide a novel adaptive method for controlling the MOSFET, which applies a gate voltage V g It uses a method that dynamically tracks the source voltage (Vs) to compensate for fluctuations in Vs at different currents. This approach can ensure that Vgs remains consistently close to its optimized design value, thus enabling highly efficient operation of the MOSFET without increased costs or a larger design.

[0098] Exemplary embodiments of this disclosure provide adaptive control for power switches (such as silicon MOSFETs, SiC, GaN, IGBTs, etc.) that optimizes their performance without increasing cost or size. It improves the efficiency of silicon MOSFETs / SiC / GaN / IGBs, reduces heat generation, and lowers the cost and size requirements for heat sinks, thereby increasing the power density of the power supply.

[0099] The embodiments described in this disclosure need not be limited to a specific type of MOSFET and can, for example, be applied to MOSFETs such as silicon MOSFETs, SiC MOSFETs, or GaN MOSFETs. The embodiments described in this disclosure can also use IGBT transistors.

[0100] Exemplary embodiments of the present disclosure may provide a novel adaptive gate drive method for MOSFETs, specifically aimed at optimizing a gate voltage and improving overall performance in terms of efficiency and EMI without additional costs.

[0101] In summary, the proposed adaptive control method maintains V gs of the MOSFET close to its optimized design value, resulting in a balanced R dson This is achieved in addition to improvements in conduction loss, EMI behavior, and switching loss. It eliminates the need for an additional isolated MOSFET driver and can be easily integrated into an integrated circuit (IC), either using a linear or non-linear method, further reducing costs and increasing power density.

[0102] Various improvements and modifications to the above are possible without deviating from the scope of disclosure.

Claims

[1] A gate control system for controlling a switching operation of a first switch, wherein the gate control system is configured to: Receiving a control signal; Providing a gate drive voltage signal to a gate terminal of the first switch to control the switching operation of the first switch; Detection of an initial voltage at a first terminal of the first switch; and Adjusting the gate drive voltage signal based on the detected first voltage. [2] The gate control system according to claim 1, wherein the gate control system is configured to: Providing the gate drive voltage signal with a first gate drive voltage when the control signal is in a first state; and Providing a second gate drive voltage signal for the gate control signal when the control signal is in a second state. [3] The gate control system according to claim 2, wherein the gate control system is configured to: Adjusting the first gate drive voltage using the detected first voltage to maintain a substantially constant difference between the first gate drive voltage and the first voltage while the control signal is in the first state; and / or Adjusting the second gate drive voltage using the detected first voltage to maintain an essentially constant difference between the second gate drive voltage and the first voltage while the control signal is in the second state. [4] The gate control system according to any one of claims 1 to 3, wherein the first switch is coupled to a sensing resistor at the first terminal and / or the first switch is coupled to an additional circuit at a second terminal. [5] The gate control system according to any one of claims 1 to 4, further comprising: a gate drive circuit configured to: Receiving the control signal; and Providing the gate drive voltage signal to the gate terminal of the first switch to control the switching operation of the first switch; and a compensation circuit configured to: Detecting the first voltage at the first terminal of the first switch; and Providing an adaptation signal, dependent on the detected first voltage, to the gate drive circuit; wherein the gate drive circuit is configured to adjust the gate drive voltage signal based on the received matching signal. [6] The gate control system according to claim 5, wherein the compensation circuit is configured to: Receiving a supply voltage; and Generating an adapted supply voltage based on the detected first voltage, where the adaptation signal depends on the adapted supply voltage. [7] The gate control system according to claim 6, wherein the matching signal is the matched supply voltage. [8] The gate control system according to claim 7, wherein the gate control system is configured to: Providing the gate drive voltage signal with a first gate drive voltage when the control signal is in a first state; Providing the gate drive voltage signal with a second gate drive voltage when the control signal is in a second state; and Provide the first gate drive voltage using the adapted supply voltage, thereby adapting the gate drive voltage signal based on the first voltage; and / or the second gate drive voltage using the adapted supply voltage, thereby adapting the gate drive voltage signal based on the first voltage. [9] The gate drive system according to any one of claims 6 to 8, wherein the compensation circuit comprises an add-in circuit configured to generate the adjusted supply voltage by adding the supply voltage and the detected first voltage. [10] The gate control system according to claim 9, wherein the add circuit is configured to successively generate the adapted supply voltage at discrete time intervals during operation. [11] A device comprising: a control device for controlling a power converter for receiving an input voltage and generating an output voltage, wherein the power converter comprises one or more power switches; wherein the control device comprises a gate control system for controlling a switching operation of each of the one or more power switches, wherein the gate control system is configured to: Receiving a control signal; and for each of the one or more circuit breakers: Providing a gate control voltage signal to a gate terminal of the power switch to control the switching operation of the power switch; Detection of an initial voltage at a first terminal of the circuit breaker; and Adjusting the gate drive voltage signal based on the detected first voltage. [12] A method for controlling a switching operation of a first switch using a gate control system, the method comprising: Receiving a control signal; Providing a gate control voltage signal to a gate terminal of the first switch to control the switching operation of the first switch; Detection of an initial voltage at a first terminal of the first switch; and Adjusting the gate drive voltage signal based on the detected first voltage.

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