DISPLAY DEVICE

Abstract

A display device is provided that can minimize the threshold voltage deviation of a thin-film transistor according to a position in a display area using a hydrogen degassing path.The display device can include a display panel comprising a display area in which gate lines, data lines and thin-film transistors are arranged, and a first and a second enclosing area surrounding the display area, a gate drive circuit located in at least one of the first and the second enclosing area and configured to drive the gate lines, and placeholder holes arranged in at least one of the display area and the first and the second enclosing area, wherein each of the gate lines has a starting end connected to the gate drive circuit located in one of the first and the second enclosing area and an end located in the farther of the first and the second enclosing area, and the density of the placeholder holes varies according to the distance from the far end of each gate line.

Description

[0001] This application claims priority over Korean patent application No. 10-2024-0152428, filed in the Republic of Korea on October 31, 2024. BACKGROUND Area of ​​the invention

[0002] The disclosure relates to a display device that has a hydrogen degassing path. Discussion of the related field

[0003] A display device contains a thin-film transistor as a switching element and / or a control element.

[0004] An oxide semiconductor thin-film transistor, using an oxide semiconductor material as the active layer, is commonly used in display devices. Oxide semiconductor thin-film transistors offer advantages such as higher mobility compared to amorphous silicon thin-film transistors and lower manufacturing costs and lower out-current compared to polycrystalline silicon thin-film transistors.

[0005] However, the oxide semiconductor thin-film transistor is strongly affected by hydrogen flowing into the active layer. Such an increase in hydrogen in the active layer can change electrical properties such as the threshold voltage.

[0006] In the display device, the amount of hydrogen flow to one end compared to the starting end of a gate line can be increased due to a structural difference between the starting end of the gate line, which is in contact with a gate drive circuit in a mounting surface on one side, and the end of the gate line, which is not in contact with the gate drive circuit in a mounting surface on the other side.

[0007] Accordingly, as the gate line in the display device approaches its end relative to its starting point, the amount of hydrogen inflow increases, such that the threshold voltage of the thin-film transistor may be shifted in a negative direction. In the display device, a threshold voltage deviation of the thin-film transistor can occur due to a difference in the amount of hydrogen inflow, which depends on the distance from the end of the gate line. SUMMARY

[0008] Accordingly, the disclosure is aimed at providing a display device that essentially avoids one or more problems due to limitations and disadvantages of the related field.

[0009] One task is to provide a display device that can minimize the threshold voltage deviation of a thin-film transistor according to a position in a display area.

[0010] One task is to provide a display device that can prevent a threshold voltage of a thin-film transistor from being shifted in a negative direction in a display area.

[0011] The problem is solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0012] Additional advantages and features of the disclosure are partly set forth in the following description and partly become apparent to those skilled in the art upon study of the following or can be learned from practical application of the disclosure. The technical benefits and further advantages of the disclosure can be realized and achieved through the structure, which is shown in particular in the written description and its claims, as well as in the accompanying drawings.

[0013] The main idea to solve the tasks mentioned above is to use a hydrogen degassing pathway.

[0014] To achieve these and other benefits, and in accordance with the purpose of the disclosure embodied and roughly described herein, the disclosure provides a display device comprising a display panel, which includes a display area in which gate lines, data lines, and thin-film transistors are arranged, and a first and a second enclosure area surrounding the display area; a gate drive circuit located in at least one of the first and second enclosure areas and configured to drive the gate lines; and placeholder holes located in at least one of the display area and the first and second enclosure areas, each of the gate lines having a starting end connected to the gate drive circuit located in one of the first and second enclosure areas, and an end located in the other of the first and second enclosure areas.may contain and the density of placeholder holes may vary according to the distance from the end of each gate line.

[0015] In one or more embodiments, the display device may include placeholder electrodes, each of which is arranged in the placeholder holes.

[0016] In one or more embodiments, the density of the placeholder holes can be higher when the placeholder holes are closer to the end of each gate line, and can be lower when the placeholder holes are closer to the starting end of each gate line.

[0017] In one or more embodiments, the gate control circuit can be arranged in the first enclosing surface.

[0018] In one or more embodiments, the gate drive circuit can be connected to the starting end of each of the gate lines located in the first enclosing surface.

[0019] In one or more embodiments, the end of each of the gate lines can be arranged in the second enclosing surface.

[0020] In one or more embodiments, the gate drive circuit can include a first gate drive circuit and a second gate drive circuit arranged on opposite sides of the display area.

[0021] In one or more embodiments, the first gate drive circuit can be arranged in the first enclosing surface and can be connected to the starting end of each of the odd-numbered gate lines below the gate lines in the first enclosing surface.

[0022] In one or more embodiments, the second gate drive circuit can be arranged in the second enclosing surface and connected to the starting end of each of the even-numbered gate lines under the gate lines in the second enclosing surface.

[0023] In one or more embodiments, the end of each of the odd-numbered gate lines can be arranged in the second enclosing surface.

[0024] In one or more embodiments, the end of each of the even-numbered gate lines can be arranged in the first enclosing surface.

[0025] In one or more embodiments, the placeholder holes may include at least one of the following: a placeholder hole of the first type that overlaps with the end of each gate line, a placeholder hole of the second type that overlaps with each gate line, and a placeholder hole of the third type that overlaps with each data line.

[0026] In one or more embodiments, the placeholder electrodes may include at least one of the following: a first placeholder electrode arranged in the placeholder hole of the first type; a second placeholder electrode arranged in the placeholder hole of the second type; and a third placeholder electrode arranged in the placeholder hole of the third type.

[0027] In one or more embodiments, each of the first-type placeholder hole and the second-type placeholder hole can pass through multiple layers of insulation stacked on top of each gate line.

[0028] In one or more embodiments, each of the first placeholder electrode and the second placeholder electrode can be arranged on a topmost insulating layer beneath the multiple insulating layers stacked on each gate line and can contact the gate line through each of the first-type placeholder hole and the second-type placeholder hole, and can preferably be arranged directly on the topmost insulating layer.

[0029] In one or more embodiments, the first placeholder electrode and the second placeholder electrode can at least partially cover the uppermost insulation layer.

[0030] In one or more embodiments, the placeholder hole of the third type can pass through multiple layers of insulation stacked on top of each data line.

[0031] In one or more embodiments, the third placeholder electrode can be arranged on a top insulation layer beneath the multiple insulation layers stacked on each data line and can contact the data line through the third type placeholder hole.

[0032] In one or more embodiments, the placeholder electrodes can be arranged as the same transparent conductive layer on the same layer as a pixel electrode connected to the thin-film transistor.

[0033] In one or more embodiments, the placeholder holes may further include placeholder holes of the fourth type, which are arranged between the end of each gate line and the gate drive circuit in at least one of the first enclosing surface and the second enclosing surface.

[0034] In one or more embodiments, the placeholder electrodes may further include a fourth placeholder electrode arranged in the placeholder hole of the fourth type and / or at least a fifth placeholder electrode arranged below the placeholder hole of the fourth type.

[0035] In one or more embodiments, the placeholder hole of the fourth type can pass through several layers of insulation stacked on top of the at least one fifth placeholder electrode.

[0036] In one or more embodiments, the fourth placeholder electrode can be arranged on an uppermost insulating layer beneath the multiple insulating layers and contacts the at least one fifth placeholder electrode through the placeholder hole of the fourth type.

[0037] In one or more embodiments, the fourth placeholder electrode can be arranged as the same transparent conductive layer on the same layer as the pixel electrode, which is connected to the thin-film transistor.

[0038] In one or more embodiments, the at least one fifth placeholder electrode can be arranged as the same metal layer on the same layer as at least one electrode of the thin-film transistor.

[0039] In one or more embodiments, the thin-film transistor can include a light-shielding electrode arranged on a substrate.

[0040] In one or more embodiments, the thin-film transistor can include an active layer arranged such that it overlaps with the light-shielding electrode and a buffer layer between the light-shielding electrode and the active layer.

[0041] In one or more embodiments, the thin-film transistor can contain a gate electrode located between the active layer and a gate insulating layer.

[0042] In one or more embodiments, the thin-film transistor may include a first and a second source / drain electrode, each connected to a first and a second junction surface of the active layer by a first and a second contact hole in an insulating intermediate layer covering the gate insulating layer and the gate electrode.

[0043] In one or more embodiments, the at least one fifth placeholder electrode can include at least one light-shielding metal layer that is identical to the light-shielding electrode, one gate metal layer that is identical to the gate electrode, and one source / drain metal layer that is identical to the first and second source / drain electrodes.

[0044] In one or more embodiments, the at least one fifth placeholder electrode can contain a hydrogen absorption metal material that is included in at least one of the light shielding metal layer, the gate metal layer and the source / drain metal layer.

[0045] In one or more embodiments, the thin-film transistor may include a light-shielding electrode arranged on a substrate; an active layer overlapping the light-shielding electrode and a buffer layer between the light-shielding electrode and the active layer; a gate electrode arranged between the active layer and a gate isolation layer; and a first and a second source / drain electrode, each connected to a first and a second interface of the active layer by a first and a second contact hole in the gate isolation layer.

[0046] In one or more embodiments, the at least one fifth placeholder electrode can include at least one light-shielding metal layer that is identical to the light-shielding electrode, one gate metal layer that is identical to the gate electrode, and one source / drain metal layer that is identical to the first and second source / drain electrodes.

[0047] In one or more embodiments, the at least one fifth placeholder electrode can contain a hydrogen absorption metal material that is included in at least one of the light shielding metal layer, the gate metal layer and the source / drain metal layer.

[0048] In another aspect, a display device is provided comprising: a display panel containing a display area in which gate lines, data lines and thin-film transistors are arranged, and a first and a second enclosing area adjacent to the display area; a gate drive circuit located in at least one of the first and the second enclosing area and configured to drive the gate lines; and passivation holes located in at least one of the display area and the first and the second enclosing area, each of the gate lines having a starting end connected to the gate drive circuit located in one of the first and the second enclosing area, and an end located in the other of the first and the second enclosing area.

[0049] In one or more embodiments, the display device may further comprise at least one of the following: first passivation holes provided in an upper passivation layer in the display surface; and second passivation holes provided in the upper passivation layer located between the remote end of each gate line and the gate drive circuit in at least one of the first enclosing surface or the second enclosing surface.

[0050] In one or more embodiments, the display device may further comprise at least one of the following: sixth placeholder electrodes, each arranged in the first passivation holes; and seventh placeholder electrodes, each arranged in the second passivation holes.

[0051] In one or more embodiments, the first passivation holes can overlap or are adjacent to at least one of the gate line, the data line and the thin-film transistor.

[0052] In one or more embodiments, the display device may further comprise at least one of the following: an eighth placeholder electrode arranged below the first passivation hole and contacting the sixth placeholder electrode through the first passivation hole; and a ninth placeholder electrode arranged below the second passivation hole and contacting the seventh placeholder electrode through the second passivation hole.

[0053] In one or more embodiments, at least one of the sixth placeholder electrode or the seventh placeholder electrode can be arranged as the same transparent conductive layer on the same layer as the pixel electrode that is connected to the thin-film transistor.

[0054] In one or more embodiments, at least one of the eighth placeholder electrode or the ninth placeholder electrode can be arranged as the same transparent conductive layer on the same layer as a common electrode that overlaps between the pixel electrode and the upper passivation layer.

[0055] It is to be understood that both the preceding general description and the following detailed description of the revelation are exemplary and are intended to provide a further explanation of the revelation that is claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings, which are included to provide a better understanding of the revelation and form part of the application, illustrate embodiments of the revelation and, together with the description, serve to explain the principle of revelation. They show: Fig. 1 a schematic block diagram illustrating a display device of an embodiment of the disclosure; Fig. 2 a view illustrating a single-feed control method of a display device of an embodiment of the disclosure; Fig. 3 a view illustrating a nesting control method of a display device of an embodiment of the disclosure; Fig. 4 a graph illustrating a threshold voltage deviation of a thin-film transistor at a distance between a starting end and an end of a gate line in a display device according to a comparative example from the related field; Fig. 5A and Fig. 5B Graphs illustrating a voltage / current characteristic deviation of a thin-film transistor adjacent to a start end and a gate end in a display device of a comparative example from the related field; Fig. 6 a top view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device of an embodiment of the disclosure; Fig. Figure 7 shows a cross-sectional view illustrating a thin-film transistor, taken along line II', which is in Fig. 6 is shown; Fig. 8A and Fig. 8B Cross-sectional views illustrating a placeholder hole structure and along lines II-II' and III-III', which are shown in Fig. 6 are shown, were taken; Fig. 9A to Fig. 9F Cross-sectional views illustrating a placeholder hole structure, taken along a line IV-IV' which is in Fig. 6 is shown; Fig. 10 a graph illustrating a hydrogen production energy for each material used in a display device of an embodiment of the disclosure; Fig. 11 a view illustrating a hydrogen diffusion path of a thin-film transistor in a display device of an embodiment of the disclosure; Fig. 12 a view illustrating a hydrogen degassing path of a thin-film transistor of an embodiment of the disclosure; Fig. 13 a plan view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device according to an embodiment of the disclosure; Fig. 14A to Fig. 14F Cross-sectional views illustrating a passivation hole structure, taken along lines V-V', VI-VI', VII-VII' and VIII-VIII', which are in Fig. 13 are shown; Fig. 15A and Fig. 15B a top view and a cross-sectional view illustrating a thin-film transistor structure in a gate drive circuit of a display device of an embodiment of the disclosure; Fig. 16 a plan view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device of an embodiment of the disclosure; Fig. 17A to Fig. 17C Cross-sectional views showing a placeholder hole structure taken along line IX-IX' and a passivation hole structure taken along line X-X', which is in Fig. 16 is shown, was taken, illustrate; Fig. 18 a view illustrating a differential application structure of a placeholder hole density in a display device of an embodiment of the disclosure; Fig. 19A to Fig. 19C Top views showing a partial area of ​​each of the first to third surfaces, which are in Fig. The 18 shown illustrate; Fig. 20A a graph illustrating voltage / current characteristics of a thin-film transistor in a display device of a comparative example from the related field, and Fig. 20B and Fig. 20C Graphene illustrating the voltage / current characteristics of a thin-film transistor in a display device of an embodiment of the disclosure; and Fig. 21A and Fig. 21B Graphs illustrating the voltage / current characteristics of a thin-film transistor of a density of a placeholder hole in a display device of an embodiment of the disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0057] Advantages and features of the disclosure and its implementation methods are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the disclosure can be embodied in various forms and should not be interpreted as being limited to the embodiments presented here. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0058] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings to describe embodiments of the disclosure are merely examples, and thus the disclosure is not limited to the illustrated details. Similar reference numerals refer to similar elements throughout. In the following description, if it is determined that a precise description of the relevant known function or configuration would unnecessarily obscure the important point of the disclosure, the precise description will be omitted.

[0059] If terms like "comprise," "exhibit," and "contain," which are described in the revelation, are used, then a further part may also be present, unless "merely" is used. Singular terms may contain plural forms unless otherwise noted.

[0060] When an element is interpreted, the element is interpreted as if it contains an error area, even though there is no explicit description of it.

[0061] When describing a positional relationship, e.g., when a positional order is described as "on", "above", "below" and "next to", the case of no contact in between may be included unless "only" or "direct" is used.

[0062] When it is mentioned that a first element is positioned "at" a second element, this does not mean that the first element in the figure is essentially positioned above the second element. The upper and lower parts of an object in question can change depending on the object's orientation. Consequently, in the figure or in an actual configuration, the case in which a first element is positioned "at" a second element includes the case in which the first element is positioned "below" the second element, as well as the case in which the first element is positioned "above" the second element.

[0063] When describing a temporal relationship, e.g., when the temporal sequence is described as "after", "subsequent", "next" and "before", a case that is not continuous may be included unless "only" or "direct" is used.

[0064] It will be understood that, although the terms "first," "second," etc., can be used here to describe different elements, the elements should not be restricted by these terms. These terms are merely used to distinguish one element from another. For example, a first element could be called a second element, and conversely, a second element could be called a first element.

[0065] It is important to understand that the expression "at least one" includes all combinations that are related to any given element. For example, "at least one among a first element, a second element, and a third element" can include all combinations of two or more elements chosen from the first, second, and third elements, as well as each element of the first, second, and third elements.

[0066] Features of different embodiments of the disclosure can be partially or completely coupled or combined and can interact and be controlled in different ways. The embodiments of the disclosure can be implemented independently of one another or can be implemented together in a mutually dependent relationship.

[0067] The following describes the aspect of the disclosure with reference to accompanying drawings. Since, for the sake of simplicity, the scale of each element shown in the accompanying drawings differs from an actual scale, the disclosure is not limited to the scale shown. Furthermore, all components of each display device, indicator, and display panel of all aspects of the disclosure are functionally coupled and configured.

[0068] Fig. Figure 1 is a schematic block diagram illustrating a display device of an embodiment of the disclosure, Fig. 2 is a view illustrating a single-feed control method of a display device of an embodiment of the disclosure, and Fig. Figure 3 is a view illustrating a nesting control method of a display device of an embodiment of the disclosure.

[0069] With reference to Fig. 1. A display device 1000 may include a display panel 100, a gate control circuit 200, a data control circuit 300, a timing control unit 400, a level shifter 500 and the like, and the gate control circuit 200 may be embedded in the display panel 100.

[0070] The display device 1000 of an embodiment can be, but is not limited to, a liquid crystal display device. The display device 200 of an embodiment can be one of various display devices, including an electroluminescent display device, a micro-light-emitting diode display device (micro-LED display device), and the like. The electroluminescent display device can be an organic light-emitting diode display device (OLED display device), a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0071] The display panel 100 according to one embodiment can include a display area DA in which several subpixels SP are arranged in a matrix form, and a border area BZ that surrounds the display area DA. The display panel 100 according to one embodiment can further include a touch sensor that overlaps with the display area DA to detect a user's touch.

[0072] The display area DA of the scoreboard 100 can contain several pixels, each composed of three or four color subpixels that emit light of different colors, thereby displaying an image. The subpixels can include a red subpixel emitting red light, a green subpixel emitting green light, and a blue subpixel emitting blue light, and can further include a white subpixel emitting white light.

[0073] The display panel 100 according to one embodiment can be a liquid crystal panel. The display panel 100 can include a first and a second substrate connected to each other by a liquid crystal layer arranged between them, and a polarization plate attached to each of the outer surfaces of the first and second substrates. A thin-film transistor for the subpixels and various signal lines and electrodes, including the gate and data lines GL and DL connected to the thin-film transistor and a pixel electrode, can be arranged on the first substrate of the display panel 100. Drive circuits, including the gate drive circuit 200, can also be arranged on the first substrate of the display panel 100. A common electrode can be arranged on either the first or the second substrate of the display panel 100. A black matrix and a color filter for the subpixels can be arranged on either the first or the second substrate of the display panel 100.

[0074] In the display panel 100, the subpixels can be independently controlled by the thin-film transistor connected to the gate line GL and the data line DL. Each subpixel can charge a differential voltage between a data signal supplied to the pixel electrode via the thin-film transistor and a common voltage supplied to a common electrode. This charge drives a liquid crystal, thereby adjusting the transmission of the light passed from a backlight unit through the display panel 100 and the polarizing plate. Each subpixel can represent a grayscale of an image by multiplying the brightness of the backlight unit by the light transmission, which is controlled according to the data signal in each subpixel.

[0075] The display panel 100 can be driven in a twisted nominal mode (TN mode) or a vertical alignment mode (VA mode) by a vertical electric field applied to the liquid crystal layer through the pixel electrode and the common electrode, can be driven in an in-plane switching mode (IPS mode) by a horizontal electric field applied to the liquid crystal layer via the pixel electrode and the common electrode, or can be driven in a perimeter field switching mode (FFS mode) by a perimeter electric field applied to the liquid crystal layer through the pixel electrode and the common electrode.

[0076] Several thin-film transistors arranged in the display area DA of the display panel 100 and the enclosure area BZ, which contains the gate drive circuit 200, can include at least one amorphous silicon thin-film transistor, a polycrystalline silicon thin-film transistor, or an oxide semiconductor thin-film transistor. According to one embodiment, the display panel 100 can contain a coplanar oxide semiconductor thin-film transistor.

[0077] The display panel 100 according to one embodiment can include a signal line containing a gate line GL and a data line DL, and / or a hydrogen degassing path (a placeholder hole, a passivation hole) arranged on at least one insulating layer that overlaps with or is adjacent to the thin-film transistor. The display panel 100 according to one embodiment can differentially apply the density of the hydrogen degassing path, which is arranged in one direction of the gate line GL, depending on the distance from the end of the gate line GL.Accordingly, the indicator panel 100 can minimize a difference in the amount of hydrogen inflow due to a structural difference between a starting end and an end of the gate line GL, thereby minimizing a threshold voltage deviation of the thin-film transistor and preventing the thin-film transistor's threshold voltage from being shifted to a negative voltage. This is described in detail below.

[0078] The gate driver circuit 200 can be located in one of the two facing enclosure surfaces BZ, with the display surface DA in the display panel 100 positioned between them, or it can be located in both enclosure surfaces BZ. The gate driver circuit 200 can be embedded in the enclosure surface BZ in a gate-in-panel (GIP) type, which contains thin-film transistors formed in the same process as the thin-film transistor in the display surface DA.

[0079] The gate control circuit 200 can operate by receiving multiple gate control signals supplied by the timing control unit 400 via the level shifter 500. The gate control circuit 200 can receive these multiple gate control signals from the timing control unit 400. It can be controlled by these multiple gate control signals and can individually control the gate lines GLs of the display panel 100. During an active period for each gate line GL, the gate control circuit 200 can output a sampled gate-on voltage signal to the corresponding gate line GL, and during an inactive period for each gate line GL, it can output a gate-off voltage to the corresponding gate line GL.

[0080] The level shifter 500 can generate multiple gate control signals by receiving control signals from the timing control unit 400 and level shifting or logic processing of the control signals, and output the gate control signals to the gate drive circuit 200.

[0081] The data control circuit 300 can convert digital data, supplied along with the data control signals from the timing control unit 400, into an analog data signal in order to supply the data signal to the data line DL of the display panel 100. The data control circuit 300 can divide several reference gamma voltages supplied by a gamma voltage generator and can convert the digital data into an analog data voltage using the divided gamma voltages.

[0082] The data control circuit 300 can contain at least one integrated data driver circuit (data driver IC). The data driver IC can be mounted on the mounting surface BZ of the display panel 100 or encapsulated in a thin circuit layer and thus electrically connected to the display panel 100.

[0083] The 400 timing control unit can receive source image data and timing signals from an external host system. The host system can be a portable device such as a computer, television, set-top box, tablet, or mobile phone. The timing signals can include a pixel clock, data activation signal, vertical synchronization signal, horizontal synchronization signal, and the like.

[0084] The timing control unit 400 can control the gate drive circuit 200 and the data drive circuit 300 using timing control signals supplied by the host system and timing setting information stored therein. The timing control unit 400 can generate multiple gate control signals to control a timing sequence of the gate drive circuit 200 and output the generated gate control signals to the gate drive circuit 200. According to one embodiment, the timing control unit 400 can generate timing control signals such that the level shifter 500 can generate multiple gate control signals to supply the gate control signals to the gate drive circuit 200 and can output the control signals to the level shifter 500.The timing control unit 400 can generate multiple data control signals for controlling the timing of the data control circuit 300 and output the generated data control signals to the data control circuit 300.

[0085] The timing control unit 400 can perform various image processing operations, including luminance correction, to reduce power consumption using input image data and can output the processed image data to the data control circuit 300. The timing control unit 400 can align the processed image data so that it is suitable for the subpixel arrangement of the display panel 100 and output the aligned data to the data control circuit 300.

[0086] The gate drive circuit 200 according to one embodiment can supply a sampling signal to both ends of each gate line GL in a dual-feed mode, or it can supply a sampling signal to a starting end of each gate line GL in a single-feed mode. The gate drive circuit 200 according to one embodiment can supply the sampling signal to the starting end of the gate line GL, which is driven section by section by a nested sampling mode in a single-feed mode.

[0087] With reference to Fig. 2. According to one embodiment, the gate control circuit 200 can comprise several step circuits GIP1 to GIPn, which are arranged in a first enclosing area BZ1 of the display panel 100 and are individually connected to the multiple gate lines GL1 to GLn of the display area DA. The multiple step circuits GIP1 to GIPn can sequentially supply sampling signals to the starting end of each of the gate lines GL1 to GLn in a single-signal manner. The end of each of the gate lines GL1 to GLn can be located in the second enclosing area BZ2.

[0088] With reference to Fig. 3. According to one embodiment, the gate control circuit can comprise a first and a second gate control circuit 200a and 200b, which are arranged compartmentally in both enclosing surfaces BZ1 and BZ2, with the display area DA in the display panel 100a located between them. The first gate control circuit 200a, which is arranged in the left enclosing surface BZ1 (the first enclosing surface), can comprise several odd-numbered step circuits GIP1, GIP3, ... GIPn-1, which are individually connected to the starting ends of the odd-numbered gate lines GL1, GL3, ... GLn-1. The second gate drive circuit 200b, located in the right-hand border area BZ2 (the second border area), can contain several even-numbered step circuits GIP2, GIP4, ... GIPn, which are individually connected to the starting ends of the even-numbered gate lines GL2, GL4, ... GLn. The end of each of the even-numbered gate lines GL2, GL4, ...GLn can be located in the left boundary area BZ1 (the first boundary area).

[0089] The step-down circuits GIP1, GIP3, ... GIPn-1 of the first gate drive circuit 200a according to one embodiment can sequentially supply the sampling signals to the left starting end of each of the odd-numbered gate lines GL1, GL3, ... GLn-1 in a single-signal manner. The step-down circuits GIP2, GIP4, ... GIPn of the second gate drive circuit 200b according to one embodiment can sequentially supply the sampling signals to the right starting end of each of the even-numbered gate lines GL2, GL4, ... GLn in a single-signal manner.Each of the gate lines GL1 to GLn in the display panels 100 and 100a according to one embodiment can have a structural difference such that a starting end located in one of the first and second enclosing surfaces BZ1 and BZ2 is connected to and in contact with one of the gate drive circuits 200, 200a, and 200b, whereas an end of the other end located in the first and second enclosing surfaces BZ1 and BZ2 is not in contact with the gate drive circuits 200, 200a, and 200b. The display panels 100 and 100a according to one embodiment can include a placeholder hole that overlaps with or is adjacent to the thin-film transistor and / or the signal line in the display surface DA and the enclosing surfaces BZ1 and BZ2 to serve as a hydrogen degassing path, thereby enhancing the hydrogen degassing effect.The display panels 100 and 100a according to one embodiment can apply the density of the placeholder hole differentially depending on the distance from the end of each gate line GL.

[0090] Accordingly, the display panel 100, according to one embodiment, can prevent the threshold voltage of the thin-film transistor from being shifted towards the negative voltage, and minimize the threshold voltage deviation of the thin-film transistor by minimizing the difference in hydrogen inflow due to the structural difference between the start end and the end of each gate line GL.

[0091] Fig. Figure 4 is a graph illustrating the threshold voltage deviation of a thin-film transistor as a function of the distance between a starting end and an end of a gate line in a display device, according to a comparative example from the related field, and Fig. 5A and Fig. Figure 5B are graphs illustrating a voltage / current characteristic deviation of a thin-film transistor adjacent to a start end and a gate end in a display device according to a comparative example from the related field.

[0092] With reference to Fig. 4. A display area DAa of the display device according to the comparative example can be controlled in a nested manner, such that an odd-numbered gate line GLo can be controlled by a left-gate drive circuit 20a and an even-numbered gate line GLe can be controlled by a right-gate drive circuit 20b. In the display device according to the comparative example, it should be noted that a threshold voltage Vth of a thin-film transistor is shifted in a negative direction from a starting position GLo-Start to an end position Glo-End of the odd-numbered gate line, which is connected to the left-gate drive circuit 20a.In the display device according to the comparative example, it should be noted that the threshold voltage Vth of the thin-film transistor is shifted in a negative direction from a starting position GLe-start to an end position GLe-end of the even-numbered gate line, which is connected to the right gate drive circuit 20b.

[0093] With reference to Fig. 4 and Fig. 5A is to be recorded in the display area DAa of the display device of the comparative example of the related area, that the threshold voltage Vth of the thin-film transistor adjacent to the starters GLo-start and GLe-start of each gate line in contact with the gate drive circuits 20a and 20b is a voltage close to 0 V.

[0094] With reference to Fig. 4 and Fig. 5B is to be recorded in the display area DAa of the display device according to the comparative example of the related field, that the thin-film transistor adjacent to the ends GLo-end and GLe-end of each gate line not in contact with the gate drive circuits 20a and 20b increases the amount of hydrogen inflow such that the threshold voltage Vth is excessively shifted in the negative direction, resulting in a difference of the threshold voltage Vth of the thin-film transistor at the starting ends GLo-start and GLe-start.

[0095] That is, as in Fig. As shown in Figure 4, the voltage threshold starts at zero in the enclosure area and then becomes negative when the gate line crosses the display area DAa, ultimately reaching a negative Vth of -6 V or more. Thus, as shown, the voltage threshold changes or varies significantly when the gate line crosses the display area. As in Fig. As shown in Figure 4, the transistor's voltage threshold remains a negative value of approximately 6.5 V from the center of the display area to the mounting areas 20a and 20b. This varying negative voltage threshold affects the transistor's characteristics (e.g., the voltage threshold). As shown in Fig. As shown in Figure 4, the effect is greatest when the gate line extends across the display area to the bezel area (e.g., in the range of 1 inch to 13 inches). Fig. 4) extends. Furthermore, it varies as described in Fig. As shown in Figure 4, the voltage threshold varies significantly between 1 inch and 6 inches, then settles at a voltage threshold of -6.5. This varying voltage-gate threshold negatively affects the operation of the transistors.

[0096] To solve this problem, the display panels 100 and 100a of an embodiment of the disclosure can include placeholder holes that serve as a hydrogen degassing path to enhance the hydrogen degassing effect. The display panels 100 and 100a of an embodiment of the disclosure can minimize the difference in hydrogen inflow by differentially applying the density of the placeholder holes according to the distance from the far end of the gate line GL, thereby minimizing the threshold voltage deviation of the thin-film transistor.

[0097] The following describes in detail the display device which has a hydrogen degassing path of an embodiment of the disclosure.

[0098] Fig. Figure 6 is a top view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device, according to an embodiment of the disclosure. Fig. Figure 7 is a cross-sectional view illustrating a thin-film transistor and along the line I-I', which is shown in Fig. 6 is shown, was taken, Fig. 8A and Fig. Figure 8B shows cross-sectional views illustrating a placeholder hole structure along lines II-II' and III-III', which are shown in Fig. 6 are shown, were taken, and Fig. 9A to Fig. 9F are cross-sectional views illustrating a placeholder hole structure along a line IV-IV' that is in Fig. 6 is shown, were taken.

[0099] With reference to Fig. 6 and Fig. 7. According to one embodiment, the display device may include a gate line GL: GLi and GL(i + 1), a data line DL, a thin-film transistor TFT, a common electrode VCOM, a pixel electrode PXL, a common power supply line VL, and a thin-film transistor substrate on which several insulating layers are arranged. The several insulating layers may include a buffer layer BF, a gate insulating layer GI, intermediate insulating layers ILD1 and ILD2, passivation layers PAS1 and PAS2, and a planarization layer PNL.

[0100] The gate line GL can be arranged in a first direction (a horizontal direction or a row direction), and the data line DL can be arranged in a second direction (a vertical direction or a column direction) and can cross the gate line GL, with the insulating intermediate layers ILD1 and ILD2 positioned between them. The thin-film transistor TFT can be positioned adjacent to the intersection of the gate line GL and the data line DL, and thus be connected to the gate line GL and the data line DL, and can be connected to the pixel electrode PXL, which is located in the pixel area.

[0101] The thin-film transistor TFT according to one embodiment can include a light-shielding electrode LS on the substrate SUB, a buffer layer BF covering the light-shielding electrode LS, an active layer ACT on the buffer layer BF, a gate-insulating layer GI and a gate electrode GE stacked on the active layer ACT, insulating intermediate layers ILD1 and ILD2 covering the gate electrode GE, and a first and a second source / drain electrode SD1 and SD2, respectively, arranged on the insulating intermediate layer ILD2 and connected to the active layer ACT by contact holes CH1 and CH2. The thin-film transistor TFT according to one embodiment can have a coplanar structure.

[0102] The light shielding electrode LS can be arranged on the substrate SUB and the buffer layer BF, which covers the light shielding electrode LS, can be arranged.

[0103] The substrate SUB can be a glass substrate or a plastic substrate.

[0104] The light-shielding electrode LS can protect a channel area of ​​the active layer ACT by shielding light incident through the substrate SUB. The light-shielding electrode LS can be formed from a light-shielding metal layer exhibiting light-shielding characteristics. For example, the light-shielding metal layer can have a single-layer structure containing at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and their alloys, or it can have a multi-layer structure in which at least two metal layers are stacked. The light-shielding electrode LS can be connected to the gate electrode GE via a contact hole CH4 to function as a double gate. A common electrode supply line VL can be formed as a light-shielding metal layer by the same process as the light-shielding electrode LS.

[0105] The buffer layer BF can prevent impurities such as hydrogen from flowing through the substrate SUB into the active layer ACT. The buffer layer BF can contain an inorganic insulating material with a low hydrogen concentration. For example, the buffer layer BF can contain an oxide-based insulating material such as silicon dioxide (SiOx) or aluminum oxide (Al₂O₃), which has a lower hydrogen content.

[0106] The active layer ACT can be arranged on the buffer layer BF, the gate isolation layer GI and the gate electrode GE can be arranged on the channel surface CA of the active layer ACT to overlap with each other, and the gate electrode GE can be formed as one piece with the gate conductor GL.

[0107] The active layer ACT can contain an oxide semiconductor material. For example, the active layer ACT can contain at least one IGZO(InGaZnO)-based, IGO(InGaO)-based, IGZTO(InGaZnSnO)-based, GZTO(GaZnSnO)-based, GZO(GaZnO)-based, Go(GaO)-based, TO(SnO)-based, ITO(InSnO)-based, ITZO(InSnZnO)-based, IZO(InZnO)-based, ZO(ZnO)-based, IO(InO)-based, InO(InO)-based, ZnO-based, and FIZO-based oxide semiconductor material. The active layer ACT can have a single-layer structure or a multi-layer structure in which at least two oxide semiconductor layers are stacked.

[0108] The active layer ACT can include a channel area CA exhibiting semiconductor characteristics and a first interconnection area SA1 and a second interconnection area SA2, which are connected to both sides of the channel area CA and made conductive. According to one embodiment, the first interconnection area SA1 and the second interconnection area SA2 of the active layer ACT can be conductive surfaces doped with a dopant by ion implantation. For example, the dopant can contain at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). According to another embodiment, the first interconnection area SA1 and the second interconnection area SA2 of the active layer ACT can be conductive surfaces made conductive by dry etching or plasma treatment when the gate insulating layer GI and the gate electrode GE are patterned.

[0109] The gate insulation layer GI can be patterned in the same shape as the gate electrode GE and the gate conductor GL on the gate insulation layer GI.

[0110] The gate insulating layer GI can contain an inorganic insulating material with a low hydrogen concentration. For example, the gate insulating layer GI can contain at least one of silicon dioxide (SiOx), aluminum oxide (Al2O3), hafnium oxide (HfOx), and zirconium oxide (ZrOx).

[0111] The gate electrode GE can overlap with the channel area CA of the active layer ACT and can overlap with the light-shielding electrode LS. The gate electrode GE can be formed from a gate metal layer together with the gate conductor GL and can be integrally formed with the gate conductor GL. The gate electrode GE can be contained as a section of the gate conductor GL or can have a shape that projects from the gate conductor GL in the second direction. The gate electrode GE can be connected to the light-shielding electrode LS by a contact hole CH4 that passes through the gate insulating layer GI and the buffer layer BF. The gate metal layer can have a single-layer structure containing at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag), and their alloys, or it can have a multi-layer structure in which at least two metal layers are stacked.

[0112] The insulating layers ILD: ILD1 and ILD2, which cover the active layer ACT, the gate insulating layer GI, the gate electrode GE, and the gate conductor GL can be arranged on the buffer layer BF. The insulating layer ILD can contain an inorganic insulating material. The insulating layer ILD can have a single-layer structure or a multi-layer structure containing at least one silicon dioxide (SiOx) and one silicon nitride (SiNx). For example, the insulating layer ILD can have a multi-layer structure in which a first insulating layer ILD1, containing silicon dioxide (SiOx) with a low hydrogen concentration, and a second insulating layer ILD2, containing silicon nitride (SiNx) with a higher hydrogen concentration than the first insulating layer ILD1, are stacked.

[0113] A first source / drain electrode SD1 and a second source / drain electrode SD2 can be arranged together with the data line DL on the insulating layer ILD2. The first source / drain electrode SD1 can be connected to the first junction SA1 of the active layer ACT through the contact hole CH1, which passes through the insulating layers ILD2 and ILD1, and can be connected to the data line DL or formed as a single unit. The second source / drain electrode SD2 can be connected to the second junction SA2 of the active layer ACT through the contact hole CH2, which passes through the insulating layers ILD2 and ILD1. The second source / drain electrode SD2 can be connected to the pixel electrode PXL through a contact hole CH3. The first and second source / drain electrodes SD1 and SD2 and the data line DL can be formed as a single source / drain metal layer.For example, the source / drain metal layer may have a single-layer structure containing at least one of aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), copper (Cu), gold (Au), silver (Ag) and their alloys, or it may have a multi-layer structure in which at least two metal layers are stacked.

[0114] The first passivation layer PAS1, which covers the source / drain electrodes SD1 and SD2 and the data line DL, can be located on the insulating intermediate layer ILD2, and the planarization layer PNL can be located on the first passivation layer PAS1. The common electrode VCOM can be located on the planarization layer PNL, and the second passivation layer PAS2, which covers the common electrode VCOM, can be located there. The pixel electrode PXL can be located on the second passivation layer PAS2.

[0115] The first passivation layer PAS1 and the second passivation layer PAS2 can contain an inorganic insulating material, and the planarization layer PNL can contain an organic insulating material. For example, the first passivation layer PAS1 can contain silicon dioxide (SiOx), which has a low hydrogen concentration, and the second passivation layer PAS2 can contain silicon nitride (SiNx), which has a higher hydrogen concentration than the first passivation layer PAS1. The planarization layer PNL can contain at least one organic insulating material consisting of an acrylic-based resin, an epoxy-based resin, a siloxane-based resin, a polyimide-based resin, and a polyamide-based resin.

[0116] Any of the pixel electrodes PX, which are arranged in the pixel area, and the common electrode COM can contain multiple slits that overlap with the other electrode, and a surrounding electric field can be applied to the liquid crystal layer such that the liquid crystal layer can be driven in an FFS mode. The pixel electrode PX and the common electrode VCOM can be formed from a transparent conductive layer. For example, the transparent conductive layer can contain one of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0117] The common electrode VCOM can overlap with the gate line GL, with the multiple insulation layers ILD1, ILD2, PAS1, and PNL positioned between them, and can overlap with the data line DL, with the multiple insulation layers PAS1 and PNL positioned between them. The common electrode VCOM can also serve as a contact electrode.

[0118] The pixel electrode PXL can be connected to the second source / drain electrode SD2 of the thin-film transistor TFT through the contact hole CH3, which passes through the second passivation layer PAS2, the planarization layer PNL and the first passivation layer PAS1.

[0119] The gate lines GLi and GL(i + 1) can be driven individually or in a nested manner. For example, one gate line GLi of the gate lines GLi and GL(i + 1) can be driven by the second gate drive circuit 200b ( Fig. 3), which is located in the right-hand border area, can be connected and can connect the further gate line GL(i + 1) to the first gate drive circuit 200a ( Fig. 3), which is located in the left border area. The thin-film transistors TFT, each connected to the adjacent gate lines GLi and GL(i + 1), can run between the adjacent gate lines GLi and GL(i + 1) and can be connected to the pixel electrodes PXL, which run between the adjacent gate lines GLi and GL(i + 1).

[0120] Each of the gate lines GLi and GL(i + 1), which are driven by a single feed or a nested feed, can have a starting end connected to the gate drive circuit ( Fig. 2: 200 or Fig. 3: 200a or 200b) is in contact in a mounting surface, and one end is connected to the gate drive circuit ( Fig. 2 is: 200 or 3: 200a or 200b) is not in contact with the further edging area, included.

[0121] The display device according to one embodiment can include a placeholder hole DH1 of the first type, which is arranged at the end of the gate lines GLi and GL(i + 1) and is used as a hydrogen degassing path.

[0122] The display device according to one embodiment may further include at least one placeholder hole DH2 of the second type, which is arranged on a signal line adjacent to the thin-film transistor TFT in the display area, i.e. the gate lines GLi and GL(i + 1), and one placeholder hole DH3 of the third type, which is arranged on the data line DL.

[0123] The display device according to one embodiment can further include several placeholder holes of the fourth type, DH4, which are arranged adjacent to the ends of the gate lines GLi and GL(i + 1) in the enclosing area between the ends of the gate lines GLi and GL(i + 1) and the gate control circuit.

[0124] The display device according to one embodiment can further include placeholder electrodes DM1, DM2, DM3 and DM4, which are arranged in the placeholder holes DH1, DH2, DH3 and DH4, respectively. The placeholder electrodes DM1, DM2, DM3 and DM4 can protect the signal lines GL and DL, which are exposed through the placeholder holes DH1, DH2, DH3 and DH4.

[0125] According to one embodiment, the placeholder holes DH1, DH2, DH3, and DH4, together with the contact holes CH2 and CH3 of the thin-film transistor TFT, can be used as hydrogen degassing paths through which hydrogen (H) contained in multiple layers diffuses and is degassed in a heat treatment process, thereby increasing hydrogen degassing. The placeholder holes DH1, DH2, DH3, and DH4, located at the ends of the gate leads GLi and GL(i+1) and adjacent areas, can enhance the degassing of hydrogen (H) flowing through the ends of the gate leads GLi and GL(i+1) and the gate insulating layer GI.

[0126] Accordingly, in one embodiment of the display device, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the hydrogen effect on the thin-film transistor TFT, thereby preventing or minimizing the change in the threshold voltage Vth.

[0127] In the display device according to one embodiment, since the placeholder holes DH1, DH2, DH3 and DH4 are closer to the ends of the gate lines GLi and GL(i + 1), the number and density of the placeholder holes DH1, DH2, DH3 and DH4 can be increased to minimize the difference in hydrogen flow according to the distance from the ends of the gate lines GLi and GL(i + 1).

[0128] Accordingly, according to one embodiment, the display device can minimize the deviation of the threshold voltage Vth of the thin-film transistor TFT according to the distance from the remote ends of the gate lines GLi and GL(i + 1).

[0129] With reference to Fig. 8A The placeholder hole DH1 of the first type according to one embodiment can pass through the multiple insulating layers stacked on the gate line GL to expose the end of the gate line GL. The placeholder hole DH2 of the second type according to one embodiment can be arranged on the gate line GL in the same structure as the placeholder hole DH1 of the first type. The placeholder holes DH1 and DH2 of the first and second types can have a structure that passes through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2 on the gate line GL. The indicator device according to one embodiment can further include placeholder electrodes DM1 and DM2, respectively, arranged in the placeholder holes DH1 and DH2 of the first and second types to contact the gate line GL.The placeholder electrodes DM1 and DM2 can be arranged on the second passivation layer PAS2 and can be in contact with the gate line GL via the placeholder holes DH1 and DH2 of the first and second types, respectively. The placeholder electrodes DM1 and DM2 can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL and can protect the gate line GL, which is exposed through the placeholder holes DH1 and DH2.

[0130] With reference to Fig. According to one embodiment, the third-type placeholder hole DH3 can pass through the multiple insulation layers stacked on the data line DL to expose the data line DL. The third-type placeholder hole DH3 can have a structure that passes through the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2 on the data line DL. The indicator device according to one embodiment can further include a placeholder electrode DM3 arranged in the third-type placeholder hole DH3 to contact the data line DL. The placeholder electrode DM3 can be located on the second passivation layer PAS2 and can be in contact with the data line DL via the third-type placeholder hole DH3.The placeholder electrode DM3 can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL and can protect the data line DL exposed through the placeholder holes DH1 and DH2.

[0131] In the display device according to one embodiment, the multiple placeholder holes DH4 of the fourth type, which are arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i + 1), can be one of various structures such as the placeholder holes DH41 to DH46 of the (4-1)th to (4-6)th type, which are in Fig. 9A to Fig. 9F are shown.

[0132] With reference to Fig. 9A According to one embodiment, the indicator device may include a placeholder hole DH41 of type (4-1) arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i+1), and several placeholder electrodes DM41a and DM41b that are in contact with each other through the placeholder hole DH41 of type (4-1). The several placeholder electrodes DM41a and DM41b may have a structure set to an electrically floating potential.

[0133] The placeholder hole DH41 of the (4-1)th type can have a structure that passes through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2 in the same way as the placeholder holes DH1 and DH2 of the first and second types on the gate line GL.

[0134] The placeholder electrode DM41a, located at the gate insulating layer GI, can be formed from the same gate metal layer in the same process as the gate conductor GL. The placeholder electrode DM41b, located at the second passivation layer PAS2 and passing through the (4-1)-type placeholder hole DH41, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL, to protect the placeholder electrode DM41a exposed through the (4-1)-type placeholder hole DH41. With reference to Fig. 9B, the indicator device according to one embodiment may include a placeholder hole DH42 of type (4-2) arranged in the enclosing surface adjacent to the remote end of the gate lines GLi and GL(i + 1), and several placeholder electrodes DM42a and DM42b that are in contact with each other through the placeholder hole DH42 of type (4-2). The several placeholder electrodes DM42a and DM42b may have a structure set to an electrically floating potential.

[0135] The placeholder hole DH42 of the (4-2)th type can have a structure passing through the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2 in the same way as the third placeholder hole DH3 on the data line DL1.

[0136] The placeholder electrode DM42a, located on the insulating intermediate layer ILD2, can be formed from the same source / drain metal layer in the same process as the data line DL. The placeholder electrode DM42b, located in the second passivation layer PAS2 and passing through the (4-2) type placeholder hole DH42, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL, in order to protect the placeholder electrode DM42a, which is exposed through the (4-1) type placeholder hole DH42.

[0137] With reference to Fig. According to one embodiment, the indicator device 9C can include a placeholder hole DH43 of type (4-3) arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i + 1), and several placeholder electrodes DM43a and DM43b that are in contact with each other through the placeholder hole DH43 of type (4-3). The several placeholder electrodes DM43a and DM43b can have a structure set to an electrically floating potential.

[0138] The placeholder hole DH43 of the (4-3)th type can have a structure passing through the buffer layer BF, the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2, which are stacked on the substrate SUB.

[0139] The placeholder electrode DM43a, located on the substrate SUB, can be formed from the same light-shielding metal layer in the same process as the light-shielding electrode LS. The placeholder electrode DM43b, located on the second passivation layer PAS2 and passing through the (4-3) type placeholder hole DH43, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL, in order to protect the placeholder electrode DM43a exposed through the (4-3) type placeholder hole DH43.

[0140] With reference to Fig. 9D, the display device according to one embodiment can include a placeholder hole DH44 of type (4-4) arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i + 1), and several placeholder electrodes DM44a, DM44b, and DM44c that are in contact with each other through the placeholder hole DH44 of type (4-4). The several placeholder electrodes DM44a, DM44b, and DM44c can have a structure set to an electrically floating potential.

[0141] The placeholder hole DH44 of the (4-4)th type can have a structure passing through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2.

[0142] The placeholder electrode DM44a, located on the substrate SUB, can be formed from the same light-shielding metal layer in the same process as the light-shielding electrode LS. The placeholder electrode DM44b, located on the gate insulating layer GI, can be formed from the same gate metal layer in the same process as the gate conductor GL and can be in contact with the placeholder electrode DM44a through a contact hole passing through the gate insulating layer GI and the buffer layer BF. The placeholder electrode DM44c, located on the second passivation layer PAS2 and passing through the (4-4)-type placeholder hole DH44, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to shield the placeholder electrode DM44b through the (4-4)-type placeholder hole DH44.

[0143] With reference to Fig. 9E The display device according to one embodiment can include a placeholder hole DH45 of type (4-5) arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i + 1), and several placeholder electrodes DM45a, DM45b and DM45c which are in contact with each other through the placeholder hole DH45 of type (4-5). The several placeholder electrodes DM45a, DM45b and DM45c can have a structure set to an electrically floating potential.

[0144] The placeholder hole DH45 of the (4-5)th type can have a structure passing through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2.

[0145] The placeholder electrode DM45a, located at the gate insulating layer GI, can be formed from the same gate metal layer in the same process as the gate line GL. The placeholder electrode DM45b, located at the second insulating layer ILD2, can be formed from the same source / drain metal layer in the same process as the data line DL and can be in contact with the placeholder electrode DM45a through a contact hole that passes through the insulating layers ILD2 and ILD1. The placeholder electrode DM45c, located at the second passivation layer PAS2 and passing through the (4-5) type placeholder hole DH45, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to protect the placeholder electrode DM45b, which is exposed through the (4-5) type placeholder hole DH45.

[0146] With reference to Fig. According to one embodiment, the indicator device 9F can include a placeholder hole DH46 of type (4-6) arranged in the enclosing surface adjacent to the end of the gate lines GLi and GL(i + 1), and several placeholder electrodes DM46a, DM46b, DM46c, and DM46d that are in contact with each other through the placeholder hole DH46 of type (4-6). The several placeholder electrodes DM46a, DM46b, DM46c, and DM46d can have a structure set to an electrically floating potential.

[0147] The placeholder hole DH46 of the (4-6)th type can have a structure passing through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2.

[0148] The placeholder electrode DM46a, located on the substrate SUB, can be formed from the same light-shielding metal layer in the same process as the light-shielding electrode LS. The placeholder electrode DM46b, located on the gate insulating layer GI, can be formed from the same gate metal layer in the same process as the gate line GL and can be in contact with the placeholder electrode DM46a via a contact hole that passes through the gate insulating layer GI and the buffer layer BF. The placeholder electrode DM46c, located on the second insulating layer ILD2, can be formed from the same source / drain metal layer in the same process as the data line DL and can be in contact with the placeholder electrode DM46b via a contact hole that passes through the insulating layers ILD2 and ILD1.The placeholder electrode DM46d, located on the second passivation layer PAS2 and passing through the (4-6)th type placeholder hole DH46, can be formed from the same transparent conductive layer in the same process as the pixel electrode PXL to protect the placeholder electrode DM46c exposed through the placeholder hole DH46. Here, as in . Fig. 9A to Fig. Figure 9F shows that the placeholder electrodes DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, DM46b, which are arranged under the placeholder hole of the fourth type, are referred to as a fifth placeholder electrode.

[0149] In the display device according to one embodiment, various types of placeholder holes DH1, DH2, DH3 and DH4, DH41 to DH46 and placeholder electrodes DM1, DM2, DM3 and DM4, DM41a to DM46d can be used as degassing paths for hydrogen (H) which diffuses during the heat treatment process from several layers containing the active layer ACT and the insulating layers ILD2 and PAS2 to increase hydrogen degassing.

[0150] In the display device according to one embodiment, the light-shielding metal layer, used as the light-shielding electrode LS and the placeholder electrodes DM43a, DM44a, and DM46a; the gate metal layer, used as the gate line GL, the gate electrode GE, and the placeholder electrodes DM41a, DM44b, DM45a, and DM46b; and the source / drain metal layer, used as the data line DL, the source / drain electrodes SD1 and SD2, and the placeholder electrodes DM42a, DM45b, and DM46c, may contain a hydrogen-absorbing metal material that absorbs hydrogen, thereby suppressing hydrogen diffusion. The hydrogen-absorbing metal material may contain a metal material that has a negative (-) hydrogen generation energy (eV).

[0151] For example, the hydrogen uptake metal material may contain at least one of a molybdenum titanium alloy (MoTi), titanium (Ti), lithium (Li), hafnium (Hf), ruthenium (Lu), tantalum (Ta), magnesium (Mg), vanadium (V), rubinium (Rb), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), niobium (Nb), cesium (Cs), barium (Ba) and lanthanum (La).

[0152] Fig. Figure 10 is a graph illustrating a hydrogen production energy for each material used in a display device according to an embodiment of the disclosure, Fig. Figure 11 is a view illustrating a hydrogen diffusion path of a thin-film transistor in a display device according to an embodiment of the disclosure, and Fig. Figure 12 is a view illustrating a hydrogen degassing path of a thin-film transistor according to an embodiment of the disclosure.

[0153] In the materials used in the display panel, hydrogen density diffusion to a layer adjacent to a corresponding material layer can occur depending on the amount of hydrogen and an intrinsic hydrogen generation energy eV of the corresponding material layer during the process.

[0154] With reference to Fig. 10. A molybdenum titanium alloy (MoTi) among materials (Cu, MoTi, Mo, Al, and Ti) used in the gate metal layer or the source / drain metal layer according to one embodiment can have a negative (-) hydrogen generation energy of -0.6 eV and can serve as a hydrogen absorption layer. Silicon oxide (SiOx), used in the insulating intermediate layer ILD1 or the gate insulating layer GI according to one embodiment, and exhibiting a relatively high hydrogen generation energy of 3.6 eV, can serve as a barrier to suppress hydrogen diffusion.

[0155] With reference to Fig. 11 In the display device according to one embodiment, hydrogen that has diffused from the passivation layer PAS2 can diffuse to the active layer ACT via the insulating layer ILD, the gate electrode GE, and the gate insulating layer GI of the thin-film transistor. The insulating layer ILD and the gate insulating layer GI, which contain silicon dioxide (SiOx) exhibiting a high hydrogen generation energy of 3.6 eV, can act as a barrier to suppress hydrogen diffusion.

[0156] The gate electrode GE can have a multilayer structure in which a lower gate metal layer containing a molybdenum titanium alloy (MoTi) and an upper gate metal layer containing copper (Cu) are stacked. The lower gate metal layer, containing a molybdenum titanium alloy (MoTi) with a negative hydrogen generation energy of -0.6 eV, can absorb hydrogen that has diffused through the upper gate metal layer, containing copper (Cu) with a positive hydrogen generation energy of 0.6 V, in order to suppress hydrogen diffusion into the gate insulating layer GI and the active layer ACT.

[0157] In one embodiment, the placeholder electrodes DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, DM46b and DM46c are formed from a light-shielding metal layer, a gate metal layer or a source / drain metal layer containing a hydrogen-absorbing metal material such as a molybdenum titanium alloy (MoTi) to suppress hydrogen diffusion, thereby reducing the hydrogen effect on the thin-film transistor TFT.

[0158] With reference to Fig. 12 In a thin-film transistor according to one embodiment, hydrogen (H) contained in the channel area CA (IGZO) of the active layer ACT can be degassed into the contact holes CH2 (air) by means of the second junction area SA2 (the conductive IGZO) of the active layer ACT, the second source / drain electrode SD2 (Cu / MoTi), and the pixel electrode PXL (ITO). The second junction area SA2 (the conductive IGZO) of the active layers ACT, the second source / drain electrode SD2 (Cu / MoTi), and the pixel electrode PXL (ITO) can have a lower hydrogen generation energy than the channel area CA (IGZO) of the active layer ACT.

[0159] The display device according to one embodiment can reduce the hydrogen effect on the thin-film transistor TFT by increasing hydrogen degassing and hydrogen uptake through the placeholder holes DH1, DH2, DH3 and DH4: DH41 to DH46 and the placeholder electrodes DM1, DM2, DM3 and DM4: DM41a to DM46d.

[0160] Fig. Figure 13 is a top view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device according to an embodiment of the disclosure. Fig. 14A to Fig. 14F are cross-sectional views showing a passivation hole structure along lines V-V', VI-VI', VII-VIII' and VIII-VIII', which are in Fig. 13 are shown, was taken, and Fig. 15A and Fig. Figure 15B are a top view and a cross-sectional view illustrating a thin-film transistor structure in a gate drive circuit of a display device according to an embodiment of the disclosure.

[0161] The display device according to one embodiment, which is in Fig. Figure 13 shows that passivation holes PH1 to PH7 can be used as hydrogen degassing pathways. In contrast to the display device according to an embodiment shown in Fig. As shown in Figure 6, elements containing passivation holes PH1 to PH7 instead of placeholder holes DH1, DH2, DH3 and DH4 will be used, from which Fig. 6 are different, and the other elements are the same as those of Fig. The 6 are merely a description of the different elements.

[0162] The indicator device according to one embodiment can include at least one of passivation holes PH1 and PH2 arranged in the second passivation layer PAS2, which overlaps or is adjacent to the end of the gate lines GLi and GL(i + 1), which are driven by the single-feed or interleaved mode. The passivation hole PH1 can be arranged in the second passivation layer PAS2 by dividing it into several sections that overlap or are adjacent to the end of the gate lines GLi and GL(i + 1). The passivation hole PH2 can be arranged as a single unit in the second passivation layer PAS2, which overlaps or is adjacent to the end of the gate lines GLi and GL(i + 1).

[0163] The display device according to one embodiment may further include at least one of the passivation holes PH3 and PH7, which are arranged in the second passivation layer PAS2, which overlaps with or is adjacent to the thin-film transistor TFT in the display area, the passivation holes PH4 and PH6, which are arranged in the second passivation layer PAS2 on a signal line that is adjacent to the thin-film transistor TFT, i.e. the data line DL, or a passivation hole PH5, which is arranged in the second passivation layer PAS2 on the gate lines GLi and GL(i + 1).

[0164] The display device according to one embodiment can include at least one of the passivation holes PH1 to PH7. Here, the passivation holes PH3, PH4, PH5, PH6, and PH7, which are provided in the second passivation layer PAS2 (i.e., an upper passivation layer) in the display area, can be referred to as first passivation holes, and the passivation holes PH1 and PH2, which are provided in the second passivation layer PAS2 located between the remote end of each gate line and the gate drive circuit in the bezel area, can be referred to as second passivation holes.

[0165] The display device according to one embodiment may further include a placeholder electrode arranged to overlap with the passivation holes PH1 to PH7 and electrically set to a floating potential.

[0166] With reference to Fig. According to one embodiment, the display device 14A can include a passivation hole PH11 located in the second passivation layer PAS2, adjacent to the ends of the gate lines GLi and GL(i + 1), and a placeholder electrode DM51 arranged to overlap with the passivation hole PH11. The placeholder electrode DM51 can be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL.

[0167] With reference to Fig. According to one embodiment, the display device 14B may include a passivation hole PH12 located in the second passivation layer PAS2 adjacent to the ends of the gate lines GLi and GL(i+1), and placeholder electrodes DM52a and DM52b arranged to overlap with the passivation hole PH12. The placeholder electrode DM52a may be formed from the same transparent conductive layer as the common electrode VCOM on the planarization layer PNL. The placeholder electrode DM52b may be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the placeholder electrode DM52a, and may be in contact with the placeholder electrode DM52a through the passivation hole PH12.

[0168] With reference to Fig. According to one embodiment, the display device 14C can include a passivation hole PH31 located in the second passivation layer PAS2 on the thin-film transistor TFT, and a placeholder electrode DM52 arranged to overlap with the passivation hole PH31. The passivation hole PH31 can be arranged to overlap with the first source / drain electrode SD1, which is connected to the active layer ACT of the thin-film transistor TFT. The placeholder electrode DM52 can be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the planarization layer PNL.

[0169] With reference to Fig. According to one embodiment, the display device can include a passivation hole PH32 located in the second passivation layer PAS2 on the thin-film transistor TFT, and placeholder electrodes DM53a and DM53b arranged to overlap with the passivation hole PH32. The passivation hole PH32 can be arranged to overlap with the first source / drain electrode SD1, which is connected to the active layer ACT of the thin-film transistor TFT. The placeholder electrode DM53a can be formed from the same transparent conductive layer as the common electrode VCOM on the planarization layer PNL. The placeholder electrode DM53b can be formed from the same transparent conductive layer as the pixel electrode PXL on the second passivation layer PAS2 and the placeholder electrode DM53a, and can be in contact with the placeholder electrode DM53a through the passivation hole PH32.

[0170] With reference to Fig. According to one embodiment, the display device 14E can include a passivation hole PH4 located in the second passivation layer PAS2 adjacent to the data line DL, and a placeholder electrode DM54 arranged to overlap with the passivation hole PH4. The passivation hole PH4 can be arranged to overlap with the data line DL adjacent to the thin-film transistor TFT. The placeholder electrode DM54 can be formed from the same transparent conductive layer as the pixel electrode PXL located in the second passivation layer PAS2 and the planarization layer PNL.

[0171] With reference to Fig. In one embodiment, the display device (14F) can include a passivation hole PH5 located in the second passivation layer PAS2 at the gate line GL, and a placeholder electrode DM55 arranged to overlap with the passivation hole PH5. The passivation hole PH5 can be arranged to overlap with the gate line GL adjacent to the thin-film transistor TFT. The placeholder electrode DM55 can be formed from the same transparent conductive layer as the pixel electrode PXL at the second passivation layer PAS2 and the planarization layer PNL. Here, as in Fig. 14A to Fig. As shown in Figure 14F, the placeholder electrodes arranged in the first passivation holes can be referred to as the sixth placeholder electrodes, the placeholder electrodes arranged in the second passivation holes can be referred to as the seventh placeholder electrodes, the placeholder electrode arranged below the first passivation hole can be referred to as the eighth placeholder electrode, and the placeholder electrode arranged below the second passivation hole can be referred to as the ninth placeholder electrode.

[0172] In the display device according to one embodiment, the placeholder electrodes DM: DM51, DM52a, DM52b, DM52, DM53a, DM53b, DM54 and DM55 cover the passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32, thereby avoiding errors that may be caused by the passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32 in subsequent processes after the heat treatment process.

[0173] In the display device according to one embodiment of the disclosure, the passivation holes PH: PH1 to PH7, PH11, PH12, PH31 and PH32 and the placeholder electrodes DM: DM51, DM52a, DM52b, DM52, DM53a, DM53b, DM54 and DM55 can be used as degassing pathways for hydrogen (H) contained in the second passivation layer PAS2 during the heat treatment process to increase hydrogen degassing. Similarly, in the display device according to one embodiment, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the effect of hydrogen on the thin-film transistor TFT, thereby preventing or minimizing changes in the threshold voltage Vth.

[0174] With reference to Fig. 15A and Fig. 15B, a thin-film transistor TFT2 of the gate drive circuit in the display device according to an embodiment of the disclosure can have a structure that differs from that of the thin-film transistor TFT of the display area, which is in Fig. 7 and Fig. 13 is shown.

[0175] In the display device according to one embodiment, the thin-film transistor TFT of the display area can have a 3-metal layer structure comprising a light-shielding metal layer, a gate metal layer, and a source / drain metal layer, as shown in Fig. Figure 7 shows that the thin-film transistor TFT2 of the gate drive circuit can have a 2-metal-layer structure containing a light-shielding metal layer and a gate metal layer, as shown in Figure 7. Fig. 15B is shown.

[0176] The thin-film transistor TFT2 of the gate drive circuit according to one embodiment can include a light-shielding electrode LS2 on the substrate SUB, a buffer layer BF covering the light-shielding electrode LS2, an active layer ACT2 on the buffer layer BF, a gate isolation layer GI and a gate electrode GE2 stacked on the active layer ACT2, and a (2-1)th and a (2-2)th source / drain electrode SD21 and SD22, respectively, connected to a first and a second contact surface of the active layer ACT2 exposed through contact holes CH21 and CH22 of the gate isolation layer GI. The light-shielding electrode LS2 can be connected to the gate electrode GE2 through a contact hole CH23 to function as a dual gate.The display device according to one embodiment can further include insulating intermediate layers ILD1 and ILD2, a first passivation layer PAS1, a planarization layer PNL and a second passivation layer PAS2, which are stacked on the thin-film transistor TFT2 of the gate drive circuit.

[0177] With reference to Fig. 15B The thin-film transistor TFT2 of the gate drive circuit according to one embodiment can have a structure in which the second insulating intermediate layer ILD2, which contains silicon nitride (SiNx), and the (2-1)th and the (2-2)th source / drain electrodes SD21 and SD22 are not in direct contact with each other, and need not have a contact hole passing through the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2.

[0178] With reference to Fig. 7 In one embodiment, the thin-film transistor TFT includes a path in the display area in which the second insulating intermediate layer ILD2 is in contact with the first and second source / drain electrodes SD1 and SD2, and a contact hole CH3 that passes through the first passivation layer PAS1, the planarization layer PNL and the second passivation layer PAS2, such that the amount of hydrogen inflow can be increased more than in the thin-film transistor TFT2 of the gate drive circuit.

[0179] The display device according to one embodiment can include at least one placeholder hole DH or passivation hole PH arranged in the display area, thereby increasing hydrogen degassing.

[0180] Accordingly, according to one embodiment, the display device can reduce or minimize the deviation of the threshold voltage Vth by reducing the difference in hydrogen content between the thin-film transistor TFT in the display area and the thin-film transistor TFT2 in the gate drive circuit.

[0181] Fig. Figure 16 is a top view illustrating a partial area adjacent to an end of a gate line in a display area of ​​a display device according to an embodiment of the disclosure, and Fig. 17A to Fig. 17C are cross-sectional views showing a placeholder hole structure taken along line IX-IX' and a passivation hole structure taken along line XX', which is in Fig. Figure 16 illustrates this.

[0182] With reference to Fig. 16 to Fig. According to one embodiment, the display device 17C can include a gate line GLa, a data line DLa, a thin-film transistor TFTa, a common electrode VCOMa, a pixel electrode PXLa, and a thin-film transistor substrate on which several insulating layers are arranged. The several insulating layers can include a buffer layer BF, a gate insulating layer GI, intermediate insulating layers ILD1 and ILD2, passivation layers PAS1 and PAS2, and a planarization layer PNL. The description of repeated elements is based on those referred to in Fig. 6 and Fig. The sections described in section 7 are omitted.

[0183] The thin-film transistor TFTa in the display area according to one embodiment can have a two-metal-layer structure. The thin-film transistor TFTa in the display area according to one embodiment can include a light-shielding electrode LSa on the substrate SUB, a buffer layer BF covering the light-shielding electrode LSa, an active layer ACTa on buffer layer BF, a gate-insulating layer GI and a gate electrode GEa stacked on the active layer ACTa, and a first and a second source / drain electrode SD1a and SD2a, respectively, connected to the first and second contact surfaces of the active layer ACTa, which are exposed through the contact holes CH1a and CH2a of the gate-insulating layer GI.

[0184] The insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS 1, the planarization layer PNL and the second passivation layer PAS2 can be stacked sequentially on the thin-film transistor TFTa according to one embodiment.

[0185] The data line DLa and the light shielding electrode LSa can be arranged on the substrate SUB as the same light shielding metal layer.

[0186] The gate line GLa, the gate electrode GEa, and a first and second source / drain electrode SD1a and SD2a can be formed on the gate insulating layer GI as the same gate metal layer. The gate electrode GEa can be connected to the light shielding electrode LSa via a contact hole CH4a that passes through the gate insulating layer GI and the buffer layer BF. The first source / drain electrode SD1a can be connected to the data line DLa via a contact hole CH5a that passes through the gate insulating layer GI and the buffer layer BF. The second source / drain electrode SD2a can be connected to the pixel electrode PXL via a contact hole CH3a that passes through the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2.

[0187] The gate line GLa, which is driven by a single feed or a nested feed, can be a starting end connected to the gate drive circuit ( Fig. 2 is: 200 or Fig. 3: 200a or 200b), which is in contact within a enclosing area, and one end which is not in contact with the gate drive circuit located within the wider enclosing area.

[0188] The indicator device according to one embodiment may include at least one of placeholder holes DH21, DH22, DH23 and DH24 or passivation holes PH31 and PH32, which are used as hydrogen degassing paths. The indicator device according to one embodiment may further include placeholder electrodes arranged to overlap with the placeholder holes DH21, DH22, DH23 and DH24 and / or the passivation holes PH31 and PH32.

[0189] Accordingly, in one embodiment of the display device, hydrogen degassing in the display area can be increased during the heat treatment process to minimize the hydrogen effect on the thin-film transistor TFTa, thereby preventing or minimizing the change in the threshold voltage Vth.

[0190] The display device according to one embodiment may include at least one placeholder hole DH21 located at the end of the gate line GLa, one placeholder hole DH22 located on a signal line, i.e., the gate line GLa adjacent to the thin-film transistor TFT in the display area, one placeholder hole DH23 located on the data line DLa, or one placeholder hole DH24 located in the bezel area adjacent to the end of the gate line GLa, and may further include a placeholder electrode arranged to overlap with the placeholder holes DH21, DH22, DH23, and DH24.

[0191] The placeholder hole DH21, which overlaps with the end of the gate line GLa, and the placeholder hole DH22, which overlaps with the gate line GLa, can have the same structure as the placeholder hole DH1, which is in Fig. 8A, which is shown above, and may further contain a placeholder electrode DM1, which is shown in Fig. 8A is shown.

[0192] The placeholder hole DH24, which is arranged in the edging surface adjacent to the end of the gate line GLa, according to one embodiment, can have the same structure as the placeholder holes DH4: DH41 to DH46, which are located in Fig. 9A to Fig. 9F, which are described above, are shown, and may further contain placeholder electrodes DM4: DM41a to DM46d, which are in Fig. 9A to Fig. 9F are shown.

[0193] With reference to Fig. In one embodiment, the placeholder hole DH23, which overlaps the data line DLa, can be arranged to pass through the buffer layer BF, the insulating intermediate layers ILD1 and ILD2, the first passivation layer PAS1, the planarization layer PNL, and the second passivation layer PAS2, which are stacked on top of the data line DLa. The placeholder electrode DM23, which is located on the second passivation layer PAS2 and passes through the placeholder hole DH23, can be in contact with the data line DLa.

[0194] With reference to Fig. 17B and Fig. In the display device according to one embodiment, 17C can overlap the passivation hole PH31, which is located in the second passivation layer PAS2 on the thin-film transistor TFTa, with the first source / drain electrode SD1a, which is connected to the active layer ACTa, and can also overlap with the data line DLa.

[0195] The display device according to one embodiment can further include a placeholder electrode DM31 ( Fig. 17B), which is arranged to overlap with the passivation hole PH31, or may further include several placeholder electrodes DM31a and DM31 ( Fig. 17C), which are arranged to overlap with the passivation hole PH31. The placeholder electrode DM31 can be formed from the same transparent conductive layer as the pixel electrode PXL. The placeholder electrode 31a can be formed from the same transparent conductive layer as the common electrode VCOM.

[0196] The passivation hole PH32, which is arranged in the enclosing surface adjacent to the end of the gate line GLa according to one embodiment, can have the same structure as the passivation holes PH11 and PH12, which are located in Fig. 14A and Fig. 14B, which are described above, are shown, and may further include placeholder electrodes DM51, DM51a and DM51b, which are shown in Fig. 14A and Fig. 14B).

[0197] Fig. 18 is a view illustrating a differential application structure of a placeholder hole density in a display device according to an embodiment of the disclosure, and Fig. 19A to Fig. 19C are top views illustrating a partial area of ​​each of the first to third surfaces, which are in Fig. 18 is shown.

[0198] With reference to Fig. In the display panel, which is controlled in a nested manner according to one embodiment, the odd-numbered gate line GLo can have a left starting end that is in contact with a stepped circuit GIPo of the left gate drive circuit 200a in the left enclosure BZ1, and a right remote end that is arranged in the right enclosure BZ2. The even-numbered gate line GLe can have a right starting end that is in contact with a stepped circuit GIPo of the right gate drive circuit 200b in the right enclosure BZ2, and a left end that is arranged in the left enclosure BZ1.

[0199] The display panel according to one embodiment may include at least one of a placeholder hole or passivation hole that overlaps with or is adjacent to the thin-film transistor or signal line in the display area DA to serve as a hydrogen degassing path, thereby increasing hydrogen degassing.

[0200] In the display panel according to one embodiment, the density of placeholder holes arranged in the display area DA can be applied differentially depending on the distance from the end of the gate lines GLo and GLe.

[0201] With reference to Fig. 18 and Fig. 19A In the display panel according to one embodiment, the placeholder holes DH can be arranged at a lower density in a first area AA1, which is located away from the remote ends of the gate lines GLO and GLe.

[0202] With reference to Fig. 18 and Fig. 19B In the display panel according to one embodiment, the placeholder holes DH can be arranged in a second area AA2, which is located between the first area AA1, which is away from the ends of the gate lines GLo and GLe, and a third area AA3, which is near the ends of the gate lines GLo and GLe, at a medium density (a mean density).

[0203] With reference to Fig. 18 and Fig. 19C, in the display panel according to one embodiment, the placeholder holes DH in the third area AA3 can be arranged near the ends of the gate lines GLo and GLe at a high density.

[0204] Accordingly, according to one embodiment, the display panel can prevent the threshold voltage of the thin-film transistor from being shifted towards the negative voltage, and minimize the threshold voltage deviation of the thin-film transistor by minimizing the difference in hydrogen inflow due to the structural difference between the start end and the end of each of the gate lines GLo and GLe.

[0205] Fig. 20A is a graph illustrating the voltage / current characteristics of a thin-film transistor in a display device, a comparative example from the related field, and Fig. 20B and Fig. Figure 20C are graphs illustrating the voltage / current characteristics of a thin-film transistor in a display device according to an embodiment of the disclosure.

[0206] With reference to Fig. 20A, it should be noted that if the indicator device, according to the comparative example of the related field, does not contain a placeholder hole that overlaps with the thin-film transistor, the hydrogen inflow to the active layer of the thin-film transistor may be increased such that the threshold voltage of the thin-film transistor is shifted in the negative direction.

[0207] With reference to Fig. According to one embodiment, the indicator device in 20B includes a placeholder hole arranged on the thin-film transistor and passing through the first passivation layer, the planarization layer, and the second passivation layer, and a placeholder electrode arranged to overlap the placeholder hole, thereby increasing hydrogen degassing through the placeholder hole and the placeholder electrode. Accordingly, the threshold voltage of the thin-film transistor is shifted in the positive direction without being shifted in the negative direction.

[0208] With reference to Fig. 20C It should be noted that, although the indicator device according to one embodiment includes a placeholder hole (a passivation hole) passing through the second passivation layer on the thin-film transistor and a placeholder electrode overlapping the placeholder hole, the hydrogen degassing through the placeholder hole and the placeholder electrode is increased such that the threshold voltage of the thin-film transistor is shifted in the positive direction instead of the negative direction.

[0209] Fig. 21A and Fig. Figure 21B are graphs illustrating voltage / current characteristics of a thin-film transistor according to a density of a placeholder hole in a display device according to an embodiment of the disclosure.

[0210] With reference to Fig. 21A and Fig. 21B It should be noted that in the display device according to one embodiment, since the density of the placeholder hole arranged around the thin-film transistor is of a low density ( Fig. 21A) to a high density ( Fig. 21B) is increased, the hydrogen degassing is increased, such that the threshold voltage of the thin-film transistor is shifted in the positive direction.

[0211] According to the disclosure, the following beneficial effects can be obtained.

[0212] As described above, according to one embodiment of the disclosure, the display device can differentially apply the density of the hydrogen degassing path (of the placeholder hole and the passivation hole) depending on the distance from the end of the gate line, which is controlled in the single feed mode or the nested mode, thereby increasing the hydrogen degassing effect and minimizing the difference in the amount of hydrogen inflow.

[0213] Accordingly, the display device, according to one embodiment of the disclosure, can improve reliability and uniformity by minimizing the threshold voltage deviation of the thin-film transistor according to its position in the display area.

[0214] The display device according to one embodiment of the disclosure can reduce or minimize leakage current by preventing the threshold voltage of the thin-film transistor from being shifted in the negative direction, thereby improving reliability and providing improved image quality with lower power consumption.

[0215] The display device according to an embodiment of the disclosure can improve reliability by minimizing the threshold voltage deviation between the first thin-film transistor in the display area and the second thin-film transistor in the gate drive circuit, which differ from each other in terms of their stack structure.

[0216] The display device according to one or more embodiments of the disclosure can be applied to various electronic devices.For example, the display device according to one or more embodiments of the disclosure can be applied to a mobile device, a video phone, a smartwatch, a watch phone, a portable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, an electronic calendar, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation device, a vehicle navigation device, a vehicle display device, a television, a background image display device, a signage device, a gaming device, a laptop computer, a surveillance device, a camera, a camcorder, and household appliances.

[0217] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified if necessary to utilize concepts from the different embodiments to provide yet more embodiments.

[0218] These and further modifications may be made to the embodiments in light of the detailed description set forth above. In general, the terms used in the following claims are not to be interpreted as limiting the claims to the specific embodiments disclosed in the application and the claims themselves, but rather as encompassing all possible embodiments together with the full range of correspondences to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

[0219] The features, structures, and effects of the disclosure described above are contained in at least one embodiment of the disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of the disclosure can be implemented by a person skilled in the art through a combination or modification of further embodiments. Therefore, the content associated with the combination and modification should be interpreted as being within the scope of the disclosure.

[0220] It is evident to those skilled in the art that the disclosure described above is not limited by the embodiments described above and the accompanying drawings, and that various substitutions, modifications, and variants can be made to the disclosure without altering its scope. Consequently, the scope of the disclosure is defined by the accompanying claims, and it is intended that all variants or modifications derived from the meaning, scope, and correspondence concept of the claims fall within the scope of the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0152428

[0001]

Claims

[1] Display device comprising the following: a display panel (100) comprising a display area (DA) in which gate lines (GL), data lines (DL) and thin-film transistors (TFT) are arranged, and a first and a second enclosing area (BZ1, BZ2) adjacent to the display area (DA); a gate drive circuit (200) arranged in at least one of the first and second enclosure surfaces (BZ1, BZ2) and configured to drive the gate lines (GL); and Placeholder holes (DH) arranged in at least one of the display area (DA) and the first and second edging areas (BZ1, BZ2), wherein each of the gate lines (GL) comprises a starting end connected to the gate drive circuit (200) located in one of the first and second enclosure areas (BZ1, BZ2), and an end located in the further of the first and second enclosure areas (BZ1, BZ2) and The density of placeholder holes (DH) varies according to the distance from the end of each gate line. [2] Display device according to claim 1, further comprising placeholder electrodes (DM) arranged in the placeholder holes (DH), and / or wherein the density of the placeholder holes (DH) is higher when the placeholder holes (DH) are closer to the end of each gate line (GL), and is lower when the placeholder holes (DH) are closer to the starting end of each gate line (GL). [3] Display device according to one of the preceding claims, wherein the gate control circuit (200) is arranged in the first enclosing surface (BZ1) and is connected to the starting end of each of the gate lines (GL) located in the first enclosing surface (BZ1) and the end of each of the gate lines (GL) is arranged in the second enclosing surface (BZ2). [4] Display device according to one of the preceding claims, wherein the gate control circuit (200) comprises: a first gate drive circuit (200a) arranged in the first enclosure area (BZ1) and connected to the starting end of each of the odd-numbered gate lines (Glo) under the gate lines in the first enclosure area (BZ1); and a second gate drive circuit (200b) which is arranged in the second enclosure area (BZ2) and is connected to the starting end of each of the even-numbered gate lines (GLe) under the gate lines in the second enclosure area (BZ2), wherein the end of each of the odd-numbered gate lines (GLo) is located in the second enclosing area (BZ2) and the end of each of the even-numbered gate lines (GLe) is located in the first enclosure area (BZ1). [5] Display device according to any of the preceding claims, wherein the placeholder holes (DH) include at least one of the following: a placeholder hole (DH1) of the first type that overlaps with the end of each gate line (GL), a placeholder hole (DH2) of the second type that overlaps with each gate line (GL), and a third-type placeholder hole (DH3) that overlaps with each data line (DL). [6] Display device according to claim 5, wherein the placeholder electrodes (DM) comprise at least one of the following: a first placeholder electrode (DM1) which is arranged in the placeholder hole (DH1) of the first type; a second placeholder electrode (DM2) arranged in the placeholder hole (DH2) of the second type; and a third placeholder electrode (DM3) which is located in the placeholder hole (DH3) of the third type. [7] Display device according to claim 5 or 6, wherein each of the placeholder hole (DH1) of the first type and the placeholder hole (DH2) of the second type passes through several insulating layers (ILD1, ILD2, PAS1, PNL, PAS2) stacked on each gate line (GL), and / or the placeholder hole (DH3) of the third type passes through several insulating layers (PAS1, PNL, PAS2) stacked on each data line. [8] Display device according to claim 6 or 7, wherein each of the first placeholder electrode (DM1) and the second placeholder electrode (DM2) is arranged on a top insulation layer (PAS2) under the multiple insulation layers stacked on each gate line (GL) and the gate line (GL) is contacted through each of the first-type placeholder hole (DH1) and the second-type placeholder hole (DH2) and / or the third placeholder electrode (DM3) is arranged on a top insulation layer (PAS3) under the multiple insulation layers stacked on each data line (DL) and the data line (DL) is contacted through the third-type placeholder hole (DH3). [9] Display device according to any one of the preceding claims 2-8, wherein the placeholder electrodes (DM) are arranged on the same layer as a pixel electrode (PXL) connected to the thin-film transistor (TFT). [10] Display device according to one of the preceding claims, wherein the placeholder holes (DH) further comprise placeholder holes (DH4) of the fourth type, which are arranged between the end of each gate line GL) and the gate drive circuit (200) in at least one of the first enclosing surface (BZ1) and the second enclosing surface (BZ2), and preferably the placeholder electrodes (DM) further comprise: a fourth placeholder electrode (DM45c) located in the fourth type placeholder hole (DH4), and at least one fifth placeholder electrode (DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, DM46b) that is located below the placeholder hole (DH4) of the fourth type. [11] Display device according to claim 10, wherein the placeholder hole (DH) of the fourth type passes through several insulating layers (ILD2, PAS1, PNL, PAS2) stacked on top of the at least one fifth placeholder electrode (DM41a, DM42a, DM43a, DM44a, DM44b, DM45a, DM45b, DM46a, DM46b), and the fourth placeholder electrode (DM45c) is arranged on an uppermost insulating layer (PAS2) under the multiple insulating layers and contacts at least one fifth placeholder electrode (DM45b) through the placeholder hole (DH4) of the fourth type. [12] Display device according to claim 10 or 11, wherein the fourth placeholder electrode (DM45c) is arranged as the same transparent conductive layer on the same layer as the pixel electrode (PXL) connected to the thin-film transistor (TFT), and the at least one fifth placeholder electrode (DM45b) is arranged as the same metal layer on the same layer as at least one electrode of the thin-film transistor (TFT). [13] Display device according to any of the preceding claims, wherein the thin-film transistor (TFT) comprises: a light shielding electrode (LS) that is arranged on a substrate (SUB); an active layer (ACT) arranged to overlap with the light shielding electrode (LS), and a buffer layer (BF) between the light shielding electrode (LS) and the active layer (ACT); a gate electrode (GE) positioned between the active layer (ACT) and a gate insulating layer (GI); and a first and a second source / drain electrode (SD1, SD2), each connected to a first and a second interface (SA1, SA2) of the active layer (ACT) by a first and a second contact hole (CH1, CH2), wherein preferably the at least one fifth placeholder electrode (DM45b) comprises at least one light shielding metal layer which is the same as the light shielding electrode (LS), one gate metal layer which is the same as the gate electrode (GE), and one source / drain metal layer which is the same as the first and the second source / drain electrode (SD1, SD2). [14] Display device according to any one of the preceding claims 10-13, wherein the at least one fifth placeholder electrode (DM45b) contains a hydrogen absorption metal material which is contained in at least one of the light shielding metal layer, the gate metal layer and the source / drain metal layer. [15] Display device comprising the following: a display panel (100) comprising a display area (DA) in which gate lines (GL), data lines (DL) and thin-film transistors (TFT) are arranged, and a first and a second enclosure area (BZ1, BZ2) adjacent to the display area (DA); a gate drive circuit (200) arranged in at least one of the first and second enclosure surfaces (BZ1, BZ2) and configured to drive the gate lines (GL); and Passivation holes (PH) arranged in at least one of the display surface (DA) and the first and second edging surfaces (BZ1, BZ2), wherein a placeholder electrode (DM51, DM52) is arranged in the passivation holes and the placeholder electrode (DM52) contains a hydrogen absorption metal material, wherein each of the gate lines (GL) comprises a starting end connected to the gate drive circuit (200) located in one of the first and second enclosure areas (BZ1, BZ2) and an end located in the further of the first and second enclosure areas (BZ1, BZ2). [16] Display device according to claim 15, further comprising at least one of the following: first passivation holes (PH1) provided in an upper passivation layer (PAS2) in the display area (DA); and second passivation holes (PH2) provided in the upper passivation layer (PAS2) located between the remote end of each gate line (GL) and the gate drive circuit (200) in at least one of the first enclosing surface (BZ1) or the second enclosing surface (BZ2), wherein the first passivation holes (PH1) preferably overlap or are adjacent to at least one of the gate line (GL), the data line (DL) and the thin-film transistor (TFT). [17] Display device according to claim 16, further comprising at least one of the following: sixth placeholder electrodes (DM51), each located in the first passivation holes (PH1); and seventh placeholder electrodes (DM52) which are each arranged in the second passivation holes (PH2), wherein preferably the sixth placeholder electrode (DM51) and / or the seventh placeholder electrode (DM52) contain a hydrogen absorption metal material. [18] Display device according to claim 17, further comprising at least one of the following: an eighth placeholder electrode (DM53a) located below the first passivation hole (PH11) and contacting the sixth placeholder electrode (DM51) through the first passivation hole; and a ninth placeholder electrode (DM52a) which is located below the second passivation hole (PH12) and contacts the seventh placeholder electrode (DM52b) through the second passivation hole (PH12). [19] Display device according to claim 18, wherein at least one of the sixth placeholder electrode (DM51) or the seventh placeholder electrode (DM52) is arranged as the same transparent conductive layer on the same layer as the pixel electrode (PXL) which is connected to the thin-film transistor (TFT) and at least one of the eighth placeholder electrode (DM53a) or the ninth placeholder electrode (DM52a) is arranged as the same transparent conductive layer on the same layer as a common electrode (VCOM) that overlaps between the pixel electrode (PXL) and the upper passivation layer (PAS2).

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