Semiconductor package with a chip array featuring an electrically insulating thickness-matching layer

Abstract

A semiconductor package comprises a laminate package body and a chip assembly embedded within the laminate package body. The laminate package body has multiple stacked dielectric laminate layers and metallization layers arranged between the dielectric laminate layers. The chip assembly comprises a thermally conductive substrate having a planar top surface, a semiconductor chip mounted on the planar top surface of the thermally conductive substrate, and an electrically insulating thickness-matching layer formed on the planar top surface of the thermally conductive substrate and surrounding the semiconductor chip. One top surface of the electrically insulating thickness-matching layer is essentially coplanar with one top surface of the semiconductor chip.The top surface of the electrically insulating thickness-matching layer and the top surface of the semiconductor chip form a top surface of the chip assembly.

Description

background

[0001] A laminate semiconductor package, sometimes referred to as an embedded package, typically comprises a chip array embedded within a PCB-like structure of stacked dielectric and metallization layers. Outer layers of the laminate package body provide electrical and / or thermal contact with the semiconductor chip(s) of the chip array. A structure of the chip array, such as a substrate, metal body, conductor frame, etc., may have one or more surface recesses or cavities structured to accommodate the semiconductor chip(s). The semiconductor chips can be electrically accessed through via structures and conductor tracks of the semiconductor body. The semiconductor chip may be mounted on a metal substrate, which can act as a heat sink mechanism and / or provide a vertical electrical connection.Although advantageous, this packaging technique presents challenges for semiconductor chips of varying thicknesses. For example, creating a recess or cavity in a substrate to accommodate a thick semiconductor chip may not be feasible using standard manufacturing processes. Alternative methods for accommodating such semiconductor chips may be cost-prohibitive and / or increase manufacturing complexity.

[0002] Therefore, there is a need for a simple, cost-effective solution for integrating thick semiconductor chips into laminate semiconductor packages. Summary

[0003] According to one embodiment of a semiconductor package, the semiconductor package comprises: a laminate package body having a plurality of stacked dielectric laminate layers and metallization layers arranged between the dielectric laminate layers; and a chip assembly embedded within the laminate package body, wherein the chip assembly comprises: a thermally conductive substrate having a planar top surface; a semiconductor chip mounted on the planar top surface of the thermally conductive substrate;and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor chip, wherein an upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor chip, and wherein the upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor chip form an upper surface of the chip assembly.

[0004] According to one embodiment of a method for forming a semiconductor package, the method comprises: forming a chip assembly by: mounting a semiconductor chip on a planar top surface of a thermally conductive substrate, and forming an electrically insulating thickness-matching layer on the planar top surface of the thermally conductive substrate such that the electrically insulating thickness-matching layer surrounds the semiconductor chip and an top surface of the electrically insulating thickness-matching layer is substantially coplanar with a top surface of the semiconductor chip; forming a laminate package body by stacking a plurality of dielectric laminate layers and metallization layers on top of each other;and embedding the chip assembly within the laminate housing body by forming a central opening through one of the dielectric laminate layers and arranging the chip assembly in the central opening.

[0005] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. Brief description of the characters

[0006] The elements in the drawings are not necessarily to scale relative to one another. Identical reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined, provided they are not mutually exclusive. Embodiments are shown in the drawings and are described in detail in the following description. Fig. Figure 1 illustrates a side cross-sectional view of a semiconductor package according to one embodiment. Fig. Figure 2 illustrates a top view of a chip arrangement according to one embodiment. Fig. Figure 3 illustrates a side cross-sectional view of a semiconductor package according to one embodiment. Fig. Figures 4A-4F illustrate a method for forming a semiconductor package according to one embodiment. Detailed description

[0007] This document describes a laminate semiconductor package, also known as an embedded package, comprising a chip assembly embedded within a laminate package body composed of stacked dielectric and metallization layers. The chip assembly features a thermally conductive substrate with a planar top surface on which a semiconductor chip is mounted. An electrically insulating thickness-matching layer, the same thickness as the semiconductor chip, is formed on the planar top surface and surrounds the mounted semiconductor chip. Matching the thickness of the electrically insulating thickness-matching layer to the thickness of the semiconductor chip provides the chip assembly with a planar top surface and no semiconductor chip protrusion. This configuration simplifies the process of embedding the chip assembly within the laminate semiconductor package.In particular, dielectric and metallization layers can be formed directly on the chip assembly without the need to create openings in these layers to accommodate the semiconductor chip.

[0008] Since the electrically insulating thickness-matching layer can be formed to any desired thickness, the configuration described here can additionally allow the laminate semiconductor package to accommodate a sufficiently thick semiconductor chip for which placement in a recess or cavity in the substrate is not feasible due to manufacturing limitations. For example, the laminate semiconductor package described here can accommodate a GaN HEMT chip with a thickness greater than 200 micrometers or even greater than 250 micrometers, which is to be embedded within the laminate semiconductor package.

[0009] Thus, the solution disclosed here can provide a cost-effective, relatively simple solution for integrating semiconductor chips, especially thick semiconductor chips, into laminate semiconductor packages.

[0010] Next, exemplary embodiments of the semiconductor package are described with reference to the figures.

[0011] Fig. Figure 1 illustrates a side cross-sectional view of a semiconductor package 10 according to one embodiment. The semiconductor package comprises a laminate package body 200 and a chip arrangement 100 embedded in the laminate package body 200.

[0012] The laminate housing body 200 comprises multiple stacked dielectric laminate layers 210 and metallization layers 220 arranged between the dielectric laminate layers 210. The laminate housing body 200 can be formed using techniques similar to those used to form a printed circuit board (PCB). Each of the dielectric laminate layers 210 can comprise an electrically insulating material such as FR-4, FR-5, CEM-4, bismaleimidrazine (BT) resin, etc. One or more of the dielectric laminate layers 210 can be pre-formed. The metallization layers 220 can comprise a conductive metal such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), etc., and alloys or combinations thereof.The metallization layers 220 can be structured to form internal interconnects within the laminate package body 200, as well as bond pads exposed on the outer surfaces of the semiconductor package 10. Each metallization layer 220 can be formed on the surface of a dielectric laminate layer 210, for example, by a plating process, or it can be a pre-formed layer bonded to the surface of a dielectric laminate layer 210. The dielectric laminate layers 210 can all be made of the same material, or some or all of the dielectric laminate layers 210 can be made of different materials. Likewise, the metallization layers 220 can all be made of the same material, or some or all of the metallization layers 220 can be made of different materials.

[0013] The laminate package body 200 has a core structure 230 that is embedded between a first 2101 of dielectric laminate layers 210 and a second 2102 of dielectric laminate layers 210. The chip arrangement 100 is arranged within a central opening 235 in the core structure 230 and is thus also embedded between the first 2101 of dielectric laminate layers 210 and a second 2102 of dielectric laminate layers 210. In the example of the semiconductor package 10 of Fig. 1 The core structure 230 has a third 2103 of dielectric laminate layers 210 (e.g., formed from a pre-formed material such as FR-4, FR-5, CEM-4) vertically between the first and second 2201 and 2202 of the metallization layers 220. The third 2103 of the dielectric laminate layers can have a thickness of more than 1 millimeter, e.g., about 1.2 millimeters. Each of the first 2201 and the second 2202 of the metallization layers 220 can have a thickness of about 25 micrometers to about 50 micrometers, e.g., about 35 micrometers. The central opening 235 can be a pre-formed opening that is formed in the third 2103 of the dielectric laminate layers 210 before the third 2103 of the dielectric laminate layers 210 is integrated into the laminate housing body 200.The section of the central opening 235 in the core structure 230, which surrounds the chip assembly, can be filled with a resin material such as bismaleimide triazine (BT) to encapsulate the chip assembly 100.

[0014] The chip arrangement 100 has a thermally conductive substrate 110 with a planar upper surface 110 S, U The thermally conductive substrate 110 can be a monolithic structure, e.g., made of a metal such as copper, aluminum, an alloy, etc., part of a conductor frame, or any other suitable substrate. In some examples, the thermally conductive substrate 110 has multiple layers. Some examples of such a multilayer thermally conductive substrate 110 include a DCB substrate (direct copper bonded substrate), an AMB substrate (active metal brazed substrate), and an insulated metal substrate (IMS).

[0015] A semiconductor chip 120 is located on the planar upper surface 110 S, UThe thermally conductive substrate 110 is mounted. The semiconductor chip 120 can be designed in any device technology (transistor, diode, resistor, capacitor, any other type of active or passive device) and can have any suitable semiconductor material. Examples of such materials include elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.The semiconductor chip 120 can be configured as a transistor chip, such as a SiC or Si power MOSFET (metal-oxide-semiconductor field-effect transistor) device, a HEMT (high-electron mobility transistor) device, an IGBT (insulated-gate bipolar transistor) device, a JFET (junction field-effect transistor) device, etc. In one embodiment, the semiconductor chip 120 is configured as a GaN HEMT device. The semiconductor chip 120 can have several of these and / or other devices. Examples in which several semiconductor chips 120 are mounted on the thermally conductive substrate 110 are considered. In the example of the semiconductor package 10 of . Fig. 1 The semiconductor chip 120 is configured as a lateral power transistor chip with gate-121, source-122 and drain-123 terminals of the semiconductor chip 120, which are located on a top surface 120 S, Uof the semiconductor chip 120. However, this example is not limiting, and other configurations of the semiconductor chip 120 are considered (e.g., a vertical power transistor).

[0016] The semiconductor chip 120 has a thickness t 120 in the z-direction of Fig. 1. In some embodiments, e.g., when the semiconductor chip 120 is configured as a GaN HEMT device, the thickness t is 120 of the semiconductor chip 120 at least 200 micrometers. In one embodiment, the thickness t is 120 of the semiconductor chip 120 approximately 250 micrometers or more.

[0017] According to one embodiment, the chip arrangement 100 has an electrically insulating thickness-matching layer 130, which is located on the planar upper surface 110 S, Uthe thermally conductive substrate 110 and surrounds the semiconductor chip 120. The electrically insulating thickness-matching layer 130 has a thickness t 130 on, which are essentially equal to a thickness t 120 of the semiconductor chip 120 plus a bond between the semiconductor chip 120 (e.g. a solder joint), such that an upper surface 130 S , U the electrically insulating thickness-adjustment layer 130 is essentially coplanar with the upper surface 120 S, U of the semiconductor chip 120. For example, the semiconductor chip 120 can have a thickness of approximately 250 and a bond between the semiconductor chip 120 and the planar upper surface 100. S, U It can have a thickness of approximately 25 micrometers. In this example, the thickness t would be 120 approximately 275 micrometers, and thus the corresponding electrically insulating thickness-adjustment layer 130 would also have a thickness t 130They measure approximately 275 micrometers. Together, they form the upper surface area of ​​130 S, U the electrically insulating thickness-adjustment layer 130 and the upper surface 120 S, U of the semiconductor chip 120 an upper surface 100 S, U of the chip arrangement 100. In the example of the semiconductor package 10 of Fig. 1 is the top surface 100 S, U The chip arrangement 100 is essentially coplanar with an upper surface area of ​​230 S, U of the core structure 230. The second 2102 of the dielectric laminate layers 210 is on (in some examples directly on) the upper surface 230 S, U the core structure 230 and the upper surface 100 S, U The chip arrangement 100 is formed.

[0018] The electrically insulating thickness-adjusting layer 130 can be formed from any electrically insulating material, such as a resin or another polymer, a polymer composite, etc. In some examples, the electrically insulating thickness-adjusting layer 130 is a molded layer formed from an electrically insulating molding compound. A molding compound is typically formed from an organic resin, such as an epoxy resin, and may contain fillers such as non-melting inorganic materials. Catalysts may be used to accelerate the curing reaction of the organic resin. Other materials, such as flame retardants, adhesion promoters, ion traps, stress relievers, dyes, etc., may optionally be added to the plastic encapsulation compound.In such examples, the electrically insulating thickness-adjusting layer 130 can be formed by injection molding, compression molding, film-assisted molding (FAM), reaction injection molding (RIM), resin transfer molding (RTM), blow molding, etc.

[0019] In the example of the semiconductor package 10 of Fig. 1 is the second 2102 of the dielectric laminate layers 210 between a third 2203 of the metallization layers 220 and the upper surface 100 S, UThe chip array 100 is arranged. In some examples, the third 2203 of the metallization layers 220 has a thickness of approximately 100 micrometers to approximately 150 micrometers, e.g., approximately 129 micrometers. A plurality of electrically conductive vias 240 extend through the second 2102 of the dielectric laminate layers 210 and connect each of the third 2203 of the metallization layers 220 to a terminal of the semiconductor chip 120 (e.g., the gate terminal 121, the source terminal 122, the drain terminal 123). The electrically conductive vias 240 can be made of electrically conductive metals such as copper, aluminum, tungsten, nickel, etc., and alloys or combinations thereof.

[0020] A fourth 2104 of the dielectric laminate layers 210 is arranged between the third 2203 of the metallization layers 220 and a fourth 2204 of the metallization layers 220. In some examples, the fourth 2104 of the dielectric laminate layers 210 has a thickness of about 50 micrometers to about 100 micrometers, e.g., about 70 micrometers. The fourth 2204 of the metallization layers 220 can have a thickness of about 50 micrometers to about 100 micrometers in some examples, e.g., about 66 micrometers. An additional electrically conductive via 240 extends through the fourth 2104 of the dielectric laminate layers 210 and connects the fourth 2204 of the metallization layers 220 to one of the plurality of electrically conductive vias 240 that extend through the second 2102 of the dielectric laminate layers 210.Alternatively, this additional electrically conductive via 240 or another additional electrically conductive via 240 extending through the fourth 2104 of the dielectric laminate layers 210 can electrically connect the fourth 2204 of the metallization layers 220 directly to a terminal of the semiconductor chip 120 (e.g. the gate terminal 121, the source terminal 122, the drain terminal 123).

[0021] The first 2101 of the dielectric laminate layers 210 is between a fifth 2205 of the metallization layers 220 and a lower surface 110 S,L of the thermally conductive substrate 110 arranged on the planar upper surface 110 S,Ua fifth dielectric laminate layer 210 is located opposite the thermally conductive substrate 110. A fifth dielectric laminate layer 210 is arranged between the fifth metallization layer 220 and a sixth metallization layer 220. In some examples, the fifth metallization layer 220 has a thickness of approximately 100 micrometers to approximately 150 micrometers, e.g., approximately 129 micrometers. In some examples, the fifth dielectric laminate layer 210 has a thickness of approximately 50 micrometers to approximately 100 micrometers, e.g., approximately 70 micrometers. In some examples, the sixth metallization layer 220 has a thickness of approximately 50 micrometers to approximately 100 micrometers, e.g., approximately 66 micrometers.

[0022] A multitude of thermally conductive vias 250 extend through the first 2101 of the dielectric laminate layers 210 and thermally connect the fifth 2205 of the metallization layers 220 to the thermally conductive substrate 110. The lower surface 110 S,L The thermally conductive substrate 110 is contacted by the thermally conductive vias 250. The thermally conductive vias 250 can comprise one or more materials with high thermal conductivity, e.g., copper, aluminum, tungsten, aluminum nitride, etc. The thermally conductive vias 250 can transfer heat to a lower surface 10. S,L derive from the semiconductor package 10.

[0023] The configuration of the laminate housing body 200 of the in Fig. The illustrated semiconductor package 10 is not limiting. The laminate package body 200 may have fewer or any number of additional dielectric laminate layers 210, metallization layers 220, electrically conductive vias 240, and / or thermally conductive vias 250 than those illustrated. Furthermore, the placement of the electrically conductive vias 240 and the thermally conductive vias 250 is not restricted to the upper or lower section of the laminate package body 200, respectively.

[0024] Fig. Figure 2 illustrates a top view of the chip arrangement 100 according to one embodiment. A section of the electrically insulating thickness-matching layer 130 is omitted to illustrate the electrically insulating thickness-matching layer 130, which is applied to the planar upper surface 110. S,Uof the thermally conductive substrate 110. The electrically insulating thickness-matching layer 130 surrounds the semiconductor chip 120. The upper surface 130 S,U the electrically insulating thickness-adjustment layer 130 and the upper surface 120 S,U The semiconductor chip's 120 form the upper surface 100 S,U of the chip arrangement 100.

[0025] Fig. Figure 3 illustrates a side cross-sectional view of the semiconductor package 10 according to one embodiment. The chip arrangement 100 of the semiconductor package 10 of Fig. Figure 3 features a thermally conductive substrate 110, which includes a ceramic layer 113 positioned between a first substrate metallization layer 111 and a second substrate metallization layer 112. The thermally conductive substrate 110 of this example can be a DCB or AMB substrate. The ceramic layer 113 can comprise aluminum nitride, aluminum oxide, silicon nitride, combinations thereof, etc. Each of the first substrate metallization layer 111 and the second substrate metallization layer 112 can comprise copper, aluminum, an alloy, etc. A plurality of thermally conductive vias 250 extend through the fifth 2105 of the dielectric laminate layers 210 and thermally connect each of the sixth 2206 of the metallization layers 220 to the fifth 2205 of the metallization layers 220.

[0026] Fig. Figures 4A-4F illustrate a method for forming the semiconductor package 10 according to one embodiment.

[0027] Fig. Figures 4A-4B illustrate the formation of the chip array 100. Fig. Figure 4A illustrates the mounting of the semiconductor chip 120 onto the planar upper surface 110 S,U of the thermally conductive substrate 110. The semiconductor chip 120 can be placed on the planar upper surface 110 S,U of the thermally conductive substrate 110 by soldering (e.g. diffusion soldering, soft soldering), sintering (e.g. Ag or Cu sintering, hybrid sintering), brazing, welding, gluing, bonding, etc.

[0028] Fig. Figure 4B illustrates the formation of the electrically insulating thickness-matching layer 130 on the planar upper surface 110 S,Uof the thermally conductive substrate 110. The electrically insulating thickness-matching layer 130 is designed to surround the semiconductor chip 120. The upper surface 130 S,U The electrically insulating thickness-adjustment layer 130 is essentially coplanar with an upper surface 120 S,U of the semiconductor chip 120. As previously noted, the electrically insulating thickness-matching layer 130 can be formed by a forming process such as injection molding, compression molding, film-assisted molding (FAM), reaction injection molding (RIM), resin transfer molding (RTM), blow molding, etc. In some examples, the formation of the electrically insulating thickness-matching layer 130 on the planar upper surface 110 exhibits S,U of the thermally conductive substrate 110 the application of a resin, a liquefied molding compound, etc. to the planar upper surface 110 S,Uand the hardening, solidification, etc., to form the electrically insulating thickness-matching layer 130. The partial chip assembly 100, which includes the semiconductor chip 120 mounted on the thermally conductive substrate 110, can be placed in a mold, and a liquefied molding compound can be injected into the mold to form the shaped electrically insulating thickness-matching layer 130. In some examples, the formation of the electrically insulating thickness-matching layer 130 on the planar upper surface 110 involves S,U of the thermally conductive substrate 110, the preforming of the electrically insulating thickness-adjusting layer 130 (e.g. by forming) and the application of the electrically insulating thickness-adjusting layer 130 to the planar upper surface 110 S,U of the thermally conductive substrate 110, e.g. by gluing, bonding, etc.

[0029] Fig. Figures 4C-4F illustrate the formation of the laminate housing body 200 by stacking the plurality of dielectric laminate layers 210 and metallization layers 210 on top of each other. As described in the Fig. As noted in point 1, the laminate housing body 200 can be formed using techniques similar to those used to form a printed circuit board (PCB). Fig. Figures 4D-4F illustrate the embedding of the chip arrangement 100 within the laminate housing body 200.

[0030] Fig. Figure 4C illustrates the formation of the core structure 230. The central opening 235 is formed by creating a central opening 235 through one of the dielectric laminate layers 210. The first 2201 and the second 2202 of the metallization layers 220 are formed on opposite sides of the third 2103 of the dielectric laminate layers.

[0031] Fig. Figure 4D illustrates the arrangement of the chip array 100 in the central opening 235 by the core structure 230 such that the upper surface 100 S, U The chip arrangement 100 is essentially coplanar with the upper surface 230 S, U of the core structure 230. In this step, the portion of the laminate housing body 200 can be provided on an external support (not shown), and the chip assembly 100 can be provided within the central opening 235. Sections of the central opening 235 not occupied by the chip assembly 100 can be filled with a resin (e.g., bismaleimide triazine) or other material to encapsulate the chip assembly 100 laterally.

[0032] Fig. Figure 4E illustrates the embedding of the core structure 230 and the chip array 100 between the first 2101 and the second 2102 of the dielectric laminate layers 210. The first 2101 and the second 2102 of the dielectric laminate layers 210 can be pre-formed and bonded to the core structure 230 and the chip array 100. In the Fig. In the illustrated example 4E, the second 2102 of the dielectric laminate layers 210 is placed directly on the upper surface 230. S, U the core structure 230 and the upper surface 100 S, U the chip arrangement 100 formed (e.g. glued).

[0033] Fig. Figure 4F illustrates the formation of the plurality of vias 240. The plurality of vias 240 can be formed by electroplating, electroless plating, or another method of depositing metal in holes 210. h, which are formed in the second 2102 of the dielectric laminate layer 210. The holes 210 h can be preformed with the second 2102 of the dielectric laminate layer 210 or can be formed after the second 2102 of the dielectric laminate layers 210 has formed on the upper surface 230 S, U the core structure 230 and the upper surface 100 S, U The chip arrangement can be formed by 100. For example, the holes can be 210 h They are formed through a lithography process and a subsequent etching process. A similar process can be used to create the in Fig. 1 and Fig. 3 illustrated thermally conductive vias to form 250.

[0034] The steps of Fig. 4E and Fig.4F can be repeated to form additional dielectric laminate layers 210, metallization layers 220, electrically conductive vias 240 and / or thermally conductive vias 250 of the laminate housing body 200.

[0035] Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation.

[0036] Example 1. A semiconductor package comprising: a laminate package body having a plurality of stacked dielectric laminate layers and metallization layers arranged between the dielectric laminate layers; and a chip assembly embedded within the laminate package body, the chip assembly comprising: a thermally conductive substrate having a planar top surface; a semiconductor chip mounted on the planar top surface of the thermally conductive substrate;and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor chip, wherein an upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor chip, and wherein the upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor chip form an upper surface of the chip assembly.

[0037] Example 2. Semiconductor package according to Example 1, wherein the laminate package body has a core structure embedded between a first of the dielectric laminate layers and a second of the dielectric laminate layers, wherein the chip arrangement is arranged within a central opening in the core structure, and wherein the top surface of the chip arrangement is substantially coplanar with a top surface of the core structure.

[0038] Example 3. Semiconductor package according to Example 2, wherein the second of the dielectric laminate layers is formed directly on the top surface of the core structure and the top surface of the chip array.

[0039] Example 4. Semiconductor package according to Example 2 or 3, wherein the core structure has a third of the dielectric laminate layers vertically between the first and second of the metallization layers.

[0040] Example 5. Semiconductor package according to one of Examples 1 to 4, wherein the semiconductor chip is configured as a lateral power transistor chip, and wherein the gate, source and drain terminals of the semiconductor chip are arranged on the top surface of the semiconductor chip.

[0041] Example 6. Semiconductor package according to Example 5, wherein the semiconductor chip is configured as a GaN HEMT device.

[0042] Example 7. Semiconductor package according to one of Examples 1 to 6, wherein a second of the dielectric laminate layers is arranged between a third of the metallization layers and the upper surface of the chip assembly, and wherein the semiconductor package further comprises a plurality of electrically conductive vias extending through the second of the dielectric laminate layers and each electrically connecting the third of the metallization layers to a terminal of the semiconductor chip.

[0043] Example 8. Semiconductor package according to Example 7, wherein a fourth of the dielectric laminate layers is arranged between the third of the metallization layers and a fourth of the metallization layers, and wherein the semiconductor package further comprises at least one additional electrically conductive via extending through the fourth of the dielectric laminate layers and electrically connecting the fourth of the metallization layers to at least one of the plurality of electrically conductive vias extending through the second of the dielectric laminate layers and / or to a terminal of the semiconductor chip.

[0044] Example 9. Semiconductor package according to any one of Examples 1 to 8, wherein a first of the dielectric laminate layers is arranged between a fifth of the metallization layers and a lower surface of the thermally conductive substrate, which is opposite the planar upper surface of the thermally conductive substrate, and wherein the semiconductor package further comprises a first plurality of thermally conductive vias extending through the first of the dielectric laminate layers and each thermally connecting the fifth of the metallization layers to the thermally conductive substrate.

[0045] Example 10. Semiconductor package according to Example 9, wherein a fifth of the dielectric laminate layers is arranged between the fifth of the metallization layers and a sixth of the metallization layers, and wherein the semiconductor package further comprises a second plurality of thermally conductive vias extending through the fifth of the dielectric laminate layers and thermally connecting the sixth of the metallization layers to the fifth of the metallization layers.

[0046] Example 11. Semiconductor package according to any of Examples 1 to 10, wherein the thermally conductive substrate is a metal structure, wherein a lower surface of the thermally conductive substrate, opposite the planar upper surface of the thermally conductive substrate, is contacted by thermally conductive vias which dissipate heat to a lower surface of the semiconductor package.

[0047] Example 12. Semiconductor package according to any of Examples 1 to 10, wherein the thermally conductive substrate has a ceramic layer arranged between a first substrate metallization layer and a second substrate metallization layer.

[0048] Example 13. Semiconductor package according to one of Examples 1 to 12, wherein a thickness of the electrically insulating thickness matching layer is essentially equal to a thickness of the semiconductor chip.

[0049] Example 14. Semiconductor package according to one of Examples 1 to 13, wherein the thickness of the semiconductor chip is at least 200 micrometers.

[0050] Example 15. Semiconductor package according to any of Examples 1 to 14, wherein the electrically insulating thickness-matching layer is a shaped layer formed from an electrically insulating molding compound.

[0051] Example 16. Method for forming a semiconductor package, the method comprising: forming a chip assembly by: mounting a semiconductor chip onto a planar top surface of a thermally conductive substrate, and forming an electrically insulating thickness-matching layer on the planar top surface of the thermally conductive substrate such that the electrically insulating thickness-matching layer surrounds the semiconductor chip and an top surface of the electrically insulating thickness-matching layer is substantially coplanar with a top surface of the semiconductor chip; forming a laminate package body by stacking a plurality of dielectric laminate layers and metallization layers one above the other; and embedding the chip assembly within the laminate package body by forming a central opening through one of the dielectric laminate layers and arranging the chip assembly in the central opening.

[0052] Example 17. Method according to Example 16, wherein the laminate housing body has a core structure having a third of the dielectric laminate layers vertically between the first and second of the metallization layers, wherein the central opening is formed by the core structure, and wherein the embedding of the chip arrangement within the laminate housing body comprises: arranging the chip arrangement in the central opening by the core structure such that an upper surface of the chip arrangement is substantially coplanar with an upper surface of the core structure, and embedding the core structure and the chip arrangement between a first of the dielectric laminate layers and a second of the dielectric laminate layers.

[0053] Example 18. Method according to Example 17, wherein the second of the dielectric laminate layers is formed directly on the upper surface of the core structure and the upper surface of the chip arrangement.

[0054] Example 19. Method according to any of Examples 16 to 18, wherein the semiconductor chip is configured as a lateral power transistor chip, and wherein the gate, source and drain terminals of the semiconductor chip are arranged on the top surface of the semiconductor chip.

[0055] Example 20. Method according to Example 19, wherein the semiconductor chip is configured as a GaN HEMT device.

[0056] Example 21. Method according to any of Examples 16 to 20, wherein the formation of the electrically insulating thickness-adjusting layer comprises a forming process which forms the electrically insulating thickness-adjusting layer as a shaped layer formed from an electrically insulating molding compound.

[0057] Terms like "first," "second," and the like are used to describe different elements, regions, sections, etc., and are not intended to be restrictive. The same terms refer to the same elements throughout the description.

[0058] As used herein, the terms "possessing," "containing," "including," "comprising," and the like are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0059] The expression "and / or" should be interpreted to include all possible conjunctive and disjunctive combinations unless explicitly stated otherwise. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same way as "and / or" unless explicitly stated otherwise. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0060] It is understood that the features of the various embodiments described herein may be combined with one another, unless expressly stated otherwise.

[0061] Although specific embodiments have been illustrated and described herein, it is understood by the person skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

Claims

[1] Semiconductor packages comprising: a laminate housing body comprising a plurality of stacked dielectric laminate layers and metallization layers arranged between the dielectric laminate layers; and a chip arrangement embedded in the laminate housing body, the chip arrangement is as follows: a thermally conductive substrate that has a planar upper surface; a semiconductor chip mounted on the planar upper surface of the thermally conductive substrate; and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor chip, wherein an upper surface of the electrically insulating thickness-matching layer is essentially coplanar with an upper surface of the semiconductor chip, and wherein the upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor chip form an upper surface of the chip assembly. [2] Semiconductor package according to claim 1, wherein the laminate housing body has a core structure that is embedded between a first of the dielectric laminate layers and a second of the dielectric laminate layers, wherein the chip arrangement is arranged within a central opening in the core structure, and wherein the upper surface of the chip array is essentially coplanar with an upper surface of the core structure. [3] Semiconductor package according to claim 2, wherein the second of the dielectric laminate layers is formed directly on the upper surface of the core structure and the upper surface of the chip arrangement. [4] Semiconductor housing according to claim 2 or 3, wherein the core structure has a third of the dielectric laminate layers vertically between the first and second of the metallization layers. [5] Semiconductor package according to one of claims 1-4, wherein the semiconductor chip is configured as a lateral power transistor chip, and wherein the gate, source and drain terminals of the semiconductor chip are arranged on the top surface of the semiconductor chip. [6] Semiconductor package according to claim 5, wherein the semiconductor chip is configured as a GaN HEMT device. [7] Semiconductor package according to any one of claims 1-6, wherein a second of the dielectric laminate layers is arranged between a third of the metallization layers and the upper surface of the chip assembly, and wherein the semiconductor package further comprises a plurality of electrically conductive vias extending through the second of the dielectric laminate layers and each electrically connecting the third of the metallization layers to a terminal of the semiconductor chip. [8] Semiconductor housing according to claim 7, wherein a fourth of the dielectric laminate layers is arranged between the third of the metallization layers and a fourth of the metallization layers, and wherein the semiconductor package further comprises at least one additional electrically conductive via extending through the fourth of the dielectric laminate layers and electrically connecting the fourth of the metallization layers to at least one of the plurality of electrically conductive vias extending through the second of the dielectric laminate layers and / or to a terminal of the semiconductor chip. [9] Semiconductor package according to any one of claims 1-8, wherein a first of the dielectric laminate layers is arranged between a fifth of the metallization layers and a lower surface of the thermally conductive substrate, which is opposite the planar upper surface of the thermally conductive substrate, and wherein the semiconductor package further comprises a first plurality of thermally conductive vias extending through the first of the dielectric laminate layers and thermally connecting the fifth of the metallization layers to the thermally conductive substrate. [10] Semiconductor package according to claim 9, wherein a fifth of the dielectric laminate layers is arranged between the fifth of the metallization layers and a sixth of the metallization layers, and wherein the semiconductor package further comprises a second plurality of thermally conductive vias extending through the fifth of the dielectric laminate layers, each thermally connecting the sixth of the metallization layers to the fifth of the metallization layers. [11] Semiconductor package according to one of claims 1-10, wherein the thermally conductive substrate is a metal structure, wherein a lower surface of the thermally conductive substrate, which is opposite the planar upper surface of the thermally conductive substrate, is contacted by thermally conductive vias which dissipate heat to a lower surface of the semiconductor package. [12] Semiconductor package according to one of claims 1-11, wherein the thermally conductive substrate has a ceramic layer arranged between a first substrate metallization layer and a second substrate metallization layer. [13] Semiconductor housing according to one of claims 1-12, wherein the thickness of the electrically insulating thickness-matching layer is essentially equal to the thickness of the semiconductor chip plus a bond between the semiconductor chip and the thermally conductive substrate. [14] Semiconductor package according to any one of claims 1-13, wherein the thickness of the semiconductor chip is at least 200 micrometers. [15] Semiconductor package according to any one of claims 1-14, wherein the electrically insulating thickness-matching layer is a shaped layer formed from an electrically insulating molding compound. [16] Method for forming a semiconductor package, the method comprising: Forming a chip array by: Mounting a semiconductor chip onto a planar top surface of a thermally conductive substrate, and Forming an electrically insulating thickness-matching layer on the planar upper surface of the thermally conductive substrate such that the electrically insulating thickness-matching layer surrounds the semiconductor chip and an upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor chip; Forming a laminate housing body by stacking a multitude of dielectric laminate layers and metallization layers on top of each other; and Embedding the chip assembly within the laminate housing body by forming a central opening through one of the dielectric laminate layers and arranging the chip assembly in the central opening. [17] Method according to claim 16, wherein the laminate housing body has a core structure which has a third of the dielectric laminate layers vertically between the first and second of the metallization layers, wherein the central opening is formed by the core structure, and wherein the embedding of the chip arrangement within the laminate housing body comprises the following: Arranging the chip array in the central opening through the core structure such that an upper surface of the chip array is substantially coplanar with an upper surface of the core structure, and Embedding the core structure and chip arrangement between a first dielectric laminate layer and a second dielectric laminate layer. [18] Method according to claim 17, wherein the second of the dielectric laminate layers is formed directly on the upper surface of the core structure and the upper surface of the chip arrangement. [19] Method according to one of claims 16-18, wherein the semiconductor chip is configured as a lateral power transistor chip, and wherein the gate, source and drain terminals of the semiconductor chip are arranged on the upper surface of the semiconductor chip, wherein, for example, the semiconductor chip is configured as a GaN HEMT device. [20] Method according to one of claims 16-19, wherein the formation of the electrically insulating thickness-adjusting layer comprises a forming process which forms the electrically insulating thickness-adjusting layer as a formed layer which is formed from an electrically insulating molding compound.

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