METHOD AND DEVICES FOR REGULATING AN AMPLIFIER

Abstract

Procedures, equipment, systems and products for controlling an amplifier are described.An exemplary apparatus includes a modulator; a comparator with one input and one output, wherein the input of the comparator is coupled to an output of the modulator; a first switch with one voltage source terminal and a second terminal; a second switch with one voltage source terminal and a second terminal; a resistor with one first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second terminal of the first switch and the second terminal of the second switch; a capacitor with one terminal coupled to the second terminal of the resistor; and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the capacitor and the second terminal of the resistor, and the output is coupled to an input of the modulator.

Description

TECHNICAL AREA

[0001] This description generally concerns amplifiers and more specifically methods and devices for controlling an amplifier. BACKGROUND

[0002] A computing device, such as a laptop, tablet, mobile phone, headphones, speakers, etc., may include one or more speakers to output audio generated by a processing unit or by an application implemented by the computing device or a connected computing device. Some computing devices use Class-D amplifiers. A Class-D amplifier is a switching amplifier that alternates between power rails to amplify an audio signal before it is applied to a speaker for output. Class-D amplifiers are efficient, small, inexpensive, and use less power than some other amplifiers. SUMMARY

[0003] An exemplary amplifier circuit includes a modulator with one input and one output; a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator; a first switch with one voltage source terminal and a second terminal; a second switch with one voltage source terminal and a second terminal; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch and the second terminal of the second switch; a first capacitor with one terminal, wherein the terminal of the first capacitor is coupled to the second terminal of the third switch;a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the first terminal of the first capacitor; a second capacitor with one terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch; and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the second capacitor and the second terminal of the fourth switch, and the output of the buffer is coupled to the input of the modulator. Further examples are described.

[0004] Another exemplary amplifier circuit includes a modulator with one input and one output; a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator; a first switch with one voltage source terminal and a second terminal; a second switch with one voltage source terminal and a second terminal; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch and the second terminal of the second switch; a first capacitor with one terminal, wherein the terminal of the first capacitor is coupled to the second terminal of the third switch;a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the first terminal of the first capacitor; a second capacitor with one terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch; and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the second capacitor and the second terminal of the fourth switch, and the output of the buffer is coupled to the input of the modulator. Further examples are described.

[0005] An exemplary apparatus includes an amplifier designed to convert an audio signal into a pulse-width modulated signal, the amplifier comprising: a modulator with a common-mode terminal; a comparator coupled to the modulator; a drive circuit arrangement coupled to the comparator; and a filter circuit arrangement coupled to the modulator, comprising: a first switch with a voltage source terminal and a second terminal; a second switch with a voltage source terminal and a second terminal; a third switch with a first terminal and a second terminal, the first terminal of the third switch being coupled to the second terminal of the first switch; a capacitor with one terminal, the terminal of the capacitor being coupled to the second terminal of the third switch;and a control designed to adjust a common-mode voltage supplied to the common-mode terminal of the modulator by controlling the first switch, the second switch, and the third switch. Further examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an exemplary computing device that includes a loudspeaker for outputting audio in the examples described herein. Fig. Figure 2 is a circuit diagram of an example of the amplifier from Fig. 1. Fig. 3 is a circuit diagram of an example of the modulator of Fig. 2. Fig. Figure 4 illustrates exemplary control phases of the switches in the amplifier of Fig. 2. Fig. Figure 5 is an example timing diagram showing voltages at different nodes of the amplifier. Fig. 2 corresponds. Fig. Figure 6 is a circuit diagram of an example of common-mode voltage delay control. Fig. 2. Fig. Figure 7 is an example timing diagram showing voltages at different nodes of the common-mode voltage delay control of Fig. 6 corresponds. Fig. Figure 8 is a flowchart that illustrates exemplary machine-readable instructions or exemplary operations that can be performed by the common-mode voltage delay control of Fig. 2 or a programmable circuit arrangement for implementing common-mode voltage delay control of Fig. 2 can be executed, instantiated, or performed. Fig. Figure 9 illustrates an alternative example circuit for implementing the common-mode voltage generation circuit arrangement of Fig. 2. Fig. Figure 10 is an exemplary timing diagram showing voltages at different nodes of the common-mode voltage generation circuit arrangement of Fig. 9 corresponds to. Fig. Figure 11 is an exemplary timing diagram showing voltages at different nodes of the common-mode voltage generation circuit arrangement of Fig. 9 and corresponding duty cycles of the amplifier of Fig. 2 corresponds. Fig. Figure 12 illustrates an exemplary state diagram representing the control of the switches of the common-mode voltage generation circuit arrangement of Fig. 9 corresponds. Fig. Figure 13 is a flowchart that presents exemplary machine-readable instructions or exemplary operations that can be performed by the common-mode voltage delay control of Fig. 9 or a programmable circuit arrangement for implementing common-mode voltage delay control of Fig. 9 can be executed, instantiated, or performed. Fig. Figure 14 is a block diagram of an exemplary processing platform that includes a programmable circuit arrangement structured to represent exemplary machine-readable instructions and / or exemplary operations of Fig. 8 or Fig. 13 to execute, instantiate, or perform the common-mode voltage delay control of Fig. 2 or Fig. 9 to implement.

[0006] The same reference numerals or other reference symbols are used in the drawings to denote the same or similar (functional or structural) features. DETAILED DESCRIPTION

[0007] The drawings are not necessarily to scale. Generally, identical reference numbers in one or more drawings and in this description refer to the same or similar parts. Although the drawings show areas with clean lines and boundaries, some or all of these lines or boundaries may be idealized. In reality, the boundaries or lines may be invisible, blended, or irregular.

[0008] Computing devices may contain or be connected to loudspeakers (e.g., via wired or wireless connections) to output audio. Such computing devices or loudspeakers may include an amplifier to boost the audio signal to drive the loudspeaker and output audio corresponding to the audio signal. Class-D audio amplifiers can be used to drive loudspeakers when high efficiency at high signal output power is required. An example audio signal path includes an input to receive a digital audio signal (e.g., from a processor), a digital-to-analog converter circuit to convert the received digital audio signal into an analog signal, and a Class-D amplifier to convert and boost the analog signal into a pulse-width modulated (PWM) high-voltage signal that drives a loudspeaker.

[0009] Some Class-D amplifiers use fully differential input audio signals. During power-up, state transitions, and so on, the Class-D amplifier initiates or terminates the generation of a pulse-width modulated signal with a specific duty cycle. For example, the duty cycle transition from a low duty cycle to a 50% duty cycle occurs during power-up, and from the 50% duty cycle back to a low duty cycle during power-down. The duty cycle of the Class-D amplifier can be controlled based on a common-mode voltage applied to a modulator within the Class-D amplifier. A common-mode voltage is a voltage at a node connected to both differential paths in an amplifier stage of the modulator. Therefore, changing the common-mode voltage adjusts the operation of the modulator.For example, a first common-mode voltage applied to the modulator might result in a 10% duty cycle, and a second common-mode voltage applied to the modulator might result in a 30% duty cycle. Any discrepancy between the resistance, capacitance, inductance, etc., in the components of the Class-D differential amplifier can lead to an increased offset at the Class-D amplifier's output. This increased offset contributes to an audible click or pop, or other audible degradation. For example, a click or pop can be caused by a DC offset, external LC filter mismatch, resistance mismatch between corresponding resistors in different differential paths, loop stabilization, etc.The clicking or popping sound occurs, for example, when the audio amplifier enters or exits a shutdown, sleep, standby mode, or any other state / mode transition.

[0010] Some techniques incorporate a circuit arrangement to linearly control the common-mode voltage, thus slowly increasing the duty cycle of the PWM signal output by the Class-D amplifier during dynamic transitions caused by component mismatch. For example, such a circuit arrangement can slowly increase (and decrease) the duty cycle linearly from 0% to 50% during power-up by gradually increasing (or decreasing) the common-mode voltage applied to the Class-D amplifier's modulator. However, such techniques result in long power-on or power-off times (e.g., greater than 10 milliseconds (ms)). Furthermore, these techniques require a large external capacitor (e.g., greater than 1 nanofarad), increasing both cost and footprint.Furthermore, with such techniques there can still be a pop of 0% to 5% duty cycle, since a low duty cycle and limited increase / decrease of a power stage can lead to loop instability of the class-D modulator.

[0011] Other techniques employ a hard duty cycle transition from an initial to a final duty cycle by applying a hard transition from an initial common-mode voltage to the final common-mode voltage. This allows for initial power-on with a low duty cycle to limit popping, followed by a transition to a higher duty cycle using a simple switching circuit arrangement. However, such techniques still result in popping if an inductor-capacitor (LC) mismatch exists at the speaker inputs; for example, the larger the LC mismatch, the greater the popping.

[0012] The examples described herein adjust the duty cycle nonlinearly to reduce popping more than the techniques above, in addition to lowering the transition time without using a larger external capacitor. Examples described herein set an initial common-mode voltage of the modulator to provide a high voltage, which is equivalent to enabling an output signal with a low duty cycle. On the initial common-mode voltage, the modulator can transient with a low PWM duty cycle, resulting in low popping. Examples described herein use a control protocol and filter circuit arrangement to gradually reduce the VCM with a delay to increase the PWM duty cycle until the final PWM duty cycle of 50% is set. Examples described herein result in a reduction of popping (e.g.,7.1-10.7 mV at an LC mismatch of 10 %) with a fast transition time (e.g. 1 ms) and small area requirement (e.g. 0.0084-0.109 square millimeters).

[0013] Fig. Figure 1 illustrates an exemplary vehicle device 100. The vehicle device 100 of Fig. Figure 1 includes an exemplary processing unit 102, an exemplary preprocessing circuit arrangement 104, an exemplary conversion circuit arrangement 106, an exemplary amplifier 108, an exemplary clock signal generation circuit arrangement 110, an exemplary filter 112, and an exemplary loudspeaker 114. Alternatively, one or more components of the vehicle device 100 may be implemented in another computing device such as a computer, laptop, television, mobile phone, tablet, monitor, receiver, set-top box, or any other type of computing device. Although the exemplary vehicle device 100 includes all of the components, one or more of the components may be implemented in one or more external devices.For example, the processing unit 102 and the preprocessing circuit arrangement 104 can be implemented in a first device such as a mobile phone, a laptop, a vehicle, etc. Furthermore, the conversion circuit arrangement 106, the amplifier 108, the clock signal generation circuit arrangement 110, the filter 112, and the loudspeaker 114 can be implemented in a second device such as an infotainment unit, loudspeakers, etc. Additionally, one or more of the components of the vehicle device 100 can be omitted or combined. Furthermore, additional components can be added to the vehicle device 100.

[0014] The processing unit 102 of Fig. 1 performs one or more functions based on applications or instructions. The processing unit 102 can be a central processing unit, a graphics processing unit, a digital signal processor, a microprocessor, a hard disk, a controller, a microcontroller, or any other processing unit. The processing unit 102 can execute or instantiate instructions or applications. The instructions or applications can generate or output an audio signal to be played through the exemplary loudspeaker 114. Accordingly, the processing unit 102 can output an audio signal to the loudspeaker 114 via the preprocessing circuit arrangement 104, the conversion circuit arrangement 106, the amplifier 108, and the filter 112. The processing unit 102 is coupled to the preprocessing circuit arrangement 104.

[0015] The preprocessing circuit arrangement 104 of Fig. Preprocessing circuit assembly 104 adapts the audio signal from processing unit 102 to optimize it, for example, to improve quality, add effects, change properties, etc. In some examples, preprocessing circuit assembly 104 includes a sound card. Preprocessing circuit assembly 104 receives the audio signal from processing unit 102, adapts the audio signal, and forwards the adapted audio signal to conversion circuit assembly 106. Preprocessing circuit assembly 104 is coupled to processing unit 102 and conversion circuit assembly 106.

[0016] The conversion circuit arrangement 106 of Fig. 1 converts a digital audio signal from the preprocessing circuit arrangement 104 into an analog audio signal. The conversion circuit arrangement 106 may include a digital-to-analog converter or other components to convert the digital audio signal into the analog audio signal. The conversion circuit arrangement 106 is coupled to the preprocessing circuit arrangement 104 and the amplifier 108.

[0017] The 108 amplifier from Fig. 1 converts the analog signal into a high-power PWM signal that can be used by the loudspeaker 114 to output audio. A high-power PWM signal can have an amplitude greater than 5 volts. As further described below, the amplifier 108 includes a circuit arrangement for reducing pops or clicks output by the loudspeaker 114 by controlling a common-mode voltage applied to a modulator of the amplifier 108. The amplifier 108 is coupled to the conversion circuit arrangement 106, the clock signal generation circuit arrangement 110, and the filter 112. The amplifier 108 is shown below in conjunction with Fig. 2 described in more detail.

[0018] The clock signal generation circuit arrangement 110 of Fig. 1 generates a clock signal that amplifier 108 uses to generate the common-mode voltage used to reduce pops or clicks. The clock signal generation circuit arrangement 110 may include an oscillator to generate the clock signal. The clock signal generation circuit arrangement 110 is coupled to amplifier 108.

[0019] The filter 112 from Fig. 1 is a low-pass filter that filters out high-frequency noise from the PWM signal generated by amplifier 108. Filter 112 can be an LC filter that includes at least one capacitor coupled to a common terminal (e.g., a ground terminal) and at least one inductor. Filter 112 is coupled to amplifier 108 and loudspeaker 114.

[0020] The speaker 114 from Fig. Speaker 1 plays audio based on the audio signal received by the conversion circuit arrangement 106. If the audio signal is, for example, music or speech, speaker 114 converts the audio signal into music or speech and plays it back. Speaker 114 is coupled to amplifier 108 via filter 112.

[0021] Fig. 2 includes an example of the 108 amplifier from Fig. 1. The 108 amplifier from Fig. Section 2 includes exemplary input resistor circuit arrangements 202a, 202b, exemplary feedback resistor circuit arrangements 204a, 204b, an exemplary modulator 206, exemplary comparators 208a, 208b, exemplary drive circuit arrangements 210a, 210b, an exemplary common-mode voltage generation circuit arrangement 212, and an exemplary control circuit arrangement 228. The common-mode voltage generation circuit arrangement 212 includes exemplary voltage sources 213, 215, exemplary switches 214, 216, 222, an exemplary resistor 218, an exemplary capacitor 220, an exemplary buffer 224, and an exemplary common-mode voltage delay control 226. Although Fig. 2 illustrates a full difference structure, can Fig. 2 be implemented in a single-entry closing system.

[0022] The input resistor circuit arrangements 202a, 202b of Fig. Each of the two circuits comprises a first terminal and a second terminal. The first terminal of input circuit arrangement 202a is coupled to the first differential output of conversion circuit arrangement 106. The first terminal of input circuit arrangement 202b is coupled to the second differential output of conversion circuit arrangement 106. The second terminal of resistor circuit arrangement 202a is coupled to resistor 228a, feedback resistors 204a, and modulator 206. The second terminal of resistor circuit arrangement 202b is coupled to feedback resistors 204b and modulator 206. As described below, the resistance of resistor circuit arrangements 202a and 202b corresponds to the gain of amplifier 108.

[0023] The feedback resistor circuit arrangements 204a, 204b of Fig. Each of the two circuits comprises a first terminal and a second terminal. The first terminal of the feedback resistor circuit arrangement 204a is coupled to the control circuit arrangement 210a and the filter 112. The first terminal of the feedback resistor circuit arrangement 204b is coupled to the control circuit arrangement 210b and the filter 112. The second terminal of the feedback resistor circuit arrangement 204a is coupled to the input resistor circuit arrangement 202a and the modulator 206. The second terminal of the feedback resistor circuit arrangement 204b is coupled to the input resistor circuit arrangement 202b and the modulator 206. The resistance of the feedback resistor circuit arrangement 204a controls the gain of the modulator 206.For example, the analog channel gain (G) = Rfb / Rin, where Rfb is the total resistance of the feedback resistor circuit arrangement 204a or 204b and Rin is the total resistance of the input resistor circuit arrangement 202a and 202b. Although... Fig. 2. Where the resistor circuit arrangements 202a, 202b, 204a, 204b are illustrated as individual resistors, one or more of the resistor circuit arrangements 202a, 202b, 204a, 204b can be implemented by one or more resistors and / or switches. For example, the resistor circuit arrangements 202a, 202b can be variable resistors implemented by a variety of resistors and switches that adjust the resistance based on the input audio signal to reduce noise.

[0024] The Modulator 206 from Fig. 2 includes a first differential input, a second differential input, a common-mode voltage (VCM) input, a first differential output, and a second differential output. The first differential input of modulator 206 is coupled to the input resistor circuit 202a and the feedback resistor 204a. The second differential input of modulator 206 is coupled to the input resistor circuit 202b and the feedback resistor 204b. The common-mode voltage (VCM) input is coupled to the output of buffer 224. The first differential output of modulator 206 is coupled to an input of comparator 208a. The second differential output of modulator 206 is coupled to an input of comparator 208b.Modulator 206 integrates the differential output signals of the output stage with the analog differential input audio signals, thereby forming a closed loop to remove or reduce errors in one or more output signals. The differential output signals of the output stage correspond to the voltages at the OUP node and the OUTN node. Modulator 206 supplies the differential output signals corresponding to the integrated output stage differential to the output signals of the drive circuit arrangements 210a and 210b. An example of modulator 206 is further described below in conjunction with [reference missing]. Fig. 3 described.

[0025] The comparators 208a, 208b of Fig. Each of the two components contains a first input, a second input, and an output. The first input of comparator 208a is... Fig. 2 is a non-inverting input. The first input of comparator 208a is coupled to the first output of modulator 206. The first input of comparator 208b is a non-inverting input. The first input of comparator 208b is a non-inverting input. The first input of comparator 208b is coupled to the second output of modulator 206. The second input of comparator 208a is an inverting input. The second input of comparator 208a is coupled to a triangle wave generator, which provides a triangle wave. The first output of comparator 208a is coupled to the control circuit arrangement 210a. The second output of comparator 208b is coupled to the control circuit arrangement 210b. The comparators 208a, 208b compare the differential output signals of the modulator 206 with one or more high-frequency signals, for example one or more triangle waves.If the triangle wave is higher than the analog voltage, for example, comparator 208a provides a logic high voltage. Otherwise, comparator 208a provides a logic low voltage. The output signals of comparators 208a and 208b correspond to one or more pulse trains, which are used to drive transistors to generate a high-voltage PWM signal for application to loudspeaker 114.

[0026] The control circuit arrangements 210a, 210b of Fig. Each of the two circuits comprises an input and an output. The input of the control circuit assembly 210a is coupled to the output of the comparator 208a. The input of the control circuit assembly 210b is coupled to the output of the comparator 208b. The output of the control circuit assembly 210a is coupled to the feedback circuit assembly 204a and the filter 112. The output of the control circuit assembly 210b is coupled to the feedback circuit assembly 204b and the filter 112. The control circuit assemblies 210a and 210b comprise high-power switching transistors and one or more drive circuits to control the high-power switching transistors based on one or more pulse series from the comparators 208a and 208b. The output of the high-power switching transistors is one or more pulse-width modulated signals that correspond to the input audio signal.The control circuit arrangements 210a, 210b supply the pulse width modulated signals to the filter 112.

[0027] The voltage sources 213, 215 of Fig. Each of the two components contains a terminal. The terminal of voltage source 213 is connected to a first terminal of switch 214. The terminal of voltage source 215 is connected to a first terminal of switch 216. Voltage sources 213 and 215 each supply a specific voltage. The voltage generated by voltage sources 213 and 215 is a common-mode voltage, which is ultimately applied to the common-mode terminal of modulator 206. The common-mode voltage corresponds to a specific duty cycle. For example, the first voltage source 213 can supply a voltage corresponding to a low duty cycle (e.g., <15%), while the second voltage source 215 can supply a voltage corresponding to a high duty cycle (e.g., 50%). Fig. 2 containing two voltage sources, there can be any number of voltage sources coupled to switches that are coupled to resistor 218 and switch 222.

[0028] Switches 214 and 216 of Fig. Each of the two switches includes a first terminal, a second terminal, and a control terminal. The first terminal of switch 214 is connected to the first voltage source 213. The first terminal of switch 216 is connected to the second voltage source 215. The first terminals of switches 214 and 216 are also referred to as voltage source terminals. The second terminal of switch 214 is connected to the second terminal of switch 216, the first terminal of switch 222, and the first terminal of resistor 218. The second terminal of switch 216 is connected to the second terminal of switch 214, the first terminal of switch 222, and the first terminal of resistor 218. The control terminals of switches 214 and 216 are each connected to the VCM delay control 226.Switches 214 and 216 can be individually controlled to operate as either an open or a closed connection, as described below. Switches 214 and 216 can be implemented using transistors, such as field-effect transistors.

[0029] The resistance 218 from Fig. 2 includes a first terminal and a second terminal. The first terminal of resistor 218 is connected to the second terminals of switches 214 and 216, and to the first terminal of switch 222. The second terminal of resistor 218 is connected to the second terminal of switch 222, the first terminal of capacitor 220, and the first input of buffer 224. Resistor 218 and capacitor 220 implement a filter circuit arrangement used to gradually match the voltages between VCM1 and VCM2.

[0030] The capacitor 220 from Fig. 2 includes a first terminal and a second terminal. The first terminal of capacitor 220 is connected to the second terminals of resistor 218 and switch 222, and to the first input of buffer 224. The second terminal of capacitor 220 is connected to a common terminal (e.g., a ground terminal). Capacitor 220 stores a charge to generate a voltage at the first input of buffer 224 based on the voltage from either the VCM1 voltage source 213 or the VCM2 voltage source 215, depending on the control of switches 214 and 216.

[0031] Switch 222 of Fig. 2 includes a first terminal, a second terminal, and a control terminal. The first terminal of switch 222 is connected to the second terminals of switches 214 and 216, and to the first terminal of resistor 218. The second terminal of switch 222 is connected to the second terminal of resistor 218, the first terminal of capacitor 220, and the first input of buffer 224. The control terminal of switch 222 is connected to the VCM delay control 226. Switch 222 can be controlled to operate as either an open or closed connection, as further described below.

[0032] The buffer 224 from Fig. The buffer 224 comprises a first input, a second input, and an output. The first input of the buffer 224 is a non-inverting connection. The first input of the buffer 224 is connected to the second terminals of switch 222 and resistor 218, and to the first terminal of capacitor 220. The second input of the buffer 224 is an inverting connection. The second input of the buffer 224 is connected to the output of the buffer 224 and the VCM terminal of modulator 206. The output of the buffer 224 is connected to the second input of the buffer 224 and the VCM terminal of modulator 206. The buffer 224 supplies the voltage at its first input to modulator 206 without drawing current from capacitor 220.

[0033] The VCM delay control 226 from Fig. The VCM delay controller 226 has three inputs and three outputs. The first input is connected to the control circuit assembly 228 to receive a state control signal. The second input is connected to the control circuit assembly 228 to receive a clock ratio control signal. The third input is connected to the clock generation circuit assembly 110 to receive a clock signal. The first output is connected to the control terminal of switch 214 to control switch 214. The second output of the VCM delay controller 226 is connected to the control terminal of switch 216 to control switch 216. The third output of the VCM delay control 226 is coupled to the control terminal of the switch 222 to control the switch 222.The VCM delay controller 226 controls switches 214, 216, and 222 in response to either a state control change and / or a clock ratio control change. For example, in response to a state change or a clock ratio control change, the VCM delay controller 226 supplies control signals to switches 214, 216, and 222 to switch from using the first voltage source 213 to charge capacitor 220 to using a second voltage source to charge capacitor 220. A state change can be a change from idle to playback, from low power to playback, from playback to idle, from playback to low power, and so on. The control sequence is shown below in conjunction with... Fig. 4 is described in more detail. The VCM delay control 226 can be implemented by any combination of hardware, software, or firmware. A hardware-based implementation of the VCM delay control 226 is described below in conjunction with Fig. 5 described.

[0034] The exemplary control circuit arrangement 228 of Fig. 2 includes a first terminal and a second terminal. The first and second terminals of the control circuit arrangement 228 are coupled to the VCM delay controller 226. The control circuit arrangement 228 can implement firmware to control or manage the operation of the amplifier 108. For example, the control circuit arrangement 228 can provide a state control signal that identifies when a state change is to occur. The control circuit arrangement 228 can also provide a clock ratio control signal that identifies when a clock ratio change is to occur. As described above, the state control signal and / or the clock ratio control signal can trigger the VCM delay controller 226 to adjust the VCM voltage applied to the VCM terminal of the modulator 206 from a first voltage to a second voltage.Changing the VCM voltage from the first to the second voltage adjusts the duty cycle of amplifier 108 from a first duty cycle to a second duty cycle.

[0035] Fig. Figure 3 is a circuit diagram of an example of the modulator 206 from Fig. 2. The modulator 206 includes exemplary full differential amplifiers 300, 306, exemplary resistors 302, 304 and exemplary capacitors 308, 310, 312, 314, 316, 318. Although Fig. 3 illustrates a full difference structure, can Fig. 3 be implemented in a single-entry closing system.

[0036] The first full differential amplifier 300 from Fig. The 300 amplifier has two inputs and two outputs. The first input is an inverting input. It is connected to the second terminal of capacitor 312, the second terminal of resistor 202a, and the second terminal of resistor 204a. The second input is a non-inverting input. It is connected to the second terminal of capacitor 318, the second terminal of resistor 202b, and the second terminal of resistor 204b. The first output is a non-inverting output. It is connected to the first terminal of capacitor 312, the first terminal of resistor 302, and the second terminal of capacitor 310. The second output is an inverting output.The second output of the full differential amplifier 300 is coupled to the first terminal of capacitor 318, the first terminal of resistor 304 and the second terminal of capacitor 316.

[0037] The resistors 302, 304 of Fig. Each of the three connections includes a first terminal and a second terminal. The first terminal of resistor 302 is connected to the first output of the full-differential amplifier 300, the first terminal of capacitor 312, and the second terminal of capacitor 310. The first terminal of resistor 302 is connected to the second output of the full-differential amplifier 300, the first terminal of capacitor 318, and the second terminal of capacitor 316. The second terminal of resistor 302 is connected to the first input of amplifier 306, the second terminal of capacitor 308, and the first terminal of capacitor 310. The second terminal of resistor 302 is connected to the second input of amplifier 306, the second terminal of capacitor 314, and the first terminal of capacitor 316.

[0038] The second full differential amplifier 306 from Fig. The 306 includes three inputs and two outputs. The first input of the 306 is an inverting input. This input is connected to the second terminal of capacitor 308, the second terminal of resistor 302, and the first terminal of capacitor 310. The second input of the 306 is a non-inverting input. This input is connected to the second terminal of capacitor 314, the second terminal of resistor 304, and the first terminal of capacitor 316. The VCM input of the 306 is connected to the output of buffer 224. Fig. 2 coupled. The first output of the full-differential amplifier 306 is a non-inverting output. The first output of the full-differential amplifier 306 is connected to the first terminal of the capacitor 308 and the comparator 208a of Fig. 2 coupled. The second output of the full-differential amplifier 306 is an inverting output. The second output of the full-differential amplifier 306 is connected to the first terminal of the capacitor 314 and the comparator 208b of Fig. 2 coupled.

[0039] The capacitors 308, 310, 312, 314, 316, 318 from Fig. Each of the 3 components contains two connections. The first connection of capacitor 308 is connected to the first output of amplifier 306 and comparator 208a. Fig. 2 coupled. The first terminal of capacitor 310 is coupled to the second terminal of capacitor 308, the second terminal of resistor 302, and the first input of amplifier 306. The first terminal of capacitor 312 is coupled to the first output of amplifier 300, the first terminal of resistor 302, and the second terminal of capacitor 310. The first terminal of capacitor 314 is coupled to the second output of amplifier 306 and comparator 208a. Fig. 2. The first terminal of capacitor 316 is connected to the second terminal of capacitor 314, the second terminal of resistor 304, and the second input of amplifier 306. The first terminal of capacitor 318 is connected to the second output of amplifier 300, the first terminal of resistor 304, and the second terminal of capacitor 316. The second terminal of capacitor 308 is connected to the first terminal of capacitor 310, the second terminal of resistor 302, and the first input of amplifier 306. The second terminal of capacitor 310 is connected to the first terminal of capacitor 312, the first output of amplifier 300, and the first terminal of resistor 302. The second terminal of capacitor 312 is connected to resistors 202a and 204a and the first input of amplifier 300.The second terminal of capacitor 314 is connected to the first terminal of capacitor 316, the second terminal of resistor 304, and the second input of amplifier 306. The second terminal of capacitor 316 is connected to the first terminal of capacitor 318, the second output of amplifier 300, and the first terminal of resistor 304. The second terminal of capacitor 318 is connected to resistors 202a and 204a and the second input of amplifier 300.

[0040] As described above, the modulator 206 uses one or more differential amplifiers 300, 306, resistors 302, 304, and one or more capacitors 308, 310, 312, 314, 316, 318 to combine the differential output signals of the output stage with the analog differential input audio signals, thereby forming a closed loop to remove or reduce errors in the one or more output signals. The modulator 206 supplies the differential output signals corresponding to the integrated output stage differential to the output signals of the drive circuit arrangements 210a, 210b.

[0041] Fig. Figure 4 illustrates different phases of the control of switches 214, 216, and 222 during a first and a second state change. The first state change could, for example, correspond to a change from phase a to phase c. The second state change could, for example, correspond to a step change from phase c to phase e. Fig. Section 4 includes exemplary phases 400, 402, 404, 406, and 408. Fig. 4 also includes the voltage sources 213, 215, the switches 214, 216, 222, the resistor 218, the capacitor 220 and the buffer 224 of Fig. 2. In Fig. Phase 4 is a first phase, phase b is a second phase, phase c is a third phase, phase d is a fourth phase and phase 3 is a fifth phase.

[0042] The first phase 400 of Fig. 4 corresponds to a low-power state / mode, idle state / mode, off state / mode, etc. In the first phase 400, the VCM delay controller 226 provides control signals to close switches 214 and 222 and open switch 216. This applies the first voltage source VCM1 213 to capacitor 220. Therefore, the voltage at the first input of buffer 224 is equal to VCM1. Since buffer 224 supplies the voltage at its first input to the VCM terminal of modulator 206, buffer 224 supplies the VCM1 voltage to the VCM terminal of modulator 206. Therefore, amplifier 108 starts a duty cycle signal with a first duty cycle, for example, less than 10%. In the second phase 402, after a change of state, the VCM delay control 226 provides control signals to close switch 216 and open switches 214 and 222.Therefore, the second voltage source 215 is coupled to resistor 218 to cause capacitor 220 to discharge from the VCMI voltage to the VCM2 voltage. Consequently, the voltage at the first input of buffer 224 drops exponentially to the VCM2 voltage. Accordingly, the duty cycle increases logarithmically from the first duty cycle to a second duty cycle, for example, 50%. In the third phase 404, the VCM duty control 226 provides control signals to open switch 214 and close switches 216 and 222. This causes the voltage at the first input of buffer 224 to settle at the VCM2 voltage, thus setting the duty cycle to the second duty cycle. Furthermore, short-circuiting resistor 218 prevents leakage currents through resistor 218.

[0043] After a state change back to sleep mode / state from playback mode / state, the third phase 404 of Fig. 4 to the fourth phase 406. In the fourth phase 406, the VCM delay control 226 provides control signals to close switch 214 and open switch 216. Therefore, the first voltage source 213 is coupled to resistor 218 to cause capacitor 220 to charge from the VCM2 voltage to the VCM1 voltage. Consequently, the voltage at the first input of buffer 224 increases logarithmically to the VCM1 voltage. Accordingly, the duty cycle decreases exponentially from the second duty cycle to the first duty cycle, for example, to a duty cycle of less than 10%. In the fifth phase 408, the VCM duty cycle control 226 provides control signals to open switch 216 and close switches 214 and 222. This causes the voltage at the first input of buffer 224 to be set to the VCMI voltage, which in turn causes the duty cycle to be set to the first duty cycle.Furthermore, short-circuiting resistor 218 prevents leakage currents through resistor 218.

[0044] Fig. Figure 5 is an exemplary timing diagram 500, illustrating voltage signals 502, 504, 506, 508, the different nodes in amplifier 108 of Fig. The first voltage signal, 502, is a state control signal corresponding to the voltage at the state control terminal of the control circuit assembly 228. The second voltage signal, 504, is a duty cycle control signal corresponding to the voltage at the duty cycle control terminal of the control circuit assembly 228. The third voltage, 506, is a VCM delay activation signal corresponding to the voltage output at the control terminal of the switch 222. The fourth voltage, 508, is the VCM signal corresponding to the voltage output from the buffer 224 to the VCM terminal of the modulator 206.

[0045] The timing diagram 500 of Fig. Step 5 begins with amplifier 108 operating in a standby mode. In response to the first voltage signal 502 transitioning from a standby to a playback mode by passing to a logic high voltage, and the second voltage signal 504 passing to a logic low voltage, the VCM delay control 226 opens switches 214 and 222 and closes switch 216, causing voltage signal 506 to decrease exponentially from the VCMI voltage to the VCM2 voltage. After a threshold time interval, the third voltage signal 506 decreases to a logic low voltage, closing switch 222 and causing the fourth voltage signal 508 to be fixed at the VCM2 voltage.

[0046] In response to the fact that the first voltage signal 502 from Fig. When the second voltage signal 504 transitions to a logic low voltage and the second voltage signal 504 transitions to a logic high voltage to transition from the playback state to the idle state, the VCM delay control 226 opens switches 216 and 222 and closes switch 214, causing the voltage signal 506 to rise logarithmically from the VCM2 voltage to the VCM1 voltage. After a threshold time interval, the third voltage signal 506 decreases to a logic low voltage, closing switch 222 and causing the fourth voltage signal 508 to be set to the VCM1 voltage.

[0047] Fig. Section 6 includes an exemplary hardware implementation of the VCM delay control 226 from Fig. 2. Fig. Section 6 includes exemplary logic gates 602, 604, 608, 612 and exemplary flip-flops 606, 610, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632. Although Fig. Figure 6 illustrates an exemplary hardware implementation of the VCM delay control 226; however, there may be alternative ways to implement the VCM delay control 226 to control the switches 214, 216, and 222 of Fig. 2 based on the in Fig. to control the 4 described phases.

[0048] The logic gate 602 from Fig. The 602 logic gate is a logic N-gate (also called an inverter). The 602 logic gate includes one input and one output. The input of the 602 logic gate is connected to the control circuit arrangement 228. Fig. 2 coupled to the duty cycle control signal (e.g., signal 504 from Fig. 5) and receive an input from flip-flop 606. The output of logic gate 602 is coupled to an input of flip-flop 610. Logic gate 602 inverts the duty cycle control signal. For example, if the duty cycle control signal is a logic low voltage, logic gate 602 outputs a logic high voltage. Conversely, if the duty cycle control signal is a logic high voltage, logic gate 602 outputs a logic low voltage. Accordingly, since the duty cycle control signal b is at the output of logic gate 602, the duty cycle control signal b is the inverse of the duty cycle control signal; for example, if the duty cycle control signal is high, the duty cycle control signal b is low, and vice versa.

[0049] The logic gate 604 from Fig. 6 is a logic AND gate. The logic gate 604 includes a first input, a second input, and an output. The first input of the logic gate 604 is coupled to the flip-flop 622 to receive the DIV32 turn-on signal. The second terminal of the logic gate 604 is connected to the control circuit arrangement 228 of Fig. 2 coupled to the state control signal (e.g., signal 502 from Fig. 5) to record. The output of logic gate 604 is coupled to flip-flop 606. Logic gate 604 provides a logic high voltage when the voltages at both inputs correspond to logic high voltages. Otherwise, logic gate 604 provides a logic low voltage.

[0050] The 606 flip-flop from Fig. The 606 is a D-type flip-flop. It includes three inputs and one output. The first input is a clock input, which is connected to the control circuit arrangement 228. Fig. The second terminal of flip-flop 606 is coupled to the input of logic gate 602 to receive the duty cycle control signal. The second terminal of flip-flop 606 is coupled to a voltage source that generates a logic high voltage (e.g., a voltage regulator). The third input of flip-flop 606 is an inverting input coupled to the output of logic gate 604. The output of flip-flop 606 is coupled to logic gate 612 and flip-flops 614, 616, 618, 620, and 622 to provide the software turn-on signal. Flip-flop 606 generates a logic high pulse at its output when the state control and duty cycle control transition from a first state to a second state. The output of logic gate 604 drives a reset signal for flip-flop 606. Furthermore, DIV32_einschalten is a logic high by default. When the state control is a logic low, flip-flop 606 is in a reset state.After the state control changes to a logic high, flip-flop 606 begins to function. When the duty cycle control signal rises from a logic low to a logic high, the SW power-on output signal becomes a logic high, which triggers logic gate 612 to provide a logic high at the VCM_delay_EN terminal. As further described below, a logic high at the SW power-on terminal then causes flip-flops 614, 616, 618, 620, and 622 to operate. After a delay, DIV32_power-on changes to a logic low, causing flip-flop 606 to return to a reset state and the SW power-on output signal to return to a logic low.

[0051] The logic gate 608 from Fig. 6 is a logic AND gate. The logic gate 608 includes a first input, a second input, and an output. The first input of the logic gate 608 is coupled to the flip-flop 632 to receive the DIV32 turn-off signal. The second terminal of the logic gate 608 is connected to the control circuit arrangement 228 of Fig. 2 coupled to the state control signal (e.g., signal 502 from Fig. 5) to record. The output of logic gate 608 is coupled to flip-flop 610. Logic gate 608 provides (e.g., outputs) a logic high voltage when the voltages at both inputs correspond to logic high voltages. Otherwise, logic gate 608 provides a logic low voltage.

[0052] The 610 flip-flop from Fig. Flip-flop 610 is a D-type flip-flop. It holds the output signal until a subsequent rising or falling edge of the input signal is detected, and the process repeats. Flip-flop 610 has three inputs and one output. The first input is the clock input, which is coupled to the output of logic gate 602 to receive a duty cycle control signal, b. The b signal is the inverse of the duty cycle control signal. The second input of flip-flop 610 is coupled to a voltage source that generates a logic high voltage (e.g., a voltage regulator). The third input of flip-flop 610 is an inverting input, which is coupled to the output of logic gate 608. The output of flip-flop 610 is coupled to logic gate 612 and flip-flops 624, 626, 628, 630, and 632 to provide the DIV32 off signal. The output signal of logic gate 608 drives a reset signal for flip-flop 610.Furthermore, the DIV32_off signal is a logic high by default. When the state control signal is a logic low, flip-flop 606 is in a reset state. After the state control changes to a logic high, flip-flop 610 begins to function. When the duty cycle control signal falls from a logic high to a logic low, duty cycle_control_b increases due to logic gate 602. Therefore, the SW off output signal becomes a logic high, which triggers logic gate 612 to provide a logic high at the VCM_delay_EN terminal. As further described below, a logic high at the SW off terminal causes flip-flops 624, 626, 628, 630, and 632 to operate.DIV32_switchoff switches to a logic low after some delay, causing the flip-flop 610 to return to its reset state, and causing the SW switch-off output signal to return to a logic low.

[0053] The logic gate 612 from Fig. Logic gate 612 is a logic OR gate. It includes a first input, a second input, and an output. The first input of logic gate 612 is connected to flip-flops 614, 616, 618, 620, 622, and the output of flip-flop 606 to receive a SW_on signal. The second input of logic gate 612 is connected to flip-flops 624, 626, 628, 630, 632, and the output of flip-flop 610 to receive the SW_off signal. The output of logic gate 612 is connected to the control terminal of switch 222. Fig. The two components are coupled to control the switch 222. The logic gate 612 provides a logic high voltage if either the SW_on signal or the SW_off signal is high. If both the SW_on signal and the SW_off signal are low, the logic gate 612 provides a logic low voltage.

[0054] The flip-flops 614, 616, 618, 620, 622 from Fig. 6 generate the DIV32_switch-on signal based on the SW_switch-on signal and a clock signal. The DIV32_switch-on signal is a logic high voltage until the SW_switch-on signal decreases to a low signal. When the SW_switch-on signal decreases to a low signal, the DIV_switch-on signal pulses to a logic low signal. Flip-flops 614, 616, 618, 620, and 622 each have three inputs and one output. The first input is a clock input terminal of flip-flop 614, which is connected to the clock generation circuit arrangement 110. Fig. The first inputs are clock inputs of flip-flops 616, 618, 620, and 622, which are coupled to the output of a previous flip-flop in the system, for example, one or more of flip-flops 614, 616, 618, and 620. The second inputs are the first inverted inputs of flip-flops 614, 616, 618, 620, and 622, which are coupled to the output of flip-flop 606 and the first input of logic gate 612 to receive the SW_on signal. Each of the third inputs of flip-flops 614, 616, 618, 620, 622 is coupled to the output of the corresponding flip-flop 614, 616, 618, 620, 622 and the clock input of a subsequent flip-flop 616, 618, 620, 622. For example, the third input of flip-flop 614 is coupled to the output of flip-flop 614 and the clock input of flip-flop 616.Each output of flip-flops 614, 616, 618, 620, 622 is connected to the third input of the corresponding flip-flop 614, 616, 618, 620, 622 and the clock input of a subsequent flip-flop 616, 618, 620, 622. The output of flip-flop 622 corresponds to the DIV32_on pin, which is connected to the first input of logic gate 604.

[0055] The flip-flops 624, 626, 628, 630, 632 from Fig. 6 generate the DIV32_off signal based on the SW_off signal and a clock signal. The DIV32_off signal is a logic high voltage until the SW_off signal decreases to a low signal. When the SW_off signal decreases to a low signal, the DIV_on signal pulses to a logic low signal. Flip-flops 624, 626, 628, 630, and 632 each have three inputs and one output. The first input is a clock input terminal of flip-flop 624, which is connected to the clock generation circuit arrangement 110. Fig. The first inputs are clock inputs of flip-flops 626, 628, 630, and 632, which are coupled to the output of a previous flip-flop in the system, for example, one or more of flip-flops 624, 626, 628, and 630. The second inputs are the first inverted inputs of flip-flops 624, 626, 628, 630, and 632, which are coupled to the output of flip-flop 606 and the first input of logic gate 612 to receive the SW_off signal. Each of the third inputs is a second inverted input of flip-flops 624, 626, 628, 630, 632, which is coupled to the output of the corresponding flip-flop 624, 626, 628, 630, 632 and the clock input of a subsequent flip-flop 626, 628, 630, 632. For example, the third input of flip-flop 624 is coupled to the output of flip-flop 624 and the clock input of flip-flop 626.Each output of flip-flops 624, 626, 628, 630, 632 is connected to the third input of the corresponding flip-flop 624, 626, 628, 630, 632 and the clock input of a subsequent flip-flop 626, 628, 630, 632. The output of flip-flop 632 corresponds to the DIV32_switchoff pin, which is connected to the first input of logic gate 608.

[0056] Fig. Figure 7 is an exemplary timing diagram 700, illustrating voltage signals 702, 704, 706, 708, 710, 712, 714, 716, which represent the different nodes in the circuit arrangement implementation of the VCM delay control 226. Fig. The first voltage signal, 702, is a CLK signal corresponding to the voltage output by the clock generation circuit arrangement 110 and received at the clock input of flip-flops 614 and 624. The second voltage signal, 704, is a state control signal corresponding to the voltage output by the control circuit arrangement 228 and received at the second inputs of logic gates 604 and 608. The third voltage signal, 706, is a clock ratio control signal corresponding to the voltage output by the control circuit arrangement 228 and received at the clock input of flip-flops 606 and 610. The fourth voltage, 708, is a DIV turn-on signal or a DIV32 turn-on signal corresponding to the voltage output by flip-flop 622 and received at the first input of logic gate 604.The fifth voltage, 710, is a DIV off signal or a DIV32 off signal, corresponding to the voltage output by flip-flop 632 and at the first input of logic gate 608. The sixth voltage, 712, is a SW on signal, corresponding to the voltage output by flip-flop 606 and received at the second inputs of flip-flops 614, 616, 618, 620, and 622. The seventh voltage, 714, is a SW off signal, corresponding to the voltage output by flip-flop 610 and received at the second inputs of flip-flops 624, 626, 628, 630, and 632. The eighth voltage 716 is a VCM delay activation signal, corresponding to the voltage output by logic gate 612 and connected to the control terminal of switch 222. Fig. 2 is created.

[0057] After the clock control voltage 704 rises to a high voltage and the duty cycle control voltage 706 falls to a low voltage, the flip-flop 606 adjusts the SW turn-on voltage 712 from a logic low to a logic high voltage. Because the SW turn-on voltage 712 is high, the output signal of logic gate 612 rises to a logic high voltage, as shown in the VCM delay activation voltage 716. The flip-flop 606 maintains the high voltage for the SW turn-on voltage 712 until the DIV_turn_on voltage 708 pulses low. After the DIV_turn_on voltage 708 pulses low, the flip-flop 606 reduces the SW turn-on voltage 712 to a logic low voltage.

[0058] After the duty cycle control voltage 706 rises back to a logic high, flip-flop 610 increases the SW turn-off voltage 714 to a logic high. Since the SW turn-off voltage 714 is high, the output signal of logic gate 612 rises to a logic high, as shown in the VCM delay-enable voltage 716. Flip-flop 610 maintains the high voltage for the SW turn-off voltage 714 until the DIV_turn-off voltage 710 pulses low. After the DIV_turn-off voltage 710 pulses low, flip-flop 610 reduces the SW turn-off voltage 714 to a logic low.

[0059] Fig. Figure 8 is a flowchart that represents exemplary machine-readable instructions or exemplary operations 800 that can be executed, instantiated and / or performed by a programmable circuit arrangement to control the switches 214, 216, 222 of Fig. 2 to control in order to reduce popping or clicking during a state or mode change. The exemplary machine-readable instructions or the exemplary operations 800 of Fig. The eighth stage begins at block 802, where the VCM delay control 226 controls switches 214, 216, and 222 to operate in sleep, off, or low-power mode. For example, in sleep mode, the VCM delay control 226 closes switches 214 and 222 and opens switch 216.

[0060] At block 804, the VCM delay control 226 determines whether a state change to playback mode has occurred. For example, the VCM delay control 226 receives a state control signal from the control circuit arrangement 228. Fig. 2, which indicates whether a state change has occurred. If the VCM delay control 226 determines that no state change to playback mode has occurred (Block 804: NO), the control returns to Block 802. If the VCM delay control 226 determines that a state change to playback mode has occurred (Block 804: YES), the VCM delay control 226 determines whether a duty cycle control signal has changed (Block 806), for example, from a logic high voltage to a logic low voltage. The duty cycle control signal is a signal received by the control circuit arrangement 228 to indicate that the duty cycle is changing based on the state change.

[0061] If the VCM delay control 226 detects that the duty cycle control signal has not changed (Block 806: NO), the control returns to Block 804. If the VCM delay control 226 detects that the duty cycle control signal has changed (Block 806: YES), the VCM delay control 226 adjusts the control of the VCM switches to couple the VCM2 voltage to the RC filter (Block 808). For example, the VCM delay control 226 opens switch 214 to disconnect the first voltage source 213, closes switch 216, and opens switch 222 to couple the second voltage source 215 to resistor 218 and capacitor 220, which form the filter circuit arrangement. In block 810, the VCM delay control 226 determines whether a threshold time interval has elapsed. The threshold time interval can correspond to the capacitance and resistance of the filter circuit arrangement.If the VCM delay controller 226 determines that the threshold time interval has not elapsed (Block 810: NO), the controller returns to Block 810. If the VCM delay controller 226 determines that the threshold time interval has elapsed (Block 810: YES), the VCM delay controller 226 decouples resistor 218 from the filter circuit arrangement by closing switch 222 in parallel with resistor 218 (Block 812). By closing switch 222, the VCM delay controller 226 shorts the terminals of resistor 218, causing the voltage output by buffer 224 to stabilize at the VCM2 voltage.

[0062] At block 814, the VCM delay controller 226 determines whether a duty cycle control signal has changed, for example, from a logic low voltage to a logic high voltage. If the VCM delay controller 226 determines that the duty cycle control signal has not changed (block 814: NO), the controller returns to block 814. If the VCM delay controller 226 determines that the duty cycle control signal has changed (block 814: YES), the VCM delay controller 226 couples resistor 218 to the filter circuit arrangement by opening switch 222, which is in parallel with resistor 218 (block 816). At block 818, the VCM delay controller 226 adjusts the control of the VCM switches to couple the VCMI voltage to the RC filter.For example, the VCM delay controller 226 closes switch 214 to couple the first voltage source 213 to resistor 218, and opens switch 216 to disconnect the second voltage source 215 from resistor 218. At block 820, the VCM delay controller 226 determines whether a threshold time interval has elapsed. The threshold time interval can correspond to the capacitance and resistance of the filter circuit arrangement. If the VCM delay controller 226 determines that the threshold time interval has not elapsed (block 820: NO), the controller returns to block 820. If the VCM delay control 226 determines that the threshold time interval has elapsed (Block 820: YES), the VCM delay control 226 decouples the resistor 218 from the filter circuit arrangement by closing the switch 222 in parallel with the resistor 218 (Block 822).By closing the switch 222, the VCM delay control 226 shorts the terminals of the resistor 218, causing the voltage supplied by the buffer 224 to stabilize at the VCMI voltage.

[0063] Fig. Figure 9 illustrates an exemplary common-mode voltage generation circuit arrangement 900, which is an alternative implementation of the common-mode voltage generation circuit arrangement 212 of Fig. 2 is. The common-mode voltage generation circuit arrangement 900 of Fig. 9 includes exemplary voltage sources 901, 903, 905, 907, 909, exemplary switches 902, 904, 906, 908, 910, 912, 914, exemplary capacitors 916, 918, an exemplary buffer 920, and an exemplary VCM delay control 922. Although the example of Fig. Since the circuit contains 9 5 voltage sources coupled to 5 switches, there can be any number of voltage sources or switches. Instead of the filter circuit arrangement of Fig. The filter circuit arrangement includes resistor 218, capacitor 220 and switch 222. Fig. 9 a switching capacitor configuration that includes switches 912, 914 and capacitors 916, 918. The switched capacitor configuration simulates a resistor. Accordingly, both the filter circuit arrangement of Fig. 2 and the filter circuit arrangement of Fig. Switch 9 acts as an RC filter to provide non-linear VCM voltage adjustment for duty cycle matching. Switch 902 corresponds to switch S1, switch 904 corresponds to switch S2, switch 906 corresponds to switch S3, switch 908 corresponds to switch S4, switch 910 corresponds to switch S5, switch 912 corresponds to switch SC1, and switch 914 corresponds to switch SC1b.

[0064] The voltage sources 901, 903, 905, 907, 909 of Fig. Each of the two terminals contains one connection. The connection of voltage source 901 is connected to the first terminal of switch 902. The connection of voltage source 903 is connected to the first terminal of switch 904. The connection of voltage source 905 is connected to the first terminal of switch 906. The connection of voltage source 907 is connected to the first terminal of switch 908. The connection of voltage source 909 is connected to the first terminal of switch 910. Voltage sources 901, 903, 905, 907, and 909 each supply a specific voltage. The voltage generated by the voltage sources 901, 903, 905, 907, 909 is a common-mode voltage, which is ultimately applied to the common-mode terminal of the modulator 206 via a filter circuit arrangement comprising switches 912, 914 and capacitors 916, 918. The common-mode voltage corresponds to a specific duty cycle.For example, the first voltage source 901 can supply a voltage corresponding to a low duty cycle (e.g. 10%), the second voltage source 903 can supply a voltage corresponding to a slightly higher duty cycle (e.g. 20%), ..., and the fifth voltage source 909 can supply a voltage corresponding to a high duty cycle (e.g. 50%).

[0065] Switches 902, 904, 906, 908, 910 of Fig. Each of the two switches has a first terminal, a second terminal, and a control terminal. The first terminal of switch 902 is connected to the first voltage source 901. The first terminal of switch 904 is connected to the second voltage source 903. The first terminal of switch 906 is connected to the third voltage source 905. The first terminal of switch 908 is connected to the fourth voltage source 907. The first terminal of switch 910 is connected to the fifth voltage source 909. The first terminal of switch 912 is connected to the second terminals of switches 902, 904, 906, 908, and 910. The first terminal of switch 914 is connected to the second terminal of switch 912 and the first terminal of capacitor 916. The first terminals of switches 902, 904, 906, 908, 910 are also referred to as voltage source terminals.The second terminal of switch 902 is connected to the second terminals of switches 904, 906, 908, 910, and the first terminal of switch 912. The second terminal of switch 904 is connected to the second terminals of switches 902, 906, 908, 910, and the first terminal of switch 912. The second terminal of switch 906 is connected to the second terminals of switches 902, 904, 908, 910, and the first terminal of switch 912. The second terminal of switch 908 is connected to the second terminals of switches 902, 904, 906, 910, and the first terminal of switch 912. The second terminal of switch 910 is connected to the second terminals of switches 902, 904, 906, 908 and the first terminal of switch 912. The second terminal of switch 912 is connected to the first terminal of switch 914 and the first terminal of capacitor 916.The control terminals of switches 902, 904, 906, 908, 910, 912, and 914 are each coupled to the VCM delay control 922. Switches 902, 904, 906, 908, 910, 912, and 914 can be individually controlled to operate as either an open or closed connection, as further described below. Switches 902, 904, 906, 908, 910, 912, and 914 can be implemented using transistors such as field-effect transistors.

[0066] The capacitors 916, 918 from Fig. Each of the nine components has a first terminal and a second terminal. The first terminal of capacitor 916 is connected to the second terminal of switch 912 and the first terminal of switch 914. The first terminal of capacitor 918 is connected to the second terminal of switch 914 and the first input of buffer 920. The second terminals of capacitors 916 and 918 are connected to a common terminal (e.g., a ground terminal). When switch 912 is closed and switch 914 is open, capacitor 916 stores a charge from the voltage source, based, for example, on which of the switches 902, 904, 906, 908, or 910 is closed. When switch 912 is open and switch 914 is closed, capacitor 916 discharges to charge capacitor 918.The charge stored in capacitor 918 generates a voltage at the first terminal of buffer 920, which is supplied to the common-mode terminal of modulator 206.

[0067] The buffer 920 from Fig. Buffer 920 comprises a first input, a second input, and an output. The first input of buffer 920 is a non-inverting connection. The first input of buffer 920 is connected to the second terminal of switch 914 and the first terminal of capacitor 918. The second input of buffer 920 is an inverting connection. The second input of buffer 920 is connected to the output of buffer 920 and the VCM terminal of modulator 206. The output of buffer 920 is connected to the second input of buffer 920 and the VCM terminal of modulator 206. Buffer 920 supplies the voltage at its first input to modulator 206 without drawing current from capacitor 916.

[0068] The VCM delay control 922 from Fig. The VCM 922 includes three inputs and several outputs. The first input is coupled to the control circuit arrangement 228 to receive a state control signal. The second input is coupled to the control circuit arrangement 228 to receive a clock ratio control signal. The third input is coupled to the clock generation circuit arrangement 110 to receive a clock signal. The outputs of the VCM 922 are coupled to the respective control terminals of switches 902, 904, 906, 908, 910, 912, and 914. The VCM delay control 922 controls the switches 902, 904, 906, 908, 910, 912, 914 based on either a state control change and / or a clock ratio control change.For example, the VCM delay control 922 switches switches 912 and 914 on and off in response to a change in state and / or a change in the duty cycle control; for example, when switch 912 is open, switch 914 is closed, and vice versa. Furthermore, the VCM delay control 922 supplies control signals to switches 902, 904, 906, 908, and 910 to switch from using the first voltage source 901 to charge one or more capacitors 916 and 918 to using a second voltage source to charge one or more capacitors 916 and 918. The control of switches 902, 904, 906, 908, 910, 912, and 914 together with capacitors 916 and 918 is described below in conjunction with... Fig. further described on pages 10-13. The VCM delay control 922 can be implemented by any combination of hardware, software, or firmware.

[0069] Fig. Figure 10 illustrates a timing diagram 1000, which includes exemplary signals 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016, 1020. The voltage signal 1002 is a state control signal that corresponds to the control circuit arrangement 228. Fig. The voltage signal 1004 is a duty cycle control signal corresponding to the voltage output by the control circuit arrangement 228. The control signal 1006 is an S1 control signal corresponding to the voltage output from the VCM delay control 922 to the control terminal of switch 902. The control signal 1008 is an S2 control signal corresponding to the voltage output from the VCM delay control 922 to the control terminal of switch 904. The control signal 1010 is an S3 control signal corresponding to the voltage output from the VCM delay control 922 to the control terminal of switch 906. The control signal 1012 is an S4 control signal corresponding to the voltage output from the VCM delay control 922 to the control terminal of switch 908. The control signal 1014 is an S5 control signal that corresponds to the voltage output from the VCM delay control 922 to the control terminal of the switch 910.Control signal 1016 is an SC1 control signal corresponding to the voltage output from VCM delay control 922 to the control terminal of switch 912. Control signal 1018 is an SC1b control signal corresponding to the voltage output from VCM delay control 922 to the control terminal of switch 914. Voltage signal 1020 is a VCM signal corresponding to the voltage at the output of buffer 920 applied to the common-mode voltage terminal of modulator 206.

[0070] When amplifier 108 is in standby mode, the state control signal 1002 is low, the duty cycle control signal 1004 is high, the first control signal 1006 is high, control signals 1016 and 1018 are high, and control signals 1008, 1010, 1012, and 1014 for the other switches are low. Accordingly, switches 902, 912, and 914 are closed, so the VCMI voltage source 901 is applied to the input of buffer 920. Therefore, the VCM voltage 1020 remains at the VCMI voltage corresponding to a first duty cycle (e.g., 10%). When the amplifier 108 enters a playback mode, the state control signal 1002 is high, the duty cycle control signal 1004 is low, which triggers the VCM delay control 922 to start switching the switches 912, 914 using the pulsating differential signal 1016, 1018.Furthermore, the VCM delay control 922 reduces the first control signal 1006 and increases the second control signal 1008 to open the first switch 902 and close the second switch 904, thereby reducing the voltage applied to capacitors 916 and 918 to the VCM2 voltage. Therefore, the VCM voltage 1020 provided by buffer 920 is reduced to the VCM2 voltage, which is applied to modulator 206 to increase the duty cycle to a second duty cycle (e.g., 20%).

[0071] After a certain period, the VCM delay control 922 reduces the second control voltage 1008 to a logic low voltage and increases the third control voltage 1010 to a logic high voltage. This closes the switch 906, allowing the third voltage source 905 to charge the capacitor 916, 918, thereby reducing the voltage at the input of the buffer 920 to VCM3. Consequently, the VCM voltage 1020 provided by the buffer 920 decreases to the VCM3 voltage applied to the modulator 206 to increase the duty cycle to a third duty cycle (e.g., 30%). This process continues by activating and deactivating (closing and opening or connecting and disconnecting) switches to reduce the VCM voltage 1020 until the final voltage source 909 is coupled to the filter circuit arrangement which includes capacitors 916, 918.When the final voltage source 909 is coupled to the filter circuit arrangement, the amplifier operates in playback mode with a final duty cycle (e.g., 50%). When the duty cycle control signal 1004 rises again to a logic high voltage to return to idle or low-power mode, the process is repeated in reverse order to raise the VCM voltage 1020 to the VCM1 voltage. Therefore, the duty cycle decreases from 50% to 10%.

[0072] Fig. Figure 11 illustrates a timing diagram 1100, which shows the VCM voltage 1102 supplied by buffer 920 and the corresponding duty cycle 1104 of amplifier 108. For example, when the VCM voltage 1102 is at the first VCM1 voltage, the duty cycle 1104 is 10%. When the VCM voltage 1102 is at the second VCM2 voltage, the duty cycle 1104 is 20%. When the VCM voltage 1102 is at the second VCM2 voltage, the duty cycle 1104 is 30%. When the VCM voltage 1102 is at the second VCM2 voltage, the duty cycle 1104 is 40%. If the VCM voltage 1102 is on the second VCM2 voltage, the duty cycle 1104 is 50%. However, other voltages can be used that correspond to other duty cycles.

[0073] Fig. Figure 12 is an example state diagram 1200, illustrating exemplary states when transitioning from a first state to a second state. For example, when the duty cycle control changes from an idle state to a playback state, the VCM voltage decreases further from the first state S1 through the other states to a fifth state. Fig. In equation 12, the first state S1 corresponds to a duty cycle of 10%, the second state S2 to a duty cycle of 20%, the third state S3 to a duty cycle of 30%, the fourth state S4 to a duty cycle of 40%, and the fifth state S5 to a duty cycle of 50%. When the duty cycle control changes from a playback state to an idle state, the VCM voltage increases further from the fifth state S5 through the other states to the first state S1.

[0074] Fig. Figure 13 is a flowchart that represents exemplary machine-readable instructions or exemplary operations 1300 that can be executed, instantiated and / or performed by a programmable circuit arrangement to control the switches 902, 904, 906, 908, 910, 912, 914 of Fig. 9 to control in order to reduce popping or clicking during a state or mode change. The exemplary machine-readable instructions or the exemplary operations 1300 of Fig. The 13th section begins at block 1302, where the VCM delay control 922 controls switches 902, 904, 906, 908, 910, 912, and 914 to operate in idle, off, or low-power mode. For example, in idle mode, the VCM delay control 922 closes switches 902, 912, and 914 and opens switches 904, 906, 908, and 910 to ensure that the voltage at the output of buffer 920 and the VCM input of modulator 206 is equal to the voltage of the first voltage source 901 (VCM1).

[0075] At block 1304, the VCM delay control 922 determines whether a state change to playback mode has occurred. For example, the VCM delay control 922 receives a state control signal from the control circuit arrangement 228. Fig. 2, which indicates whether a state change has occurred. If the VCM delay control 922 determines that no state change to playback mode has occurred (Block 1304: NO), the control returns to Block 1302. If the VCM delay control 922 determines that a state change to playback mode has occurred (Block 1304: YES), the VCM delay control 922 determines whether a duty cycle control signal has changed (Block 1306), for example, from a logic high voltage to a logic low voltage. The duty cycle control signal is a signal received from the control circuit arrangement 228 to indicate that the duty cycle is changing based on the state change.

[0076] If the VCM delay control 922 determines that a duty cycle control signal has not changed (Block 1306: NO), the control returns to Block 1304. If the VCM delay control 922 determines that the duty cycle control signal has changed (Block 1306: YES), the VCM delay control 922 begins toggling switches 912 and 914 between open and closed (Block 1308). For example, the VCM delay control 922 supplies a first pulsed signal to the control terminal of switch 912 and a second pulsed signal, differential to the first pulsed signal, to the control terminal of switch 914, so that switch 914 is open when switch 912 is closed, and vice versa.

[0077] At block 1310, the VCM delay controller 922 adjusts the control of switches S1-S5 to couple a subsequent voltage source to the filter circuit arrangement, which includes switches 912, 914 and capacitors 916, 918. For example, if the first switch 902 was initially closed to couple the first voltage source 901 to the filter circuit arrangement, the VCM delay controller 922 opens the first switch 902 and closes the second switch 904 to couple the second voltage source 903 to the filter circuit arrangement. At block 1312, the VCM delay controller 922 determines whether a threshold time interval has elapsed. The threshold time interval can be based on the capacitance of capacitors 916, 918. If the VCM delay control 922 determines that the threshold time interval has not elapsed (Block 1312: NO), the control returns to Block 1312.

[0078] If the VCM delay control 922 determines that the threshold time has elapsed (Block 1312: YES), it determines whether there is a subsequent switch that has not yet been closed (Block 1314). For example, if the second switch 904 is currently closed, the VCM delay control 922 determines that the third switch still needs to be closed, since the switches are closed sequentially. If the VCM delay control 922 determines that there is a subsequent switch that has not yet been closed (Block 1314: YES), the control returns to Block 1310 to continue closing switches sequentially until the last switch has been activated.If the VCM delay control 922 determines that there is no downstream switch that has not yet closed (Block 1314: NO), then the VCM delay control 922 stops toggling switches 912 and 914 and keeps them closed (Block 1316). In this way, the final voltage source 909 applies the VCM5 voltage to the buffer 920, causing the amplifier 108 to operate at the playback duty cycle (e.g., 50%). At Block 1318, the VCM delay control 922 determines whether a duty cycle control signal has changed, which corresponds to a return to a standby state. If the VCM delay control 922 detects that the duty cycle control signal has changed (block 1318: YES), the control returns to block 1308 to repeat the process, but in reverse order of the switches. For example, activating switch 910, then 908, then 906, ... and finally switch 902.If the VCM delay control 922 determines that the duty cycle control signal has not changed (Block 1318: NO), the instructions end.

[0079] Fig. Figure 14 is a block diagram of an exemplary programmable circuit arrangement platform 1400, which is structured to show the exemplary machine-readable instructions of the exemplary operations of Fig. 8 and Fig. 13 to execute or instantiate the VCM delay control 226, 922 of Fig. 2 or Fig. 9 to implement. The Programmable Circuit Assembly Platform 1400 can be, for example, a personal computer, an infotainment system, a processing unit within a vehicle device, a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad™), an organizer (PDA), a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or any other portable device or any other type of computing or electronic device.

[0080] The programmable circuit assembly platform 1400 of the illustrated example also includes a programmable circuit assembly 1412. The programmable circuit assembly 1412 of the illustrated example is hardware. The programmable circuit assembly 1412 can be implemented, for example, by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers of any desired family or from any desired manufacturer. The programmable circuit assembly 1412 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit assembly 1412 implements the VCM delay controller 226 of Fig. 2 or the VCM delay control 922 from Fig. 9.

[0081] The programmable circuit arrangement 1412 of the illustrated example includes a local memory 1413 (e.g., a buffer, register, etc.). The programmable circuit arrangement 1412 of the illustrated example communicates via a bus 1418 with a main memory 1414, 1416, which includes volatile memory 1414 and non-volatile memory 1416. The volatile memory 1414 can be implemented by synchronous dynamic random-access memory (SDRAM), dynamic random-access memory (DRAM), dynamic RAMBUS® random-access memory (RDRAM®), or any other type of RAM device. The non-volatile memory 1416 can be implemented by flash memory or any other type of storage device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417.In some examples, the memory control 1417 can be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family or manufacturer, or any other type of circuit arrangement to manage the data flow to and from the main memory 1414, 1416.

[0082] The programmable circuit assembly platform 1400 of the illustrated example also includes an interface circuit assembly 1420. The interface circuit assembly 1420 can be implemented by hardware of any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect Express (PCIe) interface.

[0083] In the illustrated example, one or more input devices 1422 are connected to the interface circuit arrangement 1420. The one or more input devices 1422 enable a user (e.g., a human user, a machine user, etc.) to input data or commands into the programmable circuit 1412. The one or more input devices 1422 can be implemented, for example, by an audio sensor, a microphone, a camera (still image or video), a keyboard, a button, a mouse, a touchscreen, or a speech recognition system.

[0084] One or more output devices 1424 are also connected to the interface circuit arrangement 1420 of the illustrated example. The one or more output devices 1424 can be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), a fixed switching display (IPS), a touchscreen, etc.), a tactile output device, or a loudspeaker. The interface circuit arrangement 1420 of the illustrated example therefore typically includes a graphics driver card, a graphics driver chip, or a graphics driver processor circuit arrangement, such as a GPU.

[0085] The interface circuit arrangement 1420 of the illustrated example also includes a communication device such as a transmitter, receiver, transceiver, modem, local gateway, wireless access point, or network interface to enable the exchange of data with external machines (e.g., computing devices of any type) through a network 1426. Communication may be effected, for example, by an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a wireless over-the-line system, a wireless line-of-sight system, a cellular telephone system, an optical link, etc.

[0086] The programmable circuit arrangement platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 for storing firmware, software, or data. Examples of such mass storage disks or devices 1428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices such as flash memory devices or SSDs.

[0087] The machine-readable instructions 1432, which are provided by the machine-readable instructions of Fig. 8 and Fig. 13 may be implemented, may be stored in the mass storage device 1428, in volatile memory 1414, in non-volatile memory 1416 or on at least one non-transient computer-readable storage medium such as a CD or DVD, which may be removable.

[0088] While in Fig. 2 or Fig. 9 an exemplary way of implementing VCM delay control 226, 922 of Fig. As illustrated in 1, one or more of the following can be used: Fig. 2 or Fig. The 9 illustrated elements, processes, or devices may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the exemplary VCM delay control 226, 922 of Fig. 2 or Fig. 9 can be implemented solely by hardware or by hardware in combination with software and firmware. Therefore, for example, any of the VCM delay controllers 226, 922 could be implemented by a programmable circuit arrangement in combination with machine-readable instructions (e.g., firmware or software), a processor circuit arrangement, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more ASICs, one or more programmable logic devices (PLDs), or one or more field-programmable logic devices (FPLDs), such as FPGAs. Furthermore, the exemplary VCM delay controller 226, 922 from FIGS: 2 or 9 can be implemented in addition to or instead of the one(s) in Fig. 2 or Fig. 9 may contain one or more illustrated elements, processes or devices, or may contain more than one or all of the illustrated elements, processes and devices.

[0089] One or more flowcharts representative of exemplary machine-readable instructions that can be executed by a programmable circuit arrangement to control the VCM delay control 226, 922 of Fig. 2 or Fig. 9 at least to implement and / or instantiate, or are representative of exemplary operations that can be performed by a programmable circuit arrangement to control the VCM delay control 226, 922 of Fig. 2 or Fig. 9 at least to implement and / or instantiate are in Fig. 8 and Fig. 13 shown. The machine-readable instructions can be one or more executable programs or one or more parts of one or more executable programs for execution by a programmable circuit arrangement, such as the programmable circuit arrangement 1412 shown below in conjunction with Fig. The exemplary processor platform 1400 discussed in Section 14 is shown, and can be one or more functions or one or more parts of functions to be performed by a programmable circuit arrangement (e.g., an FPGA). In some examples, the machine-readable instructions cause an operation, task, etc., to be performed or carried out in the real world in an automated manner. As used herein, "automated" means without human intervention.

[0090] The program may be formulated as instructions (e.g., software or firmware) stored on one or more non-transient computer-readable or machine-readable storage media, such as one or a combination of intermediate storage, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disc, a compact disc (CD), a digital versatile disc (DVD), etc.), a redundant array of independent disks (RAID), a register, a ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., random-access memory (RAM) of any type, etc.), or any other storage device or storage disk.The instructions of the non-transient, computer-readable, or machine-readable medium can be programmed or executed by a programmable circuit arrangement located in one or more hardware devices, but the entire program or parts thereof could alternatively be executed or instantiated by one or more hardware devices that are not part of the programmable circuit arrangement or are implemented in dedicated hardware. The machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., a server and a client hardware device). The client hardware device can be, for example, an endpoint client hardware device (e.g., a hardware device associated with a human or machine user) or an inter-client hardware device gateway (e.g., a server).a wireless access network (RAN) that can enable communication between a server and an endpoint client hardware device may be implemented. Similarly, the non-transient machine-readable storage medium may include one or more media. Furthermore, although the example program, with respect to the one or more in . Fig. 8 and Fig. As described in the 13 illustrated flowcharts, many other methods can alternatively be used to implement the VCM delay control 226, 922. For example, the order of execution of the blocks of one or more flowcharts can be changed, or some of the described blocks can be modified, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, discrete integrated analog or digital circuit arrangement, an FPGA, an ASIC, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The programmable circuit arrangement can be distributed across different network locations or local on one or more hardware devices (e.g.,The programmable circuit arrangement can be, for example, one of or a combination of a CPU and / or an FPGA located in the same package (e.g., in the same integrated circuit (IC) package or in two or more separate packages), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0091] The machine-readable instructions described herein may be stored in one or more compressed, encrypted, fragmented, compiled, executable, packaged, and other formats. Machine-readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.)) or a data structure (e.g., one or more sections of instructions, code, representations of code, etc.) that can be used to construct, manufacture, or generate machine-executable instructions.The machine-readable instructions may be fragmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations within a network or collection of networks (e.g., in the cloud, on edge devices, etc.). The machine-readable instructions may require one or more of the following actions: installation, modification, adaptation, updating, combining, augmentation, configuration, decryption, decompression, unpacking, distribution, remapping, compilation, etc., to make them directly readable, interpretable, or executable by a computing device or other machine.For example, the machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, or stored on separate computing devices, and these parts, when decrypted, decompressed, or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions or operations which together may form a program such as the one described here.

[0092] In another example, the machine-readable instructions might be stored in a state where they can be read by a programmable circuit arrangement, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a specific computing device or other device. In yet another example, the machine-readable instructions might need to be configured (e.g., settings saved, data entered, network addresses recorded, etc.) before the machine-readable instructions, or one or more corresponding programs, can be executed in whole or in part.Thus, machine-readable, computer-readable, or machine-readable media, as used herein, may contain one or a combination of instructions or one or more programs, irrespective of the specific format or state of the machine-readable instructions or the one or more programs.

[0093] The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0094] As mentioned above, the exemplary operations of Fig. 8 and Fig. 13. are implemented using executable instructions (e.g., computer-readable or machine-readable instructions) stored on one or more non-transient computer-readable or machine-readable media. As used herein, the terms non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium, or non-transient machine-readable storage medium are expressly defined to include any type of computer-readable storage device or storage disk and to exclude propagating signals and transmission media.Examples of such non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium, or non-transient machine-readable storage medium include one or more optical storage devices, magnetic storage devices, a hard disk drive (HDD), flash memory, read-only memory (ROM), a CD, a DVD, a buffer, RAM of any type, a register, or any other storage device or storage disk on which information is stored for any duration (e.g., for extended periods, permanently, for brief moments, for temporary buffering, for intermediate storage of information).As used herein, the terms “non-transient computer-readable storage medium” and “non-transient machine-readable storage medium” are defined to include any physical (mechanical, magnetic, electromechanical, or electrical) hardware for storing information for a specified period of time, but exclude propagating signals and transmission media. Examples of non-transient computer-readable storage devices or non-transient machine-readable storage devices include one or a combination of random-access storage of any type, read-only storage of any type, solid-state storage, flash memory, optical disks, magnetic disks, disk drives, or RAID (Redundant Array of Independent Disks) systems.As used herein, the term “device” refers to a physical structure such as one of, or a combination of, mechanical, electromechanical or electrical equipment, hardware or circuit arrangement which may or may not be configured by, or made to execute, computer-readable instructions, machine-readable instructions, etc.

[0095] The descriptors “first,” “second,” “third,” etc., are used herein to identify multiple elements or components that can be referred to separately. Unless otherwise stated or evident from their context of use, such descriptors do not imply any meaning of priority, physical order, arrangement in a list, or chronological sequence, but are used simply as labels to refer to multiple elements or components separately to facilitate understanding of the examples described. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element in a claim is referred to by a different descriptor, such as “second” or “third.” In such cases, these descriptors are used only to simplify the reference to multiple elements or components.

[0096] In the description and claims, the terms "including" and "comprising" and their variants shall be understood to be inclusive in a similar way to the term "comprehensive," unless otherwise specified. Unless otherwise specified, "approximately," "about," or "essentially" before a value means + / - 10% of the stated value. In another example, "approximately," "about," or "essentially" before a value means + / - 5% of the stated value. In yet another example, "approximately," "about," or "essentially" before a value means + / - 1% of the stated value.

[0097] The terms "couple," "coupled," "couples," and variations thereof, as used herein, can encompass connections, communications, or signal paths that enable a functional relationship in accordance with this description. For example, if a device A generates a signal to control a device B to perform an action, in a first example, device A is coupled to device B; or, if a second exemplary device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not substantially alter the functional relationship between device A and device B, device B is controlled by device A via the control signal generated by device A. Furthermore, the terms "couple," "coupled," "couples," and variations thereof include any indirect or direct electrical or mechanical connection.

[0098] A device that is "designed" to perform a task or function may be configured (e.g., programmed or hardwired) by a manufacturer at a point in time to perform that function, or it may be configurable (or reconfigurable) by a user after manufacture to perform that function or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the design or layout of hardware components and interconnections of the device, or a combination thereof.

[0099] Although they are in Fig.Unless otherwise indicated, components or elements of systems and circuits illustrated in Figures 1-4 have one or more conductors or terminations that allow signals to enter or leave the components or elements. The conductors or terminations (or parts thereof) may be referred to here as pins, pads, terminals (including, for example, inputs, outputs, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0100] As used herein, a “terminal” of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally means a conductor, such as a wire, trace, pin, terminal block, or other connection or intermediate link that enables the component, device, system, etc., to connect electrically or mechanically to another component, device, system, etc. A terminal may be used, for example, to receive or provide analog or digital electrical signals (or simply signals), or to electrically connect to a ground or earth reference. Accordingly, an input is used to receive a signal from another component, device, system, etc. An output is used to provide a signal to another component, device, system, etc.Other connections can be used to link a ground, earth, or reference voltage, such as a reference terminal or a ground terminal. A connection on an IC or PCB can also be called a pin (an elongated conductor) or pad (a planar conductor). A node refers to a junction or connection point between two or more connections. An example number of connections and nodes may be shown; however, depending on the specific circuit or system topology, there may be more or fewer connections and nodes. In some cases, the terms "connection," "node," "connection," "pad," and "pin" may be used interchangeably.

[0101] The expression “or”, as used, for example, in a form such as A, B or C, denotes any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A with B, (5) A with C, (6) B with C or (7) A with B and with C.

[0102] As used herein, a “programmable circuit arrangement” is defined as comprising at least one of (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific functions or one or more specific operations, and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware,which is implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors such as central processing units (CPUs) that can execute first instructions to perform one or more operations or functions; field-programmable gate arrays (FPGAs) that can be programmed with second instructions to at least configure and / or structure the FPGAs to instantiate one or more operations or functions according to the first instructions; graphics processing units (GPUs) that can execute first instructions to perform one or more operations or functions; digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions; XPUs; network processing units (NPUs); and one or more microcontrollers that can execute first instructions.to perform one or more operations or functions, or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes several types of programmable circuit arrangements (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and one or more arbitrary combinations thereof) and orchestration technology (e.g., one or more application programming interfaces (API(s))) that can assign one or more computing tasks to the one or more of the several types of programmable circuit arrangement best suited to perform the one or more computing tasks.

[0103] As used herein, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more components consisting of an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, a system-on-a-chip (SoC), etc.

[0104] As used herein, the terms "terminal," "node," "intermediate," "pin," and "conduit" are used interchangeably. Unless expressly stated otherwise, these terms are generally used to denote an intermediate connection between, or a termination of, a device element, circuit element, integrated circuit, appliance, other electronics, or semiconductor component.

[0105] In the description and claims, the described "circuit arrangement" may include one or more circuits. A circuit or device described herein as including certain components may instead be designed to be coupled with these components to form the described circuit arrangement or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as one or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage or current sources) may instead only include the semiconductor elements within a single physical device (e.g., a circuit board).a semiconductor die and / or an IC package) and may be designed to be coupled with at least some of the passive elements or sources to form the described structure either at a time of manufacture or after a time of manufacture, for example by at least one end user and / or a third party.

[0106] The circuits described herein are reconfigurable to include the replaced components in order to provide functionality that is at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise specified, are generally representative of any one or more elements coupled in series and / or parallel to provide an impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes.These can be capacitors coupled in series between the same two nodes as the single resistor or capacitor. Although certain elements of the described examples are contained within an integrated circuit and other elements are external to the integrated circuit, in other embodiments additional or fewer features may be integrated into the integrated circuit. Furthermore, some or all of the features illustrated as external to the integrated circuit may be contained within the integrated circuit, and some features illustrated as internal to the integrated circuit may be implemented outside of the integrated circuit.As used herein, the term “integrated circuit” means one or more circuits that are at least one of the following: (i) embedded in / over a semiconductor substrate; (ii) embedded in a single semiconductor package; (iii) embedded in the same module; or (iv) embedded in / on the same printed circuit board.

[0107] Exemplary methods, devices, systems, and manufactures for controlling an amplifier are described herein. Further examples and combinations thereof include the following: Example 1 includes an amplifier circuit comprising a modulator with one input and one output, a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator, a first switch with one voltage source terminal and one second terminal, a second switch with one voltage source terminal and one second terminal, a resistor with one first terminal and one second terminal, wherein the first terminal of the resistor is coupled to the second terminal of the first switch and the second terminal of the second switch, a capacitor with one terminal coupled to the second terminal of the resistor, and a buffer with one input and one output.wherein the input of the buffer is coupled to the terminal of the capacitor and the second terminal of the resistor, wherein the output of the buffer is coupled to the input of the modulator.

[0108] Example 2 includes the amplifier circuit of Example 1, which further includes a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch, the second terminal of the second switch and the first terminal of the resistor, wherein the second terminal of the third switch is coupled to the second terminal of the resistor, the terminal of the capacitor and the input of the buffer.

[0109] Example 3 includes the amplifier circuit from Example 2, which further includes a control circuit arrangement designed to control the first switch, the second switch and the third switch in response to a change of state.

[0110] Example 4 includes the amplifier circuit of Example 3, wherein the third switch further comprises a control terminal, the control circuit arrangement comprising: a first flip-flop with a first terminal and a second terminal, wherein the first terminal of the first flip-flop is configured to receive a clock signal; a second flip-flop with a first terminal and a second terminal, wherein the first terminal of the second flip-flop is coupled to the second terminal of the second flip-flop; a first logic gate with a first input, a second input, and an output, wherein the first input of the first logic gate is configured to receive an amplifier state control signal, wherein the second input of the first logic gate is coupled to the second terminal of the second flip-flop; a third flip-flop with a first terminal, a second terminal, and a third terminal.wherein the first terminal of the third flip-flop is coupled to the output of the first logic gate, wherein the second terminal is configured to receive a duty cycle control signal, and a second logic gate with one input and one output, wherein the input of the second logic gate is coupled to the third terminal of the third flip-flop, and wherein the output of the second logic gate is coupled to the control terminal of the third switch.

[0111] Example 5 includes the amplifier circuit of Example 1, which further includes a control circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the control circuit arrangement is coupled to the output of the comparator, and a feedback resistor circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the feedback resistor circuit arrangement is coupled to the second terminal of the control circuit arrangement, and wherein the second terminal of the feedback resistor circuit arrangement is coupled to the input of the modulator.

[0112] Example 6 includes the amplifier circuit from Example 1, where the input of the buffer is a first input, and the buffer has a second input that is coupled to the output of the buffer.

[0113] Example 7 includes the amplifier circuit of Example 1, wherein the modulator includes: a first amplifier with one input and one output, wherein the input of the first amplifier is the input of the modulator, a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the output of the first amplifier, and a second amplifier with a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the second terminal of the second resistor, wherein the second input of the second amplifier is coupled to the output of the buffer, and wherein the output of the second amplifier is coupled to the input of the comparator.

[0114] Example 8 includes the amplifier circuit of Example 7, wherein the capacitor is a first capacitor, and the modulated circuit further includes: a second capacitor with a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output of the second amplifier, the second terminal of the second capacitor is coupled to the input of the second amplifier and the second terminal of the second resistor; a third capacitor with a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the second terminal of the second capacitor, the second terminal of the second resistor and the input of the second amplifier, and wherein the second terminal of the third capacitor is coupled to the output of the first amplifier and the first terminal of the second resistor.and a fourth capacitor with a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the output of the first amplifier, the second terminal of the third capacitor and the first terminal of the second resistor, and wherein the second terminal of the fourth capacitor is coupled to the input of the first amplifier.

[0115] Example 9 includes an amplifier circuit comprising a modulator with one input and one output, a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator, a first switch with one voltage source terminal and one second terminal, a second switch with one voltage source terminal and one second terminal, a third switch with one first terminal and one second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch and the second terminal of the second switch, a first capacitor with one terminal, wherein the terminal of the first capacitor is coupled to the second terminal of the third switch, and a fourth switch with one first terminal and one second terminal.wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the first terminal of the first capacitor, a second capacitor with one terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch, and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the second capacitor and the second terminal of the fourth switch, and wherein the output of the buffer is coupled to the input of the modulator.

[0116] Example 10 includes the amplifier circuit of Example 9, which further includes a control circuit arrangement designed to control the first switch, the second switch, the third switch and the fourth switch in response to a change of state.

[0117] Example 11 includes the amplifier circuit of Example 9, which further includes a drive circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the drive circuit arrangement is coupled to the output of the comparator, and a feedback resistor circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the feedback resistor circuit arrangement is coupled to the second terminal of the drive circuit arrangement, and wherein the second terminal of the feedback resistor circuit arrangement is coupled to the input of the modulator.

[0118] Example 12 includes the amplifier circuit from Example 9, wherein the input of the buffer is a first input, wherein the buffer has a second input, and wherein the second input of the buffer is coupled to the output of the buffer.

[0119] Example 13 includes the amplifier circuit from Example 9, wherein the modulator includes: a first amplifier with one input and one output, wherein the input of the first amplifier is the input of the modulator, a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the output of the first amplifier, and a second amplifier with a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the second terminal of the second resistor, wherein the second input of the second amplifier is coupled to the output of the buffer, and wherein the output of the second amplifier is coupled to the input of the comparator.

[0120] Example 14 includes the amplifier circuit of Example 13, wherein the modulated circuit further includes: a third capacitor with a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output of the second amplifier, the second terminal of the third capacitor is coupled to the input of the second amplifier and the second terminal of the second resistor; a fourth capacitor with a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the second terminal of the third capacitor, the second terminal of the second resistor and the input of the second amplifier, wherein the second terminal of the fourth capacitor is coupled to the output of the first amplifier and the first terminal of the second resistor; and a fifth capacitor with a first terminal and a second terminal.wherein the first terminal of the fifth capacitor is coupled to the output of the first amplifier, the second terminal of the fourth capacitor and the first terminal of the second resistor, wherein the second terminal of the fifth capacitor is coupled to the input of the first amplifier.

[0121] Example 15 includes a device comprising: an amplifier designed to convert an audio signal into a pulse-width modulated signal, the amplifier comprising: a common-mode modulator, a comparator coupled to the modulator, a drive circuitry coupled to the comparator, and a filter circuitry coupled to the modulator, comprising: a first switch having a voltage source terminal and a second terminal, a second switch having a voltage source terminal and a second terminal, a third switch having a first terminal and a second terminal, the first terminal of the third switch being coupled to the second terminal of the first switch, a capacitor having one terminal, the terminal of the capacitor being coupled to the second terminal of the third switch, and a control designed to apply a common-mode voltage.which is supplied to the common-mode input of the modulator, by controlling the first switch, the second switch, and the third switch.

[0122] Example 16 includes the setup of Example 15, which further includes a processing unit coupled to the amplifier, designed to provide the audio signal, and a loudspeaker designed to output audio based on the pulse-width modulated signal.

[0123] Example 17 includes the setup of Example 15, wherein the filter circuit arrangement further includes a resistor having a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second terminal of the first switch, the second terminal of the second switch and the first terminal of the third switch, and wherein the second terminal of the resistor is coupled to the second terminal of the second switch and the terminal of the capacitor.

[0124] Example 18 includes the setup of Example 15, wherein the capacitor is a first capacitor, the filter circuit arrangement further comprising a fourth switch having a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the terminal of the first capacitor, and a second capacitor having a terminal and a second terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch.

[0125] Example 19 includes the setup of Example 15, wherein the amplifier includes an input resistor with one terminal and a feedback resistor with a first terminal and a second terminal, the second terminal of the feedback resistor being coupled to the terminal of the input resistor, and wherein the modulator has an input and an output, the input of the modulator being coupled to the second terminal of the input resistor and the second terminal of the feedback resistor, the comparator has a first signal generator input, a second input and an output, the second input of the comparator being coupled to the output of the modulator, and the drive circuit arrangement has an input and an output, the input of the drive circuit arrangement being coupled to the output of the comparator.wherein the output of the control circuit arrangement is coupled to the first terminal of the feedback resistor.

[0126] Example 20 includes the setup of Example 19, wherein the input resistor is a first input resistor, the feedback resistor is a first feedback resistor, the comparator is a first comparator, the drive circuit arrangement is a first drive circuit arrangement, the input of the modulator is a first input, and the output of the modulator is a first output, wherein the amplifier further includes: a second input resistor with one terminal, a second feedback resistor with a first terminal and a second terminal, wherein the second terminal of the second feedback resistor is coupled to the terminal of the second input resistor, the modulator with a second input and a second output, wherein the second input of the modulator is coupled to the second terminal of the second input resistor and the second terminal of the second feedback resistor.a second comparator with a first signal generator input, a second input and an output, wherein the second input of the second comparator is coupled to the second output of the modulator, and a second drive circuit arrangement with an input and an output, wherein the input of the second drive circuit arrangement is coupled to the output of the second comparator, and wherein the output of the second drive circuit arrangement is coupled to the first terminal of the second feedback resistor.

[0127] It will be clear from the foregoing that exemplary systems, devices, makes, and methods for controlling an amplifier have been disclosed. The described systems, devices, makes, and methods improve the efficiency of amplifier use by reducing pops or clicks caused by impedance mismatch in the amplifiers. Accordingly, the described systems, devices, makes, and methods relate to one or more improvements in the operation of a machine, such as an amplifier or other electronic device.

[0128] Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

[1] Amplifier circuit, comprising: a modulator with one input and one output; a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator; a first switch with a voltage source connection and a second connection; a second switch with one voltage source connection and one second connection; a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second terminal of the first switch and the second terminal of the second switch; a capacitor with one terminal coupled to the second terminal of the resistor; and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the capacitor and the second terminal of the resistor, and wherein the output of the buffer is coupled to the input of the modulator. [2] Amplifier circuit according to claim 1, further comprising a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch, the second terminal of the second switch and the first terminal of the resistor, wherein the second terminal of the third switch is coupled to the second terminal of the resistor, the terminal of the capacitor and the input of the buffer. [3] Amplifier circuit according to claim 2, further comprising a control circuit arrangement designed to control the first switch, the second switch and the third switch in response to a change of state. [4] Amplifier circuit according to claim 3, wherein the third switch further comprises a control terminal, the control circuit arrangement comprising: a first flip-flop with a first terminal and a second terminal, wherein the first terminal of the first flip-flop is designed to receive a clock signal; a second flip-flop with a first terminal and a second terminal, wherein the first terminal of the second flip-flop is coupled to the second terminal of the second flip-flop; a first logic gate having a first input, a second input and an output, wherein the first input of the first logic gate is configured to receive an amplifier state control signal, wherein the second input of the first logic gate is coupled to the second terminal of the second flip-flop; a third flip-flop with a first terminal, a second terminal and a third terminal, wherein the first terminal of the third flip-flop is coupled to the output of the first logic gate, and wherein the second terminal is configured to receive a duty cycle control signal; and a second logic gate with one input and one output, wherein the input of the second logic gate is coupled to the third terminal of the third flip-flop, and wherein the output of the second logic gate is coupled to the control terminal of the third switch. [5] Amplifier circuit according to claim 1, further comprising: a control circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the control circuit arrangement is coupled to the output of the comparator; and a feedback resistor circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the feedback resistor circuit arrangement is coupled to the second terminal of the control circuit arrangement, and wherein the second terminal of the feedback resistor circuit arrangement is coupled to the input of the modulator. [6] Amplifier circuit according to claim 1, wherein the input of the buffer is a first input, wherein the buffer has a second input which is coupled to the output of the buffer. [7] Amplifier circuit according to claim 1, wherein the modulator comprises: a first amplifier with one input and one output, wherein the input of the first amplifier is the input of the modulator; a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the output of the first amplifier; and a second amplifier with a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the second terminal of the second resistor, wherein the second input of the second amplifier is coupled to the output of the buffer, and wherein the output of the second amplifier is coupled to the input of the comparator. [8] Amplifier circuit according to claim 7, wherein the capacitor is a first capacitor, wherein the modulated further comprises: a second capacitor with a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output of the second amplifier, the second terminal of the second capacitor is coupled to the input of the second amplifier and the second terminal of the second resistor; a third capacitor with a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the second terminal of the second capacitor, the second terminal of the second resistor and the input of the second amplifier, and wherein the second terminal of the third capacitor is coupled to the output of the first amplifier and the first terminal of the second resistor; and a fourth capacitor with a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the output of the first amplifier, the second terminal of the third capacitor and the first terminal of the second resistor, wherein the second terminal of the fourth capacitor is coupled to the input of the first amplifier. [9] Amplifier circuit, comprising: a modulator with one input and one output; a comparator with one input and one output, wherein the input of the comparator is coupled to the output of the modulator; a first switch with a voltage source connection and a second connection; a second switch with one voltage source connection and one second connection; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch and the second terminal of the second switch; a first capacitor with one terminal, wherein the terminal of the first capacitor is coupled to the second terminal of the third switch; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the first terminal of the first capacitor; a second capacitor with one terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch; and a buffer with one input and one output, wherein the input of the buffer is coupled to the terminal of the second capacitor and the second terminal of the fourth switch, wherein the output of the buffer is coupled to the input of the modulator. [10] Amplifier circuit according to claim 9, further comprising a control circuit arrangement designed to control the first switch, the second switch, the third switch and the fourth switch in response to a change of state. [11] Amplifier circuit according to claim 9, further comprising: a control circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the control circuit arrangement is coupled to the output of the comparator; and a feedback resistor circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the feedback resistor circuit arrangement is coupled to the second terminal of the control circuit arrangement, and wherein the second terminal of the feedback resistor circuit arrangement is coupled to the input of the modulator. [12] Amplifier circuit according to claim 9, wherein the input of the buffer is a first input, wherein the buffer has a second input, wherein the second input of the buffer is coupled to the output of the buffer. [13] Amplifier circuit according to claim 9, wherein the modulator comprises: a first amplifier with one input and one output, wherein the input of the first amplifier is the input of the modulator; a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the output of the first amplifier; and a second amplifier with a first input, a second input and an output, wherein the first input of the second amplifier is coupled to the second terminal of the second resistor, wherein the second input of the second amplifier is coupled to the output of the buffer, and wherein the output of the second amplifier is coupled to the input of the comparator. [14] Amplifier circuit according to claim 13, wherein the modulated circuit further comprises: a third capacitor with a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the output of the second amplifier, the second terminal of the third capacitor is coupled to the input of the second amplifier and the second terminal of the second resistor; a fourth capacitor with a first terminal and a second terminal, wherein the first terminal of the fourth capacitor is coupled to the second terminal of the third capacitor, the second terminal of the second resistor and the input of the second amplifier, and wherein the second terminal of the fourth capacitor is coupled to the output of the first amplifier and the first terminal of the second resistor; and a fifth capacitor with a first terminal and a second terminal, wherein the first terminal of the fifth capacitor is coupled to the output of the first amplifier, the second terminal of the fourth capacitor and the first terminal of the second resistor, wherein the second terminal of the fifth capacitor is coupled to the input of the first amplifier. [15] Institution, comprehensive: an amplifier designed to convert an audio signal into a pulse-width modulated signal, wherein the amplifier includes: a modulator with a common-mode connection; a comparator coupled to the modulator; a control circuit arrangement coupled to the comparator; and a filter circuit arrangement coupled to the modulator, which includes: a first switch with a voltage source connection and a second connection; a second switch with one voltage source connection and one second connection; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the second terminal of the first switch; a capacitor with one terminal, wherein the terminal of the capacitor is coupled to the second terminal of the third switch; and a control designed to adjust a common-mode voltage supplied to the common-mode terminal of the modulator by controlling the first switch, the second switch, and the third switch. [16] Device according to claim 15, further comprising: a processing unit coupled with the amplifier, designed to provide the audio signal; and a loudspeaker designed to output audio based on the pulse width modulated signal. [17] Device according to claim 15, wherein the filter circuit arrangement further comprises a resistor having a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the second terminal of the first switch, the second terminal of the second switch and the first terminal of the third switch, wherein the second terminal of the resistor is coupled to the second terminal of the second switch and the terminal of the capacitor. [18] Device according to claim 15, wherein the capacitor is a first capacitor, wherein the filter circuit arrangement further comprises: a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch and the terminal of the first capacitor; and a second capacitor with one terminal and a second terminal, wherein the terminal of the second capacitor is coupled to the second terminal of the fourth switch. [19] Device according to claim 15, wherein the amplifier comprises: an input resistor with one terminal; and a feedback resistor with a first terminal and a second terminal, wherein the second terminal of the feedback resistor is coupled to the terminal of the input resistor and wherein: the modulator has an input and an output, wherein the input of the modulator is coupled to the second terminal of the input resistor and the second terminal of the feedback resistor; the comparator has a first signal generator input, a second input and an output, wherein the second input of the comparator is coupled to the output of the modulator; and The control circuit arrangement has an input and an output, wherein the input of the control circuit arrangement is coupled to the output of the comparator, and wherein the output of the control circuit arrangement is coupled to the first terminal of the feedback resistor. [20] Device according to claim 19, wherein the input resistance is a first input resistance, the feedback resistance is a first feedback resistance, the comparator is a first comparator, the control circuit arrangement is a first control circuit arrangement, the input of the modulator is a first input and the output of the modulator is a first output, wherein the amplifier further comprises: a second input resistor with one terminal; a second feedback resistor with a first terminal and a second terminal, wherein the second terminal of the second feedback resistor is coupled to the terminal of the second input resistor; the modulator with a second input and a second output, wherein the second input of the modulator is coupled to the second terminal of the second input resistor and the second terminal of the second feedback resistor; a second comparator with a first signal generator input, a second input and an output, wherein the second input of the second comparator is coupled to the second output of the modulator; and a second control circuit arrangement with an input and an output, wherein the input of the second control circuit arrangement is coupled to the output of the second comparator, and wherein the output of the second control circuit arrangement is coupled to the first terminal of the second feedback resistor.

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