Power amplifier circuit, radio frequency chip and electronic device

Abstract

The embodiment of the present disclosure discloses a power amplifier circuit, a radio frequency chip and an electronic device. The power amplifier circuit comprises: at least two stages of power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

Description

TECHNICAL FIELD

[0001] The embodiments of the present disclosure relate to the field of radio frequency power amplifiers, and in particular, to a power amplifier circuit, a radio frequency chip and an electronic device. BACKGROUND

[0002] In existing radio frequency front-end module (RF FEM) chips, due to layout restrictions, the active chip isolation design is limited, the direct current (DC) power supply network is multiplexed, the number of bypass capacitors is small, and there are crosstalk between digital and analog lines and coupling between radio frequency lines, which limits the stability of the radio frequency front-end module chip during operation, especially for the radio frequency power amplifier (RF PA) in the radio frequency front-end module chip. How to improve the stability of the radio frequency power amplifier becomes a challenge for the design of the radio frequency front-end module chip. SUMMARY

[0003] Therefore, the embodiments of the present disclosure provide a power amplifier circuit, a radio frequency chip and an electronic device.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present disclosure is implemented as follows:

[0005] In a first aspect, the embodiments of the present disclosure provide a power amplifier circuit, which comprises:

[0006] at least two cascaded power amplifiers;

[0007] a low-frequency resonance network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

[0008] In some embodiments, the power amplifier circuit further comprises:

[0009] a first gain-reducing network comprising a third capacitor, a second inductor and a first resistor; the second inductor and the first resistor are connected in series between a radio frequency input end and a second end of the first power amplifier; and the third capacitor is connected between the radio frequency input end and the second end of the first power amplifier.

[0010] In some embodiments, the first gain-reducing network further comprises:

[0011] a first switch; the first switch is connected in series to a branch in which the second inductor is located; the first switch controls the second inductor and the first resistor to be connected to the power amplifier circuit.

[0012] In some embodiments, the power amplifier circuit further comprises:

[0013] a second gain-reduction network comprising a fourth capacitor, a third inductor and a second resistor connected in series; the second gain-reduction network is coupled between the ground terminal and the second terminal of the first-stage power amplifier.

[0014] In some embodiments, the second gain-reduction network further comprises:

[0015] a second switch; the second switch is connected in series to a branch in which the fourth capacitor is located; the second switch controls the fourth capacitor, the third inductor and the second resistor to be connected to the power amplifier circuit.

[0016] In some embodiments, the second gain-reduction network further comprises:

[0017] a fifth capacitor and a third switch; the fifth capacitor and the third switch are connected in series to both ends of the fourth capacitor; the third switch controls the fifth capacitor to be connected to the power amplifier circuit.

[0018] In some embodiments, the power amplifier circuit further comprises:

[0019] a third gain-reduction network comprising a plurality of forward diodes connected in series and a plurality of reverse diodes connected in series; the plurality of forward diodes and the plurality of reverse diodes are connected in parallel between the second terminal of the second-stage power amplifier and the ground terminal.

[0020] In some embodiments, the third gain-reduction network further comprises:

[0021] a switch short-circuit network comprising a fourth switch connected in parallel to any of the forward diodes and a fifth switch connected in parallel to any of the reverse diodes; the fourth switch controls the forward diode to be connected to the power amplifier circuit; the fifth switch controls the reverse diode to be connected to the power amplifier circuit.

[0022] In some embodiments, the power amplifier circuit further comprises:

[0023] a first matching network comprising a sixth capacitor and a fourth inductor; the sixth capacitor and the fourth inductor are connected in series between the first terminal of the second-stage power amplifier and the ground terminal.

[0024] In some embodiments, the power amplifier circuit further comprises:

[0025] A second matching network includes a seventh capacitor and a fifth inductor; the seventh capacitor and the fifth inductor are connected in parallel between the first end of the second-stage power amplifier and the radio frequency output end.

[0026] In some embodiments, the first-stage power amplifier includes a driver-stage power amplifier, and the first-stage power amplifier includes a final-stage power amplifier.

[0027] In a second aspect, the embodiments of the present disclosure provide a radio frequency chip, which includes any of the power amplifier circuits described above.

[0028] In a third aspect, the embodiments of the present disclosure provide an electronic device, which includes any of the power amplifier circuits described above or the radio frequency chip described above.

[0029] In the embodiments of the present disclosure, a low-frequency resonance network is connected between the first end of the power amplifier and the power supply end, and the low-frequency resonance network includes a π-type low-pass filter composed of a decoupling capacitor. In this way, the low-frequency resonance network can filter out the alternating component in the direct current power supply and retain the direct current component based on the principle of low-pass filtering. On the other hand, the low-frequency resonance network can absorb noise energy of a specific frequency by using the lowest impedance characteristic of the decoupling capacitor at the self-resonance frequency point, thereby realizing filtering of the specific resonance frequency point. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A circuit diagram of a power amplifier circuit in an example;

[0031] Figure 2 A circuit diagram of a power amplifier circuit provided by the embodiments of the present disclosure;

[0032] Figure 3 A circuit diagram of a first low-frequency resonance network provided by the embodiments of the present disclosure;

[0033] Figure 4 A frequency spectrum diagram of a signal output after harmonic suppression by the low-frequency resonance network provided by the embodiments of the present disclosure;

[0034] Figure 5 A circuit diagram of another power amplifier circuit provided by the embodiments of the present disclosure;

[0035] Figure 6 A circuit diagram of a second low-frequency resonance network provided by the embodiments of the present disclosure;

[0036] Figure 7 A circuit diagram of a first gain-reducing network provided by the embodiments of the present disclosure;

[0037] Figure 8a frequency spectrum of a signal outputted after harmonics are suppressed by the first gain-reduction network provided by the embodiments of the present disclosure;

[0038] Figure 9 a circuit diagram of the second gain-reduction network provided by the embodiments of the present disclosure;

[0039] Figure 10 a frequency spectrum of a signal outputted after harmonics are suppressed by the second gain-reduction network provided by the embodiments of the present disclosure;

[0040] Figure 11 a circuit diagram of the third gain-reduction network provided by the embodiments of the present disclosure;

[0041] Figure 12 circuit diagrams of the first matching network and the second matching network provided by the embodiments of the present disclosure;

[0042] Figure 13 a frequency spectrum of a signal outputted after harmonics are suppressed by the first matching network and the second matching network provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without any creative work under the premise that the present disclosure falls within the scope of protection of the present disclosure.

[0044] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described here, and well-known functions and structures are not described in detail.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes can be exaggerated for clarity. The same reference signs represent the same elements throughout.

[0046] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0047] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be proposed in the following description in order to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can also have other implementations.

[0050] Cascode power amplifier is a high-performance amplifier circuit structure, especially suitable for high-frequency (radio frequency, microwave) and high-gain applications. It effectively overcomes some key limitations of single-tube amplifiers in high-frequency applications by skillfully connecting two active devices (usually transistors) together in a specific way.

[0051] Figure 1 A circuit diagram of the power amplifier circuit in the example.

[0052] As Figure 1 shown, the power amplifier circuit 100 includes a cascode driver PA 101 and a final PA 102. Among them, the driver PA 101 is coupled between the radio frequency signal input terminal Term1 and the final PA 102, the driver PA 101 is connected to the driving voltage Driver VCC, and the driver PA 101 is used to amplify the radio frequency input signal Rfin received by the radio frequency signal input terminal Term1 and output to the final PA 102, so as to provide sufficient voltage / current driving capability for the final PA 102. The final PA 102 is connected to the final voltage Final VCC, and the output end of the final PA 102 is connected to the radio frequency output terminal Term2. The final PA 102 is used to convert the signal amplified by the driver PA 101 into high-power, low-impedance electrical energy output to drive the terminal load (such as a loudspeaker, an antenna, a motor, etc.).

[0053] It should be noted that the design of the single cascode power amplifier as Figure 1 shown is based on the ideal input of 50 ohm, and the return loss is low. However, in actual module applications, the radio frequency reflection is significantly higher than the ideal 50 ohm, and the reflected energy can cause the power amplifier circuit to be unstable and damage the device.

[0054] In the radio frequency front-end module chip, the factors causing the instability of the power amplifier circuit are relatively complex. In order to improve the stability of the power amplifier circuit, it is necessary to consider the radio frequency coupling, the direct current power supply, the digital-analog signal crosstalk, and the influence of other power amplifier circuits in the module, which involves the problem of multi-frequency resonance.

[0055] Therefore, the present disclosure provides a power amplifier circuit, which comprises: at least two-stage power amplifiers in cascade; a low-frequency resonant network comprising a first capacitor, a second capacitor and a first inductor; the first capacitor is coupled between a power supply end and a ground end; the second capacitor is coupled between a first end of the power amplifier and the ground end; the first inductor is coupled between the first capacitor and the second capacitor; and the first capacitor comprises a decoupling capacitor.

[0056] Figure 2 A circuit diagram of a power amplifier circuit 200 provided by the present disclosure is shown.

[0057] As shown in Figure 2 , the power amplifier circuit 200 comprises a first-stage power amplifier 201 and a second-stage power amplifier 202 in cascade. Specifically, the first-stage power amplifier 201 is coupled with a radio frequency signal input end Term1, and the second-stage power amplifier 202 is coupled with a radio frequency signal output end Term2.

[0058] A low-frequency resonant network 203 is coupled between each power amplifier and a power supply end. Specifically, the low-frequency resonant network 203 is coupled between a first end of the first-stage power amplifier 201 and the power supply end, and the low-frequency resonant network 203 is coupled between a first end of the second-stage power amplifier 202 and the power supply end. The power supply end is connected to a direct current power supply VCC.

[0059] In some embodiments, the first-stage power amplifier 201 and the second-stage power amplifier 202 can each be a transistor, for example, a heterojunction bipolar transistor (HBT). In this way, the first end of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the collector of the transistor, the second end of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the base of the transistor, and the third end of the first-stage power amplifier 201 or the second-stage power amplifier 202 can be the emitter of the transistor.

[0060] Figure 3 A circuit diagram of a first low-frequency resonant network 203 provided by the present disclosure is shown.

[0061] As shown in Figure 3As shown, the low-frequency resonance network 203 includes a first capacitor C1, a second capacitor C2, and a first inductor L1, wherein the first capacitor C1 includes a decoupling capacitor, and the first capacitor C1 is coupled between the power supply end and the ground end. The second capacitor C2 is coupled between the first end of the power amplifier and the ground end. The first inductor L1 is coupled between the first capacitor C1 and the second capacitor C2. In this way, the first capacitor C1, the second capacitor C2, and the first inductor L1 together form a π-type low-pass filter (LPF) coupled between the first end of the power amplifier and the power supply end.

[0062] It should be noted that according to the foregoing, there is a problem of multi-frequency resonance in the radio frequency front-end module affecting the stability of the power amplifier circuit. That is, there may be low-frequency or high-frequency alternating components in the direct-current power supply VCC connected to the first end of the first-stage power amplifier 201 and the first end of the second-stage power amplifier 202. The alternating components in the direct-current power supply will affect the normal operation of the power amplifier, thereby affecting the stability of the power amplifier circuit.

[0063] Figure 4 The frequency spectrum diagram of the signal output after the harmonic is suppressed by the low-frequency resonance network is provided for the embodiments of the present disclosure. As shown in Figure 4 As shown, the low-frequency resonance network 203 substantially filters out the alternating components in the direct-current power supply, and the low-frequency resonance network 203 uses the self-resonant frequency of the decoupling capacitor to achieve suppression of the 810 MHz resonance frequency point.

[0064] In the embodiments of the present disclosure, the low-frequency resonance network 203 is connected between the first end of the cascaded power amplifier and the power supply end, and the low-frequency resonance network 203 includes a π-type low-pass filter composed of a decoupling capacitor. Therefore, the low-frequency resonance network 203 can filter out the alternating components in the direct-current power supply VCC based on the principle of low-pass filtering, while retaining the direct-current components. On the other hand, the low-frequency resonance network 203 can use the lowest impedance characteristic of the decoupling capacitor (i.e., the first capacitor C1) at the self-resonant frequency (SRF) point to absorb noise energy of a specific frequency, thereby achieving filtering of a specific resonance frequency point. In this way, the stability of the power amplifier circuit is effectively improved.

[0065] In some embodiments, the first-stage power amplifier 201 includes a driver-stage power amplifier, and the first-stage power amplifier 201 includes a final-stage power amplifier.

[0066] In some embodiments, the power supply end includes a first power supply end coupled to the first-stage power amplifier 201 and a second power supply end coupled to the second-stage power amplifier 202, as shown in Figure 2

[0067] With reference to the foregoing​Figure 3 In the case that the power supply end includes a first power supply end and a second power supply end, the low-frequency resonance network 203 includes two first capacitors C1, two second capacitors C2 and two first inductors L1. And, the two first capacitors C1, the two second capacitors C2 and the two first inductors L1 form two independent π-type low-pass filters. As shown in FIG. 3, one of the π-type low-pass filters is connected between the first end (PA1_Collector shown in FIG. 2) of the first-stage power amplifier and the first power supply end for connecting a first power supply voltage, for example, a driving voltage Driver VCC. The other π-type low-pass filter is connected between the first end (PA2_Collector shown in FIG. 2) of the second-stage power amplifier and the second power supply end for connecting a second power supply voltage, for example, a final-stage voltage Final VCC. Figure 3 Figure 3 Figure 3

[0068] In another embodiment, the first-stage power amplifier 201 and the second-stage power amplifier 202 are coupled to the same power supply end for connecting a power supply voltage VCC through a low-frequency resonance network 501. As shown in FIG. 4, the low-frequency resonance network 501 includes one first capacitor C1, two second capacitors C2 and two first inductors L1. The first capacitor C1 is connected between the first end (PA1_Collector shown in FIG. 2) of the first-stage power amplifier and the second end (PA2_Collector shown in FIG. 2) of the second-stage power amplifier. The two second capacitors C2 and the two first inductors L1 form two π-type low-pass filters, which share the first capacitor C1. In other words, one of the π-type low-pass filters is connected between the first end (PA1_Collector shown in FIG. 2) of the first-stage power amplifier and the power supply end, and the other π-type low-pass filter is connected between the first end (PA2_Collector shown in FIG. 2) of the second-stage power amplifier and the power supply end. Figure 5 Figure 5 FIG. 5 is a circuit diagram of another power amplifier circuit 500 provided by an embodiment of the present disclosure.

[0069] Figure 6 FIG. 6 is a circuit diagram of a second low-frequency resonance network 501 provided by an embodiment of the present disclosure. As shown in FIG. 6, in the case that the cascaded power amplifiers are connected to the same power supply end, the low-frequency resonance network 501 includes one first capacitor C1, two second capacitors C2 and two first inductors L1. The first capacitor C1 is connected between the first end (PA1_Collector shown in FIG. 2) of the first-stage power amplifier and the second end (PA2_Collector shown in FIG. 2) of the second-stage power amplifier. The two second capacitors C2 and the two first inductors L1 form two π-type low-pass filters, which share the first capacitor C1. In other words, one of the π-type low-pass filters is connected between the first end (PA1_Collector shown in FIG. 2) of the first-stage power amplifier and the power supply end, and the other π-type low-pass filter is connected between the first end (PA2_Collector shown in FIG. 2) of the second-stage power amplifier and the power supply end. Figure 6 Figure 6 Figure 6

[0070] In an embodiment of the present disclosure, the power amplifier circuit can be integrated in a power amplifier chip, and the power amplifier chip can be packaged together with other chips or devices to form a radio frequency front-end module chip.

[0071] ​​​​​​​It should be noted that since the same power amplifier chip may exhibit different characteristics in different RF front-end module chips, using the same power amplifier chip in different RF front-end module chips may result in an excessively long debugging cycle for the RF front-end module chips.

[0072] To shorten the debugging cycle of the RF front-end module chip, in some embodiments, the low-frequency resonant network further includes at least one regulating capacitor C′ and at least one regulating switch k′, the same number as the regulating capacitor C′. The regulating capacitor C′ serves as a decoupling capacitor. Each regulating capacitor C′ and its corresponding regulating switch k′ are connected in series and then in parallel across the first capacitor C1.

[0073] like Figure 6 As shown, the low-frequency resonant network 501 includes an adjusting capacitor C′ and an adjusting switch k′. When the adjusting switch k′ is closed, its branch is conducting, causing the adjusting capacitor C′ to be connected to the power amplifier circuit 500. At this time, two decoupling capacitors are connected in the power amplifier circuit 500, namely the first capacitor C1 and the adjusting capacitor C′. The self-resonant frequencies of the first capacitor C1 and the adjusting capacitor C′ can be used to suppress the two resonant frequencies in the DC power supply.

[0074] In this embodiment, the opening and closing of the adjustment switch k′ can be controlled according to actual needs to connect different numbers of adjustment capacitors C′ in the power amplifier circuit. This allows for flexible adjustment of the suppression frequency, shortening the debugging cycle. Simultaneously, the introduction of the adjustment capacitor C′ enables the low-frequency resonant network to suppress at least two resonant frequencies, thereby solving the multi-stage crosstalk problem.

[0075] In other embodiments, at least one regulating capacitor C′ and an equal number of regulating switches k′ are located within the RF front-end module chip and outside the power amplifier circuit. The regulating capacitor C′ serves as a decoupling capacitor. Each regulating capacitor C′ and its corresponding regulating switch k′ are connected in series and then in parallel across the first capacitor C1. When a regulating switch k′ is closed, its branch is turned on, connecting the regulating capacitor C′ in that branch to the RF front-end module chip. At this point, at least two decoupling capacitors are connected to the RF front-end module chip. The self-resonant frequency of these two decoupling capacitors can suppress at least two resonant frequencies in the DC power supply, thus solving the multi-stage crosstalk problem. Simultaneously, flexible adjustment of the suppression frequency can be achieved, shortening the debugging cycle.

[0076] In the embodiments of the present disclosure, the capacitance value of the first capacitor C1 can be set according to actual requirements to achieve suppression of a specific resonance frequency point. In some embodiments, the first capacitor C1 is used to filter out a low-frequency interference frequency point less than the center frequency f0 of the radio frequency input signal, for example, the first capacitor is used to filter out an interference frequency point at (f0 / 2).

[0077] In some embodiments, the capacitance value of the adjusted capacitance C' is less than the capacitance value of the first capacitor C1.

[0078] In some embodiments, the power amplifier circuit further includes a first gain reduction network 204, as shown in Figure 2 The first gain reduction network 204 is coupled between the radio frequency signal input terminal Term1 and the first-stage power amplifier 201.

[0079] In some embodiments, the first gain reduction network 204 includes a third capacitor C3, a second inductor L2, and a first resistor R1; the second inductor L2 and the first resistor R1 are connected in series between the radio frequency signal input terminal Term1 and the second end (PA1_Base) of the first-stage power amplifier 201; and the third capacitor C3 is connected between the radio frequency signal input terminal Term1 and the second end of the first-stage power amplifier 201, as shown in Figure 7 Figure 7 Figure 7 A circuit diagram of the first gain reduction network provided by the embodiments of the present disclosure.

[0080] In the embodiments of the present disclosure, during the transmission of the radio frequency input signal RFin to the first-stage power amplifier 201 through the first gain reduction network 204, the high-frequency signal in the radio frequency input signal RFin passes through the branch where the third capacitor C3 is located, and the third capacitor C3 allows the high-frequency signal to pass. The low-frequency signal in the radio frequency input signal RFin passes through the branch where the second inductor L2 and the first resistor R1 are located, and the first resistor R1 causes loss to the low-frequency signal, thereby suppressing low-frequency resonance. In this way, the third capacitor C3, the second inductor L2, and the first resistor R1 together form a high-pass network, as shown in Figure 8 Figure 8 A frequency spectrum diagram of the signal output after the first gain reduction network is used to suppress harmonics in the embodiments of the present disclosure.

[0081] Figure 8 The 800MHz frequency point shown in the above table is a low-frequency resonance point located outside the passband of the radio frequency input signal, and Figure 8 The 2GHz frequency point shown in the above table is a frequency point located within the passband of the radio frequency input signal. According to Figure 8 ​​​As can be seen, the first gain reduction network 204 suppresses low-frequency resonance outside the passband while also reducing the gain within the passband. It should be noted that appropriately reducing the gain of the RF input signal within the passband can prevent the overall gain of the power amplifier circuit from becoming too high, thereby improving the stability of the power amplifier circuit.

[0082] Continue to refer to Figure 8 , Figure 8 The diagram shows the spectrum of the signals output by the first drop-gain network 204 corresponding to multiple third capacitors C3 with different capacitance values. Furthermore, the smaller the capacitance value of the third capacitor C3, the less suppression the first drop-gain network 204 provides at the 800MHz and 2GHz frequencies. Therefore, embodiments of this disclosure can select a third capacitor C3 with a specific capacitance value according to actual design requirements to achieve suppression of specific frequencies and adjustment of the gain.

[0083] In some embodiments, the first gain reduction network 204 further includes: a first switch k1; the first switch k1 is connected in series in the branch where the second inductor L2 is located; that is, the first switch k1 is connected in series with the second inductor L2 and the first resistor R1; the first switch k1 controls the second inductor L2 and the first resistor R1 to be connected to the power amplifier circuit, such as... Figure 7 As shown.

[0084] Specifically, when the first switch k1 is open, the branch containing the second inductor L2 and the first resistor R1 is disconnected, and the second inductor L2 and the first resistor R1 are not connected to the power amplifier circuit. At this time, only the third capacitor C3 in the first gain reduction network 204 is connected to the power amplifier circuit, and the third capacitor C3 participates in the input matching of the power amplifier circuit. When the first switch k1 is closed, the branch containing the second inductor L2 and the first resistor R1 is connected, and the third capacitor C3, the second inductor L2, and the first resistor R1 are all connected to the power amplifier circuit. At this time, the third capacitor C3, the second inductor L2, and the first resistor R1 together form a high-pass network, which can suppress low-frequency resonance outside the passband while reducing the gain within the passband.

[0085] In other embodiments, the power amplifier circuit further includes a second drop-gain network 502, such as... Figure 5 As shown, the second down-gain network 502 is coupled between the RF signal input terminal Term1 and the first-stage power amplifier 201.

[0086] In some embodiments, the second drop-gain network 502 includes a fourth capacitor C4, a third inductor L3, and a second resistor R2 connected in series; the second drop-gain network 502 is coupled to the ground terminal and the second terminal of the first-stage power amplifier 201. Figure 9 Between PA1_Base, such as Figure 9 As shown,Figure 9 A circuit diagram of the second gain reduction network provided in the embodiments of the present disclosure is shown in FIG. 2B.

[0087] In the embodiments of the present disclosure, the fourth capacitor C4, the third inductor L3 and the second resistor R2 together form a series resonance circuit. The series resonance circuit has the characteristic of presenting extremely low impedance at a specific frequency (resonance point), and can be used to achieve efficient frequency selection and energy transfer. That is, the second gain reduction network 502 can suppress the harmonic at the specific frequency point, thereby improving the stability of the power amplifier circuit 500.

[0088] Figure 10 A frequency spectrum diagram of the signal output after the harmonic is suppressed by the second gain reduction network provided in the embodiments of the present disclosure is shown in FIG. 3B. Figure 10 As shown in FIG. 3B, the embodiments of the present disclosure use the second gain reduction network 502 to suppress the harmonic at the frequency point of 790 MHz.

[0089] In the embodiments of the present disclosure, in addition to being used to suppress the harmonic at the specific frequency point, the second gain reduction network 502 can also be used to participate in input matching.

[0090] In some embodiments, the second gain reduction network 502 further includes a second switch k2, and the second switch k2 is connected in series to the branch in which the fourth capacitor C4 is located. The second switch k2 controls the fourth capacitor C4, the third inductor L3 and the second resistor R2 to be connected to the power amplifier circuit, as shown in FIG. 2B. Figure 9

[0091] Specifically, when the second switch k2 is in an open state, the branch in which the fourth capacitor C4, the third inductor L3 and the second resistor R2 are located is disconnected, and the fourth capacitor C4, the third inductor L3 and the second resistor R2 are not connected to the power amplifier circuit 500. When the second switch k2 is in a closed state, the branch in which the fourth capacitor C4, the third inductor L3 and the second resistor R2 are located is connected, and the fourth capacitor C4, the third inductor L3 and the second resistor R2 are connected to the power amplifier circuit 500. At this time, the second gain reduction network 502 can suppress the harmonic at the specific frequency point.

[0092] In some embodiments, the second gain reduction network 502 further includes a fifth capacitor C5 and a third switch k3, and the fifth capacitor C5 and the third switch k3 are connected in series between the two ends of the fourth capacitor C4. The third switch k3 controls the fifth capacitor C5 to be connected to the power amplifier circuit 500, as shown in FIG. 2C. Figure 9

[0093] ​​Specifically, when the third switch k3 is in an open state, the fifth capacitor C5 is not connected to the power amplifier circuit 500. When the third switch k3 is in a closed state, the fifth capacitor C5 is connected to the power amplifier circuit 500. At this time, the fourth capacitor C4, the third inductor L3, the second resistor R2, and the fifth capacitor C5 together form a resonant network.

[0094] In some embodiments, the fifth capacitor C5 has a smaller capacitance value than the fourth capacitor C4. The fourth capacitor C4 mainly affects the selection of the suppression frequency, and the fifth capacitor C5 can make a small range adjustment to the suppression frequency (for example, shift the suppression frequency by 50 MHz). In this way, when the suppression frequency corresponding to the series resonant circuit formed by the fourth capacitor C4, the third inductor L3, and the second resistor R2 is not the target frequency, a small range adjustment to the suppression frequency can be achieved by connecting the fifth capacitor C5 in the second gain reduction network 502, so that the adjusted suppression frequency is equal to the target frequency. In this way, flexible adjustment of the suppression frequency is achieved, and the debugging period of the radio frequency front-end module chip is shortened.

[0095] In some embodiments, the power amplifier circuit further includes a third gain reduction network 205, as shown in FIG. 2B. The third gain reduction network 205 is coupled between the first-stage power amplifier 201 and the second-stage power amplifier 202. Figure 2 and Figure 5 Specifically, an inter-stage matching network 209 is further connected between the first-stage power amplifier 201 and the second-stage power amplifier 202, and the third gain reduction network 205 is coupled between the output end of the inter-stage matching network 209 and the second end of the second-stage power amplifier 202.

[0096] In some embodiments, the third gain reduction network 205 includes a plurality of series-connected forward diodes D1 and a plurality of series-connected reverse diodes D2, which are connected in parallel between the second end (PA2_Base) of the second-stage power amplifier and the ground, as shown in FIG. 2C. Figure 11 Figure 11 In some embodiments, the third gain reduction network 205 includes a plurality of series-connected forward diodes D1 and a plurality of series-connected reverse diodes D2, which are connected in parallel between the second end (PA2_Base) of the second-stage power amplifier and the ground, as shown in FIG. 2C.

[0097] In the embodiments of the present disclosure, the third gain reduction network 205 is coupled between the first end of the first-stage power amplifier 201 and the second end of the second-stage power amplifier 202. The third gain reduction network 205 is used to limit the amplitude of the signal output by the first end of the first-stage power amplifier 201. Specifically, when the voltage V1 output by the first end of the first-stage power amplifier 201 is a small signal less than the forward voltage drop V F of the diode, neither the forward diode D1 nor the reverse diode D2 is conductive. When the voltage V1 output by the first end of the first-stage power amplifier 201 is a large signal greater than the forward voltage drop V F ​During a large signal period, in the positive half-cycle, the forward diode D1 is turned on, and the reverse diode D2 is turned off in reverse. The voltage V2 output from the third drop-gain network 205 to the second terminal of the second-stage power amplifier 202 is clamped at V. F (Cut off the part above V) F (Partial). During the negative half-cycle, the forward diode D1 is reverse-biased and the reverse diode D2 is turned on. The voltage V2 output from the third drop-gain network 205 to the second terminal of the second-stage power amplifier 202 is clamped at V. F .

[0098] Thus, when the signal output from the first terminal of the first-stage power amplifier 201 is a large signal, the third drop-gain network 205 can not only suppress the voltage fluctuation of the signal output from the first terminal of the first-stage power amplifier 201, thereby improving the stability of the power amplifier circuit; the third drop-gain network 205 can also prevent the second-stage power amplifier 202 from being burned out due to the power exceeding the upper limit.

[0099] In some embodiments, the third gain reduction network 205 includes three to five forward diodes D1 and an equal number of reverse diodes D2. Here, the number of forward diodes D1 and the number of reverse diodes D2 can be selected according to specific requirements. Figure 11 The diagram illustrating the third drop-gain network 205, which includes three forward diodes D1 and three reverse diodes D2, is merely an example.

[0100] In some embodiments, the third gain reduction network 205 further includes: a switch short-circuit network, including a fourth switch k4 connected in parallel with any forward diode D1, and a fifth switch k5 connected in parallel with any reverse diode D2; the fourth switch k4 controls the forward diode D1 to be connected to the power amplifier circuit; the fifth switch k5 controls the reverse diode D2 to be connected to the power amplifier circuit.

[0101] In some embodiments, such as Figure 11 As shown, the third gain reduction network 205 includes a number of fourth switches k4 equal to the number of forward diodes D1, and a number of fifth switches k5 equal to the number of reverse diodes D2. Each fourth switch k4 is connected in parallel with a forward diode D1, and each fifth switch k5 is connected in parallel with a reverse diode D2. Thus, each fourth switch k4 can control the connection of its parallel forward diode D1 to the power amplifier circuit, and each fifth switch k5 can control the connection of its parallel reverse diode D2 to the power amplifier circuit.

[0102] In other embodiments, the number of fourth switches k4 may be less than the number of forward diodes D1, and the number of fifth switches k5 may be less than the number of reverse diodes D2.

[0103] In an example, the third gain-reduction network includes N (N>3) forward diodes D1 and N reverse diodes D2, the switch shorting network includes a fourth switch k4 in parallel with (N-3) arbitrary forward diodes D1 and a fifth switch k5 in parallel with (N-3) arbitrary reverse diodes D2. In this way, at least 3 forward diodes D1 and 3 reverse diodes D2 in the third gain-reduction network are always connected to the power amplifier circuit. Further, when the fourth switch k4 is in an open state, the fourth switch k4 controls the forward diodes D1 in parallel with it to be connected to the power amplifier circuit. When the fourth switch k4 is in a closed state, the fourth switch k4 controls the forward diodes D1 in parallel with it not to be connected to the power amplifier circuit. When the fifth switch k5 is in an open state, the fifth switch k5 controls the reverse diodes D2 in parallel with it to be connected to the power amplifier circuit. When the fifth switch k5 is in a closed state, the fifth switch k5 controls the reverse diodes D2 in parallel with it not to be connected to the power amplifier circuit. In this way, flexible adjustment of the number of forward diodes D1 and reverse diodes D2 connected to the power amplifier circuit is achieved, and the debugging period of the RF front-end module chip is shortened.

[0104] In some embodiments, the power amplifier circuit 200 further includes a first matching network 206 including a sixth capacitor C6 and a fourth inductor L4; the sixth capacitor C6 and the fourth inductor L4 are connected in series between the first end (PA2_Collector) and the ground end of the second-stage power amplifier 202, as shown in FIG. 2. Figure 12 Here, the sixth capacitor C6 and the fourth inductor L4 together form a trap, which can suppress the harmonics of a specific frequency point in the signal output by the first end of the second-stage power amplifier 202, thereby improving the stability of the power amplifier circuit. Moreover, the first matching network 206 can also be used to form an output matching network 207 of the power amplifier circuit 200, which is used to convert an external load resistance into an optimal load resistance required by the power amplifier circuit 200, so as to ensure maximum output power. Figure 12

[0105] Here, the sixth capacitor C6 and the fourth inductor L4 together form a trap, which can suppress the harmonics of a specific frequency point in the signal output by the first end of the second-stage power amplifier 202, thereby improving the stability of the power amplifier circuit. Moreover, the first matching network 206 can also be used to form an output matching network 207 of the power amplifier circuit 200, which is used to convert an external load resistance into an optimal load resistance required by the power amplifier circuit 200, so as to ensure maximum output power.

[0106] In some embodiments, the first matching network 206 further includes another capacitor C and a switch k (the capacitor C and the switch k are not shown in FIG. 2) connected in parallel across the sixth capacitor C6, and the switch k can selectively connect the capacitor C to the first matching network 206, thereby achieving flexible adjustment of the suppression frequency and shortening the debugging period of the RF front-end module chip. Figure 12

[0107] ​​In some embodiments, the power amplifier circuit 500 further comprises a second matching network 503 including a seventh capacitor C7 and a fifth inductor L5, the seventh capacitor C7 and the fifth inductor L5 being connected in parallel between the first terminal of the second stage power amplifier 202 (PA2_Collector) and the radio frequency output terminal, as shown in FIG. 2B. Figure 12 Here, the seventh capacitor C7 and the fifth inductor L5 together form a tank, which can suppress the harmonics of a specific frequency point in the signal output from the first terminal of the second stage power amplifier 202, thereby improving the stability of the power amplifier circuit. In addition, the second matching network 503 can also be used to form an output matching network 504 of the power amplifier circuit 500, which is used to convert an external load resistance into an optimal load resistance required by the power amplifier circuit 500 to ensure maximum output power. Figure 12

[0108] Here, the seventh capacitor C7 and the fifth inductor L5 together form a tank, which can suppress the harmonics of a specific frequency point in the signal output from the first terminal of the second stage power amplifier 202, thereby improving the stability of the power amplifier circuit. In addition, the second matching network 503 can also be used to form an output matching network 504 of the power amplifier circuit 500, which is used to convert an external load resistance into an optimal load resistance required by the power amplifier circuit 500 to ensure maximum output power.

[0109] In other embodiments, the power amplifier circuit comprises both the first matching network 206 and the second matching network 503, as shown in FIG. 2C. Figure 12 The first matching network 206 and the second matching network 503 are respectively used to suppress the harmonics of different frequency points. For example, the first matching network 206 is used to suppress the harmonics of the 2f0 frequency point, and the second matching network 503 is used to suppress the harmonics of the 3f0 frequency point. In addition, the first matching network 206 and the second matching network 503 can together form an output matching network of the power amplifier circuit.

[0110] Reference is made to the frequency spectrum diagram of the signal output after the harmonics are suppressed by the first matching network and the second matching network provided by the embodiments of the present disclosure. Figure 13 , Figure 13 For example, when f0 is 800MHz, the first matching network 206 and the second matching network 503 are used to respectively suppress the harmonics of the 1.63GHz (about 2f0) frequency point and the harmonics of the 2.44GHz (about 3f0) frequency point. Figure 13

[0111] In some embodiments, the power amplifier circuit 200 further comprises an input matching network 208 and an inter-stage matching network 209, as shown in FIG. 2A. Figure 2

[0112] The input matching network 208 is used to match the output impedance of the signal source and the input impedance of the first stage power amplifier 201, so that the first stage power amplifier 201 obtains the maximum excitation power. The inter-stage matching network 209 can act as a buffer between the first stage power amplifier 201 and the second stage power amplifier 202, which realizes the optimization of impedance conversion and reduces signal reflection. ​​​

[0113] It should be noted that the closing and opening of each switch mentioned above in the embodiments of the present disclosure is controlled by a control signal provided by a control circuit located outside the power amplifier circuit. In actual applications, the closing or opening of the first switch can be controlled by different control signals according to different application scenarios (for example, the power amplifier circuit is applied to different modules), so as to realize flexible adjustment of the suppression frequency point and shorten the debugging period of the radio frequency front-end module chip.

[0114] In the embodiments of the present disclosure, by adding a low-frequency resonance network, a first gain reduction network, a second gain reduction network, a third gain reduction network, a first matching network and a second matching network in the single-stage power amplifier circuit as shown in Figure 1 The stability of the power amplifier circuit is effectively improved by analyzing the gain, resonance frequency point and direct current coupling from the aspects of adding a low-frequency resonance network, a first gain reduction network, a second gain reduction network, a third gain reduction network, a first matching network and a second matching network in the single-stage power amplifier circuit. At the same time, the power amplifier circuit of the embodiments of the present disclosure can adaptively and flexibly adjust the suppression frequency point and the gain for different radio frequency front-end module chips, has strong universality, reduces the design difficulty of the radio frequency front-end module chip, and shortens the debugging period of the radio frequency front-end module chip.

[0115] The embodiments of the present disclosure also provide a radio frequency chip, which includes any of the power amplifier circuits described above.

[0116] In some embodiments, the radio frequency chip can further include at least one of the following: an antenna switch (Switch), a filter (Filter), a duplexer (Duplexer and Diplexer), a low noise amplifier (LNA), etc.

[0117] The embodiments of the present disclosure also provide an electronic device, which includes any of the power amplifier circuits described above, or the electronic device includes the radio frequency chip described above.

[0118] In some embodiments, the electronic device can be one of a server, a mobile phone, a tablet, a computer with wireless transceiver function, a palmtop computer, a desktop computer, a personal digital assistant, a portable media player, a smart speaker, a navigation device, a smart watch, smart glasses, a wearable device such as a smart necklace, a pedometer, a digital TV, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a car in a car networking system, a car-mounted device, a car-mounted module, and the like.

[0119] It should be understood that every feature, structure, or characteristic mentioned in the specification, whether explicitly mentioned or not, is considered to be part of at least one embodiment of the present disclosure. Therefore, the appearance of "in one embodiment" or "in an embodiment" in various places in the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the sequence numbers of the above processes does not mean the order of execution in various embodiments of the present disclosure, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence numbers of the above embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0120] The above description is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made according to the disclosure content of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A power amplifier circuit, characterized in that, The power amplifier circuit includes: At least two cascaded power amplifiers; A low-frequency resonant network includes at least one first capacitor, at least two second capacitors, and at least two first inductors; At least one power supply terminal is provided for supplying power voltage to at least two stages of the power amplifier; Each of the first capacitors is coupled between the power supply terminal and the ground terminal; each of the second capacitors is coupled between the first terminal of the corresponding stage of the power amplifier and the ground terminal; each stage of the power amplifier is coupled to a first inductor, and the first inductor is connected between the first terminal of the power amplifier and the power supply terminal that provides the power supply voltage to the power amplifier; the first capacitor includes a decoupling capacitor.

2. The power amplifier circuit according to claim 1, characterized in that, Also includes: The first gain reduction network includes a third capacitor, a second inductor, and a first resistor; the second inductor and the first resistor are connected in series between the RF input terminal and the second terminal of the first-stage power amplifier; the third capacitor is connected between the RF input terminal and the second terminal of the first-stage power amplifier.

3. The power amplifier circuit according to claim 2, characterized in that, The first degaussing network further includes: A first switch; the first switch is connected in series in the branch where the second inductor is located; the first switch controls the second inductor and the first resistor to be connected to the power amplifier circuit.

4. The power amplifier circuit according to claim 1, characterized in that, Also includes: The second gain reduction network includes a fourth capacitor, a third inductor, and a second resistor connected in series; the second gain reduction network is coupled between the ground terminal and the second terminal of the first-stage power amplifier.

5. The power amplifier circuit according to claim 4, characterized in that, The second gain reduction network also includes: The second switch is connected in series in the branch where the fourth capacitor is located; the second switch controls the fourth capacitor, the third inductor and the second resistor to be connected to the power amplifier circuit.

6. The power amplifier circuit according to claim 4, characterized in that, The second gain reduction network also includes: A fifth capacitor and a third switch; the fifth capacitor and the third switch are connected in series between the two ends of the fourth capacitor; the third switch controls the fifth capacitor to be connected to the power amplifier circuit.

7. The power amplifier circuit according to claim 1, characterized in that, Also includes: The third gain reduction network consists of multiple forward diodes connected in series and multiple reverse diodes connected in series. The plurality of series-connected forward diodes and the plurality of series-connected reverse diodes are connected in parallel between the second terminal of the second-stage power amplifier and the ground terminal.

8. The power amplifier circuit according to claim 7, characterized in that, The third gain reduction network also includes: The switch short-circuit network includes a fourth switch connected in parallel with any of the forward diodes and a fifth switch connected in parallel with any of the reverse diodes; the fourth switch controls the forward diodes to be connected to the power amplifier circuit; the fifth switch controls the reverse diodes to be connected to the power amplifier circuit.

9. The power amplifier circuit according to claim 1, characterized in that, Also includes: The first matching network includes a sixth capacitor and a fourth inductor; the sixth capacitor and the fourth inductor are connected in series between the first terminal of the second-stage power amplifier and the ground terminal.

10. The power amplifier circuit according to claim 1, characterized in that, Also includes: The second matching network includes a seventh capacitor and a fifth inductor; the seventh capacitor and the fifth inductor are connected in parallel between the first terminal and the RF output terminal of the second-stage power amplifier.

11. The power amplifier circuit according to claim 1, characterized in that, The first-stage power amplifier includes a driver-stage power amplifier and a final-stage power amplifier.

12. A radio frequency chip, characterized in that, The radio frequency chip includes the power amplifier circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that, The electronic device includes the power amplifier circuit according to any one of claims 1 to 11, or the electronic device includes the radio frequency chip according to claim 12.

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