Semiconductor storage device and method for manufacturing a semiconductor storage device

Abstract

A semiconductor storage device (1) of an embodiment comprises: a disk-like region (LI) extending in a stacked body (LM) in a first direction that intersects a stacking direction of the stacked body (LM) and the stacking direction; a column (PL) arranged adjacent to the disk-like region (LI) in the second direction and containing a semiconductor layer (CN) extending in the stacked body (LM) in the stacking direction; a first layer (DSLb) arranged above the stacked body (LM) and comprising a semiconductor as its main component;and a second layer (ASL) arranged above the first layer (DSLb) comprising a semiconductor as its main component, wherein the plate-like region (LI) includes a protruding section penetrating the first layer (DSLb) and extending upwards, and the protruding section is covered with a third layer (DSLa) arranged between the first and second layers (DSLb, ASL) comprising a semiconductor as its main component.

Description

AREA

[0001] The embodiments described here generally relate to a semiconductor storage device and a method for manufacturing the semiconductor storage device. BACKGROUND

[0002] In a semiconductor storage device, such as a three-dimensional non-volatile memory, a column is formed that penetrates a stacked structure in which multiple conductive and insulating layers are alternately stacked. At this point, laser light or similar light can be emitted from above the semiconductor storage device to crystallize a channel layer of the column and activate impurities within that channel layer. However, crystallization of the channel may be insufficient around the column if it borders another element or similar component. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A and Fig. Figure 1B shows views illustrating a schematic configuration example of a semiconductor storage device according to one embodiment; Fig. Figures 2A to 2C are cross-sectional views illustrating an example of a configuration of the semiconductor storage device according to the embodiment; Fig. Figures 3A to 3C are views that successively illustrate part of a procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 4A and Fig. Figures 4B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 5A and Fig. Figures 5B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 6A and Fig. Figure 6B shows views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 7A and Fig. 7B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 8A and Fig. Figures 8B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 9A and Fig. Figure 9B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. 10A and Fig. 10B are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. Figures 11A to 11D are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. Figures 12A to 12D are views that successively illustrate part of the procedure for manufacturing the semiconductor storage device according to the embodiment; Fig. Figures 13A to 13D are views illustrating a method for doping impurities into a channel layer of a semiconductor memory device according to a comparative example; and Fig. Figures 14A to 14C are views illustrating a method for doping impurities into the channel layer of the semiconductor memory device according to the comparative example. DETAILED DESCRIPTION

[0003] A semiconductor storage device of one embodiment comprises: a stacked body in which a plurality of conductive layers and a plurality of first insulating layers are stacked alternately one after the other; a plate-like section extending in the stacked body in a first direction that intersects a stacking direction of the stacked body and the stacking direction, and dividing the stacked body in a second direction that intersects the first direction and the stacking direction; a column arranged adjacent to the plate-like section in the second direction and comprising a semiconductor layer extending in the stacked body in the stacking direction; a first layer arranged above the stacked body and comprising a semiconductor as its main component;and a second layer arranged above the first layer and containing a semiconductor as a major component, the plate-like section including a projection section penetrating the first layer and extending upwards, and the projection section being covered with a third layer arranged between the first and second layers and containing a semiconductor as a major component.

[0004] One embodiment of the present invention is described in detail below with reference to the drawings. It should be noted that the present invention is not limited to the embodiment described below. Furthermore, the components of the embodiment described below include those that are readily conceivable to those skilled in the art or those that are essentially the same. (Configuration example of a semiconductor storage device)

[0005] The Fig. 1A and Fig. Figure 1B shows views illustrating a schematic configuration example of a semiconductor storage device 1 according to the embodiment. More specifically, Fig. 1A a cross-sectional view of the semiconductor storage device 1 along an X-direction, and Fig. Figure 1B is a schematic top view illustrating a layout of the semiconductor storage device 1.

[0006] In Fig. However, hatching was omitted in section 1A for the sake of clarity. Furthermore, in Fig. 1A configurations are illustrated which are not necessarily present in the same cross-section, and some of the top layer wiring and the like has been omitted.

[0007] Furthermore, in the present description, both the X-direction and the Y-direction are directions along the orientation of the surfaces of the word lines WL, and the X-direction and the Y-direction are orthogonal to each other. Additionally, the electrical output direction of the word lines WL can be referred to as the first direction, and the first direction is a direction along the X-direction. Furthermore, a direction intersecting the first direction can be referred to as the second direction, and the second direction is a direction along the Y-direction. However, since the semiconductor memory device 1 may have a manufacturing defect, the first direction and the second direction are not necessarily orthogonal to each other.

[0008] As in Fig. As illustrated in Figure 1A, the semiconductor storage device 1 comprises a semiconductor substrate SB, peripheral circuits CBA, one or more select gate lines SGD, a plurality of word lines WL, one or more select gate lines SGS, a source line SL and an electrode film EL in order from the bottom of the drawing.

[0009] The semiconductor substrate SB is, for example, a silicon substrate. The peripheral circuits CBA, comprising transistors TR, wiring, and the like, are arranged on the surface of the semiconductor substrate SB and are completely covered with an insulating layer 40. Above the semiconductor substrate SB, on which the peripheral circuits CBA and the like are arranged, are a plurality of word lines WL and the select-gate lines SGD and SGS, which are completely covered with an insulating layer 50.

[0010] As in the Fig. 1A and Fig. As illustrated in Figure 1B, a storage region MR is arranged in a central section of the multiple word lines WL and the like in the X direction, and staircase regions SR are arranged at both end sections of the plurality of word lines WL and the like in the X direction. The storage region MR and the staircase regions SR are subdivided into a plurality of areas by a plurality of plate-like contacts LI that penetrate the plurality of word lines WL and the like and extend along the X direction.

[0011] It should be noted that the areas located between the plate-like contacts LI adjacent in the Y-direction, and encompassing the memory region MR and the stair regions SR, are designated as block regions BLK. As described below, the memory region MR comprises a multitude of memory cells that store data non-volatilely, and the block region BLK described above is a data erasure unit.

[0012] Additionally, a multitude of separating layers SHE are arranged between the plate-like contacts LI adjacent in the Y-direction. These layers penetrate the selection gate lines SGD and extend in the X-direction. The multitude of separating layers SHE extend in the X-direction across the entire storage region MR and reach to a portion of the stair regions SR at both end sections in the X-direction.

[0013] In the memory region MR, a multitude of columns PL are arranged. The multitude of columns PL penetrates the multitude of word lines WL and the selection gate lines SGD and SGS, and an end section of each of the multiple columns PL extends into the source line SL.

[0014] The electrode film EL is arranged over a metal layer TS, with an insulating layer 60 positioned between them. The entire electrode film EL, with the exception of a pad area PD located in a boundary region PR on the outside of the word lines WL and the like in the X direction, is covered with an insulating layer 70. The insulating layer 70 has a configuration in which, for example, a silicon oxide layer, a silicon nitride layer, a polyimide layer, and the like are stacked from the bottom side of the layer.

[0015] The electrode film EL is connected to the source line SL, a through-hole C3, and the like by a connector PG or the like, which penetrates the insulating layer 60. The through-hole C3 is provided in the edge region PR, penetrates the insulating layer 50 covering the word lines WL and the like, and the insulating layer 40 covering the edge circuits CBA, and is connected to the semiconductor substrate SB on which the edge circuits CBA are arranged.

[0016] From outside the semiconductor storage device 1, the semiconductor substrate SB is controlled to a predetermined potential via the pad area PD and the through-contact C3. Additionally, current and a signal are supplied from outside the pad area PD to the semiconductor storage device 1.

[0017] A large number of memory cells are formed at the intersections of the columns PL and the word lines WL. This allows the semiconductor memory device 1, for example, to be configured as a three-dimensional non-volatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the stair region SR, stair sections SP are arranged in which the multiple word lines WL and the select gate lines SGD and SGS are processed and terminated to form a stair configuration. The separation layers SHE described above extend from the storage region MR to a section of the stair region SR in which the select gate lines SGD are processed to form a stair configuration. As a result, in a block region BLK, the select gate lines SGD are subdivided into several areas. In other words, the separation layers SHE penetrate the sections below the multiple word lines WL, so that these sections are subdivided into patterns of multiple select gate lines SGD.

[0019] Contacts CC, which extend upwards in the insulating layer 50 and are connected to the word lines WL and the select gate lines SGD and SGS of the layers, are arranged on terrace sections of steps that include the multitude of word lines WL and the select gate lines SGD and SGS.

[0020] It should be noted that in the present description, the direction in which the terrace surfaces of the multiple word lines WL and the select gate lines SGD and SGS point is defined as the underside of the semiconductor storage device 1.

[0021] In the word lines WL and the select-gate lines SGS, a contact CC is connected for each layer. In the select-gate lines SGD, a contact CC is connected for each segment separated by the separator layers SHE per layer.

[0022] Here, in a block region BLK, several contacts CC are arranged on one of the stair regions SR on both sides in the X direction. Furthermore, when viewed, for example, on one side in the X direction, the multiple contacts CC are arranged every two block regions BLK.

[0023] That means, in the example of Fig. In the uppermost block region BLK in the drawing, several contacts CC are arranged, for example, in the stair region SR on the left side of the drawing, extending from the stair regions SR at both end sections in the X-direction. Furthermore, in the block regions BLK located one and two below the block region BLK described above, several contacts CC are arranged in the stair region SR on the right side of the drawing, outside the stair regions SR, at both end sections in the X-direction. Finally, in the lowest block region BLK in the drawing, several contacts CC are again arranged in the stair region SR on the left side of the drawing.

[0024] Accordingly, the CC contacts of the stair regions SR belong to both end sections in the X direction, which are in Fig. The areas shown in 1A belong to different block regions BLK and are not actually located in the same cross-section.

[0025] The word lines WL and the like, stacked in multiple layers, are individually brought out through these contacts CC. More precisely, a write voltage, a read voltage, and the like are applied by these contacts CC, via the word lines WL, to the memory cells located in the memory region MR in the middle section of the multiple word lines WL at the same vertical positions as the memory cells.

[0026] It should be noted that the semiconductor storage device 1 of the embodiment is configured such that the insulating layer 40 covering the peripheral circuits CBA and the insulating layer 50 covering the word lines WL and the like are connected to each other. In this way, the insulating layers 40 and 50 function as interconnecting layers. Furthermore, the electrode pads arranged on the surfaces of the insulating layers 40 and 50 are connected to each other by connecting them, so that the peripheral circuits CBA are electrically connected to the contacts CC, the multiple word lines WL, the select gate lines SGS and SGD, and the columns PL.

[0027] The application of a predetermined voltage from the CC contacts to the memory cells is controlled by the peripheral circuits CBA, which are electrically connected to these configurations. In this way, the peripheral circuits CBA control the electrical operation of the memory cells.

[0028] Next, a detailed configuration example of the semiconductor storage device 1 will be given with reference to the Fig. 2A to 2C described. The Fig. Figures 2A to 2C are cross-sectional views illustrating an example of a configuration of the semiconductor storage device 1 according to the embodiment.

[0029] More specifically, Fig. 2A a cross-sectional view along the Y-direction of the memory region MR of the semiconductor memory device 1. In Fig. 2A structures above the insulating layer 60 and below an insulating layer 52 described below have been omitted.

[0030] Fig. 2B is an enlarged cross-sectional view of column PL at the height position of word line WL. Fig. 2C is an enlarged cross-sectional view of the column PL at the height position of the selection gate line SGD or SGS.

[0031] As in Fig. Figure 2A illustrates that the metal layer TS, a barrier metal layer BM and the source conductor SL are arranged below the insulating layer 60 in the following order starting from the insulating layer 60.

[0032] The insulating layer 60 is, for example, a silicon oxide layer or the like. The metal layer TS is, for example, a tungsten layer or the like and, in addition to the underlying source conductor SL, functions as the source conductor metal of the semiconductor memory device 1. The barrier metal layer BM is, for example, at least one titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer and suppresses the diffusion of tungsten atoms from the metal layer TS into an adjacent structure.

[0033] The source line SL has a multilayer structure in which, for example, an auxiliary source line ASL and a main source line DSLb are arranged downwards from the barrier metal layer BM in that order. The auxiliary source line ASL is, for example, an undoped amorphous layer, an undoped polysilicon layer, or an undoped semiconductor layer in which an amorphous layer and a polysilicon layer are mixed. The main source line DSLb is, for example, a polycrystalline semiconductor layer, such as an undoped polysilicon layer, or an amorphous semiconductor layer, such as an undoped amorphous silicon layer. However, at least one of the auxiliary source lines ASL and the main source line DSLb may contain impurities that lead to N-type conductivity, such as phosphorus or arsenic.

[0034] It should be noted that the source line SL may contain a stop layer DSLa as described below. The stop layer DSLa is, for example, a polycrystalline semiconductor layer, such as a polysilicon layer, containing N-type impurities such as phosphorus or arsenic.

[0035] Below the source line SL is a stacked body LM in which the plurality of word lines WL and plurality of insulating layers OL are stacked alternately. The stacked body LM is configured to include a stacked body LMa located below the source line SL and a stacked body LMb located further below the stacked body LMa.

[0036] The stacked body LMa contains the select gate lines SGS1 and SGS0 in the order starting from the source line SL-side above the top word line WL. These select gate lines SGS1 and SGS0 are source-side select gate lines.

[0037] The stacked body LMb contains selection gate lines SGD1 and SGD0 in the order from the bottommost word line WL-side further downstream. These selection gate lines SGD1 and SGD0 are drain-side selection gate lines.

[0038] The number of word lines WL and selection gate lines SGS and SGD contained in the stacked body LM is arbitrary. Accordingly, the stacked body LM can contain one, three, or more selection gate lines SGS and SGD. The word lines WL and selection gate lines SGS and SGD are, for example, tungsten or molybdenum layers, and the insulating layers OL are, for example, silicon oxide layers.

[0039] Insulating layers 52 and 53 are arranged in sequence from the side of the stacked body LM below the stacked body LM. These insulating layers 52 and 53 form part of the insulating layer 50 described above (see Fig. 1A).

[0040] As described above, the multitude of plate-like contacts LI extend in the stacking direction of the stacking body LM and along the X-direction. More precisely, the plate-like contacts LI penetrate the stacking body LM and the main source line DSLb and project into the stop layer DSLa, which is located between the main source line DSLb and the auxiliary source line ASL.

[0041] The stop layer DSLa is unevenly distributed near the plate-like contacts LI, arranged over an intermediate insulating layer OSL on the main source line DSLb, and covers the upper end sections of the plate-like contacts LI. The plate-like contacts LI also penetrate the intermediate insulating layer OSL. The intermediate insulating layer OSL is, for example, a silicon oxide layer or the like.

[0042] Each of these plate-like contacts LI comprises a conductive layer 24, for example a tungsten layer, and an insulating layer 54 that covers one side wall of the conductive layer 24. The insulating layer 54 also covers an upper end section of the conductive layer 24 that projects into the stop layer DSLa.

[0043] However, as described above, the main source line DSLb, the stop layer DSLa, and the auxiliary source line ASL are each semiconductor layers, for example, silicon layers. Accordingly, in the actual semiconductor memory device 1, the interfaces and the like of the main source line DSLb, the stop layer DSLa, and the auxiliary source line ASL cannot be distinguished, and these layers may not be individually identifiable.

[0044] Even in such a case, it can be identified that among the various semiconductor layers described above, the semiconductor layer located on the upper end sections of the columns PL is the thin auxiliary source line ASL, while the relatively thick semiconductor layers of the stop layer DSLa and the auxiliary source line ASL are located on the upper end sections of the plate-like contacts LI. Since the main source line DSLb and the stop layer DSLa are layers of different materials, it can also be determined that the intermediate insulating layer OSL is located between them, and thus a distinction can be made between the main source line DSLb and the stop layer DSLa. While the main source line DSLb and the auxiliary source line ASL are undoped semiconductor layers, the stop layer DSLa, which covers the upper end sections of the plate-like contacts LI, still contains N-type impurities.Even if the main source line DSLb and the auxiliary source line ASL contain N-type impurities, they can be distinguished from the stop layer DSLa because the crystallinity varies depending on the type of heat treatment in the manufacturing process or depending on the type or concentration of impurities.

[0045] It is evident from the above that the upper end sections of the columns PL are not covered with the stop layer DSLa, while the upper end sections of the plate-like contacts LI are covered with the stop layer DSLa.

[0046] Furthermore, the plate-like contacts LI, for example, have a tapered shape where the width in the Y-direction increases from the upper end section to the lower end section. Alternatively, the plate-like contacts LI, for example, have a convex shape where the width in the Y-direction is maximized at a predetermined position between the upper end section and the lower end section.

[0047] Between the plate-shaped contacts LI adjacent in the Y-direction of the plurality of plate-shaped contacts LI, one or more separating layers SHE, which are insulating layers 55 such as silicon oxide layers, extend in a lower layer section of the stacked body LM in the direction along the X-direction. In the example of Fig. 2A The separating layers SHE penetrate the selection gate lines SGD0 and SGD1 described above and reach the insulation layer OL, which is adjacent to selection gate line SGD1 in the stacking direction. This divides the selection gate lines SGD0 and SGD1 into several sections.

[0048] Furthermore, the multitude of columns PL extend between the plate-like contacts LI adjacent in the Y-direction within the stacked body LM in the stacking direction of the stacked body LM. More precisely, these columns PL extend within the stacked body LM in the stacking direction of the stacked body LM from the lowest insulating layer OL of the stacked body LM and penetrate the stacked body LM and the main source line DSLb.

[0049] The multitude of columns PL are, for example, arranged offset in the stacking direction of the stacked body LM. The individual columns PL have, for example, a circular shape, an elliptical shape, an elongated shape (oval shape), or the like as a cross-sectional shape in a direction along the layering direction of the stacked body LM, i.e., in a direction along the XY plane.

[0050] Furthermore, each of the columns PL has a conical shape, in which the diameter and cross-sectional area increase from the upper layer surface to the lower layer surface in a section penetrating the stacked body LMa and a section penetrating the stacked body LMb. Alternatively, each of the columns PL has, for example, a curved shape, in which the diameter and cross-sectional area are maximized at a predetermined position between the upper layer surface and the lower layer surface in a section penetrating the stacked body LMa and a section penetrating the stacked body LMb.

[0051] In addition, the column PL contains a core layer CR, which serves as the core material, a channel layer CN, which covers a side wall of the core layer CR, a storage layer ME, which covers a side wall of the channel layer CN, and a cover layer CP, which is located at a lower end section of the column PL.

[0052] From the core layer CR, the channel layer CN, and the storage layer ME, the storage layer ME penetrates the stacked body LM and the main source line DSLb, reaching the auxiliary source line ASL. Furthermore, the core layer CR and the channel layer CN penetrate the stacked body LM and the main source line DSLb, and their upper end sections extend into the metal layer TS. The upper end section of the channel layer CN in the metal layer TS is covered, in this order, by the auxiliary source line ASL and the barrier metal layer BM.

[0053] This means that the portion of channel layer CN extending into the metal layer TS is not covered by the storage layer ME, and channel layer CN is in direct contact with the auxiliary source line ASL. Thus, channel layer CN is electrically connected to the main source line DSLb via the auxiliary source line ASL. N-type impurities such as phosphorus and arsenic are contained within channel layer CN from the upper end section connected to the auxiliary source line ASL down to the depth positions of the selection gate lines SGS0 and SGS1 described above.

[0054] It should be noted that the stop layer DSLa and the intermediate insulation layer OSL described above are unevenly distributed near the plate-like contacts LI and are not located near the columns PL.

[0055] The cover layers CP, located at the lower end sections of the columns PL, connect the channel layers CN and the connectors CH, which extend such that they penetrate the lowest insulating layer OL of the stacked body LM and the insulating layer 52 below it. The connectors CH connect a bit line BL located in insulating layer 53 to the columns PL arranged in the stacked body LM. The bit line BL extends below the stacked body LM in the Y direction, intersecting the output direction of the word lines WL.

[0056] As in the Fig. 2B and Fig. As illustrated in Figure 2C, the storage layer ME has a stacked structure comprising a block insulation layer BK, a charge storage layer CT, and a tunnel insulation layer TN, in that order, around an outer circumferential side of the column PL. The charge storage layer CT of the storage layer ME is, for example, a silicon nitride layer or the like. The block insulation layer BK and the tunnel insulation layer TN of the storage layer ME, as well as the core layer CR, are, for example, silicon oxide layers or the like. The channel layer CN and the cover layer CP are polycrystalline semiconductor layers, such as polysilicon layers or the like.

[0057] As in Fig. As illustrated in Figure 2B, the above configuration forms a memory cell MC in each section facing the individual word lines WL on the side face of the pillar PL. When a predetermined voltage is applied to the word line WL, data is written to and read from the memory cell MC.

[0058] As in Fig. Figure 2C illustrates a selection gate STD in a section where the side surface of the pillar PL faces the selection gate lines SGD0 and SGD1. Additionally, a selection gate STS is formed in a section where the side surface of the pillar PL faces the selection gate lines SGS0 and SGS1 below the word lines WL.

[0059] When predetermined voltages are applied to the selection gate lines SGD and SGS, the selection gates STD and STS are switched on or off, and the memory cells MC of column PL, to which the selection gate STD or STS belongs, can be brought into a selected or unselected state. As described above, the channel layer CN contains impurities such as phosphorus or arsenic at the depth positions of the selection gate lines SGD and SGS, so a threshold voltage of the selection gate STS can be set to a desired value. (Method for manufacturing a semiconductor storage device)

[0060] Next, with reference to the Fig. Sections 3A to 12D describe a method for manufacturing the semiconductor storage device 1 of the embodiment. Fig. Figures 3A to 12D are views that successively illustrate a part of the process for manufacturing the semiconductor storage device 1 according to the embodiment. More precisely, they show Fig. 3A to 12D a cross-section along the Y-direction of an area that will later become the storage region MR.

[0061] It should be noted that in the following description, the direction in which a surface of a support substrate SS, described below, or of the semiconductor substrate SB faces on a side where various types of treatments are performed, is defined as the top side of the semiconductor storage device 1 during fabrication. In other words, the top side of the following drawings is the top side of the semiconductor storage device 1 during fabrication, and the bottom side of the drawing is the bottom side of the semiconductor storage device 1 during fabrication.

[0062] As in Fig. Figure 3A illustrates the preparation of the support substrate SS. The support substrate SS can be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, a conductive substrate, or the like.

[0063] The following describes the formation steps for creating the configuration later serving as the source line SL, the stacked body LM, the columns PL, and the like on the top of the support substrate SS in a state where the up-down direction is oriented relative to the examples described above. Fig. 1A and 2A to 2C are the reverse.

[0064] First, the stop layer DSLa, the intermediate insulating layer OSL, and the main source line DSLb are formed on the substrate SS in that order. The stop layer DSLa and the main source line DSLb are polycrystalline semiconductor layers, such as undoped polysilicon layers. At this stage, the stop layer DSLa and the main source line DSLb can be amorphous silicon layers. The intermediate insulating layer OSL is a silicon oxide layer or the like.

[0065] Additionally, a stacked body LMsa, in which several insulating layers NL and several insulating layers OL are alternately stacked on top of each other, is formed on the main source line DSLb. The insulating layers NL are, for example, silicon nitride layers or the like and act as sacrificial layers, which are later replaced by conductive materials and become the word lines WL or the select-gate lines SGS.

[0066] Subsequently, the insulating layers NL and OL, although not illustrated, are processed into a stepped shape in a portion of the stacked body LMsa. Such processing can be carried out by repeatedly thinning a mask pattern, such as a photoresist layer, and etching the insulating layers NL and OL of the stacked body LMsa.

[0067] This means that a mask pattern is formed on the top surface of the stacked body LMsa, and the insulating layer NL and the insulating layer OL in an exposed area are etched away sequentially. Additionally, an end section of the mask pattern is retracted by treatment with oxygen plasma or the like to re-expose the top surface of the stacked body LMsa, and the insulating layer NL and the insulating layer OL are again etched away sequentially. By repeating this treatment several times, the stacked body LMsa is formed with a step-like structure at both end sections in the X-direction.

[0068] The stair-shaped section is then covered at both end sections in the X-direction with a portion of the insulating layer 50 described above (see Fig. 1A).

[0069] As in Fig. As illustrated in Figure 3B, a multitude of storage holes MHa are formed, extending in the stacking direction through the stacked body LMsa. These storage holes MHa penetrate the stacked body LMsa, the main source line DSLb, and the intermediate insulation layer OSL, reaching a predetermined depth in the stop layer DSLa. These storage holes MHa are regions that later become regions of the columns PL penetrating the stacked body LMa.

[0070] As in Fig. As illustrated in Figure 3C, the storage cavities MHa are filled with sacrificial layers 26, for example CVD carbon layers. This forms columns PLc in which the multiple storage cavities MHa are filled with the sacrificial layers 26.

[0071] As in Fig. As illustrated in Figure 4A, a stacked body LMsb is formed, covering the stacked body LMsa, in which the multiple insulating layers NL and the multiple insulating layers OL are stacked alternately. The insulating layers NL of the stacked body LMsb act as sacrificial layers, which are later replaced by conductive layers and become the word lines WL or the select-gate lines SGD.

[0072] Subsequently, the insulating layers NL and OL, although not illustrated, are processed into a stepped shape in a subregion of the stacked body LMsb. Such processing can be carried out by repeatedly thinning a mask pattern, such as a photoresist layer, and etching the insulating layers NL and OL of the stacked body LMsb, similar to the treatment of the stacked body LMsa described above.

[0073] At this point, the top step of the stair segment formed in the stacked body LMsa and the bottom step of the stair segment formed in the stacked body LMsb are brought close together to form a stair shape that extends continuously from the bottom layer of the stacked body LMsa to the top layer of the stacked body LMsb. As a result, the stacked bodies LMsa and LMsb are formed, in which the stair regions SR are formed with a stair shape extending from the stacked body LMsa to the stacked body LMsb at both end sections in the X-direction.

[0074] The stair shape is then continued at both end sections in the X direction with a part of the insulating layer 50 described above (see Fig. 1A) covered.

[0075] As in Fig. As illustrated in Figure 4B, several storage holes MHb are formed that penetrate the stacked body LMsb and are connected to the several columns PLc formed within the stacked body LMsa. The storage holes MHb are regions that later become regions of the columns PL penetrating the stacked body LMb.

[0076] As in Fig. As illustrated in Figure 5A, the sacrificial layers 26 are removed from the columns PLc at the bottoms of the storage holes MHb. This opens the storage holes MHa at the bottoms of the multiple storage holes MHb, and multiple storage holes MH are formed that penetrate the stacked bodies LMsb and LMsa, the main source line DSLb, and the intermediate insulation layer OSL, reaching the predetermined depth of the stop layer DSLa.

[0077] It should be noted that in a case where the sacrificial layers loaded in the columns PLc are CVD carbon layers or the like, the sacrificial layers 26 can be removed together from these columns PLc if this occurs during the formation of the storage holes MHb in Fig. 4B used mask patterns or the like are removed by ashling or the like using oxygen plasma.

[0078] As in Fig. 5B illustrates the storage layer ME, the block insulation layer BK, the charge storage layer CT and the tunnel insulation layer TN (see Fig. 2B and Fig. 2C) in this order, the storage layer ME is formed on the side walls and bottom surfaces of the storage holes MH. The storage layer ME is also formed on the top of the stacked body LMsb.

[0079] Furthermore, the channel layer CN and the core layer CR are formed in this order in the storage opening MH over the storage layer ME. This results in the channel layer CN being formed on top of the storage layer ME, covering the side and bottom surfaces of the storage opening MH, and the core layer CR being loaded into the middle part of the storage opening MH. The channel layer CN and the core layer CR are also formed in this order on the top of the stacked body LMsb over the storage layer ME.

[0080] It should be noted that the channel layer CN is not doped with impurities at this time and may be in an amorphous state, for example as an amorphous silicon layer.

[0081] As in Fig. As illustrated in Figure 6A, the core layers CR, the channel layers CN and the storage layers ME formed on the top of the stacked body LMsb are etched back and removed together with part of the top insulating layer OL of the stacked body LMsb, and the core layers CR are retracted to a predetermined depth of the storage holes MH to form recesses DN at the upper end sections of the storage holes MH.

[0082] As in Fig. Figure 6B illustrates that the cover layers CP are formed in the depressions DN at the upper end sections of the storage holes MH. At this point, the cover layers CP may be in an amorphous state, for example as amorphous silicon layers.

[0083] As in Fig. Figure 7A illustrates that by etching back the core layers CR, channel layers CN, storage layers ME, and the like, which are formed on the top of the stacked body LMsb, the uppermost insulating layer OL of the stacked body LMb, whose thickness has been reduced, is stacked. This forms the columns PL, whose upper end regions are embedded in the uppermost insulating layer OL of the stacked body LMsb. At this point, however, the storage layers ME cover the channel layers CN at the lower end sections of the columns PL.

[0084] As in Fig. As illustrated in Figure 7B, slots ST are formed that penetrate the stacked bodies LMsb and LMsa, the main source conductor DSLb, and the intermediate insulating layer OSL, reaching a predetermined depth in the stop layer DSLa. The slots ST also extend along the X-direction within the stacked bodies LMsa and LMsb.

[0085] As in Fig. Figure 8A illustrates how a removal fluid for the insulating layers NL, such as hot phosphoric acid, is allowed to flow from the slots ST into the stacked bodies LMsa and LMsb to remove the insulating layers NL from the stacked bodies LMsa and LMsb. As a result, stacked bodies LMga and LMgb are formed, containing a variety of cleavage layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0086] The stacked bodies LMga and LMgb with multiple cleavage layers GP have a fragile structure. The multiple columns PL support these fragile stacked bodies LMga and LMgb. This prevents bending of the insulating layers OL remaining in the stacked bodies LMga and LMgb and suppresses deformation or collapse of the stacked bodies LMga and LMgb.

[0087] As in Fig. As illustrated in Figure 8B, a source gas of a conductive material such as tungsten or molybdenum is injected from the slots ST into the stacked bodies LMga and LMgb, and the cleavage layers GP of the stacked bodies LMga and LMgb are filled with the conductive material to form the multitude of word lines WL and the like. As a result, the stacked body LM is formed, comprising the stacked bodies LMa and LMb in which the multitude of word lines WL and the like and the multitude of insulating layers OL are stacked alternately.

[0088] As described above, the treatment for forming the word lines WL from the insulating layers NL is also called replacement treatment.

[0089] As in Fig. Figure 9A illustrates that after the formation of the insulating layers 54 in the slots ST, the conductive layers 24 are formed to create the plate-like contacts LI.

[0090] As in Fig. Figure 9B illustrates that grooves GR are formed which penetrate one or more conductive layers, including the top conductive layer of the stacked body LMb.

[0091] As in Fig. As illustrated in Figure 10A, the insulating layers 55 are placed in the grooves GR to form the separating layers SHE, which divide the conductive layer on the top layer side of the stacked body LM into the pattern of selection gate leads SGD.

[0092] Additionally, although not illustrated, the multitude of contacts CC, which reach the word lines WL and the selection gate lines SGD and SGS, forming the steps of the stair structure of the stair regions SR, are formed from the top of the stair regions SR.

[0093] As in Fig. As illustrated in Figure 10B, after the formation of the insulating layer 52 covering the stacked body LM, the connectors CH are formed, which penetrate the top insulating layer OL of the stacked body LM and the insulating layer 52 and are connected to the cap layers CP at the upper end sections of the columns PL. Additionally, the insulating layer 53, which covers the insulating layer 52, is formed, and the bit line BL, to which the individual connectors CH are connected, is formed in the insulating layer 53.

[0094] It should be noted that, for example, the CH connector, the BL bit line and the like can be formed together using a dual-Damascus process or the like.

[0095] Furthermore, the peripheral circuits CBA, although not illustrated, are formed on the semiconductor substrate SB separately from the support substrate SS on which the stacked body LM is formed and are covered with the insulating layer 40. Contacts, vias, wiring, or the like are formed in the insulating layer 40, which connect the peripheral circuits CBA to the surface of the insulating layer 40 and to the electrode pad or the like formed on the top surface of the insulating layer 40.

[0096] Furthermore, the support substrate SS and the semiconductor substrate SB are connected to each other by the insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected to each other. These insulating layers 50 and 40 can be connected to each other by prior activation, for example by plasma treatment or the like. Additionally, by tempering after connecting the insulating layers 50 and 40, the electrode pads in the insulating layers 50 and 40 can be connected by a Cu-Cu connection or the like.

[0097] As in Fig. As shown in Figure 11A, various types of treatments are subsequently performed from the side of the support substrate SS, which is bonded in reverse to the semiconductor substrate SB. Accordingly, the following drawings illustrate a state in which various types of treatments are performed from the top of the columns PL and the plate-like contacts LI, with the portions of the columns PL and the plate-like contacts LI projecting into the stop position DSLa as upper end parts.

[0098] It should be noted that in the drawings according to Fig. 11A only illustrates the upper end sections of the columns PL and the plate-like contacts LI.

[0099] As in Fig. As illustrated in Figure 11B, the support substrate SS is removed by splitting the interface between the stop layer DSLa and the support substrate SS. Additionally, in the storage region MR, where the columns PL and the like are formed, the stop layer DSLa is removed using the intermediate insulating layer OSL as a stop layer. At this point, a photomask (not illustrated) or the like is formed on the stop layer DSLa at a position that overlaps the upper end sections of the plate-like contacts LI, and the stop layer DSLa covering the upper end sections of the plate-like contacts LI is not removed.

[0100] As a result, in the storage region MR, the upper end sections of the columns PL protrude beyond the intermediate insulating layer OSL. On the other hand, the upper end sections of the plate-like contacts LI remain in a state where they are covered by the stop layer DSLa.

[0101] As in Fig. Figure 11C illustrates that an implantation treatment with phosphorus, arsenic, or the like is performed on the upper end sections of the pillars PL that extend beyond the intermediate insulating layer OSL, and the semiconductor layers CN of the pillars PL are doped with N-type impurities via the storage layers ME. Doping with these impurities transforms at least the upper end sections of the channel layers CN into amorphous semiconductor layers, such as amorphous silicon layers.

[0102] On the other hand, the intermediate insulating layer OSL suppresses the doping of the main source conductor DSLb with these impurities. However, the above treatment allows the stop layer DSLa, which covers the upper end sections of the plate-shaped contacts LI, to be doped with impurities, and the stop layer DSLa can be transformed from a polysilicon layer or the like to an amorphous silicon layer or the like. If the stop layer DSLa is doped with impurities, the main source conductor DSLb can be further doped with impurities via the intermediate insulating layer OSL or the like. At this point, the impurity concentration of the stop layer DSLa can be higher than the impurity concentration of the main source conductor DSLb.If the stop layer DSLa is not doped with impurities, its impurity concentration can also be lower than that of the main source line DSLb. If both the stop layer DSLa and the main source line DSLb are not doped with impurities, both the stop layer DSLa and the main source line DSLb remain undoped polysilicon layers or amorphous silicon layers.

[0103] As in Fig. As illustrated in Figure 11D, the storage layers ME are removed from the upper end sections of the columns PL that extend beyond the intermediate insulating layer OSL. Simultaneously, the intermediate insulating layer OSL is removed. This exposes the upper end sections of the channel layers CN of the columns PL above the main source line DSLb. Since the insulating layers 54 of the plate-shaped contacts LI are covered by the stop layer DSLa at this point, they remain unaffected. Furthermore, the intermediate insulating layer OSL, located between the stop layer DSLa and the main source line DSLb, and through which the plate-shaped contacts LI extend, also remains intact.

[0104] As in Fig. As illustrated in Figure 12A, the auxiliary source line ASL is formed, covering the main source line DSLb, which was exposed as a result of removing the intermediate insulating layer OSL. At this point, the auxiliary source line ASL is formed in such a way that it also covers the upper end sections of the columns PL that extend beyond the main source line DSLb, as well as the stop layer DSLa, which covers the upper end sections of the plate-like contacts LI.

[0105] The auxiliary source layer (ASL) is formed as an undoped amorphous silicon layer. The ASL acts as a heat source, absorbing laser light during annealing. Subsequently, to reduce the contact resistance with the metal deposited on the ASL, ion implantation (implantation) of impurities that lead to N-type conductivity, such as phosphorus or arsenic, can be performed on the ASL surface. After ion implantation, annealing or a similar process can be carried out to improve the conductivity of the ASL.

[0106] As in Fig. As illustrated in Figure 12B, the channel layers CN of the columns PL covered with the auxiliary source line ASL are irradiated with laser light, and the channel layers CN are heated by the heat of the laser light. For example, laser light with a wavelength of 540 nm, such as from a green laser, can be used for this purpose. If laser light with a wavelength of 540 nm is used, the channel layers CN can be heated to approximately 1100°C.

[0107] As described above, the auxiliary source line ASL absorbs the laser light at the time of laser irradiation and acts as a heat source. Consequently, the auxiliary source line ASL is heated by the laser light, and the heat from the auxiliary source line ASL is further transferred to the upper end sections of the channel layers CN of the columns PL, thus annealing the channel layers CN.

[0108] As described above, performing the annealing treatment using laser light crystallizes the channel layers CN, which are amorphous due to impurity doping, and the N-type impurities doped into the channel layers CN can be activated. It should be noted that through such annealing treatment or the like, part or all of the auxiliary source line ASL, which is originally an amorphous silicon layer or the like, may become a polysilicon layer or the like, and part or all of the stop layer DSLa, which is an amorphous silicon layer or the like due to impurity doping, may become a polysilicon layer.

[0109] Additionally, at this time, the laser light is also emitted onto the formation area of ​​the plate-like contacts LI. The plate-like contacts LI comprise the conductive layers 24, such as tungsten layers, which have a relatively large volume and extend in the X-direction and in the stacking direction of the stacked body LM. However, the conductive layers 24 of the plate-like contacts LI are covered with insulating layers 54, such as silicon oxide layers, which have a lower thermal conductivity than the conductive layers 24. Therefore, the heating of the conductive layers 24 by the laser light is suppressed.

[0110] As in Fig. As illustrated in Figure 12C, the barrier metal BM is formed on the auxiliary source line ASL, which covers the main source line DSLb including the foreground sections of the columns PL and the plate-like contacts LI.

[0111] As in Fig. As illustrated in 12D, the metal layer TS, which covers the barrier metal BM, is further formed.

[0112] Next, the insulating layer 60 is formed on the metal layer TS, and the connector PG penetrating the insulating layer 60 is formed. Additionally, the electrode foil EL, connected to the connector PG in the insulating layer 60, is formed, and the insulating layer 70 covering the electrode foil EL is formed. Furthermore, an opening is provided in the insulating layer 70 to expose part of the electrode foil EL, thus forming the pad area PD.

[0113] In this way, the semiconductor storage device 1 of the embodiment is manufactured. (Overview)

[0114] A semiconductor memory device, such as a three-dimensional non-volatile memory, can be fabricated by forming peripheral circuits, including transistors and the like, and a stacked body, including word lines, columns PL and the like, on separate substrates and connecting these substrates together.

[0115] Furthermore, after joining the substrates together, various types of treatments can be performed from the back side of a support substrate that carries the stacked body or the like. These different types of backside treatments can include, for example, doping the column's channel layer with N-type impurities or the like, and activating the channel layer by annealing using laser light. A state at this point is described in the Fig. 13A to 14C shown.

[0116] The Fig. Figures 13A to 14C are views illustrating a method for doping impurities in channel layers CNx of the semiconductor memory device according to a comparative example.

[0117] As in Fig. Figure 13A illustrates that on the top surface of a semiconductor substrate, on which the peripheral circuits and the stacked body are mounted, columns PLx with channel layers CNx, whose upper end sections project into a stop layer DSLa, and plate-like contacts LIx with insulating layers 54x covering conductive layers 24, whose upper end sections project into the stop layer DSLa, are formed. As described above, the state of the semiconductor storage device of the comparison example in Fig. 13A the state of Fig. 11A of the embodiment described above.

[0118] As in Fig. Figure 13B illustrates the removal of a support substrate SS and the stop layer DSLa. In the comparative example, the entire stop layer DSLa is removed at this point. Consequently, not only the upper end sections of the columns PLx, but also the upper end sections of the plate-like contacts LIx are exposed above an intermediate insulating layer OSL.

[0119] As in Fig. As illustrated in Figure 13C, the leading portions of the channel layers CNx of the columns PLx are doped with N-type impurities via storage layers ME. This transforms the upper end regions of the channel layers CNx into amorphous semiconductor layers, for example, amorphous silicon layers.

[0120] As in Fig. As illustrated in Figure 13D, the storage layers ME are removed from the upper end sections of the protruding columns PLx, and the intermediate insulating layer OSL covering a main source conductor DSLb is removed. At this point, the insulating layers 54x covering the conductive layers 24 of the plate-like contacts LIx are exposed at the upper end sections. Therefore, the insulating layers 54x of the plate-like contacts LIx are partially removed, thinning along with the storage layers ME of the columns PLx and the intermediate insulating layer OSL.

[0121] As in Fig. Figure 14A illustrates that an auxiliary source line ASL is formed, which completely covers the main source line DSLb and the like.

[0122] As in Fig. As illustrated in Figure 14B, the channel layers CNx of the columns PLx covered with the auxiliary source line ASL are irradiated with laser light to crystallize the channel layers CNx and activate impurities in the channel layers CNx.

[0123] In the semiconductor storage device of the comparison example, however, the threshold voltage of the source-side selection gate formed in the columns PLx can vary between the several columns PLx. More precisely, in the columns PLx adjacent to the plate-like contacts LIx, the threshold voltage of the selection gate line can shift to a higher voltage than a desired value.

[0124] The inventor here has conducted intensive investigations to solve the aforementioned problem and has determined that the heat from the laser light is transferred to the conductive layers 24, which have a relatively large volume and are contained within the plate-like contacts LIx. As a result, it was found that the temperature in the columns PLx adjacent to the plate-like contacts LIx is not sufficiently increased by the laser light.

[0125] As in Fig. As illustrated in Figure 14C, it is assumed that the heat from the laser light is transferred to the conductive layers 24 of the plate-like contacts LIx, resulting in insufficient crystallization of the channel layers CNx in the columns PLx adjacent to the plate-like contacts LIx and insufficient activation of the impurities in the channel layers CNx. Consequently, the threshold voltage of the selection gate line is assumed to shift.

[0126] The local inventor has further investigated and found that the degree of heat dissipation of the laser light changes depending on the thickness of the insulating layers of the plate-like contacts LIx.

[0127] In the semiconductor storage device 1 of the embodiment, the plate-like contacts LI have protruding sections that penetrate the main source line DSLb and extend upwards, and the protruding sections are covered with the stop layer DSLa, which is arranged between the main source line DSLb and the auxiliary source line ASL and contains a semiconductor as its main component.

[0128] In this way, by retaining the stop layer DSLa, which covers the upper end sections of the plate-like contacts LI, it is possible to prevent the insulating layers 54 of the plate-like contacts LI from becoming thinner when the storage layers ME and the like are removed from the upper end sections of the columns PL. Since the insulating layers 54 maintain a sufficient thickness, the heat from the laser light being dissipated from the conductive layers 24 of the plate-like contacts LI can be prevented. Accordingly, it is possible to sufficiently crystallize the channel layers CN and to sufficiently activate the impurities in the channel layers CN by irradiation with the laser light, and it is possible to suppress the fluctuation of the threshold voltage of the selection gate STD formed in the columns PL.

[0129] In the semiconductor storage device 1 of the embodiment, the plate-like contacts LI comprise the insulating layers 54 arranged on the top and side walls of the plate-like contacts LI and the conductive layers 24 serving as core materials, which have a higher thermal conductivity than the insulating layers 54. As described above, it is possible to suppress the transfer of heat by the laser light to the conductive layers 24 and its dissipation, since the conductive layers 24, with their relatively large volume, are insulated by the insulating layers 54 of sufficient thickness.

[0130] In the semiconductor storage device 1 of the embodiment, the semiconductor layer covering the upper end sections of the plate-like contacts LI comprises, in addition to the auxiliary source line ASL, the stop layer DSLa and is thicker than the auxiliary source line ASL, which is a semiconductor layer covering the upper end sections of the columns PL and does not include the stop layer DSLa. This makes it possible to sufficiently activate the impurities in the channel layers CN by irradiation with the laser light and to suppress the fluctuation of the threshold voltage of the selection gates STD formed in the columns PL.

[0131] In the method for manufacturing the semiconductor storage device 1 of the embodiment, before impurities are implanted into the channel layers CN of the columns PL, a part of the stop layer DSLa is removed to expose one end region of each of the columns PL, while a section covering one end region of each of the plate-like contacts LI is left, whereby the channel layers CN can be sufficiently crystallized by irradiation with the laser light and the fluctuation of the threshold voltage of the selection gates STD formed in the columns PL can be suppressed.

[0132] In the method for manufacturing the semiconductor storage device 1 of the embodiment, the main source line DSLb and the auxiliary source line ASL are stacked over the intermediate insulation layer OSL. This allows the intermediate insulation layer OSL to be used as a stop layer when the stop layer DSLa is removed to expose the upper end regions of the columns PL.

[0133] In the method for manufacturing the semiconductor storage device 1 of the embodiment, after the implantation of impurities into the channel layers CN of the columns PL, the intermediate insulating layer OSL is removed together with the storage layers ME. Since at this point the upper end sections of the plate-like contacts LI are protected by the stop layer DSLa as described above, thinning of the insulating layers 54 of the plate-like contacts LI is suppressed.

[0134] In the method for manufacturing the semiconductor storage device 1 of the embodiment, the laser irradiation involves irradiating one end section of each of the plate-like contacts LI covered with the stop layer DSLa, together with the channel layers CN of the columns PL, with the laser light. As described above, the configuration described above suppresses the transfer of heat by the laser light to the conductive layers 24 and its dissipation, even in a case where the entire surface is irradiated with the laser light.

[0135] In the method for manufacturing the semiconductor storage device 1 of the embodiment, irradiation with laser light comprises the crystallization of the channel layers CN of the columns PL, which have become amorphous due to doping with impurities. As described above, the channel layers CN can be sufficiently crystallized and the impurities activated because the heat from the laser light is prevented from being dissipated by transfer to the conductive layers 24 of the plate-shaped contacts LI.

[0136] It should be noted that in the embodiment described above, the semiconductor storage device 1 comprises the stacked body LM with a two-stage structure in which two stacked bodies LMa and LMb are stacked on top and bottom. However, the configuration of the stacked body is not limited to two stages, but can include one stage, three stages, or more.

[0137] Furthermore, in the embodiment described above, the stair regions SR are arranged at both end sections in the X-direction of the stacked body LM. However, the stair region can also be arranged in the middle section in the X-direction of the stacked body, and the storage regions MR can be arranged at both end sections in the X-direction.

[0138] Furthermore, in the embodiment described above, the conductive layers 24 of the plate-like contacts LI comprise a metal such as tungsten, but a semiconductor containing Si or Ge can also be used instead. The semiconductor containing Si or Ge has a higher thermal conductivity than the insulating layers 54. As described above, the effect of the present embodiment can be achieved if a core material with a higher thermal conductivity than the insulating layers 54 is used for the plate-like contacts LI.

[0139] While certain embodiments have been described, these embodiments are given only as examples and are not intended to limit the scope of the inventions. In fact, the novel embodiments described herein can be embodied in a multitude of other forms; moreover, various omissions, substitutions, and modifications in the form of the embodiments described herein can be made without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or modifications that would fall within the scope and spirit of the inventions.

Claims

[1] Semiconductor storage device (1), comprising: a stacked body (LM) in which several conductive layers (WL, SGD, SGS) and several first insulating layers (OL) are stacked alternately one after the other; a plate-like area (LI) extending in the stacked body (LM) in a first direction that intersects a stacking direction of the stacked body (LM) and the stacking direction, and dividing the stacked body (LM) in a second direction that intersects the first direction and the stacking direction; a column (PL) that is adjacent to the plate-like section (LI) in the second direction and comprises a semiconductor layer (CN) that extends in the stacked body (LM) in the stacking direction; a first layer (DSLb) arranged above the stacked body (LM) and comprising a semiconductor as its main component; and a second layer (ASL) arranged above the first layer (DSLb) and containing a semiconductor as its main component, wherein the plate-like region (LI) contains a protrusion section that penetrates the first layer (DSLb) and extends upwards, and the protrusion section is covered with a third layer (DSLa) that is positioned between the first and second layers (DSLb, ASL) and contains a semiconductor as its main component. [2] Semiconductor storage device (1) according to claim 1, wherein the third layer (DSLa) is selectively arranged at a position that overlaps the plate-like area (LI) in the stacking direction from the plate-like area (LI) and the column (PL). [3] Semiconductor storage device (1) according to claim 2, further comprising: a second insulating layer (OSL) that is positioned between the first layer (DSLb) and the third layer (DSLa). [4] Semiconductor storage device (1) according to claim 1, wherein the plate-like area (LI) includes a third insulating layer (54) arranged on a top and a side wall of the plate-like area (LI), and a core material (24) with a higher thermal conductivity than the third insulating layer (54). [5] Semiconductor storage device (1) according to claim 1, wherein The first to third layers (DSLb, ASL, DSLa) contain at least one polysilicon layer or one amorphous silicon layer, and at least the third layer (DSLa) beneath the first to third layers (DSLb, ASL, DSLa) contains impurities of a first conductivity type. [6] Method for manufacturing a semiconductor storage device (1), comprising: Forming a stacked body (LM) in which several conductive layers (WL, SGD, SGS) and several first insulating layers (OL) are alternately stacked on a first layer (DSLb) containing a semiconductor as the main component, a disk-like region (LI) penetrating the stacked body (LM) and the first layer (DSLb) and extending in a first direction intersecting a stacking direction of the stacked body (LM), and subdividing the stacked body (LM) in a second direction intersecting the first direction and the stacking direction, and a column (PL) arranged adjacent to the disk-like region (LI) in the second direction, penetrating the stacked body (LM) and the first layer (DSLb) and including a semiconductor layer (CN) covered with a storage layer (ME); and Implanting impurities of a first conductivity type into the semiconductor layer (CN) projecting from the first layer (DSLb) and covered with the storage layer (ME), removing the storage layer (ME) at a section projecting from the first layer (DSLb), covering the semiconductor layer (CN) projecting from the first layer (DSLb) with a second layer (ASL) containing a semiconductor as its main component, and irradiating the semiconductor layer (CN) in the second layer (ASL) with laser light; wherein the formation of the plate-like area (LI) and the column (PL) involves Causing the plate-like region (LI) and the column (PL) to penetrate the stacked body (LM) and the first layer (DSLb) to reach a third layer (DSLa) containing a semiconductor as its main component, and before implanting the impurities into the semiconductor layer (CN) Removing part of the third layer (DSLa) to expose an end section of the pillar (PL), while leaving part of the third layer (DSLa) covering an end section of the plate-like area (LI). [7] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the first layer (DSLb) and the second layer (ASL) are stacked with a second insulating layer (OSL) inserted in between and The second insulating layer (OSL) is removed along with the storage layer (ME) after the impurities have been implanted into the semiconductor layer (CN). [8] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the second layer (ASL) is formed over the first layer (DSLb), which comprises the semiconductor layer (CN) and the plate-like area (LI) covered with the third layer (DSLa). [9] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the formation of the plate-like area (LI) involves the formation of a third insulating layer (54) covering one end section and one side wall of the plate-like area (LI), and the formation of a core material (24) with a higher thermal conductivity than the third insulating layer (54). [10] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the irradiation with laser light includes Irradiation of one end section of the plate-like area (LI), which is covered with the third layer (DSLa), with the laser light together with the semiconductor layer (CN). [11] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the stacked body (LM) is formed with the column (PL) above the first layer (DSLb) which is formed on a first substrate (SS), and before removing the third layer (DSLa) a second substrate (SB) is prepared on which a peripheral circuit (CBA) is formed that contributes to the electrical operation of the column (PL), and The first substrate (SS) and the second substrate (SB) are bonded, and the first substrate (SS) is removed. [12] Method for manufacturing a semiconductor storage device (1) according to claim 6, wherein the irradiation with laser light includes Crystallization of the semiconductor layer (CN), which becomes amorphous through doping with the impurities.

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