DISPLAY DEVICE

Abstract

The display device comprises a power line and a driver transistor, several light-emitting elements, each comprising a first electrode and a second electrode, a first planarization layer partially surrounding the side faces of the several light-emitting elements, a first connecting electrode arranged on the first planarization layer and configured to connect the first electrode and the driver transistor, a second connecting electrode arranged on the first planarization layer, a passivation layer arranged on the first connecting electrode and the second connecting electrode, and a second planarization layer arranged on the passivation layer and configured to partially surround the side faces of the several light-emitting elements, the passivation layer being one end of the first connecting electrode arranged as follows:that it surrounds and exposes part of a side surface of one of the light-emitting elements, with the second planarization layer covering the end of the first connecting electrode.

Description

[0001] This application claims priority over Korean patent application No. 10-2024-0188392, which was filed on December 17, 2024. BACKGROUND area

[0002] The disclosure relates to a display device and, in particular, to a display device that can minimize or reduce a short-circuit defect between connecting electrodes. Description of the related technique

[0003] Display devices used for computer monitors, televisions, mobile phones, and the like already include organic light-emitting displays (OLEDs), which are designed to emit light independently, and liquid crystal displays (LCDs), which require a separate light source.

[0004] The application range of display devices is expanding from computer monitors and televisions to personal mobile devices, and research is being conducted on display devices with large display areas and reduced volume and weight.

[0005] Furthermore, a display device incorporating a light-emitting diode (LED) has recently attracted attention as a next-generation display device. Because the LED is made of an inorganic material rather than an organic one, it is more reliable and has a longer lifespan than a liquid crystal display or an organic light-emitting display. In addition, the LED can be switched on and off quickly, has excellent luminous efficacy, high impact resistance, and great stability, and displays images with high brightness. SUMMARY

[0006] One task is to provide a display device that minimizes or reduces separation of a reflective electrode caused by moisture ingress.

[0007] Another task is to provide a display device that reduces crystallization of a reflecting electrode.

[0008] A further task is to provide a display device in which a first connecting electrode and a first electrode of a light-emitting element can be self-aligning.

[0009] A further task is to provide a display device in which a third connecting electrode and a second electrode of a light-emitting element can be self-aligning.

[0010] A further task is to provide a display device that minimizes or reduces a short-circuit fault between connecting electrodes.

[0011] An additional task is to provide a display device that reduces line resistance.

[0012] Another additional task is to provide a display device that can detect whether a light-emitting element is defective, regardless of whether a drive transistor is defective.

[0013] Another additional task is to provide a display device that improves an electrical connection by minimizing or reducing a connection error caused by a residual film during a process.

[0014] The problem is solved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0015] A display device of an embodiment of the disclosure comprises: a substrate on which several subpixels are defined; a current conductor and a driver transistor arranged on the substrate; a first reflective electrode and a second reflective electrode arranged on the current conductor and the driver transistor and spaced apart from each other, the first reflective electrode being connected to the driver transistor and the second reflective electrode being connected to the current conductor; a connecting layer arranged on the first reflective electrode and the second reflective electrode; several light-emitting elements, each arranged in the several subpixels on the connecting layer and comprising a first electrode and a second electrode;a first planarization layer arranged on the interconnect layer and designed to partially surround the side faces of the multiple light-emitting elements; a first interconnect electrode arranged on the first planarization layer and designed to connect the first electrode and the drive transistor; a second interconnect electrode arranged on the first planarization layer, spaced apart from the first interconnect electrode and connected to the second reflecting electrode; a passivation layer arranged on the first interconnect electrode and the second interconnect electrode; a second planarization layer arranged on the passivation layer and designed to partially surround the side faces of the multiple light-emitting elements;and a third connecting electrode arranged on the second planarization layer and designed to connect the second electrode and the current conductor, wherein the passivation layer exposes an end of the first connecting electrode which is arranged to surround part of a side surface of a light-emitting element comprising several light-emitting elements, and wherein the second planarization layer covers the end of the first connecting electrode.

[0016] A display device according to a further embodiment of the disclosure comprises: a substrate on which several pixels are defined, each pixel comprising several subpixels; a power line and a driver transistor arranged on the substrate; a first reflective electrode and a second reflective electrode arranged on the power line and the driver transistor and spaced apart from each other, the first reflective electrode being connected to the driver transistor and the second reflective electrode being connected to the power line; a connecting layer arranged on the first reflective electrode and the second reflective electrode; several light-emitting elements, each arranged in the several subpixels on the connecting layer and comprising a first electrode and a second electrode;a first planarization layer arranged on the interconnect layer and designed to partially surround the side faces of the multiple light-emitting elements; a first interconnect electrode arranged on the first planarization layer and designed to connect the first electrode and the driver transistor; a second interconnect electrode arranged on the first planarization layer, spaced apart from the first interconnect electrode and connected to the second reflecting electrode; a passivation layer arranged on the first interconnect electrode and the second interconnect electrode; a second planarization layer arranged on the passivation layer and having a height that decreases towards the multiple light-emitting elements;and a third connecting electrode, which is arranged on the second planar layer and is designed to connect the second electrode and the current conductor. Therefore, it is possible to minimize or reduce a short-circuit fault between the connecting electrodes.

[0017] In one or more embodiments, the second planarization layer can be arranged such that it covers the end of the first connecting electrode and an end of the passivation layer corresponding to the end of the first connecting electrode.

[0018] In one or more embodiments, an inclination direction of the end of the first connecting electrode and the end of the passivation layer, which are arranged on the side surface of the light-emitting element, can be identical to an inclination direction of the second planarization layer, which covers the end of the first connecting electrode and the end of the passivation layer.

[0019] In one or more embodiments, the second planarization layer can have a V-shape in an area that contacts the light-emitting element.

[0020] In one or more embodiments, the height of a section of the second planarization layer that overlaps the end of the first connecting electrode can be less than the height of a section of the second planarization layer that does not overlap the end of the first connecting electrode.

[0021] In one or more embodiments, the passivation layer may have a first section that exposes the first planarization layer.

[0022] In one or more embodiments, the second planarization layer may have a second section that overlaps the first section.

[0023] In one or more embodiments, the width of the first section can be greater than the width of the second section.

[0024] In one or more embodiments, the second planarization layer can be arranged in the first section and cover another end of the first connecting electrode and one end of the second connecting electrode.

[0025] In one or more embodiments, the third connecting electrode can be arranged in the first section and the second section and provided in such a way that it is in contact with the first planarization layer.

[0026] In one or more embodiments, the connecting layer can have a first contact hole that exposes the second reflective electrode.

[0027] In one or more embodiments, the first planarization layer can have a second contact hole that overlaps the first contact hole and exposes the second reflective electrode.

[0028] In one or more embodiments, the second connecting electrode can be arranged in the first contact hole and the second contact hole and contact the second reflective electrode.

[0029] In one or more embodiments, the passivation layer may have a third contact hole that overlaps the first contact hole and the second contact hole, exposing the second connecting electrode.

[0030] In one or more embodiments, the second planarization layer may have a fourth contact hole that overlaps the first contact hole, the second contact hole and the third contact hole, exposing the second connecting electrode.

[0031] In one or more embodiments, the third connecting electrode can be arranged in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole and contact the second connecting electrode.

[0032] In one or more embodiments, the width of the third contact hole can be larger than the width of the fourth contact hole.

[0033] In one or more embodiments, the second planarization layer can be arranged in the third contact hole and cover one end of the passivation layer.

[0034] In one or more embodiments, the connecting layer can have a first contact hole that exposes the second reflective electrode.

[0035] In one or more embodiments, the first planarization layer can have a second contact hole that overlaps the first contact hole and exposes the second reflective electrode.

[0036] In one or more embodiments, the second connecting electrode can be arranged in the first contact hole and the second contact hole and contact the second reflective electrode.

[0037] In one or more embodiments, the passivation layer may have a fifth contact hole that exposes the second connecting electrode without overlapping the first and second contact holes.

[0038] In one or more embodiments, the second planarization layer can have a sixth contact hole that overlaps the fifth contact hole.

[0039] In one or more embodiments, the third connecting electrode can be arranged in the fifth contact hole and the sixth contact hole and contact the second connecting electrode.

[0040] In one or more embodiments, the width of the fifth contact hole can be greater than the width of the sixth contact hole.

[0041] In one or more embodiments, the second planarization layer can be arranged in the fifth contact hole and cover one end of the passivation layer.

[0042] In one or more embodiments, the display device may further comprise a conductive pattern arranged on the second planarization layer.

[0043] In one or more embodiments, the passivation layer may have a seventh contact hole that exposes the first connecting electrode.

[0044] In one or more embodiments, the second planarization layer may have an eighth contact hole that overlaps the seventh contact hole.

[0045] In one or more embodiments, the conductive pattern can be connected to the first connecting electrode via the seventh contact hole and the eighth contact hole.

[0046] In one or more embodiments, the width of the seventh contact hole can be greater than the width of the eighth contact hole.

[0047] In one or more embodiments, the second planarization layer can be arranged in the seventh contact hole and cover one end of the passivation layer.

[0048] In one or more embodiments, the height of the first planarization layer can be less than the height of the first electrode.

[0049] In one or more embodiments, the height of the second planarization layer can be less than the height of the second electrode.

[0050] In one or more embodiments, the side surfaces of the multiple light-emitting elements can be any one or both of the two side surfaces of the multiple light-emitting elements.

[0051] In one or more embodiments, the passivation layer can surround the multiple light-emitting elements and expose part of the first connecting electrode.

[0052] In one or more embodiments, the height of a lowermost end of an upper surface of the second planarization layer can be higher than the height of a topmost end of an upper surface of the exposed part of the first connecting electrode.

[0053] In one or more embodiments, the passivation layer may have a section that exposes the first planarization layer.

[0054] In one or more embodiments, the second planarization layer may have a section that overlaps the section of the passivation layer and may have a smaller width than the section of the passivation layer.

[0055] In one or more embodiments, the second planarization layer can be arranged in the opening section of the passivation layer and separate the first connecting electrode and the second connecting electrode.

[0056] In one or more embodiments, the multiple pixels can each comprise a first area in which the third connecting electrode and the current conductor can be electrically connected, and a second area adjacent to the first area.

[0057] In one or more embodiments, the third connecting electrode in the first area can be connected to the current conductor via the second reflective electrode and the second connecting electrode.

[0058] In one or more embodiments, the third connecting electrode in the second region can be connected to the current conductor via the second connecting electrode extending from the first region.

[0059] In one or more embodiments, the connecting layer can have a contact hole located in the first area, exposing the second reflective electrode.

[0060] In one or more embodiments, the first planarization layer may have a contact hole located in the first region that overlaps the contact hole of the bonding layer.

[0061] In one or more embodiments, the second connecting electrode can be connected to the second reflective electrode via the contact hole of the first planarization layer and the contact hole of the connecting layer.

[0062] In one or more embodiments, the passivation layer may have a contact hole located in the first region, overlapping the contact hole of the first planarization layer and the contact hole of the connection layer, and exposing the second connection electrode.

[0063] In one or more embodiments, the second planarization layer may have a contact hole located in the first region, overlapping the contact hole of the first planarization layer, the contact hole of the interconnection layer and the contact hole of the passivation layer, and exposing the second interconnection electrode.

[0064] In one or more embodiments, the third connecting electrode can be connected to the second connecting electrode via the contact hole of the second planarization layer, the contact hole of the passivation layer, the contact hole of the first planarization layer and the contact hole of the connecting layer.

[0065] In one or more embodiments, the passivation layer may further include a contact hole located in the second region, exposing the second connecting electrode extending from the first region.

[0066] In one or more embodiments, the second planarization layer may further include a contact hole located in the second region, exposing the second connecting electrode extending from the first region.

[0067] In one or more embodiments, the third connecting electrode can be connected to the second connecting electrode via the contact hole of the passivation layer located in the second area and the contact hole of the second planarization layer.

[0068] In one or more embodiments, the display device may further comprise an illumination test area arranged in each of the multiple pixels and an illumination test pattern arranged on the second planarization layer in the illumination test area.

[0069] In one or more embodiments, the passivation layer may have a contact hole located in the illumination test area, exposing the first connecting electrode.

[0070] In one or more embodiments, the second planarization layer may have a contact hole that overlaps the contact hole of the passivation layer and exposes the first connecting electrode.

[0071] In one or more embodiments, the illumination test pattern can be connected to the first connecting electrode via the contact hole of the second planarization layer and the contact hole of the passivation layer.

[0072] The passivation layer and the first connecting electrode may also have heights that decrease in the direction of the multiple light-emitting elements.

[0073] The side surfaces of the multiple light-emitting elements can be one or both of the two side surfaces of the multiple light-emitting elements.

[0074] Further details regarding the embodiments are contained in the detailed description and the drawings.

[0075] In one embodiment of the disclosure, the passivation layer is arranged on the connecting electrode connected to the reflecting electrode, thereby minimizing or reducing the penetration of moisture into the reflecting electrode.

[0076] In one embodiment of the disclosure, it is possible to minimize or reduce the separation of the reflecting electrode caused by the ingress of moisture.

[0077] In one embodiment of the disclosure, the display device can be operated with low power consumption with regard to reducing production energy by minimizing or reducing a potential defect caused by corrosion of the line and improving the service life of the display device.

[0078] In one embodiment of the disclosure, during the process of ashing the first planarization layer and the second planarization layer, the first connecting electrode and the third connecting electrode are connected to the light-emitting elements by self-alignment without a separate alignment process, so that a transfer margin for the light-emitting elements can be ensured.

[0079] In one embodiment of the disclosure, the passivation layer is arranged on the first connecting electrode to enable separation of the first connecting electrode and the third connecting electrode, thereby suppressing a short-circuit fault between the first connecting electrode and the third connecting electrode.

[0080] In one embodiment of the disclosure, the second planarization layer flows anew onto the section in which the first connecting electrode is exposed through the passivation layer, so that the first connecting electrode and the third connecting electrode are separated, which can suppress a short-circuit fault in which the first connecting electrode and the third connecting electrode are connected.

[0081] In one embodiment of the disclosure, the illumination test signal is applied to the light-emitting element without passing through the control transistor, whereby it is possible to detect whether the light-emitting element is defective, regardless of whether the control transistor is defective.

[0082] The effects according to the revelation are not limited to the content exemplified above, and various additional effects are included in the present revelation.

[0083] Additional features and aspects of the disclosure are set forth in the following description and are partly evident from the description or can be learned through the practical implementation of the inventive concepts provided herein. Other features and aspects of the inventive concepts can be realized and achieved through the structure that is particularly emphasized in or can be derived from the written description, the claims, and the accompanying drawings.

[0084] It is understood that both the preceding general description and the following detailed description of the revelation are exemplary and are intended to further explain the claimed revelations. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] The attached drawings, which are included for a better understanding of the revelation and are incorporated into this application as a part thereof, illustrate various aspects of the revelation and, together with the description, serve to explain various principles of the present revelation; they show: Fig. 1 a schematic configuration view of a display device according to an embodiment of the disclosure; Fig. 2 an enlarged top view of a pixel of the display device according to an embodiment of the disclosure; Fig. 3 a sectional view along line III-III' in Fig. 2; and Fig. 4A to 4H Process diagrams of a method for manufacturing the display device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0086] The advantages and features of the disclosure and a method for achieving these advantages and features will become apparent with reference to the embodiments described in detail below, together with the accompanying drawings. However, the disclosure is not limited to the embodiments disclosed herein, but can be implemented in various other forms. The embodiments described below serve only as examples to enable those skilled in the art to fully understand the disclosure and its scope.

[0087] The shapes, sizes, ratios, angles, numbers, and the like shown in the accompanying drawings to describe embodiments of the disclosure are merely examples, and the present disclosure is not limited to them. The same reference numerals generally denote the same elements throughout the description. Furthermore, a detailed explanation of known related technologies may be omitted from the following description of the disclosure in order to avoid unnecessarily obscuring the subject matter of the disclosure. The terms used herein, such as "comprise," "include," and "consist of," are generally intended to permit the addition of further components, unless the terms are used with a limiting term such as "only." All references in the singular form may also include the plural form and vice versa, unless expressly stated otherwise.

[0088] Components should be interpreted as having a normal error range, even if this is not explicitly stated.

[0089] When the positional relationship between two parts is described using terms such as "on", "above", "below" and "next to", one or more parts can be positioned between the two parts unless the terms are used with a limiting term such as "immediately" or "directly".

[0090] When an element or layer is described as being placed “on” another element or layer, that other layer or element can be placed directly on top of the other element or in between.

[0091] Although the terms "first," "second," and the like can be used to describe different components, these components are not limited to these terms. These terms are merely used to distinguish one component from the others. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure, and vice versa.

[0092] The same reference symbols generally denote identical elements throughout the entire description.

[0093] The size and thickness of each component shown in the drawing are shown for the convenience of description and the disclosure is not limited to the size and thickness of the component shown.

[0094] The features of different embodiments of the disclosure can be partially or completely adhered to or combined with one another and can be interlocked and operated in technically different ways, and the embodiments can be carried out independently of one another or in conjunction with one another.

[0095] In the following, a display device of embodiments of the disclosure is described in detail with reference to the accompanying drawings.

[0096] Fig. Figure 1 is a schematic configuration view of a display device according to an embodiment of the disclosure. For the sake of simplicity, the description shows Fig. 1 only one display panel PN, one gate driver GD, one data driver DD and one time controller TC among different components of a display device 100.

[0097] With reference to Fig. 1 The display device 100 includes the display panel PN, which includes several subpixels SP, the gate driver GD, which is designed to supply various types of signals to the display panel PN, and the timing controller TC, which is designed to control the data driver DD, the gate driver GD and the data driver DD.

[0098] The gate driver GD delivers multiple sample signals to multiple sample lines SL in response to multiple gate control signals supplied by the timing controller TC. Fig. Figure 1 shows that the single gate driver GD is positioned so that it is spaced away from one side of the display panel PN. However, the number and arrangement of the gate drivers GD are not limited to this.

[0099] The data driver DD converts image data input from the timing controller TC into a data voltage using a reference gamma voltage in response to several data control signals supplied by the timing controller TC. The data driver DD can supply the converted data voltage to multiple data lines DL.

[0100] The timing controller (TC) aligns externally inputted image data and delivers the image data to the data driver (DD). The timing controller (TC) can generate gate control signals and data control signals using externally input synchronization signals, i.e., point clock signals, data release signals, and horizontal / vertical synchronization signals. Furthermore, the timing controller (TC) can control the gate driver (GD) and the data driver (DD) by delivering the generated gate control signals and data control signals to the gate driver (GD) and the data driver (DD), respectively.

[0101] The display panel PN is designed to show images to a user and comprises several subpixels SP. Several scanning lines SL and several data lines DL intersect in the display panel PN, and each of the several subpixels SP is connected to both the scanning line SL and the data line DL. Furthermore, although not shown in the drawings, each of the several subpixels SP can also be connected to a high-potential power line, a low-potential power line, a reference line, and so on.

[0102] The display panel PN can have a display area AA and a non-display area NA, which is designed to at least partially or completely surround the display area AA.

[0103] The display area AA is a region of the display device 100 in which images are displayed. The display area AA can comprise multiple subpixels SP, which together form multiple pixels PX, and a circuit designed to operate the multiple subpixels SP. The multiple subpixels SP are minimal units that constitute the display area AA. The n subpixels SP can form one pixel PX. Each of the multiple subpixels SP can contain a light-emitting element, a thin-film transistor for operating the light-emitting element, and the like. The multiple light-emitting elements can be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting element can be a light-emitting diode (LED) or a micro-light-emitting diode (micro-LED).

[0104] In the display area AA, several signal lines are arranged for transmitting various types of signals to the multiple subpixels SP. For example, the multiple signal lines can include the multiple data lines DL for supplying data voltages to the multiple subpixels SP and the multiple sample lines SL for supplying gate voltages to the multiple subpixels SP. The multiple sample lines SL can extend in one direction within the display area AA and be connected to the multiple subpixels SP. The multiple data lines DL can extend in a direction other than the one in the display area AA and be connected to the multiple subpixels SP. Additionally, a low-potential power line, a high-potential power line, and the like can also be arranged in the display area AA. However, the disclosure is not limited to these.

[0105] The non-display area NA can be defined as an area where no image is displayed, i.e., an area extending from the display area AA. The non-display area NA can include interconnects and contact electrodes for transmitting signals to the subpixels SP in the display area AA. Alternatively, the non-display area NA can include driver ICs such as gate driver ICs and data driver ICs. The non-display area NA can be located on a rear surface of the display panel PN, i.e., a surface where the subpixel SP is not present. Alternatively, the non-display area NA can be omitted. However, the disclosure is not limited to the configuration shown in the drawings.

[0106] Meanwhile, the drivers, such as the gate driver GD, the data driver DD, and the timing controller TC, can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in a non-display area NA using a gate-in-panel (GIP) method or between the multiple subpixels SP in a display area AA using a gate-in-active area (GIA) method. Similarly, the data driver DD and the timing controller TC can be formed on separate flexible films and printed circuit boards, and electrically connected to the display panel PN by connecting the flexible film and the circuit board to a contact electrode formed in the non-display area NA of the display panel PN.If the gate driver GD is mounted using the GIP method and the data driver DD and the timing controller TC send signals to the display panel PN via the contact electrode in the non-display area NA, ensuring a portion of the non-display area NA for arranging the gate driver GD and the contact electrode may require increasing the size of the enclosure.

[0107] Alternatively, in a case where the gate driver GD is mounted in the display area AA using the GIA method, and a side conductor is formed to connect a signal line on a front surface of the display board PN to the contact electrode on the rear surface of the display board PN, the non-display area NA on the front surface of the display board PN can be minimized or reduced. That is, if the gate driver GD, the data driver DD, and the timing controller TC are connected to the display board PN using the method described above, a zero border can be achieved, where the border is essentially non-existent.

[0108] Fig. Figure 2 is an enlarged top view of the pixel of the display device according to one embodiment of the disclosure. Fig. 3 is a sectional view along line III-III' in Fig. 2. Fig. Figure 2 shows only a first reflective electrode RE1, a second reflective electrode RE1, a first connecting electrode CE1, a second connecting electrode CE2 and a light-emitting element LED among the components of the display device 100. Fig. Figure 3 is a cross-sectional view showing a first subpixel with a first light-emitting element 120. The cross-section of the first subpixel containing the first light-emitting element 120 is identical to a cross-section of a second subpixel containing a second light-emitting element 130, and a cross-section of a third subpixel containing a third light-emitting element 140.

[0109] Initially, the display board includes PN with reference to Fig. 1 and Fig. Three multiple pixels PX, each comprising multiple subpixels SP. Each subpixel SP can include the light-emitting element LED and a pixel circuit and emit light independently. A pixel PX can comprise a first subpixel, a second subpixel, and a third subpixel. For example, a pixel PX can comprise a first subpixel, a second subpixel, and a third subpixel. In this case, the first subpixel can be a red subpixel, the second subpixel a green subpixel, and the third subpixel a blue subpixel. However, the present disclosure is not limited to this.

[0110] The multiple light-emitting elements LED can each be arranged in the multiple subpixels SP. Specifically, the multiple light-emitting elements LED comprise the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140. The first light-emitting element 120 can be located in the first subpixel, the second light-emitting element 130 in the second subpixel, and the third light-emitting element 140 in the third subpixel. For example, the first light-emitting element 120 can be a red light-emitting element, the second light-emitting element 130 can be a green light-emitting element, and the third light-emitting element 140 can be a blue light-emitting element.

[0111] However, with reference to Fig. 2. The first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 may have different shapes. For example, the planar shape of the first light-emitting element 120 may be circular, and the planar shapes of the second light-emitting element 130 and the third light-emitting element 140 may each be elliptical. In this case, the second light-emitting element 130 and the third light-emitting element 140 may have different sizes and thus different elliptical shapes. However, the second light-emitting element 130 and the third light-emitting element 140 may be identical in their principal axis directions. The disclosure is not limited to this, however.

[0112] With reference to Fig. 3. The first light-emitting element 120 can comprise a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126. Although not shown in the drawings, the planar shape of the first semiconductor layer 121 of the first light-emitting element 120 can be circular, and the planar shape of the second semiconductor layer 123 can be semicircular. The planar shape of the first electrode 124 can be elliptical. The second electrode 125 can be semicircular, similar to the upper surface of the second semiconductor layer 123.

[0113] The second light-emitting element 130 can comprise a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the drawings, the planar shapes of the first semiconductor layer and the first electrode of the second light-emitting element 130 can be elliptical. In this case, the principal axis direction of the first semiconductor layer can be oriented differently from the principal axis direction of the first electrode. For example, if the first semiconductor layer has an elliptical shape with a principal axis in the horizontal direction, the first electrode can have an elliptical shape with a principal axis in the vertical direction.For example, the first electrode can be located on the upper surface of the first semiconductor layer and, based on the principal axis direction, at one end of the first semiconductor layer. The second semiconductor layer and the second electrode can have a planar shape and be a cut-out elliptical shape.

[0114] The third light-emitting element 140 can comprise a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the drawings, the planar shapes of the first semiconductor layer and the first electrode of the third light-emitting element 140 can be elliptical. Unlike the second light-emitting element, the principal axis direction of the first semiconductor layer can be identical to the principal axis direction of the first electrode in the third light-emitting element 140. For example, the first electrode can be located on a top surface of the first semiconductor layer and, based on the principal axis direction, at one end of the first semiconductor layer. The planar shape of the second semiconductor layer and the second electrode can be a cut-out elliptical shape.

[0115] That is, in the display device 100 according to the embodiment of the disclosure, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 can have different shapes, so that the multiple light-emitting LED elements can be distinguished. For example, during a self-assembly process of the light-emitting LED elements, the multiple light-emitting LED elements can be formed in different shapes, so that the multiple light-emitting LED elements can be self-assembled at positions that each correspond to the multiple subpixels SP. However, the shapes of the multiple light-emitting LED elements are examples, and the disclosure is not limited to them.

[0116] With reference to Fig. 2. However, a first contact area CA1, a second contact area CA2 and an illumination test area APA can be defined in each of the multiple pixels PX of the display panel PN of the display device 100 according to the embodiment of the disclosure.

[0117] The first contact area CA1 and the second contact area CA2 can be areas where a current conductor VDD and a third connecting electrode CE3 are electrically connected. For example, in the first contact area CA1, the third connecting electrode CE3 can be electrically connected to the current conductor via a second reflective electrode RE2 and the second connecting electrode CE2. In the second contact area CA2, the third connecting electrode CE3, extending from the first contact area CA1, can additionally be connected to the second connecting electrode CE2, which also extends from the first contact area CA1, so that the third connecting electrode CE3 can be electrically connected to the current conductor.

[0118] The illumination test area APA can be an area that transmits an illumination test signal to detect whether the LED light-emitting element is defective. For example, in the illumination test area APA, an illumination test pattern can transmit illumination test signals to the first electrodes of the LED light-emitting element via the first junction electrode CE1 without passing through a drive transistor DT. Therefore, it is possible to detect whether the LED light-emitting element is defective, regardless of whether the drive transistor DT is defective. The details of the above configuration are described below. Fig. 3 explained.

[0119] Next, with simultaneous reference to Fig. 3 a substrate 110, a buffer layer 111, a gate insulating layer 112, a first intermediate insulating layer 113a, a second intermediate insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, a coating layer 115, a connection layer 116, a first planarization layer 117a, a second planarization layer 117b, a bank 118, a third planarization layer 119, the drive transistor DT, the light-emitting element LED, a reflective electrode RE, a light-blocking layer LS, an auxiliary electrode LE, the first connection electrode CE1, the second connection electrode CE2, the third connection electrode CE3, a capacitor Cst, an intermediate electrode TM and an illumination test pattern APP arranged in each of the several subpixels SP on the display panel PN of the display device 100 according to the embodiment of the disclosure be.

[0120] First, the substrate 110 is a component for supporting various parts contained in the display device 100 and can consist of an insulating material. For example, the substrate 110 can be made of glass, resin, or the like. Furthermore, the substrate 110 can contain plastic such as polymer and be made of a flexible material.

[0121] The light-blocking layer LS can be arranged in any of the multiple subpixels SP on the substrate 110. The light-blocking layer LS blocks light entering an active layer ACT of the driver transistor DT from a bottom surface of the substrate 110, as described below. The light-blocking layer LS can block light entering the active layer ACT of the driver transistor DT, thereby minimizing or reducing leakage current.

[0122] The buffer layer 111 can be arranged on the substrate 110 and the light-blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or contaminants through the substrate 110. For example, the buffer layer 111 can be configured as a single layer or multiple layer of silicon dioxide (SiOx) or silicon nitride (SiNx). However, the disclosure is not limited to this. The buffer layer 111 can also be omitted depending on the type of substrate 110 or the type of transistor. However, the disclosure is not limited to this.

[0123] The driver transistor DT can be located on the buffer layer 111. The driver transistor DT comprises the active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0124] The active layer ACT can be arranged on the buffer layer 111. The active layer ACT can consist of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. However, the disclosure is not limited to these materials.

[0125] The gate insulating layer 112 can be arranged on the active layer ACT. The gate insulating layer 112 is an insulating layer for isolating the active layer ACT and the gate electrode GE. The gate insulating layer 112 can be formed as a single layer or as a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, the disclosure is not limited to this.

[0126] The gate electrode GE can be arranged on the gate insulating layer 112. The gate electrode GE can be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the disclosure is not limited to these.

[0127] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be arranged on the gate electrode GE. Contact holes, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT, are formed in the gate insulating layer 112, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b can be insulating layers for protecting components arranged below the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, respectively, and each formed as a single layer or as a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, the disclosure is not limited to this.

[0128] The source electrode SE and the drain electrode DE, which are electrically connected to the active layer ACT, can be arranged on the second intermediate insulating layer 113b. The source electrode SE and the drain electrode DE can each be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the disclosure is not limited to these materials.

[0129] However, the disclosure describes a configuration in which the first intermediate insulating layer 113a and the second intermediate insulating layer 113b, i.e., the multiple insulating layers, are arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, it is also possible for only a single insulating layer to be arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE. The disclosure is not limited to this, however.

[0130] Furthermore, although not shown in the drawings, the pixel circuit may include, in addition to the drive transistor DT, a switching transistor, a sampling transistor, a light emission control transistor, and the like. However, the disclosure is not limited to this.

[0131] Meanwhile, the intermediate electrode TM can be arranged on the first intermediate insulating layer 113a. The intermediate electrode TM can be arranged such that it overlaps the gate electrode GE of the drive transistor DT, with the first intermediate insulating layer 113a positioned between them, and together with the gate electrode GE of the drive transistor DT, forms a capacitor. However, the disclosure is not limited to this.

[0132] The auxiliary electrode LE can be arranged on the gate insulating layer 112. The auxiliary electrode LE is an electrode designed to electrically connect the light-blocking layer LS, located below the buffer layer 111, to one of the source electrode SE and the drain electrode DE of the driver transistor DT on the second intermediate insulating layer 113b. For example, the light-blocking layer LS can be electrically connected via the auxiliary electrode LE to one of the source electrode SE and the drain electrode DE of the driver transistor DT to prevent it from operating as a floating gate, thereby minimizing or reducing any change in the threshold of the driver transistor DT caused by the floating light-blocking layer LS. The drawing shows the light-blocking layer LS connected to the source electrode SE of the driver transistor DT.The light-blocking layer LS can also be connected to the drain electrode DE of the driver transistor DT. However, the disclosure is not limited to this.

[0133] The capacitor Cst can be arranged on the gate insulating layer 112. The capacitor Cst can comprise a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0134] Initially, the first capacitor electrode Cst1 can be arranged on the gate insulating layer 112. The first capacitor electrode Cst1 can be arranged on the same layer and made of the same material as the gate electrode GE. However, the disclosure is not limited to this.

[0135] The second capacitor electrode Cst2 can be arranged on the first intermediate insulating layer 113a. The second capacitor electrode Cst2 can be arranged on the same layer and made of the same material as the intermediate electrode TM. However, the disclosure is not limited to this. The second capacitor electrode Cst2 can be arranged to overlap the first capacitor electrode Cst1, with the first intermediate insulating layer 113a positioned between them. The second capacitor electrode Cst2 can be connected to the source electrode SE of the drive transistor DT.

[0136] The power conductor VDD can be arranged on the second intermediate insulating layer 113b. The power conductor VDD, together with the driver transistor DT, can be electrically connected to the light-emitting element LED, enabling the LED to emit light. The power conductor VDD can be made of an electrically conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the disclosure is not limited to these materials.

[0137] The first passivation layer 114a can be arranged on the drive transistor DT and the power line VDD. The first passivation layer 114a can protect the drive transistor DT and the power line VDD from the ingress of moisture or contaminants. For example, the first passivation layer 114a can be formed as a single layer or as a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, the disclosure is not limited to this. The first passivation layer 114a can also be omitted depending on the type of substrate 110 or the type of transistor. However, the disclosure is not limited to this.

[0138] The coating layer 115 can be arranged on the first passivation layer 114a. The coating layer 115 can planarize an upper section of the substrate 110 on which the drive transistor DT is arranged. The coating layer 115 can be formed as a single layer or multiple layers and may consist, for example, of a photoresist or an acrylic-based organic material. However, the disclosure is not limited to this.

[0139] The multiple reflective electrodes RE, spaced apart from one another, can be arranged on the coating layer 115. These electrodes can serve to electrically connect the light-emitting element LED to the power line VDD and the driver transistor DT, and act as reflective plates, reflecting light emitted from the LED back to its upper section. Each electrode can be made of an electrically conductive material with excellent reflectivity, reflecting light emitted from the LED back to its upper section. Therefore, the electrodes can be composed of various conductive layers, taking into account their light reflection efficiency and resistance.For example, the reflective plate can be manufactured using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof, together with a transparent conductive layer of indium tin oxide (ITO). However, the structure and material of the reflective plate RE are not limited to this.

[0140] The multiple reflective electrodes RE can include the first reflective electrode RE1 and the second reflective electrode RE2. The first reflective electrode RE1 can electrically connect the driver transistor DT and the light-emitting element LED. The first reflective electrode RE1 can be connected to the source electrode SE or the drain electrode DE of the driver transistor DT via contact holes formed in the first passivation layer 114a and the coating layer 115. Furthermore, the first reflective electrode RE1 can be electrically connected to the first electrode 124 of the light-emitting element LED via the first connecting electrode CE1.

[0141] The second reflective electrode RE2 can electrically connect the power conductor VDD and the light-emitting element LED. The second reflective electrode RE2 can be connected to the power conductor VDD via contact holes formed in the first passivation layer 114a and the coating layer 115, and electrically connected to the second electrode 125 of the light-emitting element LED via the second connecting electrode CE2 and the third connecting electrode CE3, which are described below.

[0142] On the multiple reflective electrodes RE, the compound layer 116 can be formed on the front surface of the substrate 110 and fix the light-emitting element LED arranged on the compound layer 116. The compound layer 116 can consist of a light-curable or heat-curable compound material that can be cured by light or heat. For example, the compound layer 116 can be made of an acrylic-based material containing a photosensitive agent. However, the disclosure is not limited to this.

[0143] The multiple light-emitting elements (LEDs) can be provided at layer 116 and arranged in each of the multiple subpixels (SP). The LEDs can be elements designed to emit light using an electric current, and can include LEDs designed to emit red, green, blue, and the like. The LEDs can produce light of various colors, including white light using a combination of red, green, blue, and the like. For example, the LEDs can each be a single light-emitting diode (LED) or a micro-LED. However, the disclosure is not limited to these.

[0144] The first light-emitting element 120 can comprise the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, the second electrode 125 and the passivation layer 126.

[0145] The first semiconductor layer 121 can be arranged on the interconnect layer 116, and the second semiconductor layer 123 can be arranged on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 can each be a layer formed by doping a specific material with n-type and p-type impurities, respectively. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can each be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type and p-type impurities, respectively. Furthermore, the p-type impurity can be magnesium, zinc (Zn), beryllium (Be), or the like. The n-type impurity can be silicon (Si), germanium, tin (Sn), or the like. However, the disclosure is not limited to these.

[0146] A portion of the first semiconductor layer 121 can be arranged to project from the second semiconductor layer 123. The upper surface of the first semiconductor layer 121 can have a section that overlaps a lower surface of the second semiconductor layer 123, as well as a section that is located outside a lower surface of the second semiconductor layer 123. The light-emitting element LED can be a lateral LED. However, the first semiconductor layer 121 and the second semiconductor layer 123 can be modified differently in size and shape. The disclosure is not limited to these modifications.

[0147] For example, the first semiconductor layer 121 can protrude outwards from the second semiconductor layer 123 in one direction. The first semiconductor layer 121 can protrude outwards from the second semiconductor layer 123 at an edge of a portion of the second semiconductor layer 123. A portion of the first semiconductor layer 121 can protrude outwards from the second semiconductor layer 123 in a specific direction.

[0148] The light-emitting layer 122 can be arranged between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving positive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123.

[0149] The light-emitting layer 122 can be configured as a single layer or as a multiple quantum well (MQW) structure. For example, the light-emitting layer 122 can consist of indium gallium nitride (InGaN), gallium nitride (GaN), or the like. However, the disclosure is not limited to this.

[0150] The first electrode 124 can be located on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the drive transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 can be an n-type doped semiconductor layer, and the first electrode 124 can be a cathode. The first electrode 124 can be located on the top surface of the first semiconductor layer 121, exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 can be arranged around the top surface of the first semiconductor layer 121, and the planar shape of the first electrode 124 can be a ring shape.The first electrode 124 can consist of an electrically conductive material such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the disclosure is not limited to this.

[0151] The second electrode 125 can be located on the second semiconductor layer 123. The second electrode 125 can be located on an upper surface of the second semiconductor layer 123. Since, in this case, the second semiconductor layer 123 is located on top of the first semiconductor layer 121, the second electrode 125, located on the upper surface of the second semiconductor layer 123, can be positioned higher than the first electrode 124, which is located on the upper surface of the first semiconductor layer 121. The second electrode 125 is an electrode for electrically connecting the power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 can be a p-type doped semiconductor layer, and the second electrode 125 can be an anode.The second electrode 125 can be made of an electrically conductive material such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the disclosure is not limited to this.

[0152] Next, the passivation layer 126 can be arranged to surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation layer 126 can consist of an insulating material and protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, a contact hole can be formed in the passivation layer 126 through which the first electrode 124 and the second electrode 125 are exposed, so that the first connecting electrode CE1, the third connecting electrode CE3, the first electrode 124, and the second electrode 125, which are subsequently formed, can be electrically connected.

[0153] Although this in Fig. Although not shown in Figure 3, the second light-emitting element 130 and the third light-emitting element 140 can be arranged in essentially the same way as the first light-emitting element 120.

[0154] The first planarization layer 117a can be arranged on the connection layer 116. The first planarization layer 117a can be arranged such that it partially surrounds the side surfaces of the multiple light-emitting LED elements and fixes and protects the multiple light-emitting LED elements.

[0155] For example, the first planarization layer 117a can be arranged to surround the passivation layer 126, which is located at the bottom edge of the LED. Therefore, it is possible to suppress separation of the first junction electrode CE1 caused by tearing of the passivation layer 126. For example, during a process to separate the LED from a wafer, part of the passivation layer 126 may tear away from the bottom edge of the LED. Therefore, the passivation layer 126 may expose part of the first semiconductor layer 121 at the bottom edge of the LED. Consequently, a height difference may occur at the bottom edge of the LED due to the tearing of the passivation layer 126.In this case, the first connecting electrode CE1 can be separated by the height difference caused by the tearing off of the passivation layer 126, in a case where the first connecting electrode CE1 is arranged such that it surrounds the side surface of the passivation layer 126.

[0156] Therefore, the first planarization layer 117a is positioned to surround the lower edge of the light-emitting element LED before the first connection electrode CE1 is positioned, allowing the lower edge of the LED and the first connection electrode CE1 to be spaced apart. Even if an undercut structure forms at the lower edge of the LED due to the delamination of the passivation layer 126, the first planarization layer 117a fills the undercut structure and simultaneously contacts at least part of the side surface of the LED, thereby minimizing or reducing the separation of the first connection electrode CE1 caused by the undercut structure.

[0157] Meanwhile, the first planarization layer 117a can be arranged such that it is lower than the height of the first electrode 124, thus exposing the first electrode 124. Therefore, the first connecting electrode CE1, located on the first planarization layer 117a, can be easily connected to the first electrode 124. The details of the above configuration are described below. Fig. 4A to 4H, which are described below, are explained in detail.

[0158] Furthermore, the first planarization layer 117a can have a relatively low-height section in an area adjacent to the light-emitting element LED. For example, the relatively low section can be formed by removing part of the first planarization layer 117a in the area adjacent to the light-emitting element LED during a process to form the contact hole of the passivation layer 126 to expose the first electrode 124 and the second electrode 125. The details of the above configuration are described by reference to Fig. 4A to 4H, which are described below, are explained in detail.

[0159] The first planarization layer 117a can be formed as a single layer or multiple layers and may consist, for example, of a photoresist or an acrylic-based organic material. However, the disclosure is not limited to this.

[0160] Meanwhile, the first planarization layer 117a can be thinner than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a can be adjusted by performing an ashing process. For instance, after applying a layer of material from the first planarization layer 117a to cover the light-emitting element LED, an ashing process can be performed to reduce the overall thickness of the material layer of the first planarization layer 117a, so that the height of the first planarization layer 117a can be less than the height of the first electrode 124. Therefore, the first planarization layer 117a can expose the first electrode 124. Consequently, the first connecting electrode CE1, which is located on the first planarization layer 117a, can be easily connected to the first electrode 124 without a separate contact hole.Therefore, the first connecting electrode CE3 and the first electrode 124 can be self-aligning without having to ensure a process margin.

[0161] The first interconnect electrode CE1 can be located on the first planarization layer 117a. CE1 is an electrode positioned within each of the multiple subpixels SP and is designed to electrically connect the light-emitting element LED and the driver transistor DT. CE1 can be arranged in a shape that surrounds the LED. CE1 can be connected to the first reflective electrode RE1 via contact holes formed in the first planarization layer 117a and the interconnection layer 116. Therefore, CE1 can be electrically connected to either the source electrode SE or the drain electrode DE of the driver transistor DT via the first reflective electrode RE1.For example, the first connecting electrode CE1 can connect the first electrode 124 of the light-emitting element LED to the source electrode SE of the driver transistor DT. However, the disclosure is not limited to this. For example, the first connecting electrode CE1 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the disclosure is not limited to this.

[0162] In the first contact area CA1 and in the second contact area CA2, the second connecting electrode CE2 can be arranged on the first planarization layer 117a. The second connecting electrode CE2 is an electrode that electrically connects the light-emitting element LED and the power conductor VDD. The second connecting electrode CE2 can be connected to the second reflective electrode RE2 via contact holes formed in the first planarization layer 117a and the connecting layer 116. For example, the second connecting electrode CE2 can be electrically connected to the second reflective electrode RE2 via a first contact hole CH1 of the connecting layer 116, which is arranged in the first contact area CA1, and a second contact hole CH2 of the first planarization layer 117a, which overlaps the first contact hole CH1.Therefore, the second connecting electrode CE2 can be electrically connected to the power line VDD via the second reflective electrode RE2. For example, the second connecting electrode CE2 can connect the second electrode 125 of the light-emitting element LED and the power line VDD. However, the disclosure is not limited to this.

[0163] However, the second connecting electrode CE2 can be arranged on the same layer and made of the same material as the first connecting electrode CE1. The disclosure is not limited to this, however. For example, the second connecting electrode CE2 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The disclosure is not limited to this, however.

[0164] The second passivation layer 114b can be arranged on several first connection electrodes CE1 and several second connection electrodes CE2. The second passivation layer 114b can be arranged on several first connection electrodes CE1 and several second connection electrodes CE2 and block the ingress of moisture or impurities into the several reflective electrodes RE1 connected to the several first connection electrodes CE1 and the several second connection electrodes CE2. For example, the second passivation layer 114b can be formed as a single layer or as a multiple layer of silicon dioxide (SiOx) or silicon nitride (SiNx). However, the disclosure is not limited to this.

[0165] Furthermore, the second passivation layer 114b can be arranged to cover at least part of the first connection electrode CE1, thus allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated from each other. Therefore, the second passivation layer 114b can prevent the first connection electrode CE1 and the third connection electrode CE3 from being short-circuited.

[0166] The second passivation layer 114b can have a first section OP1 through which the first planarization layer 117a is exposed. For example, the first section OP1 can be located between the first connecting electrode CE1 and the second connecting electrode CE2.

[0167] The second planarization layer 117b can be arranged on the second passivation layer 114b. The second planarization layer 117b, together with the first planarization layer 117a, can planarize the upper section of the substrate 110 on which the light-emitting element LED is arranged. The second planarization layer 117b, together with the bonding layer 116, can fix the light-emitting element LED to the substrate 110.

[0168] Furthermore, the second planarization layer 117b can be arranged to cover the first connection electrode CE1, thus separating the first connection electrode CE1 and the third connection electrode CE3 from each other. Therefore, it is possible to prevent a short circuit between the first connection electrode CE1 and the third connection electrode CE3.

[0169] In particular, the second planarization layer 117b can be arranged to cover an end of the first connection electrode CE1 that is exposed by the second passivation layer 114b, thus allowing the first connection electrode CE1 and the third connection electrode CE3 to be separated. For example, during the process of forming the second planarization layer 117b, a curing process can cause the second planarization layer 117b to flow downwards, i.e., to flow anew onto the end of the first connection electrode CE1 that is exposed by the second passivation layer 114b. Therefore, a portion of the second planarization layer 117b that overlaps the end of the first connection electrode CE1 exposed by the second passivation layer 114b can have a relatively small height.In other words, a section of the second planarization layer 117b surrounding the end of the first connecting electrode CE1 may have an inclination.

[0170] For example, the end of the first connecting electrode CE1, which contacts the light-emitting element LED, may be exposed by the second passivation layer 114b. Therefore, the height of the second planarization layer 117b may decrease towards the light-emitting element LED. However, since the second planarization layer 117b is arranged to cover the end of the first connecting electrode CE1 that is exposed by the second passivation layer 114b, the height of the bottom end of an upper surface of the second planarization layer 117b may be greater than the height of the top end of an upper surface of the end of the first connecting electrode CE1 that is exposed by the second passivation layer 114b.

[0171] Meanwhile, the second planarization layer 117b can be arranged in the first opening section OP1 and cover the end of the first connecting electrode CE1 and the end of the second connecting electrode CE2 in such a way that the first connecting electrode CE1 and the second connecting electrode CE2 can be separated from each other. Therefore, it is possible to prevent the first connecting electrode CE1 and the second connecting electrode CE2 from being short-circuited.

[0172] In particular, a section may be formed in the second planarization layer 117b that overlaps the first section OP1 of the second passivation layer 114b, and the curing process may allow the second planarization layer 117b to flow again into the first section OP1. Therefore, the width of a second opening section OP2 formed during the reflow of the second planarization layer 117b may be smaller than the width of the first opening section OP1. The details of the above configuration are described below with reference to Fig. 4A to 4H described.

[0173] The second planarization layer 117b can be configured as a single layer or as a multiple layer. For example, the second planarization layer 117b, like the first planarization layer 117a, can consist of a photoresist or an acrylic-based organic material. However, the disclosure is not limited to this.

[0174] The third connecting electrode CE3 can be arranged on the second planarization layer 117b. The third connecting electrode CE3 is an electrode that electrically connects the light-emitting element LED and the power conductor VDD. The third connecting electrode CE3 can be connected to the second reflective electrode RE2 via contact holes formed in the second planarization layer 117b, the second passivation layer 114b, the first planarization layer 117a, and the connecting layer 116. Therefore, the third connecting electrode CE3 can be electrically connected to the power conductor VDD via the second reflective electrode RE2. For example, the third connecting electrode CE3 can connect the second electrode 125 of the light-emitting element LED and the power conductor VDD. However, the disclosure is not limited to this.For example, the third connecting electrode CE3 can consist of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the disclosure is not limited to this.

[0175] For example, the third connecting electrode CE3 can be located in the first contact hole CH1 of the connecting layer 116, which is located in the first contact area CA1; in the second contact hole CH2 of the first planarization layer 117a; in a third contact hole CH3 of the second passivation layer 114b, which overlaps the first contact hole CH1 and the second contact hole CH2; and in a fourth contact hole CH4 of the second planarization layer 117b, which overlaps the first contact hole CH1, the second contact hole CH2, and the third contact hole CH3. The third connecting electrode CE3 contacts the second connecting electrode CE2. Therefore, the third connecting electrode CE3 can be electrically connected to the second reflective electrode RE2 via the second connecting electrode CE2 and to the current conductor VDD via the second reflective electrode RE2.

[0176] In this case, the third connecting electrode CE3 can additionally be electrically connected to the second connecting electrode CE2 in the second contact area CA2. For example, the third connecting electrode CE3 can be continuously arranged in the first contact area CA1 and in the second contact area CA2 and electrically connected to the second connecting electrode CE2, which extends from the first contact area CA1, via a fifth contact hole CH5 of the second passivation layer 114b, located in the second contact area CA2, and a sixth contact hole CH6 of the second planarization layer 117b. That is, the third connecting electrode CE3 can receive a power voltage from the current conductor VDD via the second connecting electrode CE2 in the second contact area CA2 as well as in the first contact area CA1. Therefore, it is possible to reduce the resistance between the current conductor VDD and the third connecting electrode CE3.

[0177] In particular, the fifth contact hole CH5 and the sixth contact hole CH6 of the second contact area CA2, unlike the third contact hole CH3 and the fourth contact hole CH4 of the first contact area CA1, may not overlap the first contact hole CH1 of the compound layer 116 and the second contact hole CH2 of the first planarization layer 117a. Therefore, it is possible to improve the electrical connection between the third compound electrode CE3 and the second compound electrode CE2 by minimizing or reducing defects in the compound layer 116 and the first planarization layer 117a caused by a residual film.

[0178] Furthermore, although the second connecting electrode CE2 and the third connecting electrode CE3 are not electrically connected to each other in either of the first contact areas CA1 and CA2, they can be connected in the one remaining area. Therefore, it is possible to improve the electrical connection between the second connecting electrode CE2 and the third connecting electrode CE3.

[0179] Meanwhile, the third connecting electrode CE3 is arranged on the second electrode 125 and positioned so that it is in direct contact with the second electrode 125. This allows a lighting test signal to be sent directly to the second electrode 125 during a lighting test, bypassing the drive transistor DT. Therefore, it is not necessary to operate the drive transistor DT separately, so a defect in the light-emitting element LED can be detected independently of a defect in the drive transistor DT.

[0180] Furthermore, the third connecting electrode CE3 can be formed prior to the bank 118 formation process described below. Therefore, a defect in the light-emitting element LED can be detected prior to the bank 118 formation process.

[0181] However, the third connecting electrode CE3 can be arranged in the first opening section OP1 and the second opening section OP2 and positioned so that it is in contact with the second planarization layer 117b. In this case, the third connecting electrode CE3 may not be in contact with the second passivation layer 114b, since the width of the second section OP2 is smaller than the width of the first section OP1. However, the disclosure is not limited to this.

[0182] The illumination test pattern APP can be arranged on the second planarization layer 117b in the illumination test area APA. The illumination test pattern APP can contact the first junction electrode CE1 via a seventh contact hole CH7 formed in the second passivation layer 114b and an eighth contact hole CH8 formed in the second planarization layer 117b.

[0183] Therefore, the illumination test pattern APP can be electrically connected to the first electrode 124 of the light-emitting element LED via the first connection electrode CE1. Consequently, the illumination test signal can be sent directly to the first electrode 124 of the light-emitting element LED without passing through the drive transistor DT. Therefore, it is not necessary to operate the drive transistor DT separately, so that a defect in the light-emitting element LED can be detected independently of a defect in the drive transistor DT. The illumination test pattern APP can be located on the same layer and made of the same material as the third connection electrode CE3. However, the disclosure is not limited to this.Therefore, the illumination test pattern APP, like the third connecting electrode CE3, is formed prior to the bank 118 formation process described below, so that a defect in the light-emitting element LED can be detected prior to the bank 118 formation process. For example, the illumination test pattern APP may consist of a transparent conductive material or the like, such as indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, the illumination test pattern APP may be referred to as a conductive pattern. However, the disclosure is not limited to this.

[0184] A protective pattern PP can be arranged on the second planarization layer 117b. The protective pattern PP can be positioned to cover the first reflective electrode RE1, which is exposed through the contact hole of the interconnection layer 116. Therefore, the protective pattern PP can protect the first interconnection electrode RE1. For example, the protective pattern PP can act as a mask during the ashing process of the second planarization layer 117b, so that the ashing process can suppress the oxidation of the first reflective electrode RE1.

[0185] Furthermore, the protective pattern PP can be connected to the first connecting electrode RE1 and reduce the conduction resistance of the first connecting electrode RE1.

[0186] The bank 118 can be arranged on the second planarization layer 117b, the third connection electrode CE3, and the second illumination test pattern APP. Therefore, the bank 118 can be in direct contact with the second planarization layer 117b, the third connection electrode CE3, and the second illumination test pattern APP. However, the disclosure is not limited to this. The bank 118 can be arranged so that it does not overlap the light-emitting element LED, and the bank 118 can define a light-emitting area. For example, the bank 118 can define the light-emitting area by covering the edge of the third connection electrode CE3, which is connected to the light-emitting element LED. That is, the bank 118 can separate the multiple subpixels SP. The bank 118 can be made of an insulating material to insulate the second connection electrodes CE3 of the adjacent subpixels SP.Furthermore, bank 118 can contain a black component with a high optical absorption rate to suppress color mixing between neighboring subpixels SP, and bank 118 can be configured as a black bank. For example, bank 118 can be made of polyimide resin, acrylic resin, or benzocyclobutene resin (BCB resin). However, the disclosure is not limited to these.

[0187] The third planarization layer 119 can be arranged on top of the second planarization layer 117b and the substrate 118. The third planarization layer 119 can be arranged to cover an upper surface of the light-emitting element LED, thereby fixing and protecting the LED, while simultaneously planarizing the upper section of the substrate 110 on which the LED is mounted. Therefore, the third planarization layer 119 can be referred to as a protective layer or a covering layer. However, the disclosure is not limited to this. The third planarization layer 119 can be configured as a single layer or as a multiple layer and may consist, for example, of a photoresist or an acrylic-based organic material. However, the disclosure is not limited to this.

[0188] The following describes a method for manufacturing the display device according to the embodiment of the disclosure with reference to Fig. 4A to 4H described.

[0189] Fig. Figures 4A to 4H are process diagrams of the method for manufacturing the display device according to one embodiment of the disclosure.

[0190] First, with reference to Fig. 4A to 4H the light-emitting element LED can be arranged on the interconnection layer 116, and the first planarization layer 117a can be arranged on the interconnection layer 116 and surround the light-emitting element LED.

[0191] A connecting electrode material layer CE' and a second-first passivation material layer 114b' can be arranged successively on the front surface of the substrate 110 on the first planarization layer 117a and the light-emitting element LED.

[0192] The interconnect electrode material layer CE' can be arranged on the front surface of the substrate 110 and cover the light-emitting element LED and the first planarization layer 117a. Therefore, the interconnect electrode material layer CE' can also be arranged in the second contact hole CH2 formed in the first planarization layer 117a and in the first contact hole CH1 of the interconnect layer 116, which overlaps the second contact hole CH2. Additionally, the interconnect electrode material layer CE' can be arranged to cover both the side and top surfaces of the light-emitting element LED.

[0193] The second-first passivation material layer 114b' can be arranged on the front surface of the substrate 110 on the connecting electrode material layer CE'. The second-first passivation material layer 114b' can be arranged such that it is spaced apart by the connecting electrode material layer CE' from the light-emitting element LED, the first planarization layer 117a, and the connecting layer 116.

[0194] Meanwhile, the second-first passivation material layer 114b' can be formed by a deposition process. In this case, a deposition process temperature for the second-first passivation material layer 114b' can be determined taking into account the connection electrode material layer CE' located below the second-first passivation material layer 114b'. For example, if the connection electrode material layer CE' consists of indium tin oxide (ITO), a transparent conductive material, the connection electrode material layer CE' can crystallize at approximately 250 °C. To suppress crystallization, the deposition process for the second-first passivation material layer 114b' can be carried out under relatively low temperature conditions of approximately 200 °C or less, for example, approximately 180 °C.

[0195] Next, with reference to Fig. 4B A second-first planarization material layer 117b' is arranged on the second-first passivation material layer 114b' and surrounds the light-emitting element LED. The height of the second-first planarization material layer 117b' can be less than the height of the second electrode 125 of the light-emitting element LED. For example, the thickness of the second-first planarization material layer 117b' can be adjusted by an ashing process. For example, after applying the second-first planarization material layer 117b' so that it covers the light-emitting element LED, the ashing process can be carried out to reduce the overall thickness of the second-first planarization material layer 117b', so that the height of the second-first planarization material layer 117b' can be less than the height of the second electrode 125.Therefore, during a subsequent process, the third connecting electrode CE3, which is located on the second-first planarization material layer 117b', can easily be connected to the second electrode 125.

[0196] Meanwhile, an initial second opening section OP2' can be formed in the second-first planarization material layer 117b'. The initial second opening section OP2' can expose the second-first passivation material layer 114b'.

[0197] Next, with reference to Fig. 4C a second-second passivation material layer 114b'‚ can be formed by etching the second-first passivation material layer 114b'. The second-second passivation material layer 114b'' can be formed by etching the second-first passivation material layer 114b', which is exposed from the second-first planarization material layer 117b'.

[0198] Since, for example, the second-first planarization material layer 117b' is designed to have a thickness that is less than the thickness of the light-emitting element LED, the second-first passivation material layer 114b', which covers a top surface of the light-emitting element LED, can be exposed from the second-first planarization material layer 117b'.

[0199] Since the second-first planarization material layer 117b' is open in the initial second aperture section OP2', the second-first passivation material layer 114b', which overlaps the initial second section OP2', can be exposed from the second-first planarization material layer 117b'. Therefore, the second-second passivation material layer 114b'' can be formed by etching a section of the second-first passivation material layer 114b' that covers the top surface of the light-emitting element LED and a section of the second-first passivation material layer 114b' that overlaps the initial second aperture section OP2'. Therefore, the first aperture section OP1, which overlaps the initial second aperture section OP2', can be formed in the second-second passivation material layer 114b''.

[0200] For example, the second-second passivation material layer 114b'' can be formed by a wet etching process. Therefore, not only can the portion of the second-first passivation material layer 114b' exposed by the second-first planarization material layer 117b' be partially removed, but also the portion of the second-first passivation material layer 114b' that overlaps the second-first planarization material layer 117b'. Therefore, one end of the second-second passivation material layer 114b'' can be located within one end of the second-first planarization material layer 117b'. Therefore, the width of the first opening section OP1 can be greater than the width of the initial second opening section OP2'. However, the disclosure is not limited to this.

[0201] Meanwhile, a second-second planarization material layer 117b'' ​​can be formed by etching a portion of the second-first planarization material layer 117b' during the etching process of the second-second passivation material layer 114b''. For example, a portion of a section of the second-first planarization material layer 117b' adjacent to the light-emitting element LED can also be etched. However, the disclosure is not limited to this.

[0202] Next, with reference to Fig. 4D The first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE'. The first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE' exposed from the second-first planarization material layer 117b'' ​​and the second-second passivation material layer 114b''.

[0203] In particular, the second-second planarization material layer 117b'' ​​is opened in the initial second opening section OP2' and the second-second passivation material layer 114b'' is opened in the first opening section OP1, so that the connecting electrode material layer CE', which overlaps the initial second opening section OP2' and the first opening section OP1, can be exposed from the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b''. Therefore, the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching a section of the connecting electrode material layer CE' that overlaps the initial second opening section OP2' and the first opening section OP1.

[0204] For example, the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by a wet etching process. Therefore, not only can the portion of the connecting electrode material layer CE' exposed by the second-second planarizing material layer 117b'' ​​and the second-second passivation material layer 114b'' be partially removed, but also the portion of the connecting electrode material layer CE' that overlaps the second-second planarizing material layer 117b'' ​​and the second-second passivation material layer 114b''. Therefore, the end of the first connecting electrode CE1, the end of the second connecting electrode CE2, and the end of the protective pattern PP can be positioned inward of the end of the second-second planarizing material layer 117b'' ​​and the end of the second-second passivation material layer 114b''. However, the disclosure is not limited to this.

[0205] Furthermore, a second-third passivation layer 114b''' can be formed by etching a portion of the second-second passivation material layer 114b''. For example, not only the connecting electrode material layer CE', which is located on the side face of the light-emitting element LED, but also the second-second passivation material layer 114b'' can be exposed by the second-second planarization material layer 117b''. Therefore, the second-third passivation layer 114b''' can be formed by removing a portion of the second-second passivation material layer 114b'' located on the side face of the light-emitting element LED.

[0206] Meanwhile, a portion of the second-second passivation layer 114b'', adjacent to the light-emitting element LED, is removed, allowing the end of the first connecting electrode CE1, which contacts the light-emitting element LED, to be exposed through the second-third passivation layer 114b'''. However, the disclosure is not limited to this.

[0207] Next, with reference to Fig. 4E a second-third planarization material layer 117b''' is formed by partial ashing, e.g. halftone ashing, of the second-second planarization material layer 117b''.

[0208] For example, a section of the second-second planarization material layer 117b'' ​​that overlaps the second connection electrode CE2 can be partially ashed. For example, an initial fourth contact hole CH4' can be formed by ashing a section of the second-second planarization material layer 117b'' ​​that overlaps the first contact hole CH1 and the second contact hole CH2. Therefore, the initial fourth contact hole CH4' can overlap the first contact hole CH1 and the second contact hole CH2. The initial fourth contact hole CH4' can be positioned on the second connection electrode CE2 so that the third connection electrode CE3 and the second connection electrode CE2 are joined during a subsequent process.

[0209] Additionally, an initial sixth contact hole CH6' can be formed by ashing a section of the second-second planarization material layer 117b'' ​​that overlaps the second connecting electrode CE2 but does not overlap the first contact hole CH1 and the second contact hole CH2. The initial sixth contact hole CH6' can be positioned on the second connecting electrode CE2 so that the third connecting electrode CE3 and the second connecting electrode CE2 are additionally connected during a subsequent process.

[0210] Furthermore, an initial eighth contact hole CH8' can be formed by partially ashing a section of the second-second planarization material layer 117b'' ​​that overlaps the first connecting electrode CE1. The initial eighth contact hole CH8' can allow the illumination test pattern APP and the first connecting electrode CE1 to be joined during a subsequent process.

[0211] Next, with reference to Fig. 4F The second passivation layer 114b can be formed by etching the second-third passivation material layer 114b'''. The second passivation layer 114b can be formed by etching the second-third passivation material layer 114b''', which is exposed from the second-third planarization material layer 117b'''.

[0212] Since, for example, the second-third planarization material layer 117b''' is open at the initial fourth contact hole CH4', at the initial sixth contact hole CH6', and at the initial eighth contact hole CH8', the second-third passivation material layer 114b''', which overlaps the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8', can be exposed from the second-third planarization material layer 117b'''. Therefore, the second passivation layer 114b can be formed by etching the second-third passivation material layer 114b''', which is exposed through the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8'.Therefore, the third contact hole CH3, which overlaps the initial fourth contact hole CH4', the fifth contact hole CH5, which overlaps the initial sixth contact hole CH6', and the seventh contact hole CH7, which overlaps the initial eighth contact hole CH8', can be formed in the second passivation layer 114b.

[0213] For example, the second passivation layer 114b can be formed by a dry etching process. Therefore, unlike the wet etching process, the portion of the second-third passivation material layer 114b''' that overlaps the second-third planarization material layer 117b''' may not be removed, but only the portion of the second-third passivation material layer 114b''' that is exposed by the second-third planarization material layer 117b'''. Thus, an end of a portion of the second passivation layer 114b exposed by the third contact hole CH3, the fifth contact hole CH5, and the seventh contact hole CH7 may be consistent with an end of a portion of the second-third planarization material layer 117b''' exposed by the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8'. However, the disclosure is not limited to this.

[0214] Next, with reference to Fig. 4G the second planarization layer 117b is formed by curing the second-third planarization material layer 117b'''. In particular, the curing process can allow the second-third planarization material layer 117b''' to flow again, so that the second-third planarization material layer 117b''' can cover the end of the second passivation layer 114b, which is located below the second-third planarization material layer.

[0215] In particular, the second-third planarization material layer 117b''', which is opened by the initial fourth contact hole CH4', can flow again and be arranged in the third contact hole CH3. Therefore, the second planarization layer 117b can be arranged to cover one end of the second passivation layer 114b, which is opened by the third contact hole CH3. Therefore, the width of the fourth contact hole CH4 can be smaller than the width of the third contact hole CH3.

[0216] The second-third planarization material layer 117b''', which is opened through the initial sixth contact hole CH6', can flow again and be arranged in the fifth contact hole CH5. Therefore, the second planarization layer 117b can be arranged to cover one end of the second passivation layer 114b, which is opened through the fifth contact hole CH5. Therefore, the width of the sixth contact hole CH6 can be smaller than the width of the fifth contact hole CH5.

[0217] The second-third planarization material layer 117b''', which is opened through the initial eighth contact hole CH8', can flow again and be arranged in the seventh contact hole CH7. Therefore, the second planarization layer 117b can be arranged to cover one end of the second passivation layer 114b, which is opened through the seventh contact hole CH7. Therefore, the width of the eighth contact hole CH8 of the second planarization layer 117b can be smaller than the width of the seventh contact hole CH7.

[0218] The second-third planarization material layer 117b''', which is opened by an initial second opening section OP2', can flow again and be arranged in the first opening section OP1. Therefore, the second planarization layer 117b can be arranged to cover one end of the second passivation layer 114b, which is opened by the first opening section OP1. Therefore, the width of the second opening section OP2 of the second planarization layer 117b can be smaller than the width of the first opening section OP1.

[0219] Meanwhile, the second planarization layer 117b can flow anew to the first opening section OP1 and be arranged on the first planarization layer 117a, which overlaps the first opening section OP1. In this case, the second planarization layer 117b can be arranged to cover the end of the first connecting electrode CE1 and the end of the second connecting electrode CE2, since the first section OP1 is located between the first connecting electrode CE1 and the second connecting electrode CE2. Therefore, the second planarization layer 117b can enable the separation of the first connecting electrode CE1 and the second connecting electrode CE2.

[0220] In particular, the second planarization layer 117b can be arranged to cover not only the end of the second passivation layer 114b, but also the end of the first connecting electrode CE1, which is exposed by the second passivation layer 114b. Therefore, the second planarization layer 117b can allow the first connecting electrode CE1 and the third connecting electrode CE3 to be separated from each other during a subsequent process.

[0221] As described above, the end of the first connection electrode CE1, which contacts the light-emitting element LED, may be exposed by the second passivation layer 114b. In this case, the curing process can allow the second planarization layer 117b to flow again, so that the second planarization layer 117b can be positioned on the end of the first connection electrode CE1 that is exposed by the second passivation layer 114b. Therefore, the second planarization layer 117b can flow again and cover the end of the first connection electrode CE1 that contacts the light-emitting element LED. Consequently, the height of the second planarization layer 117b can decrease towards the light-emitting element LED.The second planarization layer 117b can be arranged to cover the end of the first connecting electrode CE1 and the end of the second passivation layer 114b, which is arranged to surround part of the side surface of the light-emitting element LED. The inclination direction of the end of the first connecting electrode CE1, the side surface of the light-emitting element LED, and the end of the second passivation layer 114b can be identical to the inclination direction of the second planarization layer 117b, which covers the end of the first connecting electrode CE1 and the end of the second passivation layer 114b. The second planarization layer 117b and the light-emitting element LED can form a "V" shape at a section where the second planarization layer 117b contacts the side surface of the light-emitting element LED. As shown in . Fig. 3 and Fig. As shown in 4H, the side surface of the light-emitting element LED can be a left surface of the light-emitting element LED, a right surface of the light-emitting element LED, or both the left surface and the right surface of the light-emitting element LED.

[0222] Next, with reference to Fig. 4H the third connecting electrode CE3 and the illumination test pattern APP are arranged on the second planarization layer 117b and spaced apart from each other. The third connecting electrode CE3 can be arranged on the light-emitting element LED and the illumination test pattern APP can be arranged so that it overlaps the eighth contact hole CH8.

[0223] As described above, the second planarization layer 117b is formed by carrying out the ashing process only until the second electrode 125 of the light-emitting element LED is exposed. The third interconnect electrode CE3, located on the second planarization layer 117b, may only contact the upper surface of the second electrode 125 exposed by the second planarization layer 117b, and the third interconnect electrode CE3 may be spaced from the first interconnect electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121, which are located below the second planarization layer 117b. Therefore, the third interconnect electrode CE3 and the second electrode 125 can be self-aligning without ensuring a process margin.

[0224] Meanwhile, the illumination test pattern APP can be arranged in the seventh contact hole CH7 and the eighth contact hole CH8 on the second planarization layer 117b and electrically connected to the first connecting electrode CE1, which is exposed through the seventh contact hole CH7 and the eighth contact hole CH8.

[0225] In this case, the illumination test can be performed. For example, the illumination test signals can be applied to the illumination test pattern APP and the third connection electrode CE3. Therefore, the illumination test signal applied via the illumination test pattern APP can be sent via the first connection electrode CE1 to the first electrode 124 of the light-emitting element LED. The illumination test signals applied via the third connection electrode CE3 can be sent to the second electrode 125 of the light-emitting element LED. Therefore, it is possible to detect whether the light-emitting element LED is defective, regardless of whether the drive transistor DT is faulty.

[0226] Next, bank 118 and the third planarization layer 119 are arranged on the second planarization layer 117b, the third connecting electrode CE3 and the illumination test pattern APP, so that the process of manufacturing the display device 100 can be completed.

[0227] During a process to arrange or transfer multiple light-emitting elements onto the substrate, some of the light-emitting elements may be misaligned or incorrectly positioned. In this case, a short-circuit fault between the electrodes can occur if a subsequent process is carried out in the condition where some of the light-emitting elements are misaligned or incorrectly positioned.In a case where, for example, the light-emitting elements are misaligned and the same electrode is connected to both the first and second electrodes of the light-emitting element, or where the electrodes connected to both the first and second electrodes of the light-emitting element are arranged in such a way that they overlap without being separated from each other, a short-circuit fault occurs and the light-emitting element may not be able to emit light normally.

[0228] Therefore, in the display device 100 according to the embodiment of the disclosure, the first connecting electrode CE1 and the first electrode 124 of the light-emitting element LED can be self-aligning and connected. For example, after the material layer of the first planarization layer 117a has been applied to cover the light-emitting element LED, the material layer of the first planarization layer 117a can be ashed so that the first electrode 124 can be exposed. Therefore, the first connecting electrode CE1 arranged on the first planarization layer 117a can be easily connected to the first electrode 124 without a separate contact hole. Therefore, the first connecting electrode CE1 and the first electrode 124 can be self-aligning without having to ensure a process clearance.Therefore, it is possible to minimize or reduce short-circuit faults of the first connecting electrode CE1 and the third connecting electrode CE3 caused by a process error.

[0229] Similarly, in the display device 100 according to the embodiment of the disclosure, the third connecting electrode CE3 and the second electrode 125 of the light-emitting element LED can be self-aligning and connected. For example, after the material layer of the second planarization layer 117b has been applied to cover the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED, the material layer of the second planarization layer 117b is ashed such that possibly only the second electrode 125 is exposed. Therefore, although the second connecting electrode CE2 is formed by forming and structuring the material layer of the second connecting electrode CE2 on the front surface of the substrate 110, including the second planarization layer 117b, possibly only contacts the upper surface of the second electrode 125 that is exposed from the second planarization layer 117b.This means that the third connecting electrode CE3 and the second electrode 125 can be self-aligning without having to ensure a process margin. Therefore, it is possible to minimize or reduce short-circuit faults of the first connecting electrode CE1 and the third connecting electrode CE3 caused by a process error.

[0230] Furthermore, in the display device 100 according to the embodiment of the disclosure, the second passivation layer 114b can be arranged on the first connecting electrode CE1 and the second connecting electrode CE2. Since the second passivation layer 114b is arranged such that it covers at least a portion of the first connecting electrode CE1, the second passivation layer 114b, together with the second planarization layer 117b, can enable the first connecting electrode CE1 and the third connecting electrode CE3 to be separated from each other. Therefore, the second passivation layer 114b can prevent the first connecting electrode CE1 and the third connecting electrode CE3 from being short-circuited.

[0231] Furthermore, the second passivation layer 114b consists of an inorganic insulating material that can suppress the ingress of moisture or impurities into the multiple reflective electrodes RE, which are connected to the multiple first connecting electrodes CE1 and the multiple second connecting electrodes CE2. Therefore, it is possible to suppress the separation and corrosion of the multiple reflective electrodes RE caused by the ingress of moisture.

[0232] In particular, in the display device 100 according to the embodiment of the disclosure, the second planarization layer 117b flows anew onto the exposed first connection electrode CE1 when the first connection electrode CE1 is exposed by the second passivation layer 114b, so that the first connection electrode CE1 and the third connection electrode CE3 can be separated. For example, the curing process allows the second planarization layer 117b to flow again, so that the second planarization layer 117b can be arranged to cover the first connection electrode CE1 exposed by the second passivation layer 114b.Therefore, in the display device 100 according to the embodiment of the disclosure, although the first connecting electrode CE1 is exposed during the process by the second passivation layer 114b, the second planarization layer 117b can flow again, so that the first connecting electrode CE1 and the third connecting electrode CE3 can be separated, thereby suppressing a short-circuit fault in which the first connecting electrode CE1 and the third connecting electrode CE3 are connected.

[0233] Although the embodiments of the disclosure mentioned above have been described in detail with reference to the accompanying drawings, the disclosure is not limited to them and can be embodied in many different forms without deviating from the technical concept of the disclosure. Therefore, the embodiments mentioned above serve only for illustration and are not intended to limit the technical concept of the disclosure. The scope of the technical concept of the disclosure is not limited thereto. It should therefore be understood that the embodiments described above are illustrative in every respect and do not limit the disclosure. All technical concepts within the equivalent scope of the disclosure are to be interpreted as falling within the scope of the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0188392

[0001]

Claims

[1] Display device comprising: a substrate (110) on which several subpixels (SP) are defined; a power line (VDD) and a drive transistor (DT) arranged on the substrate (110); a first reflective electrode (RE1) and a second reflective electrode (RE2) arranged on the power line (VDD) and the drive transistor (DT) and spaced apart from each other, wherein the first reflective electrode (RE1) is connected to the drive transistor (DT) and the second reflective electrode (RE2) is connected to the power line (VDD); a connecting layer (116) arranged on the first reflecting electrode (RE1) and the second reflecting electrode (RE2); several light-emitting elements (120) which are each arranged in the several subpixels (SP) on the interconnect layer (116) and comprise a first electrode (124) and a second electrode (125); a first planarization layer (117a) which is arranged on the connecting layer (116) and is designed to partially surround the side surfaces of the several light-emitting elements (120); a first connecting electrode (CE1) which is arranged on the first planarization layer (117a) and is designed to connect the first electrode (124) and the drive transistor (DT); a second connecting electrode (CE2) which is arranged on the first planarization layer (117a), spaced apart from the first connecting electrode (CE1) and connected to the second reflecting electrode (RE2); a passivation layer (114b) arranged on the first connecting electrode (CE1) and the second connecting electrode (CE2); a second planarization layer (117b) arranged on the passivation layer (114b) and designed to partially surround the side surfaces of the multiple light-emitting elements (120); and a third connecting electrode (CE3) which is arranged on the second planarization layer (117b) and is designed to connect the second electrode (CE2) and the current conductor (VDD), wherein the passivation layer (114b) exposes an end of the first connecting electrode (CE1) which is arranged to surround part of a side surface of one of the light-emitting elements (120) of the multiple light-emitting elements (120), and wherein the second planarization layer (117b) covers the end of the first connecting electrode (CE1). [2] Display device according to claim 1, wherein the second planarization layer (117b) is arranged to cover the end of the first connecting electrode (CE1) and an end of the passivation layer (114b) corresponding to the end of the first connecting electrode (CE1). [3] Display device according to claim 1 or 2, wherein a direction of inclination of the end of the first connecting electrode (CE1) and the end of the passivation layer (114b) arranged on the side surface of the light-emitting element (120) is identical to a direction of inclination of the second planarization layer (117b) covering the end of the first connecting electrode (CE1) and the end of the passivation layer (114b), and the second planarization layer (117b) preferably defines a ‘V’ shape in an area contacting the light-emitting element (120). [4] Display device according to one of the preceding claims, wherein the height of a section of the second planarization layer (117b) that overlaps the end of the first connecting electrode (CE1) is less than the height of a section of the second planarization layer (117b) that does not overlap the end of the first connecting electrode (CE1). [5] Display device according to one of the preceding claims, wherein the passivation layer (114b) has a first opening section (OP1) that exposes the first planarization layer (117a), wherein the second planarization layer (117b) has a second opening section (OP2) that overlaps the first opening section (OP1), where the width of the first opening section (OP1) is greater than the width of the second opening section (OP2), and wherein the second planarization layer (117b) is arranged in the first opening section (OP1) and covers another end of the first connecting electrode (CE1) and an end of the second connecting electrode (CE2), wherein the third connecting electrode (CE3) is preferably arranged in the first section (OP1) and the second opening section (OP3) and is provided such that it is in contact with the first planarization layer (117a). [6] Display device according to one of the preceding claims, wherein the connecting layer (116) has a first contact hole (CH1) that exposes the second reflective electrode (RE2), wherein the first planarization layer (117a) has a second contact hole (CH2) that overlaps the first contact hole (CH1) and exposes the second reflective electrode (RE2), wherein the second connecting electrode (RE2) is arranged in the first contact hole (CH1) and the second contact hole (CH2) and contacts the second reflective electrode (RE2), wherein the passivation layer (114b) has a third contact hole (CH3) that overlaps the first contact hole (CH1) and the second contact hole (CH2) and exposes the second connecting electrode (RE2), wherein the second planarization layer (117b) has a fourth contact hole (CH4) that overlaps the first contact hole (CH1), the second contact hole (CH2) and the third contact hole (CH3) and exposes the second connecting electrode (RE2), and wherein the third connecting electrode (RE3) is arranged in the first contact hole (CH1), the second contact hole (CH2), the third contact hole (CH3) and the fourth contact hole (CH4) and contacts the second connecting electrode (RE2), wherein a width of the third contact hole (CH3) is preferably larger than a width of the fourth contact hole (CH4) and / or the second planarization layer (117b) is arranged in the third contact hole (CH3) and covers one end of the passivation layer (114b). [7] Display device according to one of the preceding claims, wherein the connecting layer (116) has a first contact hole (CH1) that exposes the second reflective electrode (RE2), wherein the first planarization layer (117a) has a second contact hole (CH2) that overlaps the first contact hole (CH1) and exposes the second reflective electrode (RE2), wherein the second connecting electrode (RE2) is arranged in the first contact hole (CH1) and the second contact hole (CH2) and contacts the second reflective electrode (RE2), wherein the passivation layer (114b) has a fifth contact hole (CH5) that exposes the second connecting electrode (RE2) without overlapping the first contact hole (CH1) and the second contact hole (CH2), wherein the second planarization layer (117b) has a sixth contact hole (CH6) that overlaps the fifth contact hole (CH5), and wherein the third connecting electrode (CE3) is arranged in the fifth contact hole (CH5) and the sixth contact hole (CH6) and contacts the second connecting electrode (RE2), wherein the width of the fifth contact hole (CH5) is preferably larger than the width of the sixth contact hole (CH6) and / or the second planarization layer (117b) is arranged in the fifth contact hole (CH5) and covers one end of the passivation layer (114). [8] Display device according to any one of the preceding claims, further comprising: a conductive pattern (APP) arranged on the second planarization layer (117b), wherein the passivation layer (114b) has a seventh contact hole (CH7) that exposes the first connecting electrode (RE1), wherein the second planarization layer (117b) has an eighth contact hole (CH8) that overlaps the seventh contact hole (CH7), and wherein the conductive pattern (APP) is connected to the first connecting electrode (RE1) via the seventh contact hole (CH7) and the eighth contact hole (CH8), wherein the width of the seventh contact hole (CH7) is preferably larger than the width of the eighth contact hole (CH8) and / or the second planarization layer (117b) is arranged in the seventh contact hole (CH7) and covers one end of the passivation layer (114b). [9] Display device comprising: a substrate (110) with multiple pixels (PX) that are defined, each pixel (PX) having multiple subpixels (SP); a power line (VDD) and a drive transistor (DT) arranged on the substrate (110); a first reflective electrode (RE1) and a second reflective electrode (RE2) arranged on the power line (VDD) and the drive transistor (DT) and spaced apart from each other, wherein the first reflective electrode (RE1) is connected to the drive transistor (DT) and the second reflective electrode (RE2) is connected to the power line (VDD); a connecting layer (116) arranged on the first reflecting electrode (RE1) and the second reflecting electrode (RE2); several light-emitting elements (120) which are each arranged in the several subpixels (SP) on the interconnect layer (116) and comprise a first electrode (124) and a second electrode (125); a first planarization layer (117a) which is arranged on the connecting layer (116) and is designed to partially surround the side surfaces of the several light-emitting elements (120); a first connecting electrode (CE1) which is arranged on the first planarization layer (117a) and is designed to connect the first electrode (124) and the drive transistor (DT); a second connecting electrode (CE2) which is arranged on the first planarization layer (117a), spaced apart from the first connecting electrode (117b) and connected to the second reflecting electrode (RE2); a passivation layer (114b) arranged on the first connecting electrode (CE1) and the second connecting electrode (CE2); a second planarization layer (117b) arranged on top of the passivation layer (114b) and having a height that decreases towards the multiple light-emitting elements (120); and a third connecting electrode (CE3) which is arranged on the second planarization layer (117b) and is designed to connect the second electrode (125) and the power conductor (VDD). [10] Display device according to one of the preceding claims, wherein the passivation layer (114b) surrounds the multiple light-emitting elements (120) and exposes part of the first connecting electrode (CE1), and wherein a height of a lower end of an upper surface of the second planarization layer (117b) is higher than a height of a top end of an upper surface of the exposed part of the first connecting electrode (CE1). [11] Display device according to one of the preceding claims, wherein the passivation layer (114b) has an opening section (OP1) that exposes the first planarization layer (117a), wherein the second planarization layer (117b) has an opening section (OP2) that overlaps the opening section (OP1) of the passivation layer (114b) and has a smaller width than the opening section (OP1) of the passivation layer (114b), and wherein the second planarization layer (117b) is arranged in the opening section of the passivation layer (114b) and separates the first connecting electrode (CE1) and the second connecting electrode (CE2). [12] Display device according to one of the preceding claims, wherein the multiple pixels (PX) each have a first area (CA1) in which the third connecting electrode (CE3) and the current line (VDD) are electrically connected, and a second area (CA2) which is spaced apart from the first area, wherein in the first area (CA1) the third connecting electrode (CE3) is connected to the current conductor (VDD) via the second reflective electrode (RE2) and the second connecting electrode (CE2), and wherein in the second area (CA2) the third connecting electrode (CE3) is connected to the current conductor (VDD) via the second connecting electrode (CE2) which extends from the first area (CA1). [13] Display device according to claim 12, wherein the connecting layer (116) has a contact hole (CH1) which is arranged in the first region (CA1) and exposes the second reflective electrode (RE2), wherein the first planarization layer (117a) has a contact hole (CH2) which is located in the first region (CA1) and overlaps the contact hole (CH1) of the connection layer (116), and wherein the second connecting electrode (CE2) is connected to the second reflective electrode (RE2) via the contact hole (CH2) of the first planarization layer (117a) and the contact hole (CH1) of the connecting layer (116). [14] Display device according to claim 12 or 13, wherein the passivation layer (114b) has a contact hole (CH3) which is arranged in the first region (CA1), overlaps the contact hole (CH2) of the first planarization layer (117a) and the contact hole (CH1) of the connection layer (116) and exposes the second connection electrode (CE2), wherein the second planarization layer (117b) has a contact hole (CH4) located in the first region (CA1), overlapping the contact hole (CH2) of the first planarization layer (117a), the contact hole (CH1) of the connection layer (116) and the contact hole (CH3) of the passivation layer (114b), and exposing the second connection electrode (CE2), and wherein the third connecting electrode (CE3) is connected to the second connecting electrode (CE2) via the contact hole (CH4) of the second planarization layer (117b), the contact hole (CH3) of the passivation layer (114b), the contact hole (CH) of the first planarization layer (117a) and the contact hole (CH1) of the connecting layer (116). [15] Display device according to claim 12, 13 or 14, wherein the passivation layer (114b) further comprises a contact hole (CH5) located in the second region (CA2) and exposing the second connecting electrode (CE2) extending from the first region (CA1), wherein the second planarization layer (117b) further comprises a contact hole (CH6) located in the second region (CA2) and exposing the second connecting electrode (CE2) extending from the first region (CA1), and wherein the third connecting electrode (CE3) is connected to the second connecting electrode (CE3) via the contact hole (CH5) of the passivation layer (114b) located in the second region and the contact hole (CH6) of the second planarization layer (117b). [16] Display device according to any one of the preceding claims, further comprising: an illumination test area (APA) arranged in each of the multiple pixels (PX), wherein an illumination test pattern (APP) is arranged on the second planarization layer (117b) in the illumination test area (APA), wherein the passivation layer (114b) has a contact hole (CH7) which is located in the illumination test area (APP) and exposes the first connecting electrode (CE1), wherein the second planarization layer (117b) has a contact hole (CH8) that overlaps the contact hole (CH7) of the passivation layer (114b) and exposes the first connecting electrode (CE1), and wherein the illumination test pattern (APA) is connected to the first connecting electrode (CE1) via the contact hole (CH6) of the second planarization layer (117b) and the contact hole (CH5) of the passivation layer (114b). [17] Display device according to one of the preceding claims, wherein the height of the first planarization layer (117a) is less than the height of the first electrode (124) and the height of the second planarization layer (117b) is less than the height of the second electrode (125) and / or the side surfaces of the multiple light-emitting elements (120) are one or both of the two side surfaces of the multiple light-emitting elements (120) and / or the passivation layer (114b) and the first connecting electrode (RE1) have heights that decrease towards the multiple light-emitting elements (120).

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