DISPLAY DEVICE

Abstract

A display device (100) comprises a display panel (109, PNL) with a display area (AA) and a sensor area (SA) within the display area (AA), wherein the sensor area (SA) has a sensor display area (SDA) for displaying an image and a sensor transparency area (STA) for transmitting light, and a sensor module (SM) arranged on a lower surface of the display panel (109, PNL) to be aligned with the sensor area (SA). A first sensor sub-pixel (SDSP1), a second sensor sub-pixel (SDSP2), and a third sensor sub-pixel, displaying different colors, are arranged in the sensor display area (SDA), and a plurality of second sensor sub-pixels (SDSP2) and a plurality of third sensor sub-pixels (SDSP3) are arranged in the sensor display area (SDA).

Description

Technical field The present disclosure relates to a display device, and in particular a camera-integrated display device with an advantageous lifetime. background With the development of information technologies, numerous small and thin display devices have been developed, such as a liquid crystal display device, an organic light-emitting display device, a plasma device and a micro-LED display device. These display devices are equipped with a camera to offer users numerous functions. The camera-integrated display device has a camera opening for positioning the camera. In this case, no images are displayed in the area where the camera opening is located, so the problem was that the image displayed on the device was interrupted, and this interruption was perceived by the user. Brief explanation of the Revelation Accordingly, some embodiments of the present disclosure relate to a display device which essentially eliminates one or more of the problems arising from the limitations and disadvantages of the related technology. One aspect of the present disclosure is to provide a display device in which an image of an area in which a sensor is embedded within a display area is not interrupted or separated. Another aspect of the present disclosure is to provide a display device which is able to prevent a reduction in lifetime due to excessive current flow by maximizing a light-emitting area of ​​the region in which the sensor is embedded. Additional features and aspects are set forth in the following description and are partly evident from the description or can be learned through the practical application of the concepts disclosed herein. Further features and aspects of the disclosed concept can be realized and achieved through the structure particularly highlighted in or derivable from the written description, as well as through the claims and the accompanying drawings. To achieve these and other aspects of the inventive concepts as they are realized and generally described, the present disclosure provides a display device comprising a display panel having a display area and a sensor area within the display area, wherein the sensor area has a sensor display area for displaying an image and a sensor transparency area for transmitting light, a sensor module arranged on a lower surface of the display panel and aligned with the sensor area, and a sensor display area pixel comprising a first sensor sub-pixel, a plurality of second sensor sub-pixels, and a plurality of third sensor sub-pixels arranged in the sensor display area, wherein the first sensor sub-pixel is configured to display a first color, and wherein the plurality of second sensor sub-pixels are configured to display a second color.and wherein the majority of third sensor sub-pixels are configured to display a third color. The majority of second sensor sub-pixels and the majority of third sensor sub-pixels are arranged around the first sensor sub-pixel. The first sensor sub-pixel, the second sensor sub-pixel and the third sensor sub-pixel can each display a color from red, green and blue. In one embodiment, the first sensor sub-pixel can be arranged in a central area of ​​the sensor display area. The first sensor sub-pixel can extend to a boundary area between the sensor display area and the sensor transparency area. The first sensor sub-pixel can extend from the sensor display area to the sensor transparency area. The second sensor sub-pixel and the third sensor sub-pixel can be arranged around the first sensor sub-pixel. The second sensor sub-pixels and the third sensor sub-pixels can extend from the sensor display area to the sensor transparency area. The display device can further comprise a first thin-film transistor arranged in the first sensor sub-pixel, a second thin-film transistor arranged in the second sensor sub-pixels, a third thin-film transistor arranged in the third sensor sub-pixels, a first light-emitting diode arranged in the first sensor sub-pixel, a plurality of second light-emitting diodes arranged in each of the second sensor sub-pixels, and a plurality of third light-emitting diodes arranged in each of the third sensor sub-pixels. The emission layers of most second light-emitting diodes can be integrally formed. In one embodiment, the majority of second light-emitting diodes can be electrically connected to the second thin-film transistor, and the majority of third light-emitting diodes can be electrically connected to the third thin-film transistor. Each of the first thin-film transistor, the second thin-film transistor and the third thin-film transistor has a semiconductor layer, a gate insulating layer arranged on the semiconductor layer, a gate electrode arranged on the gate insulating layer, an interlayer insulating layer arranged on the gate electrode and a source electrode and drain electrode which are arranged on the interlayer insulating layer. The second sensor sub-pixel can have a first second sensor sub-pixel and at least one second second sensor sub-pixel, and the third sensor sub-pixel can have a first third sensor sub-pixel and at least one second third sensor sub-pixel. In a further embodiment, the display device can also have a first connecting electrode, which is arranged on the intermediate layer insulating layer of the at least one second second sensor sub-pixel, and a second connecting electrode, which is arranged on the intermediate layer insulating layer of the at least one second third sensor sub-pixel. For example, the first connecting electrode can be made of the same material as the drain electrode of the second thin-film transistor, and the second connecting electrode can be made of the same material as the drain electrode material of the third thin-film transistor. The second thin-film transistor can be directly connected to the second light-emitting diode, which is located in the first second sensor sub-pixel, and can be connected to the second light-emitting diode, which is located in the second second sensor sub-pixel, via the first connecting electrode. The third thin-film transistor can be directly connected to the third light-emitting diode located in the first third sensor sub-pixel, and can be connected to the third light-emitting diode via the second connecting electrode located in the second third sensor sub-pixel. For example, the display area can have a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sensor sub-pixel can have an area that is larger than the area of ​​the first sub-pixel. The second sensor sub-pixel can have an area that is essentially equal to the area of ​​the second sub-pixel. The third sensor sub-pixel can have an area that is essentially equal to the area of ​​the third sub-pixel. The first sensor sub-pixel can only have a single emission layer. The first sensor sub-pixel can be directly surrounded by a plurality of sensor transparency areas. The first sensor sub-pixel can be directly adjacent to at least four sensor transparency areas. The second sensor sub-pixel and the third sensor sub-pixel can be directly adjacent to the first sensor sub-pixel. The size of a sensor display area pixel can be larger than the size of a display area pixel. A sensor area can have at least four sensor transparency areas. In one or more embodiments, the sensor area comprises the sensor display area, in which the image is displayed, and the sensor transparency area, so that the sensor area can simultaneously display the image and detect external light. Therefore, compared to a conventional configuration in which a sensor is arranged in a recess or a configuration in which a hole is formed in the display area, it is possible to prevent a reduction in the area of ​​the display area or a separation or interruption of the image. Furthermore, several sensor sub-pixels are arranged in a sensor display area within the display device, thereby increasing the light-emitting area that emits light in the sensor area. By increasing the light-emitting area, the brightness difference between the display area and the sensor area can be minimized, even without increasing the current supplied to the sensor sub-pixels, thus preventing a reduction in the display device's lifespan. Furthermore, since the amount of current supplied to the sensor sub-pixels in the display device can be reduced, a power-saving display device that can lower power consumption can be realized. It is understood that both the preceding general description and the following detailed description are exemplary and explanatory and serve to provide a more detailed explanation of the concepts according to the invention, as claimed. Brief description of the drawings The accompanying drawings, which facilitate a better understanding of the disclosure, are included in this application and form part thereof. They illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. Fig. 1 shows a schematic block diagram of a display device according to the present disclosure. Fig. 2 shows a schematic block diagram of a sub-pixel in the display device according to the present disclosure. Fig. 3 shows a schematic circuit diagram of a sub-pixel in the display device according to the present disclosure. Fig. 4 shows a perspective exploded view of the display device according to an embodiment of the present disclosure. Fig. 5 shows a top view of a display panel of the display device according to an embodiment of the present disclosure. Fig. 6 shows a top view that enlarges area “A” in Fig. 5.Figure 7 shows a schematic top view of sensor sub-pixels of the display device according to an embodiment of the present disclosure. Figure 8A shows a cross-sectional view along line II' in Figure 7. Figure 8B shows a cross-sectional view along line II-II' in Figure 7. Detailed description of the embodiments The advantages and features of the present disclosure and the methods for its implementation will become clear with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different embodiments and should not be considered limited to the embodiments set forth herein, and the embodiments are provided so that this disclosure becomes complete and comprehensive and fully conveys to those skilled in the art in the field to which the present disclosure relates the scope of the present disclosure. Shapes, sizes, ratios, angles, numbers, and the like, which are disclosed in the drawings to describe embodiments of the present disclosure, are merely illustrative examples, and therefore the present disclosure is not limited to the examples shown. Unless otherwise indicated, identical reference numerals in this disclosure refer to identical components. Furthermore, in the subsequent description of the present disclosure, if a detailed description of a known related technique might unnecessarily obscure the core of the present disclosure, the detailed description of that technique may be omitted or briefly discussed. Where terms such as "exhibiting," "having," "comprising," and the like are used in this revelation, further parts may be added, provided that no more restrictive term such as "only" is used herein. Furthermore, unless otherwise indicated, when a component is described in the singular, it also includes the plural, and vice versa. When analyzing a component, a fault area should be interpreted as included, even if no explicit description is provided. When describing a positional relationship, for example when a positional relationship between two parts / layers is described as "above", "on", "above", "below", "under", "next to" or the like, one or more further parts / layers may be provided between the two parts / layers, unless a more restrictive term such as "immediately" or "directly" is used. When describing a temporal relationship, for example when a temporal precursor relationship is described as "after", "subsequent", "next to", "before" or similar, cases that are not continuous or sequential can also be included, provided that no more restrictive term such as "immediately" or "directly" is used. Although the terms first, second, and the like can be used to describe numerous components, these terms do not significantly restrict these components. These terms are only used to distinguish one component from another and cannot define a specific order or sequence. Therefore, a first component described below could essentially be a second component, and vice versa. In describing the components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. These terms serve only to distinguish the components from one another, and the nature, order, sequence, or number of the components are not restricted by these terms. When it is described that a component is "connected," "coupled," or "linked" to another component, it should be understood that the component may be directly connected or linked to the other component, but that further components may also be "interposed" between the individual components, or that each component may be "connected," "coupled," or "linked" by another component. Features of numerous embodiments of the present disclosure can be partially or completely combined or merged with one another, with numerous interactions and operations being technically possible, and each of the embodiments can be implemented independently or in a mutually dependent relationship. All components of each display device according to all embodiments of the present disclosure are operatively connected and configured. As used here, "display device" or "display assembly" can encompass a narrowly defined display device, such as a display module with a display panel and a driver unit for controlling the display panel. Furthermore, the display device can also include an electronic set or assembly such as a notebook computer, a television, a computer monitor, a vehicle display device, or other configurations of a vehicle, which are complete products (or end products), including a display module, a device display, a mobile electronic device such as a smartphone or an electronic tablet, and the like. Therefore, the display device in the present disclosure can comprise a narrowly defined display device itself, such as a display module, and a set device, which is an application product or an end-user device with a display module. The following section will discuss in detail aspects of the revelation, examples of which are illustrated in the accompanying drawings. Where possible, the same reference symbols are used in the drawings to indicate identical or similar parts. Fig. 1 shows a schematic block diagram of a display device according to the present disclosure. Fig. 2 shows a schematic block diagram of a sub-pixel in the display device according to the present disclosure. As shown in Fig. 1, a display device 100 can include an image processor 102, a timing controller 104, a gate driver 106, a data driver 107, a power supply 108 and a display panel 109. The image processor 102 outputs control signals for numerous components along with externally supplied image data. The control signal output by the image processor 102 can include, for example, a data release signal, a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like, but is not limited to these. The timing control unit 104 receives control signals along with image data from the image processor 102. The timing control unit 104 generates and outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 106 and a data timing control signal DDC for controlling the operating timing of the data driver 107 based on the control signal input from the image processor 102. The gate driver 106 outputs a sampling signal to the display panel 109 in response to the gate timing control signal GDC supplied by the timing control unit 104. The gate driver 106 outputs the sampling signal via a plurality of gate lines GL1 to GLm (where m is an integer greater than or equal to 2). In one embodiment, the gate driver 106 can be implemented as an integrated circuit (IC), but this is not limited to this. The data driver 107 outputs a data voltage to the display panel 109 in response to the data timing control signal DDC input from the timing control unit 104. The data driver 107 samples and buffers a digital data signal DATA supplied by the timing control unit 104 and converts the digital data signal DATA into an analog data voltage based on a gamma voltage. The data driver 107 outputs the data voltage through a plurality of data lines DL1 to DLn (n is an integer greater than or equal to 2). In one embodiment, the data driver 107 can be implemented as an integrated circuit (IC), but this is not limited to this. The power supply 108 outputs a high potential voltage VDD and a low potential voltage VSS and supplies the display panel 109 with these voltages. The high potential voltage VDD is supplied to the display panel 109 via a first power line EVDD, and the low potential voltage VSS is supplied to the display panel 109 via a second power line EVSS. Alternatively or additionally, the voltages output by the power supply 108 can be output to the gate driver 106 and / or the data driver 107 to control these drivers. The display panel 109 displays images in response to the sampling signal supplied by the gate driver 106, the data voltage supplied by the data driver 107, and the power supplied by the power supply 108. The display panel 109 has a plurality of sub-pixels (SPs) for displaying an image. In one embodiment, the sub-pixel SP can have a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Alternatively, the sub-pixel SP can have a white (W) sub-pixel, a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In one embodiment, the white (W), red (R), green (G), and blue (B) sub-pixels can have substantially the same areas. Alternatively, the white (W), red (R), green (G), and blue (B) sub-pixels can have different areas. As shown in Fig. 2, each sub-pixel SP can be connected to a gate line GL, a data line DL, a first power line EVDD, and a second power line EVSS. The number and control methods of a transistor and a capacitor can be determined by the configuration of the pixel circuitry within the sub-pixel SP. Fig. 3 shows a schematic circuit diagram of a sub-pixel in the display device according to the present disclosure. As shown in Fig. 3, the display device 100 has a gate line GL, a data line DL, and a power line PL, which intersect to define the sub-pixel SP. A switching thin-film transistor Ts, a drive thin-film transistor Td, a storage capacitor Cst, and a light-emitting diode D can be arranged in the sub-pixel SP. The switching thin-film transistor Ts is connected to the gate line GL and the data line DL. The driver thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL, and the LED D is connected to the driver thin-film transistor Td. In the display device, when the switching thin-film transistor Ts is switched on by a gate signal applied to the gate line GL, a data signal applied to the data line DL is applied to a gate electrode of the control thin-film transistor Td (for example, the gate electrodes 115 and 125 in Fig. 8A and Fig. 8B) and to an electrode of the storage capacitor Cst by the switching thin-film transistor Ts. The driver thin-film transistor Td is switched on by the data signal applied to its gate electrode (e.g., gate electrode 124 in Fig. 8B), so that a current proportional to the data signal is supplied from the current line PL through the driver thin-film transistor Td to the light-emitting diode D. The light-emitting diode D then emits light with a brightness proportional to the current flowing through the driver thin-film transistor Td. In this case, the storage capacitor Cst is charged with a voltage proportional to the data signal, so that the voltage of the gate electrode in the driver thin-film transistor Td (e.g., gate electrode 124 in Fig. 8B) is kept constant during a frame. This allows the display device 100 to display a desired image. In Fig. 3, the display device 100 has two thin-film transistors Ts and Td and a storage capacitor Cst in the sub-pixel SP. However, the display device 100 can have three or more thin-film transistors and two or more storage capacitors. Fig. 4 shows a perspective exploded view of the display device according to one embodiment of the present disclosure. Fig. 5 shows a top view of a display panel of the display device according to one embodiment of the present disclosure. As shown in Fig. 4, the display device 100 in one embodiment of the present disclosure comprises a display panel PNL, a sensor module SM, a printed circuit board CB, a cover window CW, and a frame FRA. As shown in Fig. 5, the display panel PNL can have a display area AA in which an image is displayed and a non-display area NA, which is arranged outside the display area AA. A pixel area P with a plurality of sub-pixels SP1, SP2, and SP3 is arranged in the display area AA. The sub-pixels SP1, SP2, and SP3 can contain a red (R), a green (G), or a blue (B) sub-pixel, respectively. Alternatively or additionally, the pixel area P can also contain a white (W) sub-pixel. A plurality of gate lines GLs and a plurality of data lines DLs are arranged in the display area AA. Each of the sub-pixels SP1, SP2, and SP3 is located at an intersection of the gate line GL and the data lines DL. A thin-film transistor, acting as a switching element, and a display device for converting an image can be located within each sub-pixel SP1, SP2, and SP3. The display device can include various display devices. For example, the display device can include, among others, an organic light-emitting display device, a liquid crystal display device, a quantum dot display device, a micro-LED (light-emitting diode) display device, and a mini-LED display device. The gate driver 106 (Fig. 1) and the data driver 107 (Fig. 1), which apply numerous signals to the display panel PNL, can be located in the non-display area NA. The gate driver 106 applies the sampling signal to sub-pixels SP1, SP2, and SP3 via the gate line GL, and the data driver 107 applies a video signal to sub-pixels SP1, SP2, and SP3 via the data line DL. In one embodiment, the gate driver 106 can, but is not limited to, be a gate-in-panel (GIP) circuit in which gate drive circuits are arranged directly on a substrate. The sensor module SM can be located on the rear of the display panel PNL. In one embodiment, the sensor module SM can be positioned to overlap the display area AA of the display panel PNL. The sensor module SM can include any components that utilize external inputs provided via the display panel PNL. For example, the sensor module SM can include, but is not limited to, a camera, a light sensor, a fingerprint sensor, and the like. In one embodiment, the display device 100 can be a UDC display device (under-display camera display device) or a UDIR display device (under-display IR display device), in which the sensor module SM is arranged below the display panel PNL. In a conventional display device, a recess is formed in the upper part of the display area AA, and an optical sensor, such as a camera or an infrared sensor, is then positioned in the recess. However, in this case, since the recess is formed by removing a section of the upper part of the display area AA, not only is the area of ​​the display area AA reduced, but this also presents the problem of aesthetically displeasing results. To solve these problems, a display device is proposed in which a hole is formed in the display area AA, and an optical sensor is then placed in the hole. However, since the hole is located in an area where no image is displayed, there is a problem in that the image is cut off or interrupted in the hole. Since the sensor module SM of the optical sensor is located under the display panel PNL in the display device 100, it is possible to prevent the display area AA from being reduced in size or the image from being cut off. The circuit board CB can be arranged on the back side of the display panel PNL. In one embodiment, the circuit board CB can comprise a printed circuit board (PCB) and / or a flexible printed circuit board (FPCB). The cover window CW can be positioned on the upper surface of the display panel PNL. The cover window CW covers the entire surface of the display panel PNL to protect it from external influences. In one embodiment, the cover window CW may, but is not limited to, a plastic material, a glass material, and / or a reinforced glass material. For example, the cover window CW may be made of sapphire glass or Gorilla Glass, or it may have a laminate structure of sapphire glass and Gorilla Glass. Alternatively or additionally, the cover window CW may, but is not limited to, polyethylene terephthalate (PET), polycarbonate (PC), polyethersulfone (PES), polyethylene naphthalate (PEN), polynorbornene (PNB), and combinations thereof. In another embodiment, the cover window CW may be made of reinforced glass, taking into account scratch resistance and / or transparency. Frame FRA houses the display panel PNL and supports the cover window CW. Frame FRA also houses the sensor module SM and the circuit board CB. Frame FRA enables the mounting of display panel PNL, sensor module SM, and circuit board CB to the display device 100 and protects these components from external influences. As shown in Fig. 5, a sensor area SA is defined or formed in the display panel PNL. The sensor area SA is aligned with the sensor module SM and transmits a stimulus, such as externally incident light, unchanged to the sensor module SM. In one embodiment, a plurality of sub-pixels, which display an image, are provided in the sensor area SA to transmit external light to the sensor module SM and simultaneously display an image on the display panel PNL. Fig. 6 shows a top view, which enlarges an area “A” in Fig. 5 to conceptually represent the display area AA and a sensor area SA. As shown in Fig. 6, the display area AA has several pixel areas PAs. Each pixel area PA has a pixel P with a plurality of sub-pixels SP1, SP2, and SP3. The sensor area SA can have a sensor display area SDA and a sensor transparency area STA. The sensor display area SDA is an area in which an image is displayed within the sensor area SA, and the sensor transparency area STA is an area through which the external stimulus, such as external light, is transmitted and input into the sensor module SM. The sensor display area SDA has a plurality of sensor sub-pixels SDSP1, SDSP2, and SDSP3, which together form a sensor display area pixel. The size of a sensor display area pixel can be larger than the size of a display area pixel. In one embodiment, the total area of ​​the sub-pixels SP1, SP2, and SP3 of the pixel area PA in the display area AA can be essentially equal to the entire light-emitting area in which light is actually emitted. Therefore, a plurality of sub-pixels SP1, SP2, and SP3 can constitute the actual light-emitting area within the display area AA. In contrast, a light emission area within the sensor area SA is not limited to the sensor display area SDA, but extends to a boundary region between the sensor display area SDA and the sensor transparency area STA, and optionally to a specific region of the sensor transparency area STA. Accordingly, the sensor sub-pixels SDSP1, SDSP2, and SDSP3 shown in Fig. 6 (one or more of which may even extend to the sensor transparency area STA) can constitute a light emission area corresponding to the sensor display area SDA. Subsequently, the sub-pixels SP1, SP2 and SP3 can be defined as the pixel area PA of the display area AA, and the sensor sub-pixels SDSP1, SDSP2 and SDSP3 can be defined as the light-emitting area in the sensor display area SDA of the sensor area SA. The multiple sub-pixels SP1, SP2, and SP3 within the pixel area PA can be, but are not limited to, a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, respectively. Alternatively or additionally, the multiple sub-pixels SP1, SP2, and SP3 can also include a white (W) sub-pixel. The multiple sensor sub-pixels SDSP1, SDSP2, and SDSP3 within the sensor display area SDA can be, but are not limited to, a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Alternatively or additionally, the multiple sensor sub-pixels SDSP1, SDSP2, and SDSP3 can also include a white (W) sub-pixel. Figure 6 shows, using an example of four grids in the upper left corner of the sensor area SA, one sensor display area SDA and three sensor transparency areas STAs as an example of the arrangement with respect to the number of sensor display area(s) SDA and sensor transparency area(s) STA in the entire sensor area SA, but the configuration of these areas is not limited to this. In another embodiment, the sensor area SA can have two or three sensor display areas SDAs and one or two sensor transparency areas STAs. If the sensor area SA has two sensor display areas SDAs and one sensor transparency area STA, a problem may occur in the detection of light by the sensor area SA. In one embodiment, the sensor area SA can have one sensor display area SDA and three sensor transparency areas STAs in the display device 100.In one embodiment, a sensor area SA has at least four sensor transparency areas STA. The sub-pixels SP1, SP2, and SP3 within the display area AA and / or the sensor sub-pixels SDSP1, SDSP2, and SDSP3 within the sensor display area SDA can have numerous shapes and / or configurations. For example, the first sub-pixel SP1 can have a diamond shape, each of the second and third sub-pixels SP2 and SP3 and the second and third sensor sub-pixels SDSP2 and SDSP3 can have a triangular shape, and the first sensor sub-pixel SDSP1 can have a hexagonal shape with long sides. However, the shapes of the sub-pixels SP1, SP2, and SP3 and the sensor sub-pixels SDSP1, SDSP2, and SDSP3 are not limited to these and can have numerous shapes. As described above, the sensor area SA comprises the sensor display area SDA, in which the image is displayed, and the sensor transparency area STA in the display device 100 with the UDC structure and / or the UDIR structure. Therefore, the image can be displayed and external light can be detected simultaneously within the sensor area SA. Accordingly, compared to the configuration where the sensor is located at the recess and / or the configuration where the hole is formed within the display area, it is possible to prevent the display area AA from being reduced in size or the image from being cut off. However, the following problems arise with the display device using the UDC structure or the UDIR structure. As described above, the image is displayed in sensor area SA to prevent the image from being cut off in the display device with the UDC or UDIR structure. However, it is necessary that the brightness in display area AA and the brightness of sensor area SA are kept nearly identical so that the user does not perceive the brightness differences in the individual areas, thus preventing the image from being cut off. Both the sensor display area SDA, where the image is displayed, and the sensor transparency area STA, which detects light, are located within sensor area SA in the display device with the UDC or UDIR structure. Therefore, the brightness of the sensor display area SDA within sensor area SA should be set higher than the brightness of the pixel area PA within display area AA, in order to match the brightness of sensor area SA, where only a very small area displays the image, with the brightness of display area AA, where most of the area is the image display area. Assuming the areas of the sensor display area SDA and the sensor transparency area STA are substantially equal, then if the sensor area SA has one sensor display area SDA and three sensor transparency areas STAs, the brightness of the sensor display area SDA within the sensor area SA should be four times the brightness of the pixel area PA within the display area AA. Alternatively, if the sensor area SA has three sensor display areas SDAs and one sensor transparency area STA, the brightness of the sensor display area SDA within the sensor area SA should be approximately 1.3 times the brightness of the pixel area PA within the display area AA. Therefore, the current supplied to the sensor display area SDA should be significantly increased (e.g., by supplying four times the current compared to the pixel area PA) to increase the brightness of the sensor display area SDA within the sensor area SA more than the brightness of the pixel area PA within the display area AA. In this case, the lifespan of the LED within the sensor area SA may be shortened due to the increased current. The present disclosure provides a structure that maximizes the sensor display area SDA within the sensor area SA in order to improve the brightness within the sensor area SA without decreasing the transmittance within the sensor transparency area STA. As shown in Fig. 6, if a central grid in sensor area SA in Fig. 6 is considered a sensor display area SDA in a relatively narrow definition, a first sensor sub-pixel SDSP1, four second sensor sub-pixels SDSP2, or third sensor sub-pixels SDSP3 are arranged within a sensor display area SDA (i.e., the second sensor sub-pixels SDSP2-2 and SDSP2-4, and the third sensor sub-pixels SDSP3-1 and SDSP3-2). The first sensor sub-pixel SDSP1 can be directly surrounded by a plurality of sensor transparency areas STA. For example, the first sensor sub-pixel SDSP1 can be directly adjacent to at least four sensor transparency areas STA. The second sensor sub-pixels SDSP2 and the third sensor sub-pixels SDSP3 can be directly adjacent to the first sensor sub-pixel SDSP1. Furthermore, as shown in Fig. 6, the light-emitting area within the sensor area SA is not limited to the sensor display area SDA in the narrow definition above, but can instead extend close to the sensor transparency area STA, thus including, for example, the second sensor sub-pixels SDSP2-1 and SDSP2-3 and / or the third sensor sub-pixels SDSP3-3 and SDSP3-4. In other words, in a more general definition, a first sensor sub-pixel SDSP1, four second sensor sub-pixels SDSP2, and a third sensor sub-pixel SDSP3 can be arranged within a sensor display area SDA. It should be noted that this general definition is merely exemplary and can be modified according to the pixel arrangement or layout.For example, if the four grids in the upper left area of ​​the sensor area SA are considered, these grids can also be seen as representing a sensor display area SDA of the general definition and three sensor transparency areas STA, with eight second and third sensor sub-pixels, each represented as a triangle, and one first sensor sub-pixel SDSP1 arranged in the wide sensor display area SDA. In one embodiment, each of the multiple second sensor sub-pixels SDSP2-1, SDSP2-2, SDSP2-3, and SDSP2-4 can be arranged outside the first sensor sub-pixel SDSP1. Each of the multiple third sensor sub-pixels SDSP3-1, SDSP3-2, SDSP3-3, and SDSP3-4 can be arranged outside the first sensor sub-pixel SDSP1. Comparing the sub-pixels SP1, SP2, and SP3 within the display area AA with the sensor sub-pixels SDSP1, SDSP2, and SDSP3 within the sensor area SA, the first sensor sub-pixel SDSP1 has an area larger than the area of ​​the first sub-pixel SP1. However, each of the second and third sensor sub-pixels SDSP2 and SDSP3 can have an area that is essentially equal to the area of ​​the second and third sub-pixels SP2 and SP3, respectively. While only one second sub-pixel SP2 and one third sub-pixel SP3 are arranged in a pixel area PA within the display area AA, four second sensor sub-pixels SDSP2 or third sensor sub-pixels SDSP3 (i.e., the sum of the number of second sub-pixels and the third sub-pixel is four) are arranged in a narrowly defined sensor display area SDA of the sensor area SA, and four second sensor sub-pixels SDSP2 and four third sensor sub-pixels SDSP3 (i.e.,The sum of the number of second sub-pixels and third sub-pixels is eight) are arranged in a generally defined sensor display area SDA of the sensor area SA. Accordingly, each of the areas of the second and third sensor sub-pixels SDSP2 and SDSP3 within a generally defined sensor display area SDA of the sensor area SA is approximately four times the size of each of the areas of the second and third sub-pixels SP2 and SP3 of a pixel area PA whose area is equal to the sensor display area SDA within the display area AA. The amount of light emitted by the sensor sub-pixels SDSP1, SDSP2, and SDSP3 can be increased. Therefore, it is possible to significantly increase the brightness provided by the sensor sub-pixels SDSP1, SDSP2, and SDSP3 without increasing the current. In one embodiment, the sensor sub-pixels SDSP1, SDSP2, and SDSP3 can be arranged within the sensor display area SDA and the sensor area SA. In another embodiment, at least one of the sensor sub-pixels SDSP1, SDSP2, or SDSP3 can extend to the boundary between the sensor display area SDA and the sensor transparency area STA. In yet another embodiment, at least one of the sensor sub-pixels SDSP1, SDSP2, and SDSP3 can extend to a specific region of the sensor transparency area STA. In Fig. 6, four second sensor sub-pixels SDSP2 and four third sensor sub-pixels SDSP3 are arranged in a (generally defined) sensor display area SDA. In another embodiment, two or three second sensor sub-pixels SDSP2 and / or two or three third sensor sub-pixels SDSP3 are arranged in a (generally defined) sensor display area SDA. In another embodiment, five or more second sensor sub-pixels SDSP2 and / or five or more third sensor sub-pixels SDSP3 are arranged in a (generally defined) sensor display area SDA. In yet another embodiment, different numbers of second sensor sub-pixels SDSP2 and third sensor sub-pixels SDSP3 are arranged in a sensor display area SDA. In one embodiment, each of the first to third sub-pixels SP1, SP2, and SP3 in pixel area PA and each of the first to third sensor sub-pixels SDSP1, SDSP2, and SDSP3 in sensor display area SDA can emit their respective colored light. In another embodiment, each of the first to third sub-pixels SP1, SP2, and SP3 in pixel area PA and each of the first to third sensor sub-pixels SDSP1, SDSP2, and SDSP3 in sensor display area SDA can emit different colored light. For example, the first to third sub-pixels SP1, SP2, and SP3 can emit red light, green light, and blue light, respectively, and the first to third sensor sub-pixels SDSP1, SDSP2, and SDSP3 can emit red light, green light, and blue light, respectively. Alternatively, the first to third sub-pixels SP1, SP2, and SP3 can emit red light, green light, and blue light, respectively.The first three sensor sub-pixels (SDSP1, SDSP2, and SDSP3) emit blue light, while the third three can emit blue, green, and red light, respectively. It is possible to configure the first three sensor sub-pixels (SDSP1, SDSP2, and SDSP3) differently depending on their surface area and other characteristics. Fig. 7 shows a schematic top view of the sensor sub-pixels of the display device according to an embodiment of the present disclosure. As shown in Fig. 7, a plurality of sensor sub-pixels SDSP1, SDSP2, and SDSP3 are arranged within the sensor display area SDA and the sensor area SA. For example, the first sensor sub-pixel SDSP1 is located in the central area of ​​the sensor display area SDA, and each of the plurality of second sensor sub-pixels SDSP2 and the plurality of third sensor sub-pixels SDSP3 is arranged around the first sensor sub-pixel SDSP1. In one embodiment, the first sensor sub-pixel SDSP1 is arranged longitudinally along a vertical direction in the central region of the sensor area SA, such that part of the upper and lower sections of the first sensor sub-pixel SDSP1 can extend to the boundary between the sensor display area SDA and the sensor transparency area STA, or to a part of the sensor transparency area STA. Alternatively, the first sensor sub-pixel SDSP1 can be formed or arranged within the sensor display area SDA. In one embodiment, each of the second sensor sub-pixel SDSP2 and the third sensor sub-pixel SDSP3 can extend to the boundary of the sensor transparency area STA, which borders the sensor display area SDA, or to a part of the sensor transparency area STA. The second sensor sub-pixel SDSP2 can, without limitation, have four sensor sub-pixels SDSP2-1, SDSP2-2, SDSP2-3 and SDSP2-4, and the third sensor sub-pixel SDSP3 can, without limitation, have four sensor sub-pixels SDSP3-1, SDSP3-2, SDSP3-3 and SDSP3-4. The sensor display area SDA can be defined by a plurality of gate lines and data lines arranged vertically and horizontally. Each of the gate lines and data lines can be electrically connected to each of the first to third sensor sub-pixels SDSP1, SDSP2, and SDSP3. The sensor transparency area STA is an area through which light is transmitted and introduced into the sensor module SM (Fig. 4). The transparency of the sensor transparency area STA must be maximized to improve the sensing efficiency of the sensor module SM. Accordingly, the gate line and the data line can be located on the outside of the sensor transparency area STA. Additionally, to simplify the design, the gate line and the data line located in the sensor display area SDA can also be arranged in the same way as the sensor transparency area STA, but are not limited to this. As shown in Fig. 7, a first thin-film transistor T1 is electrically connected to the first sensor sub-pixel SDSP1, allowing external signals to be applied to the first sensor sub-pixel SDSP1 via the first thin-film transistor T1. Furthermore, a second thin-film transistor T2 is electrically connected to the second sensor sub-pixel SDSP2, allowing external signals to be applied to the second sensor sub-pixel SDSP2 via the second thin-film transistor T2. Additionally, a third thin-film transistor T3 is electrically connected to the third sensor sub-pixel SDSP3, allowing external signals to be applied to the third sensor sub-pixel SDSP3 via the third thin-film transistor T3. The multiple second sensor sub-pixels SDSP2-1, SDSP2-2, SDSP2-3, and SDSP2-4 share the second thin-film transistor T2, allowing external signals to be applied simultaneously to these sub-pixels via the second thin-film transistor T2. These external signals can also be applied simultaneously to the sub-pixels via a first connecting electrode 128a, which is electrically connected to them. An identical signal is applied to the multiple second sensor sub-pixels SDSP2-1, SDSP2-2, SDSP2-3 and SDSP2-4, which are arranged in a sensor display area SDA, with the same image being displayed in each. The multiple third sensor sub-pixels SDSP3-1, SDSP3-2, SDSP3-3, and SDSP3-4 share the third thin-film transistor T3, allowing external signals to be applied simultaneously to these sub-pixels via the same transistor. These external signals can also be applied simultaneously to the sub-pixels via a second connecting electrode 128b, which is electrically connected to them. An identical signal is applied to the multiple third sensor sub-pixels SDSP3-1, SDSP3-2, SDSP3-3 and SDSP3-4, which are arranged in a sensor display area SDA, with the same image being displayed in each. Thus, several second sensor sub-pixels SDSP2 and several third sensor sub-pixels SDSP3 are arranged in a sensor display area SDA in the display device 100. The brightness of the sensor display area SDA can be improved by increasing the emission area. Since the multiple sensor sub-pixels SDSP2 and SDSP3 share a thin-film transistor T2 or T3, it is possible to minimize the area occupied by the thin-film transistor and reduce manufacturing costs. Fig. 8A shows a cross-sectional view along line II' in Fig. 7. Fig. 8B shows a cross-sectional view along line II-II' in Fig. 7. Fig. 8A is a cross-sectional view of the first sensor sub-pixel SDSP1, and Fig. 8B is a cross-sectional view of the second sensor sub-pixel SDSP2. For simplicity, Fig. 8B shows only two second sensor sub-pixels, SDSP2-1 and SDSP2-2, instead of four second sensor sub-pixels SDSP2. Since the structure of the third sensor sub-pixel SDSP3 is identical to that of the second sensor sub-pixel SDSP2, the description of the structure of the third sensor sub-pixel SDSP3 is replaced by the explanation of the structure of the second sensor sub-pixel SDSP2. As shown in Figs. 8A and 8B, a first buffer layer 142 is arranged on an entire substrate 140, which has the first sensor sub-pixel SDSP1 and the second sensor sub-pixels SDSP2-1 and SDSP2-2. The substrate 140 can be made of a hard material such as glass and / or a flexible plastic material. If the substrate 140 is formed from plastic material, the substrate 140 may, but is not limited to, polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone (PS), polycarbonate (PC). For example, if substrate 140 contains polyimide, the substrate may have multiple layers, each containing polyimide, and an inorganic layer may be placed between these polyimide substrates, but is not limited to this. A first buffer layer 142 is arranged across the entire substrate 140. This first buffer layer 142 can improve the adhesive forces between the substrate 140 and the layers arranged on the substrate 140 and play a role in blocking alkaline components leaching from the substrate 140. Furthermore, the first buffer layer 142 can delay the diffusion of moisture and / or oxygen that have penetrated the substrate 140. In one embodiment, the first buffer layer 142 can have a single-layer or multi-layer structure made of inorganic material such as SiNx or SiOx (where 0 < x ≤ 2). In another embodiment, the first buffer layer 142 has a multi-layer structure in which a layer of SiOx and a layer of SiNx are arranged alternately. In some embodiments, the first buffer layer 142 can be omitted, taking into account the types and materials of the substrate 140 and the structure and types of the thin-film transistor. A first thin-film transistor T1 in the first sensor sub-pixel SDSP1 and a second thin-film transistor T2 in the second sensor sub-pixel SDSP2 are each arranged on the first buffer layer. For the sake of simplicity, only one driver thin-film transistor is shown on the first buffer layer 142 in Figures 8A and 8B, among numerous thin-film transistors that may be arranged in the display area AA and / or the sensor area SA. However, other thin-film transistors, such as a switching thin-film transistor, may also be arranged on the first buffer layer 142. While the first and second thin-film transistors T1 and T2 are shown with a gate-up structure in Figures 8A and 8B, they may also have a different structure, such as a gate-down structure. While the second thin-film transistor T2 is formed in the first second sensor sub-pixel SDSP2-1, the second thin-film transistor T2 is shared by the first second sensor sub-pixel SDSP2-1 and the second second sensor sub-pixel SDSP2-2. In Fig. 8B, the second thin-film transistor T2 is located in the first second sensor sub-pixel SDSP2-1, but the second thin-film transistor T2 can alternatively also be located in the second second sensor sub-pixel SDSP2-2. Furthermore, the second thin-film transistor T2 can be located in the third second sensor sub-pixel SDSP2-3 and in the fourth second sensor sub-pixel SDSP2-4. The first thin-film transistor T1 can have a first semiconductor layer 112 arranged on the first buffer layer 142, a gate insulating layer 144 arranged on the first semiconductor layer 112, a first gate electrode 114 arranged on the gate insulating layer 144, a first intermediate insulating layer 146 arranged on the first gate electrode 114, and a first source electrode 115 and a first drain electrode 116 arranged on the first intermediate insulating layer 146. The second thin-film transistor T2 can have a second semiconductor layer 122 arranged on the first buffer layer 142, a gate insulating layer 144 arranged on the second semiconductor layer 122, a second gate electrode 124 arranged on the gate insulating layer 144, a first intermediate insulating layer 146 arranged on the second gate electrode 124, and a second source electrode 125 and a second drain electrode 126 arranged on the first intermediate insulating layer 146. In one embodiment, both the first semiconductor layer 112 and the second semiconductor layer 122 can comprise a polycrystalline semiconductor. The polycrystalline semiconductor can, but is not limited to, comprise, for example, high-mobility low-temperature polysilicon (LTPS). In a further embodiment, both the first semiconductor layer 112 and the second semiconductor layer 122 can comprise an oxide semiconductor. For example, both the first and the second semiconductor layers 112 and 122 can, independently of one another and without limitation, comprise indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and / or indium gallium oxide (IGO). The first semiconductor layer 112 can have a first channel region 112a of the central region and a first source region 112b and a first drain region 112c of doping layers on both sides. The second semiconductor layer 122 can have a second channel region 122a of the central region and a second source region 122b and a second drain region 122c of doping layers on both sides. In one embodiment, the first semiconductor layer 112 can be made of the same material as the second semiconductor layer 122. In another embodiment, the first semiconductor layer 112 can be made of a different material than the second semiconductor layer 122. The gate insulating layer 144 can, but is not limited to, comprise inorganic material such as SiOx and SiNx (where 0 < x ≤ 2). The gate insulating layer 144 can have a single-layer or a multi-layer structure. Both the first gate electrode 114 and the second gate electrode 124 can contain metal. For example, both the first gate electrode 114 and the second gate electrode 124 can independently contain, but are not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof, and / or alloys thereof. Each of the first gate electrode 114 and the second gate electrode 124 can have a single-layer or multi-layer structure. The first intermediate insulating layer 146 can comprise organic material, such as photoacrylic, or inorganic material, such as SiNx and / or SiOx (where 0 < x ≤ 2). The first intermediate insulating layer 146 can have a single-layer or a multi-layer structure. In a further embodiment, the first intermediate insulating layer 146 can have a multi-layer structure consisting of an organic layer and an inorganic layer, but is not limited to this. Each of the first source electrode 115, the first drain electrode 116, the second source electrode 125, and the second drain electrode 126 can independently contain, but is not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof, and / or alloys thereof. Each of the first source electrode 115, the first drain electrode 116, the second source electrode 125, and the second drain electrode 126 can have a single-layer or a multi-layer structure. The first source electrode 115 and the first drain electrode 116 can be in contact with the first source region 112b and the first drain region 112c, respectively, of the first semiconductor layer 112 via through-holes formed in the gate insulating layer 144 and the first intermediate insulating layer 146. The second source electrode 125 and the second drain electrode 126 can be in contact with the second source region 122b and the second drain region 122c, respectively, of the second semiconductor layer 122 via through-holes formed in the gate insulating layer 144 and the first insulating layer 146. In one embodiment, a lower shielding metal layer is arranged between the substrate 140 and the first semiconductor layer 112 and the second semiconductor layer 122. The lower shielding metal layer minimizes the backchannel phenomenon caused by charges trapped in the substrate 140 and prevents afterimages or degradation of transistor performance. The lower shielding metal layer can, for example, comprise titanium (Ti), molybdenum (Mo), combinations thereof, and / or alloys thereof, but is not limited to these materials. The lower shielding metal layer can have a single-layer or a multi-layer structure. A passivation layer 148 is arranged on the substrate 140, above which the first thin-film transistor T1 and the second thin-film transistor T2 are arranged. In one embodiment, the passivation layer 148 can comprise, among other things, an organic material, such as photoacrylic. In another embodiment, the passivation layer 148 can comprise several layers, which include an inorganic layer and / or an organic layer. A first light-emitting diode D1 is arranged on the passivation layer 148 in the first sensor sub-pixel SDSP1, a second light-emitting diode D2-1 is arranged on the passivation layer 148 in the first second sensor sub-pixel SDSP2-1, and a further second light-emitting diode D2-2 is arranged on the passivation layer 148 in the second second sensor sub-pixel SDSP2-2. The first LED D1 can have a first anode electrode 132, a first emissive layer 134, and a first cathode electrode 136. The second LED D2-1 can have a second anode electrode 151, a second emissive layer 152, and a second cathode electrode 153. The further second LED D2-2 can have a second anode electrode 155, a second emissive layer 156, and a second cathode electrode 157. Since in some embodiments each sensor display area pixel has only a single first LED D1, each sensor sub-pixel can have only a single emissive layer. The first anode electrode 132 of the first light-emitting diode D1 is arranged on the passivation layer 148 and can be electrically connected to the first drain electrode 116 of the first thin-film transistor T1 via a contact hole formed in the passivation layer 148. The second anode electrode 151 of the second light-emitting diode D2-1 can be electrically connected to the second drain electrode 126 of the second thin-film transistor T2. The connecting electrode 128 is arranged on the first intermediate insulating layer 146. Alternatively or additionally, the connecting electrode 128 can be arranged on the passivation layer 148. In this case, the connecting electrode 128 can be arranged using the same process and / or the same materials as the second anode electrode 151, but is not limited to this. The connecting electrode 128 extends from the first second sensor sub-pixel SDSP2-1 to the second second sensor sub-pixel SDSP2-2, so that the thin-film transistor T2, which is arranged in the first second sensor sub-pixel SDSP2-1, can be connected to the second light-emitting diode D2-2, which is arranged in the second second sensor sub-pixel SDSP2-2. In one embodiment, the connecting electrode 128 can be formed integrally with the second drain electrode 126 of the second thin-film transistor T2, but is not limited to this. The second anode electrode 155 of the second LED D2-2 is electrically connected to the second drain electrode 126 of the second thin-film transistor T2 via the through holes formed in the passivation layer 148 and the connecting electrode 128 arranged on the passivation layer 148. In other words, both the second anode electrode 151 of the second LED D2-1 and the second anode electrode 155 of the second LED D2-2 are electrically connected to the second drain electrode 126 of the second thin-film transistor T2, so that the second LED D2-1 and the second LED D2-2 can be controlled simultaneously. Furthermore, the above description applies to the second sensor sub-pixel with the second LEDs (D2-1 and D2-2, which can be collectively referred to as D2) with respect to Fig.8B similarly for the third sensor sub-pixel, which has the third LED, although this is not shown in the figure. Although not shown in the figure, a third light-emitting diode (LED) of the third sensor sub-pixel is arranged on the passivation layer 148 within the third sensor sub-pixel. The third LED may have a third anode electrode, a third emission layer, and a third cathode electrode. In one embodiment, each of the first anode electrode 132, the second anode electrode 151 or 155, and the third anode electrode (not shown in the drawings) may be independent of each other. The materials used include, but are not limited to, silver (Ag), aluminum (Al), gold (Au), tungsten (W), chromium (Cr), combinations thereof, and / or alloys thereof. In another embodiment, each of the first anode electrode 132, the second anode electrode 151 or 155 and the third anode electrode can independently have, but is not limited to, a metal oxide material layer, such as indium tin oxide (ITO), indium zinc oxide (IZO) and the like. If the display device 100 is a top-emission type display device, each of the first anode electrode 132, the second anode electrode 151 or 155, and the third anode electrode can independently have an opaque conductive material to act as a reflective electrode for reflecting light. Alternatively, if the display device 100 is a bottom-emission type display device, each of the first anode electrode 132, the second anode electrode 151 or 155, and the third anode electrode can be independently arranged by means of a transparent conductive material that transmits light, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like. A wall layer BNK is located at the boundary between the sub-pixels and sensor sub-pixels on the passivation layer 148. The wall layer BNK can act as a partition, defining each sub-pixel and sensor sub-pixel. The wall layer BNK can divide each sub-pixel and sensor sub-pixel to prevent light of a specific color emitted by neighboring sub-pixels from mixing and being emitted. In one embodiment, the wall layer BNK is arranged at the boundary between the first second sensor sub-pixel SDSP2-1 and the second second sensor sub-pixel SDSP2-2, as shown in Fig. 8B. In another embodiment, no wall layer needs to be arranged at the boundary between the first second sensor sub-pixel SDSP2-1 and the second second sensor sub-pixel SDSP2-2 if the first second sensor sub-pixel SDSP2-1 and the second second sub-pixel SDSP2-2 emit light of the same color. The wall layer BNK may contain, but is not limited to, an inorganic insulating material such as SiNx and / or SiOx (where 0 < x ≤ 2), an organic insulating material such as benzocyclobutene (BCB), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin and combinations thereof, as well as a photosensitive material such as black pigment and / or dye. The first emission layer 134 is arranged on the first anode electrode 132, which is exposed by the wall layer BNK, on ​​an inclined surface of the wall layer BNK, and on at least a section of an upper surface of the wall layer BNK. Similarly, the second emission layer 152 is arranged on the second anode electrode 151, which is exposed by the wall layer BNK, on ​​an inclined surface of the wall layer BNK, and on at least a section of an upper surface of the wall layer BNK. The second emission layer 156 is arranged on the second anode electrode 155, on an inclined surface of the wall layer BNK, and on at least a section of an upper surface of the wall layer BNK. In one embodiment, the second emission layer 152, located in the first second sensor sub-pixel SDSP2-1, is arranged at a distance from the second emission layer 156, located in the second second sensor sub-pixel SDSP2-2, as shown in Fig. 8B. In another embodiment, the second emission layer 152, located in the first second sensor sub-pixel SDSP2-1, can be integral with the second emission layer 156, located in the second second sensor sub-pixel SDSP2-2, or formed as a single unit. Furthermore, the above description for the second emission layers 152 and 156 of the second sensor sub-pixel with reference to Fig. 8B also applies similarly to the third emission layers of the third sensor sub-pixel, although these are not shown in the drawings. In one embodiment, each of the first emission layer 134, the second emission layer 152 or 156, and the third emission layer (not shown in the drawings) can independently comprise a red (R) emission layer emitting red light and located in the red sub-pixel, a green (G) emission layer emitting green light and located in the green sub-pixel, and a blue (B) emission layer emitting blue light and located in the blue sub-pixel. For example, each of the first emission layer 134, the second emission layer 152 or 156, and the third emission layer can independently comprise, but is not limited to, an organic emission layer, an inorganic emission layer, a nanoscale emission layer, a quantum dot emission layer, a micro-LED emission layer, and / or a mini-LED emission layer. In one embodiment, each of the first emission layer 134, the second emission layer 152 or 156, and the third emission layer can independently comprise an emission material layer. In another embodiment, each of the first emission layer 134, the second emission layer 152 or 156, and the third emission layer can independently comprise, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a hole-blocking layer, an electron transport layer, and / or an electron injection layer. The first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode (not shown in the drawings) can each be arranged on the first emission layer 134, the second emission layer 152 or 156, and the third emission layer (not shown in the drawings), respectively, and can have a single-layer or multi-layer structure comprising metal and / or a metal alloy. Alternatively, each of the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can independently comprise, but is not limited to, a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like. In one embodiment, the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can be integrally formed as a single unit, but are not limited to this. In another embodiment, the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can be spaced apart from each other between the sensor sub-pixels SDSP1, SDSP2, and SDSP3. This means that each cathode electrode 136, 153, 157 can be spaced apart from each other in the sensor display area SDA. In yet another embodiment, the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can be spaced apart from each other on the wall layer BNK (Fig. 8B). In one embodiment, where the display device 100 is a top-emission type display device, each of the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can be arranged independently of one another using a semi-transparent, conductive material that transmits light. For example, each of the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can, but is not limited to, a metal alloy such as LiF / Al, CsF:Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, LiF / Ca:Ag, and combinations thereof. In a further embodiment, if the display device 100 is a bottom-emission display device, each of the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can be arranged independently of one another using an opaque conductive material as a reflective electrode that reflects light. For example, each of the first cathode electrode 136, the second cathode electrode 153 or 157, and the third cathode electrode can, but is not limited to, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), combinations thereof, and / or alloys thereof. Furthermore, the first LED D1, second LED D2, and third LED can independently possess a tandem structure. The tandem structure comprises multiple light-emitting components and at least one charge-generating layer located between the light-emitting components. Each of the light-emitting components can have an emissive layer. The charge-generating layer balances the charge levels between the multiple light-emitting parts and can consist of multiple layers, including a first charge-generating layer and a second charge-generating layer. For example, the charge-generating layer can include an N-type charge-generating layer and a P-type charge-generating layer, and may or may not be limited to a layer doped with an alkali metal, such as Li, Na, K and / or Cs, or an alkaline earth metal, such as Mg, Sr, Ba and / or Ra. An encapsulation layer 160 is arranged on the first LED D1, the second LED D2, and / or the third LED (not shown in the drawings), such that the first LED D1, the second LED D2, and the third LED can be encapsulated by the encapsulation layer 160. If the first LED D1, the second LED D2, and the third LED are exposed to moisture or oxygen, a pixel shrinkage phenomenon can occur, in which the light-emitting area is reduced, or a defect can occur, in which a dark spot forms within the light-emitting area. Furthermore, moisture or oxygen oxidizes the electrode, which is made of a metal component.The encapsulation layer 160 blocks the ingress of moisture and / or oxygen from the outside, thus preventing defects in the first light-emitting diode D1, the second light-emitting diode D2, the third light-emitting diode and / or numerous electrodes. In one embodiment, the encapsulation layer 160 can comprise a first encapsulation layer 162, a second encapsulation layer 164, and a third encapsulation layer 166. In another embodiment, the encapsulation layer 160 can consist of two layers or of four or more layers. Each of the first encapsulation layer 162 and the third encapsulation layer 166 can comprise a single layer of an inorganic material, such as SiOx, SiON, and / or SiNx (where 0 < x ≤ 2), or multiple layers comprising the inorganic material, but is not limited to this. In a further embodiment, each of the first encapsulation layer 162 and the third encapsulation layer 166 can also comprise, but is not limited to, at least one organic layer arranged between the inorganic layers of SiOx, SiON, and / or SiNx (where 0 < x ≤ 2). The second encapsulation layer 164 can comprise an organic material, such as an epoxy resin. A second buffer layer 171 is arranged on the encapsulation layer 160, and a light-shielding layer BM is arranged on the second buffer layer 171. The light-shielding layer BM corresponds to a contact electrode 184. In further embodiments, the light-shielding layer BM can be arranged on a layer above the second buffer layer 171. The light-shielding layer BM can overlap a contact electrode 184. The second buffer layer 171 can, but is not limited to, an inorganic material such as SiNx and / or SiOx (where 0 < x ≤ 2). The second buffer layer 171 can have a single-layer or a multi-layer structure. The light-shielding layer BM absorbs light. More precisely, the light-shielding layer BM blocks or absorbs the light emission to the adjacent sensor display area SDA and the sensor transparency area STA to prevent color mixing.The light shielding layer BM can, among other things, contain a metal-containing material, such as Cr and / or CrOx (where 0 < x ≤ 2). A second intermediate insulating layer 171 is arranged on the second buffer layer 172, where the light-shielding layer BM is located. A touch element TOUCH is arranged on the second intermediate insulating layer 172. The touch element TOUCH is positioned within the display area AA to detect touch input. In one embodiment, the touch element TOUCH can detect external touch information from the user's finger and / or stylus. The second intermediate insulating layer 172 prevents chemical solutions, such as a developer and / or an etchant used in the formation of the TOUCH touch element, and / or external moisture or oxygen from penetrating the first to third light-emitting diodes. Furthermore, the second intermediate insulating layer 172 prevents multiple touch electrodes 184, arranged on the second intermediate insulating layer 172, from being short-circuited by external influences and blocks interference signals that may occur when the TOUCH touch element is in operation. In one embodiment, the second intermediate insulating layer 172 can comprise, but is not limited to, an organic material, such as photoacrylic, or an inorganic material, such as SiNx and / or SiOx (where 0 < x ≤ 2). The second intermediate insulating layer 172 can have a single-layer or a multi-layer structure. In another embodiment, the second intermediate insulating layer 172 can comprise, but is not limited to, several layers consisting of an organic layer and an inorganic layer. The TOUCH touch element can have a touch connection electrode 182, which is arranged on the second intermediate insulating layer 172, a first passivation layer 174, which is arranged on the touch connection electrode 182, a plurality of touch electrodes 184, which are arranged on the first passivation layer 174, and a second passivation layer 176, which is arranged on the touch electrode 184. The contact electrode 184 is electrically connected to the contact connection electrode 182 via a contact hole formed in the first passivation layer 174. The multiple contact electrodes 184 are arranged on the first passivation layer 174, and the contact connection electrode 182 electrically connects the adjacent multiple contact electrodes 184 to each other. In one embodiment, each of the contact connection electrode 182 and the contact electrode 184 can independently comprise, but is not limited to, a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), and the like. In another embodiment, each of the contact connection electrode 182 and the contact electrode 184 can independently comprise, but is not limited to, a metal component, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof, and / or alloys thereof. Each of the contact connection electrode 182 and the contact electrode 184 can have a single-layer or a multi-layer structure. In one embodiment, the second passivation layer 176 can comprise an organic material, such as photoacrylic, but is not limited to this. In another embodiment, the second passivation layer 176 can comprise several layers, each consisting of an inorganic layer and an organic layer. As described above, the display device 100 has a plurality of sensor sub-pixels SDSP1, SDSP2, and SDSP3 within a sensor display area SDA, so that the brightness of the sensor display area SDA can be increased with increasing light-emitting area. Furthermore, since the multiple sensor sub-pixels SDSP2-1 and SDSP2-2 share a thin-film transistor T2, it is possible to minimize the area occupied by the thin-film transistor T2 and thus reduce manufacturing costs.

Claims

A display device (100) comprising: a display panel (109, PNL) with a display area (AA) and a sensor area (SA) within the display area (AA), wherein the sensor area (SA) comprises a sensor display area (SDA) for displaying an image and a sensor transparency area (STA) for transmitting light; a sensor module (SM) arranged on a lower surface of the display panel (109, PNL) and aligned with the sensor area (SA); and a sensor display area pixel comprising a first sensor sub-pixel (SDSP1), a plurality of second sensor sub-pixels (SDSP2), and a plurality of third sensor sub-pixels (SDSP3) arranged within the sensor display area, wherein the first sensor sub-pixel (SDSP1) is configured to display a first color, the plurality of second sensor sub-pixels (SDSP2) are configured to display a second color, and the plurality of third Sensor sub-pixels (SDSP3) are set up for this purpose,to display a third color, wherein the majority of second sensor sub-pixels (SDSP2) and the majority of third sensor sub-pixels (SDSP3) are arranged around the first sensor sub-pixel (SDSP1). The display device (100) according to claim 1, wherein the first sensor sub-pixel (SDSP1), the second sensor sub-pixel (SDSP2) and the third sensor sub-pixel (SDSP3) are configured to display red, green and blue respectively. The display device (100) according to claim 1 or 2, wherein the first sensor sub-pixel (SDSP1) is arranged in a central area of ​​the sensor display area (SDA). The display device (100) according to one of the preceding claims, wherein the display device (100) further comprises: a first thin-film transistor (T1) arranged in the first sensor sub-pixel (SDSP1), a second thin-film transistor (T2) arranged in the plurality of second sensor sub-pixels (SDSP2), a third thin-film transistor (T3) arranged in the plurality of third sensor sub-pixels (SDSP3), a first light-emitting diode (D1) arranged in the first sensor sub-pixel (SDSP1), a second light-emitting diode (D2-1, D2-2) arranged in each of the plurality of second sensor sub-pixels (SDSP2), and a third light-emitting diode arranged in each of the plurality of third sensor sub-pixels (SDSP3). The display device (100) according to claim 4, wherein the plurality of second sensor sub-pixels (SDSP2) comprises: a first second sensor sub-pixel (SDSP2-1), and a second second sensor sub-pixel (SDSP2-2), and wherein the plurality of third sensor sub-pixels (SDSP3) comprises: a first third sensor sub-pixel (SDSP3-1), and a second third sub-pixel (SDSP3-2). The display device (100) according to claim 5, wherein the display device (100) further comprises: a first connecting electrode (128a) which is electrically connected to the first second sensor sub-pixel (SDSP2-1) and the second second sensor sub-pixel (SDSP2-12), and a second connecting electrode (128b) which is electrically connected to the first third sensor sub-pixel (SDSP3-1) and the second third sensor sub-pixel (SDSP3-2). The display device (100) according to claim 6, wherein each of the first thin-film transistor (T1), the second thin-film transistor (T2) and the third thin-film transistor (T3) comprises: a semiconductor layer (112, 122), a gate insulating layer (144) arranged on the semiconductor layer (112, 122), a gate electrode (114, 124) arranged on the gate insulating layer (144), an intermediate insulating layer (146) arranged on the gate electrode (114, 124), and a source electrode (115, 125) and a drain electrode (116, 126) arranged on the intermediate insulating layer (146). The display device according to claim 7, wherein the first connecting electrode (128a) and the second connecting electrode (128b) are arranged on the intermediate insulating layer (146). The display device (100) according to claim 7 or 8, wherein the first light-emitting diode (D1), every second light-emitting diode (D2-1, D2-2) and every third light-emitting diode comprises: an anode electrode (132, 151, 155) which is electrically connected to the source electrode (115, 125) or the drain electrode (116, 126), a cathode electrode (136, 153, 157) which is opposite the anode electrode (132, 151, 155), and an emission layer (134, 152, 156) which is spaced apart between the anode electrode (132, 151, 155) and the cathode electrode (136, 153, 157). The display device (100) according to claim 9, wherein each cathode electrode (136, 153, 157) is arranged at a distance from each other cathode electrode (136, 153, 157) in the sensor display area (SDA). The display device (100) according to claim 9 or 10, wherein the cathode electrode (153, 157) is arranged in the plurality of second sensor sub-pixels (SDSP2) between the first second sensor sub-pixel (SDSP2-1) and the second second sensor sub-pixel (SDSP2-2). The display device (100) according to claim 9, 10 or 11, wherein the display device (100) further comprises: an encapsulation layer (160) arranged on the cathode electrode (136, 153, 157), and a touch element (TOUCH) arranged on the encapsulation layer (160). The display device (100) according to claim 12, wherein the touch element (TOUCH) comprises: a touch insulating layer, and a touch electrode (184) arranged on the touch insulating layer, and wherein the touch electrode (184) is arranged between the first second sensor sub-pixel (SDSP2-1) and the second second sensor sub-pixel (SDSP2-2). The display device (100) according to claim 13, wherein the display device (100) further comprises a light shielding layer (BM) which is arranged on the encapsulation layer (160) corresponding to the contact electrode (184). The display device (100) according to one of claims 9 to 14, wherein the first sensor sub-pixel (SDSP1) has only a single emission layer. The display device (100) according to one of the preceding claims, wherein the first sensor sub-pixel (SDSP1) is directly surrounded by a plurality of sensor transparency areas (STA). The display device (100) according to claim 16, wherein the first sensor sub-pixel (SDSP1) is directly adjacent to at least four sensor transparency areas (STA). The display device (100) according to one of the preceding claims, wherein the second sensor sub-pixels (SDSP2) and the third sensor sub-pixels (SDSP3) are directly adjacent to the first sensor sub-pixel (SDSP1). The display device (100) according to one of the preceding claims, wherein the size of a sensor display area pixel is larger than the size of a display area pixel. The display device (100) according to claim 19, wherein a sensor area (SA) has at least four sensor transparency areas (STA).

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