JITTER ATTENTION CRYSTALLESS TRANSCEIVER

Abstract

A system comprises a crystal oscillator, a central switch transceiver coupled to the crystal oscillator, and a sensor transceiver. The central switch transceiver includes a transmitter circuit to take a time reference from the crystal oscillator to generate a self-clocking signal carrying initial data, and a clock and data recovery loop circuit to operate with a first bandwidth for sampling second data received from the sensor transceiver. The sensor transceiver includes a reference clock recovery circuit to decode a reference clock from the self-clocking signal. A phase-locked loop (PLL) circuit generates a transmit clock from the reference clock, operating with a second bandwidth for use in generating the second data.The first bandwidth is greater than or equal to a second bandwidth of the PLL circuit to reduce jitter experienced by the clock and data recovery loop circuit due to jitter in the transmit clock.