Pulse signal output circuit and shift register

Abstract

A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is directly connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is directly connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is directly connected to a first power supply line (31), the other of the source and drain of the second transistor (104) being directly connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is directly connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is directly connected to a second power supply line (32), wherein a gate of the third transistor (108) is directly connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is directly connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is directly connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is directly connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is directly connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is directly connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is directly connected to the first power supply line (31), the other of the source and drain of the seventh transistor being directly connected to the second wiring, wherein one of a source and a drain of the eighth transistor is directly connected to a gate of the seventh transistor, the other of the source and drain of the eighth transistor being directly connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is directly connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is directly connected to the first power supply line (31), wherein a gate of the tenth transistor is directly connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, and wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor.

Description

TECHNICAL FIELD

[0001] The disclosed invention relates to a pulse signal output circuit and a shift register. STATE OF THE ART

[0002] Transistors formed over flat screens such as glass substrates, typically used in liquid crystal display devices, generally contain semiconductor materials such as amorphous silicon or polycrystalline silicon. Although transistors containing amorphous silicon have low field-effect mobility, they can be formed over larger glass substrates. In contrast, although transistors containing polycrystalline silicon have high field-effect mobility, they require a crystallization process such as laser annealing and are not always suitable for larger glass substrates.

[0003] On the other hand, transistors containing oxide semiconductors as semiconductor materials have attracted attention. For example, Patent Documents 1 and 2 disclose a technique by which a transistor is formed using zinc oxide or an In-Ga-Zn-O-based oxide semiconductor as a semiconductor material and used as a switching element of an image display device.

[0004] Transistors containing oxide semiconductors in channel regions exhibit higher field-effect mobility than transistors containing amorphous silicon. Furthermore, oxide semiconductor layers can be formed at a temperature of 300°C or lower by sputtering or the like, and the manufacturing process is simpler than that of transistors containing polycrystalline silicon.

[0005] Such transistors containing oxide semiconductors are expected to be used as switching elements included in pixel portions and drive circuits of semiconductor devices such as liquid crystal displays, electroluminescent displays, and electronic papers. For example, Non-Patent Document 1 discloses a technique by which a pixel portion and a drive circuit of a display device include transistors containing oxide semiconductors.

[0006] Note that the transistors containing oxide semiconductors are all n-channel transistors. Thus, in the case of a driver circuit containing transistors containing oxide semiconductors, the driver circuit contains only n-channel transistors. [Literature reference][Patent document] [Patent Document 1] Japanese Published Patent Application No. 2007-123861 [Patent Document 2] Japanese Published Patent Application No. 2007-096055 [Non-patent document]

[0007] [Non-Patent Document 1] T. Osada et al., “Development of Driver-Integrated Panel using Amorphous In-Ga-Zn-Oxide TFT,” Proc. SID'09 Digest, 2009, pp. 184-187.

[0008] US 2004 / 0 140 839 A1 teaches a pulse output circuit and a shift register.

[0009] US 2006 / 0 125 518 A1 teaches a shift register having a plurality of stages, each stage comprising a plurality of cascade shift circuits. DISCLOSURE OF THE INVENTION

[0010] The driver circuit used in a display device or the like includes a shift register having, for example, a pulse signal output circuit. If the shift register includes transistors with the same conductivity type, the shift register may have a problem of unstable operation, for example.

[0011] In view of the above problem, an object of an embodiment of the present invention is to provide a pulse signal output circuit that can operate stably and a shift register including the pulse signal output circuit.

[0012] The invention relates to a semiconductor device according to claims 1 to 6. In the following, "embodiments" which do not fall under the claimed invention are to be regarded as illustrative examples.

[0013] Preferably, an oxide semiconductor is used for each of the transistors included in the pulse signal output circuit or in the shift register. The shift register may include multiple pulse signal output circuits.

[0014] It is noted that the transistor in the above pulse signal output circuit includes an oxide semiconductor in some cases; however, the disclosed invention is not limited thereto. It may include a material whose off-state current characteristics are equivalent to those of the oxide semiconductor, for example, a wide bandgap material such as silicon carbide (more specifically, a semiconductor material whose energy gap E g greater than 3 eV).

[0015] It should be noted that in this specification and the like, a term such as "above" or "below" does not necessarily imply that a component is disposed "directly on" or "directly below" another component. For example, the phrase "a gate electrode above a gate insulating layer" does not exclude the possibility of another component being disposed between the gate insulating layer and the gate electrode.

[0016] Furthermore, in this specification and the like, terms such as "electrode" and "wiring" do not limit the functions of components. For example, an "electrode" may be used as part of a "wiring," and the "wiring" may be used as part of the "electrode." Terms such as "electrode" and "wiring" may also mean, for example, a combination of multiple "electrodes" and "wirings."

[0017] The functions of a "source" and a "drain" can be reversed if a transistor with opposite polarity is used or if, for example, the direction of current flow is changed during circuit operation. Thus, the terms "source" and "drain" may be interchanged in this patent.

[0018] It should be noted that the term "electrically connected" in this patent and the like includes the case where components are connected to each other via an object having some electrical function. As long as electrical signals can be sent and received between the components connected to each other via the object, there is no specific limitation on an object having some electrical function.

[0019] Examples of an “object having any electrical function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having a plurality of functions other than an electrode and wiring.

[0020] A pulse signal output circuit that can operate stably and a shift register containing the pulse signal output circuit can be provided. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to 1C show configuration examples of a pulse signal output circuit and a shift register. Fig. 2 is a timing diagram of a shift register. Fig. 3A to 3C show an operation of a pulse signal output circuit. Fig. 4A to 4C show an operation of a pulse signal output circuit. Fig. 5A to 5C show configuration examples of a pulse signal output circuit and a shift register. Fig. 6 is a timing diagram of a shift register. Fig. 7A to 7C show an operation of a pulse signal output circuit. Fig. 8A and Fig. 8B show an operation of a pulse signal output circuit. Fig. 9A to 9C show configuration examples of a pulse signal output circuit and a shift register. Fig. 10A to 10D each show a structural example of a transistor. Fig. 11A to 11E show an example of a method for manufacturing a transistor. Fig. 12A to 12C each show an operation mode of a semiconductor device. Fig. 13A to 13F each show an electronic device. Fig. 14 is a timing chart of a shift register. BEST MODE FOR CARRYING OUT THE INVENTION

[0021] Examples of embodiments of the present invention will now be described with reference to the drawings. It should be noted that the present invention is not limited to the following description. Those skilled in the art will readily appreciate that the modes and details of the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be construed as being limited to the following description of the embodiments.

[0022] It should be noted that the position, size, range, or the like of each component illustrated in the drawings and the like are not precisely illustrated in some cases for ease of understanding. Thus, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

[0023] It is noted that in this patent specification and the like, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion between components and are not limiting in number. [Embodiment 1]

[0024] In this embodiment, Fig. 1A to 1C, Fig. 2, Fig. 3A to 3C and Fig. 4A to 4C describe configuration examples of a pulse signal output circuit and a shift register including the pulse signal output circuit. <schaltungskonfiguration>

[0025] First, Fig. 1A to 1C describe configuration examples of a pulse signal output circuit and a shift register including the pulse signal output circuit.

[0026] A shift register described in this embodiment includes a first to n-th pulse signal output circuit 10 _1 up to 10 _n (where n is a natural number greater than or equal to 2) and a first to fourth signal line 11 to 14, which transmit clock signals (see Fig. 1A). A first clock signal CLK1 is supplied to the first signal line 11. A second clock signal CLK2 is supplied to the second signal line 12. A third clock signal CLK3 is supplied to the third signal line 13. A fourth clock signal CLK4 is supplied to the fourth signal line 14.

[0027] The clock signal is a signal that alternates between an H-level signal (high potential) and an L-level signal (low potential) at regular intervals. Here, the first to fourth clock signals CLK1 to CLK4 are successively delayed by 1 / 4 period. In this embodiment, control or the like of the pulse signal output circuit is performed using the clock signals.

[0028] Each of the first to n-th pulse signal output circuits 10 _1 up to 10 _n includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26 and a second output terminal 27 (see Fig. 1B).

[0029] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first to fourth signal lines 11 to 14. For example, the first input terminal 21 in the first pulse signal output circuit 10 _1 electrically connected to the first signal line 11, the second input terminal 22 in the first pulse signal output circuit 10 _1 electrically connected to the second signal line 12 and is the third input terminal 23 in the first pulse signal output circuit 10 _1 electrically connected to the third signal line 13. In addition, the first input terminal 21 in the second pulse signal output circuit 10 _2 electrically connected to the second signal line 12, the second input terminal 22 in the second pulse signal output circuit 10 _2 electrically connected to the third signal line 13 and is the third input terminal 23 in the second pulse signal output circuit 10 _2 electrically connected to the fourth signal line 14. It is noted that the case is described here that the second to fourth signal lines 12 to 14 are connected to the n-th pulse signal output circuit 10 _n However, the signal line connected to the n-th pulse signal output circuit 10 _n connected, changes depending on the value of n. That is, it is noted that the configuration described here is only an example.

[0030] In the m-th pulse signal output circuit (m is a natural number greater than or equal to 2) of the shift register described in this embodiment, the fourth pulse terminal 24 in the m-th pulse signal output circuit is electrically connected to the first output terminal 26 in the (m-1)th pulse signal output circuit. The fifth input terminal 25 in the m-th pulse signal output circuit is electrically connected to the first output terminal 26 in the (m+2)th pulse signal output circuit. The first input terminal 26 in the m-th pulse signal output circuit is electrically connected to the fourth input terminal 24 in the (m+1)th pulse signal output circuit. The second output terminal 27 in the m-th pulse signal output circuit outputs a signal to OUT(m).

[0031] For example, the fourth input terminal 24 in the third pulse signal output circuit 10 _3 with the first output terminal 26 in the second pulse signal output circuit 10 _2 electrically connected. The fifth input terminal 25 in the third pulse signal output circuit 10 _3 is connected to the first output terminal 26 in the fifth pulse signal output circuit 10 _5 electrically connected. The first input terminal 26 in the third pulse signal output circuit 10 _3 is connected to the fourth input terminal 24 in the fourth pulse signal output circuit 10 _4 and to the fifth input terminal 25 in the first pulse signal output circuit 10 _1 electrically connected.

[0032] In addition, a first initial pulse (SP1) is input from the fifth wiring 15 into the fourth input terminal 24 in the first pulse signal output circuit 10 _1 A pulse output from the previous stage is input to the fourth input terminal 24 in the k-th pulse signal output circuit 10 _k (k is a natural number greater than or equal to 2 and less than or equal to n). A second initial pulse (SP2) is input to the fifth input terminal 25 in the (n-1)th pulse signal output circuit 10 _n-1 A third initial pulse (SP3) is input to the fifth input terminal 25 in the n-th pulse signal output circuit 10 _n The second initial pulse (SP2) and the third initial pulse (SP3) can be input externally or generated within the circuit.

[0033] The following are specific configurations of the first to n-th pulse signal output circuits 10 _1 up to 10 _n described.

[0034] Each of the first to n-th pulse signal output circuits 10 _1 up to 10 _n includes a pulse signal generating circuit 200 including first to fourth transistors 101 to 104; a first input signal generating circuit 201 including fifth to seventh transistors 105 to 107; and a second input signal generating circuit 202 including eighth to eleventh transistors 108 to 111 (see Fig. 1C). Further, signals are supplied to the first to eleventh transistors 101 to 111 from a first power supply line 31 and a second power supply line 32, in addition to the first to fifth input terminals 21 to 25.

[0035] A specific example of a configuration of the pulse signal generating circuit is as follows.

[0036] A first terminal (hereinafter, "first terminal" means a source terminal and a drain terminal) of the first transistor 101, a first terminal of the second transistor 102, and a first output terminal 26 are electrically connected to each other. Similarly, a first terminal of the third transistor 103, a first terminal of the fourth transistor 104, and a second output terminal 27 are electrically connected to each other. A gate terminal of the first transistor 101, a gate terminal of the third transistor 103, and an output terminal of the first input signal generating circuit are electrically connected to each other. A gate terminal of the second transistor 102, a gate terminal of the fourth transistor 104, and an output terminal of the second input signal generating circuit are electrically connected to each other.

[0037] A second terminal (hereinafter, "second terminal" means the other of the source terminal and the drain terminal) of the first transistor 101 and a second terminal of the third transistor are electrically connected to each other, and the first clock signal CLK1 is input to a node where they are connected to each other. The second terminal of the first transistor 101 and the second terminal of the third transistor function as the first input terminal 21 of the pulse signal output circuit. A second terminal of the second transistor 102 is supplied with a first potential (e.g., a low potential V ss ). The first potential is supplied to a second terminal of the fourth transistor 104 via the first power supply line 31.

[0038] A specific example of a configuration of the first input signal generating circuit is as follows.

[0039] A first terminal of the fifth transistor 105, a first terminal of the sixth transistor 106, and a first terminal of the seventh transistor 107 are electrically connected to each other. Furthermore, a second terminal of the seventh transistor 107 functions as the output terminal of the first input signal generating circuit. The gate terminal of the fifth transistor 105 functions as a first input terminal of the first input signal generating circuit and also as the fourth input terminal 24 of the pulse signal output circuit.

[0040] A second potential is supplied to a second terminal of the fifth transistor 105 via the second power supply line 32. The first potential is supplied to a second terminal of the sixth transistor 106 via the first power supply line 31. A pulse signal from the previous stage (in the first pulse signal output circuit, the pulse signal is an initial pulse signal) is input to a gate terminal of the fifth transistor 105. An output signal of the second input signal generating circuit is input to a gate terminal of the sixth transistor 106. The gate terminal of the sixth transistor 106 functions as a second input terminal of the first input signal generating circuit. The second potential is supplied to the gate terminal of the seventh transistor 107 via the second power supply line 32.

[0041] Although the seventh transistor 107 is provided in this embodiment, a configuration without the seventh transistor 107 may be used. With the seventh transistor 107, an increase in the potential of the first terminal of the fifth transistor 105, which might be caused by a bootstrap operation, can be suppressed. That is, the application of a high voltage to a region between the gate and source (or between the gate and drain) of the fifth transistor 105 can be prevented; thus, deterioration of the fifth transistor 105 can be suppressed.

[0042] A specific example of a configuration of the second input signal generating circuit is as follows.

[0043] A second terminal of the tenth transistor 110 and a first terminal of the eighth transistor 108 are electrically connected to each other. A second terminal of the eighth transistor, a second terminal of the eleventh transistor, and a first terminal of the ninth transistor are electrically connected to each other and function as the output terminal of the second input signal generating circuit.

[0044] The second potential is supplied to a first terminal of the eleventh transistor 111 and a first terminal of the tenth transistor 110 via the second power supply line 32. The first potential is supplied to a second terminal of the ninth transistor 109 via the first power supply line 31. A pulse signal from the stage following the next stage is input to a gate terminal of the eleventh transistor 111. The gate terminal of the eleventh transistor 111 functions as the first input terminal of the second input signal generating circuit and also as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal CLK2 is input to a gate terminal of the eighth transistor 108. The gate terminal of the eighth transistor 108 functions as a second input terminal of the second input signal generating circuit and also as the second input terminal 22 of the pulse signal output circuit.A pulse signal from the previous stage (in the first pulse signal output circuit, the pulse signal is an initial pulse signal) is input to a gate terminal of the ninth transistor 109. The gate terminal of the ninth transistor 109 functions as a third input terminal of the second input signal generation circuit and also as the fourth input terminal 24 of the pulse signal output circuit. The third clock signal CLK3 is input to a gate terminal of the tenth transistor 110. The gate terminal of the tenth transistor 110 functions as a fourth input terminal of the second input signal generation circuit and also as the third input terminal 23 of the pulse signal output circuit.

[0045] It is noted that the components of the pulse signal output circuit (e.g., the configuration examples of the pulse signal generating circuit, the first input signal generating circuit, and the second input signal generating circuit) are only examples, and the disclosed invention is not limited thereto.

[0046] In the following description of this embodiment, a node at which the gate terminal of the first transistor 101, the gate terminal of the third transistor 103 and the output terminal of the first input signal generating circuit in the pulse signal output circuit are Fig. 1C are connected to each other is referred to as a node A. In addition, a node at which the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, and the output terminal of the second input signal generating circuit are connected to each other is referred to as a node B.

[0047] A capacitor may be provided between node A and the first output terminal 26 to advantageously perform a bootstrap operation. Furthermore, a capacitor electrically connected to node B may be provided to maintain the potential of node B.

[0048] In Fig. 1C, the ratio W / L of the channel width W to the channel length L of the first transistor 101 and the ratio W / L of the channel width W to the channel length L of the third transistor 103 are each preferably greater than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106.

[0049] In Fig. 1C, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106. The ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is preferably equal to the ratio W / L of the channel width W to the channel length L of the seventh transistor 107. Alternatively, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W / L of the channel width W to the channel length L of the seventh transistor 107.

[0050] In Fig. 1C, the ratio W / L of the channel width W to the channel length L of the third transistor 103 is preferably greater than the ratio W / L of the channel width W to the channel length L of the fourth transistor 104.

[0051] In Fig. 1C, the channel width W of the eighth transistor 108 and the channel width W of the tenth transistor 110 are each preferably smaller than the channel width W of the eleventh transistor 111.

[0052] Preferably, an oxide semiconductor is used for the first to eleventh transistors 101 to 111. By using an oxide semiconductor, the off-state current of the transistors can be reduced. Furthermore, the on-state current and the field-effect mobility can be increased compared to those in the case where amorphous silicon or the like is used. Moreover, deterioration of the transistors can be suppressed. Consequently, an electronic circuit that consumes little power, can operate at high speed, and operates with higher accuracy is realized. Note that the description of the transistor including an oxide semiconductor is omitted here because it is described in detail in a subsequent embodiment. <betrieb>

[0053] The following is based on Fig. 2, Fig. 3A to 3C, Fig. 4A to 4C and Fig. 14 the operation of the shift register in Fig. 1A to 1C. More precisely, Fig. 3A to 3C and Fig. 4A to 4C, the operation in each of the first to sixth periods 51 to 56 in a time schedule in Fig. 2. In the timing chart, CLK1 to CLK4 denote clock signals; SP1 denotes a first initial pulse; OUT1 to OUT4 denote outputs from the second output terminals of the first to fourth pulse signal output circuits 10. _1 up to 10 _4 ; node A and node B denote potentials of node A and node B; and SROUT1 to SROUT4 denote outputs from the first output terminals of the first to fourth pulse signal output circuits 10 _1 up to 10 _4 .

[0054] It is noted that the first to eleventh transistors 101 to 111 in the following description are all n-channel transistors. Furthermore, in Fig. 3A to 3C and in Fig. 4A to 4C Transistors indicated by solid lines mean that the transistors are in a conducting state (turned on), and transistors indicated by dashed lines mean that the transistors are in a non-conducting state (turned off).

[0055] Typically, the operation of the first pulse signal output circuit 10 _1 described. The configuration of the first pulse signal output circuit 10 _1 is as described above. Furthermore, the relationship between the input signals and the applied potentials is also as described above. It is noted that in the following description, V DD used for all high potentials (also called H-levels, H-level signals, or the like) to be supplied to input terminals and power supply lines, and V ss used for all low potentials (also called L-level, L-level signals or the like) to be supplied to input terminals and power supply lines.

[0056] In the first period 51, SP1 is at the H level, so that the gate terminal of the fifth transistor 105 and the gate terminal of the ninth transistor 109, which serve as the fourth input terminal 24 in the first pulse signal output circuit 10 _1 function, a high potential is applied. Thus, the fifth transistor 105 and the ninth transistor 109 are turned on. In the first period 51, CLK3 is also at the H level, so that the tenth transistor 110 is also turned on. Since a high potential is also applied to the gate terminal of the seventh transistor 107, the seventh transistor 107 is also turned on (see Fig. 3A).

[0057] When the fifth transistor 105 and the seventh transistor 107 are turned on, the potential of node A is increased. When the ninth transistor 109 is turned on, the potential of node B is decreased. The potential of the second terminal of the fifth transistor 105 is V DD . Thus, the potential of the first terminal of the fifth transistor 105 becomes V DD - V th105 , that is, to a potential obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the second terminal. The potential of the gate terminal of the seventh transistor 107 is V DD . Thus, the potential of node A becomes V DD - V th107 , if V th107 , ie the threshold voltage of the seventh transistor 107, greater than or equal to V th105 is, which turns off the seventh transistor 107. On the other hand, if V th107 lower than V th105 the potential of node A is set to V DD - V th105 increased while the seventh transistor 107 is kept on. In the following, a mark (the highest potential) of node A in the first period 51 is represented by V AH designated.

[0058] If the potential of node A is V AH is turned on, the first transistor 101 and the third transistor 103 are turned on. Since CLK1 is at the L level, an L-level signal is output from the first output terminal 26 and the second output terminal 27.

[0059] In the second period 52, the potential of CLK1 is changed from the L level to the H level. Since the first transistor 101 and the third transistor 103 are turned on, the potential of the first output terminal 26 and the potential of the second output terminal 27 are increased. Further, a capacitance is generated between the gate terminal and the source terminal (or the drain terminal) of the first transistor 101; with the capacitance, the gate terminal and the source terminal (or the drain terminal) thereof are capacitively coupled. Similarly, a capacitance is generated between the gate terminal and the source terminal (or the drain terminal) of the third transistor 103; with the capacitance, the gate terminal and the source terminal (or the drain terminal) thereof are capacitively coupled.Thus, the potential of node A is increased in a floating state because the potential of the first output terminal 26 and the potential of the second output terminal 27 are increased (bootstrap operation). Eventually, the potential of node A becomes higher than V. DD + V th101 , wherein both the potential of the first output terminal 26 and the potential of the second output terminal 27 are V DD (H-level) (see Fig. 2 and Fig. 3B).

[0060] In the second period 52, the ninth transistor 109 is in an on state; thus, the node B is maintained at the L level. Thus, the change in the potential of the node B due to capacitive coupling, which occurs when the potential of the first output terminal 26 is changed from the L level to the H level, can be suppressed, so that noise due to the change in the potential can be prevented.

[0061] As described above, in the second period 52 a gate voltage (V gs ) of the third transistor 103 must be sufficiently high to turn on the third transistor 103 in order to safely set the potential of the second output terminal 27 to V DD (H level) if the potential of the second output terminal 27 is at the H level. If V gs of the third transistor 103 is low, a drain current of the third transistor 103 is small, so it takes a long time to lower the potential of the second output terminal 27 to V in the specified period (here, in the second period). DD (H level). Accordingly, the rise of a waveform of the second output terminal 27 becomes weak, resulting in noise.

[0062] It is noted that V gs of the third transistor 103 in the second period 52 depends on the potential of node A in the first period 51. Thus, the potential of node A in the first period 51 should be as high as possible (given the circuit design, the maximum value V DD - V th105 or V DD - V th107 ) to V gs of the third transistor 103. The same can also be done for the first output terminal 26 and for V gs of the first transistor 101.

[0063] Thus, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is preferably greater than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106. When the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is greater than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106, the potential of the node A in the first period 51 can be reduced to V in a shorter time. DD - V th105 or on V DD - V th107 increased. It is noted that the sixth transistor 106 is in an off state in the first period 51. If the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is made larger than the ratio W / L of the channel width W to the channel length L of the sixth transistor 106, a leakage current (I off ) in the sixth transistor 106 can be made small, so that the potential of the node A can be reduced to V in a shorter time. DD - V th105 can be increased.

[0064] When the channel length L becomes short due to miniaturization of the transistor, the threshold voltage shifts, and the sixth transistor 106 functions as a normally-on transistor in some cases. Even in this case, the on-resistance of the sixth transistor 106 can be larger than the on-resistance of the fifth transistor 105 if the ratio W / L of the channel width W to the channel length L of the sixth transistor 106 is made smaller than the ratio W / L of the channel width W to the channel length L of the fifth transistor 105. Accordingly, the potential of node A can be set to a potential close to V DD - V th105 or V DD - V th107 be made.

[0065] Preferably, the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 is almost equal to the ratio W / L of the channel width W to the channel length L of the seventh transistor 107. The term "almost equal" may be used if it is understood that two objects had the same value despite a small difference due to a manufacturing error or variation. When the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 and the ratio W / L of the channel width W to the channel length L of the seventh transistor 107 are equal to each other, the current-carrying capability of the fifth transistor 105 and that of the seventh transistor 107 can be equal to each other; thus, the potential of node A can be efficiently increased. Note that the threshold voltage V th of the fifth transistor 105 and that of the seventh transistor 107 are preferably almost equal to each other.

[0066] It is noted that the ratio W / L of the channel width W to the channel length L of the fifth transistor 105 can be determined depending on the transistor characteristics, the clock frequency, the gate capacitance of the first transistor 101, the gate capacitance of the third transistor 103, the operating voltage of the shift register, or the like.

[0067] When the channel width W of the sixth transistor 106 is large, a leakage current is increased if the sixth transistor 106 functions as a normally-on transistor; accordingly, the potential of node A is reduced. Furthermore, the charging of node A is prevented by the fifth transistor 105. If high-speed operation is required, the potential of node B must be reduced in a short time to charge node A. In this case, the potential of the sixth transistor must be reduced in a short time.

[0068] Thus, a change in the potential of node A can be prevented when the channel width W of the sixth transistor is smaller than that of the fifth transistor. Furthermore, a load of node B can be reduced. In this way, the sizes of the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are determined by considering the transistor characteristics and the drive specification, whereby a high-efficiency shift register can be realized.

[0069] In the third period 53, SP1 becomes L-level, so that the fifth transistor 105 and the ninth transistor 109 are turned off. Furthermore, CLK1 is kept at H-level and the potential of node A is not changed; thus, voltage is output from the first output terminal 26 and the second output terminal 27 (see Fig. 3C) V DD (an H-level signal) is output. Note that the potential of the first output terminal 26 is not changed in the third period 53 even though node B is in a floating state; thus, noise due to capacitive coupling is negligible.

[0070] Since both CLK2 and CLK3 are at the H level in the fourth period 54, the potential of node B is increased in a short time. Furthermore, CLK1 becomes the L level. Consequently, the second transistor 102 and the fourth transistor 104 are turned on, so that the potentials of the first output terminal 26 and the second output terminal 27 are reduced in a short time (see Fig. 4A). Further, the sixth transistor 106 is turned on, so that the potential of node A becomes the L level. Thus, the first transistor 101 and the third transistor 103 are turned off, causing the potential of the first output terminal 26 and the second output terminal 27 to become the L level.

[0071] In the fourth period 54, the potential of node A should be V ss be reduced before CLK1 becomes H-level in the sixth period (i.e., during the fourth period 54 and the fifth period 55). If the potential of node A does not fall to V during the fifth period 55 ss is decreased, the potential of node A is increased again due to the capacitive coupling between the gate and the source of the third transistor 103; thus, the first transistor 101 and the third transistor 103 are turned on and charge flows through the first output terminal 26 and the second output terminal 27, so that a fault may occur.

[0072] Thus, a relationship among the first transistor 101, the third transistor 103, and the sixth transistor 106 is determined according to the following formulas (1) to (7), whereby the operation disturbance due to a load is reduced and stabilization of the operation can be achieved. i106=(C101+C103)×Vftoff i106=W1062L106×μ×Cox×(Vgs106−Vth106)2 1fclk=T=tCKH+tCKL toff=tCLK−tα C101=L101×W101×Cox C103=L103×W103×Cox(Cox=εo×εrtox) Vf=(Vdd−Vth105)+Vdd

[0073] In the above formulas, t CKH a period during which CLK1 is at the H level, ie the second period 52 and the third period 53; corresponds to t CKL a period during which CLK1 is at the L level, ie the fourth period 54 and the fifth period 55; and corresponds to t off a period of time required to reduce the potential of node A to V ss is required. That is, in t CKL the potential of node A in t off on V ss reduced. The time period t off is not particularly restricted as long as it is spent in a period from the fourth period 54 to the fifth period 55; e.g., t off in a fourth period 54_1, in a period from the fourth period 54_1 to a fourth period 54_3 or in a period from the fourth period 54_1 to a fourth period 54_5 (see Fig. 14). In particular, the period from the fourth period 54_1 to the fourth period 54_3, which corresponds to 1 / 2 of the period from the fourth period 54 to the fifth period 55, is preferred. The reason for this is as follows: When t off in relation to t CKL is set too short, the channel width W of the sixth transistor 106 must be set large in order to quickly reduce the potential of the node A, and on the other hand, the potential of the node A cannot be reduced to V until the time when a next H-level clock signal is input. ss be reduced, so that a disturbance could occur if t off long. That is, t off must be determined taking into account the frequency of the clock signal or the like. It is noted that in a timing chart in Fig. 14 parts of the periods (e.g. the period from the fourth period 54_1 to the fourth period 54_5) are excessive; however, this schedule does not differ significantly from the schedule in Fig. 2.

[0074] C 101 and C 103 denote the gate capacitance of the first transistor 101 and the gate capacitance of the third transistor 103, respectively. V f denotes the potential of node A in the third period 53.

[0075] i 106 In formula (2), the drain current of the sixth transistor 106 is used to determine the size (e.g., W / L) of the sixth transistor 106. In other words, the size of the sixth transistor 106 can be determined by considering the operating frequency of CLK1, the size of the first transistor 101, the size of the third transistor 103, and the potential of node A.

[0076] For example, if the operating frequency of CLK1 is high, the potential of node A must be reduced quickly; as can be seen from formula (1), t off therefore be short. Therefore, i 106 be big. W 106 is in accordance with i 106 calculated from formula (2) and can be determined.

[0077] On the other hand, if the size of the first transistor 101 and the size of the third transistor 103 are small, i 106 be small; thus W 106 from formula (2) is small. Note that by increasing the size of the third transistor at the time of discharge, not only the fourth transistor 104 but also the third transistor 103 can be discharged because the third transistor 103 is used for charging and discharging an output load. Accordingly, the output potential can be reduced in a short time. Thus, compared with the case where only the fourth transistor 104 is discharged, the output potential can be reduced in a short time when the potential of node A is gradually reduced because the third transistor 103 is in an on state. In this way, the size of the sixth transistor 106 is determined taking into account the transistor characteristics and the drive specification, whereby a shift register with high efficiency can be realized.

[0078] In the fourth period 54, the potential of CLK1 is changed from the H level to the L level, and at the same time, a pulse signal (SROUT3) is input to the fifth input terminal 25. Accordingly, the eleventh transistor 111 is turned on. Since the eleventh transistor 111 is turned on, the potential of node B is increased to V DD - V th111 increased. Thus, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are turned on. When the second transistor 102 and the fourth transistor 104 are turned on, the potential of the first output terminal 26 and that of the second output terminal 27 become V ss . Note that the first transistor 101 and the third transistor 103 are turned off.

[0079] At the same time, node B is charged via the tenth transistor 110 and the eighth transistor 108 in addition to the eleventh transistor 111. The gate of the tenth transistor 110 and the gate of the eighth transistor 108 are connected to the third input terminal 23 and the second input terminal 22, respectively, with the gate capacitance of the tenth transistor 110 and the gate capacitance of the eighth transistor 108 corresponding to the load of the third input terminal 23 and the load of the second input terminal 22, respectively.

[0080] It is noted that the loads of the transistors connected to a clock line in the shift register described in this embodiment are defined as “the total number of stages of the shift register + 4 × (L ov the third transistor 103 + L ov of the first transistor 101 + the gate capacitance of the tenth transistor 110 + the gate capacitance of the eighth transistor 108). It is noted that the gate capacitance is expressed as "ε0 × ε × (L × W) / tox". It is noted that L ov represents the length of a region in which a source electrode layer or a drain electrode layer of a transistor overlaps with a semiconductor layer in a channel length direction.

[0081] To reduce the gate capacitance associated with the clock line, the channel width W of the eighth transistor 108 and the channel width W of the tenth transistor 110 are each preferably smaller than the channel width W of the eleventh transistor 111. With such a structure, the load on the clock line can be reduced, thereby realizing high-speed operation. Reducing the channel width W of the tenth transistor 110 and the eighth transistor 108 can achieve a reduction in device area.

[0082] In the fifth period 55, the potential of the fifth input terminal 25 (ie, SROUT3) is kept at the H level, thereby holding the potential of node B. Thus, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept on, so that the potentials of the first output terminal 26 and the second output terminal 27 are kept at the L level (see Fig. 4B).

[0083] In the sixth period 56, the fifth input terminal 25 (i.e., SROUT3) becomes the L level, so that the eleventh transistor 111 is turned off. At this time, node B is caused to be in a floating state while holding the potential. Thus, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept turned on (see Fig. 4C). Note that the potential of node B is generally reduced, for example, due to the off-state current of a transistor. However, a transistor with a sufficiently low off-state current (e.g., a transistor including an oxide semiconductor) does not have such a problem. Note that a capacitor may be provided to mitigate a decrease in the potential of node B.

[0084] If both CLK2 and CLK3 become H level in a subsequent period, the eighth transistor 108 and the tenth transistor 110 are turned on, and a potential is periodically supplied to node B. Thus, even if a transistor whose off-state current is relatively high is used, malfunction of the pulse signal output circuit can be prevented.

[0085] Note that, as with the outputs (such as OUT1 to OUT4) from the shift register, there are two cases where the value of the time at which the potential is increased is determined, and the case where the value of the time at which the potential is decreased is determined. For example, in the case where data is determined by a potential increase (e.g., when data is written), the value of the time at which the potential is increased is determined. If the data is determined by a potential decrease, the value of the time at which the potential is decreased is determined.

[0086] If data is determined by the potential increase, the time required to increase the potential need not be short. For this purpose, the ratio W / L of the channel width W to the channel length L of the third transistor 103 is preferably larger than the ratio W / L of the channel width W to the channel length L of the fourth transistor 104.

[0087] If data is determined by potential reduction, the time required to reduce the potential must be short. For this purpose, the ratio W / L of the channel width W to the channel length L of the third transistor 103 is preferably larger than the ratio W / L of the channel width W to the channel length L of the fourth transistor 104.

[0088] It is noted that in one embodiment of the disclosed invention, the potential of node A is increased to a predetermined potential by a bootstrap operation that utilizes the capacitive coupling between the gate and source of the third transistor 103. Accordingly, the third transistor 103 is turned on, and an H-level signal is output. Thus, a problem may arise that an H-level potential output from the shift register does not reach V DD is increased when the ratio W / L of the channel width W to the channel length L of the third transistor 103 is not sufficiently large. Thus, it is preferable that the ratio W / L of the channel width W to the channel length L of the third transistor 103 is sufficiently large.

[0089] Furthermore, the shift register of this embodiment is driven by a driving method in which a pulse output from the mth pulse signal output circuit overlaps with half of a pulse output from the (m+1)th pulse signal output circuit. Thus, a wiring can be charged for a longer period of time compared to the case where the driving method is not used. That is, with the driving method, a pulse signal output circuit that can withstand a heavy load and operate at a high frequency is provided. [Embodiment 2]

[0090] In this embodiment, Fig. 5A to 5C, Fig. 6, Fig. 7A to 7C and Fig. 8A to 8B describe configuration examples of a pulse signal output circuit and a shift register which are types other than the pulse signal output circuit and the shift register described in the above embodiment, and their operations. <schaltungskonfiguration>

[0091] First, Fig. 5A to 5C describe configuration examples of a pulse signal output circuit and a shift register including the pulse signal output circuit.

[0092] The configuration of the shift register described in this embodiment is similar to that of the shift register described in the above embodiment. One of the differences between them is that the third input terminal 23 in the first to n-th pulse signal output circuits 10 _1 up to 10 _n is not provided (see Fig. 5A to 5C). That is, two types of clock signals are input to a pulse signal output circuit. The other structures are similar to those in the above embodiment.

[0093] Since the third input terminal 23 in the first to n-th pulse signal output circuit 10 _1 up to 10 _n is not provided, the tenth transistor connected to the third input terminal 23 is not provided (see Fig. 5C). Accordingly, the connection relationship of the second input signal generating circuit 202 in Fig. 1C and the connection relationship of a second input signal generating circuit 203 in Fig. 5C partly different from each other.

[0094] More specifically, each of the first to n-th pulse signal output circuits 10 includes _1 up to 10 _n the pulse signal generating circuit 200, which includes the first to fourth transistors 101 to 104; the first input signal generating circuit 201, which includes the fifth to seventh transistors 105 to 107; and the second input signal generating circuit 203, which includes the eighth transistor 108, the ninth transistor 109, and the eleventh transistor 111. The first to eleventh transistors 101 to 111 are supplied with signals from the first power supply line 31 and the second power supply line 32, in addition to the first to fifth input terminals 21 to 25.

[0095] A specific example of a configuration of the second input signal generating circuit 203 is as follows.

[0096] The second terminal of the eighth transistor 108, the second terminal of the eleventh transistor 111 and the first terminal of the ninth transistor 109 are electrically connected to each other and function as the output terminal of the second input signal generating circuit.

[0097] The second potential is supplied to the first terminal of the eleventh transistor 111 and the first terminal of the eighth transistor 108 via the second power supply line 32. The first potential is supplied to the second terminal of the ninth transistor 109 via the first power supply line 31. A pulse signal is input to the gate terminal of the eleventh transistor 111. The gate terminal of the eleventh transistor 111 functions as the first input terminal of the second input signal generating circuit and also as the fifth input terminal 25 of the pulse signal output circuit. The second clock signal CLK2 is input to the gate terminal of the eighth transistor 108. The gate terminal of the eighth transistor 108 functions as the second input terminal of the second input signal generating circuit and also as the second input terminal 22 of the pulse signal output circuit.A pulse signal is input to the gate terminal of the ninth transistor 109. The gate terminal of the ninth transistor 109 functions as the third input terminal of the second input signal generating circuit and also as the fourth input terminal 24 of the pulse signal output circuit.

[0098] It is noted that the above configuration is merely an example and that the disclosed invention is not limited thereto.

[0099] In the following description of this embodiment, a node at which the gate terminal of the first transistor 101, the gate terminal of the third transistor 103 and the output terminal of the first input signal generating circuit in the pulse signal output circuit are Fig. 5C are connected to each other, as referred to as the node A in the above embodiment. In addition, a node at which the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, the second terminal of the eighth transistor 108, the second terminal of the eleventh transistor 111, and the first terminal of the ninth transistor 109 are connected to each other is referred to as the node B.

[0100] A capacitor may be provided between node A and the first output terminal 26 to conveniently perform a bootstrap operation. Furthermore, a capacitor electrically connected to node B may be provided to maintain the potential of node B.

[0101] For the first to ninth transistors 101 to 109 and for the eleventh transistor 111, an oxide semiconductor is preferably used. By using an oxide semiconductor, the off-state current of the transistors can be reduced. Furthermore, the on-state current and the field-effect mobility can be increased compared to those in the case where amorphous silicon or the like are used. Moreover, deterioration of the transistors can be suppressed. Consequently, an electronic circuit that consumes little power, can operate at high speed, and operates with higher accuracy can be realized. Note that the description of the transistor including an oxide semiconductor is omitted here because it is described in detail in a subsequent embodiment. <betrieb>

[0102] The following is based on Fig. 6, Fig. 7A to 7C and Fig. 8A to 8B the operation of the shift register in Fig. 5A to 5C. More precisely, Fig. 7A to 7C and Fig. 8A to 8B the operation in each of the first to fifth periods 51 to 55 in a time schedule in Fig. 6. In the timing chart, CLK1 to CLK4 denote clock signals; SP1 denotes a first initial pulse; OUT1 to OUT4 denote outputs from the second output terminals of the first to fourth pulse signal output circuits 10. _1 up to 10 _4 ; Node A and Node B denote potentials of node A and node B; and SROUT1 to SROUT4 denote outputs from the first output terminals of the first to fourth pulse signal output circuits 10 _1 up to 10 _4 .

[0103] It is noted that the first to ninth transistors 101 to 109 and the eleventh transistor 111 in the following description are all n-channel transistors. Furthermore, in Fig. 7A to 7C and in Fig. 8A to 8B Transistors indicated by solid lines mean that the transistors are in a conductive state (turned on), and transistors indicated by dashed lines mean that the transistors are in a non-conductive state (turned off).

[0104] Typically, the operation of the first pulse signal output circuit 10 _1 described. The configuration of the first pulse signal output circuit 10 _1 is as described above. Furthermore, the relationship between the input signals and the applied potentials is also as described above. It is noted that in the following description, V DD is used for all high potentials (also called H-potentials, H-level signals or the like) to be supplied to input terminals and power supply lines, and V ss used for all low potentials (also called L-level, L-level signals or the like) to be supplied to input terminals and power supply lines.

[0105] In the first period 51, SP1 is at the H level, so that the gate terminal of the fifth transistor 105 and the gate terminal of the ninth transistor 109, which serve as the fourth input terminal 24 in the first pulse signal output circuit 10 _1 function, a high potential is applied. Thus, the fifth transistor 105 and the ninth transistor 109 are turned on. Since a high potential is applied to the gate terminal of the seventh transistor 107, the seventh transistor 107 is also turned on (see Fig. 7A).

[0106] The fifth transistor 105 and the seventh transistor 107 are turned on, increasing the potential of node A. The ninth transistor 109 is turned on, decreasing the potential of node B. When the potential of node AV AH (V AH - V DD - V th105 - V th107 ), the fifth transistor 105 and the seventh transistor 107 are turned off and the node A is brought into a floating state while its potential is set to V AH is held.

[0107] If the potential of node A is V AH is turned on, the first transistor 101 and the third transistor 103 are turned on. Since CLK1 is at the L level, an L-level signal is output from the first output terminal 26 and the second output terminal 27.

[0108] In the second period 52, the potential of CLK1 is changed from the L level to the H level. Since the first transistor 101 and the third transistor 103 are turned on, the potential of the first output terminal 26 and the potential of the second output terminal 27 are increased. Furthermore, a capacitance is generated between the gate terminal and the source terminal (or the drain terminal) of the first transistor 101; with the capacitance, the gate terminal and the source terminal (or the drain terminal) thereof are capacitively coupled. Similarly, a capacitance is generated between the gate terminal and the source terminal (or the drain terminal) of the third transistor 103; with the capacitance, the gate terminal and the source terminal (or the drain terminal) are capacitively coupled.Thus, the potential of node A is increased in a floating state while the potential of the first output terminal 26 and the potential of the second output terminal 27 are increased (bootstrap operation). Eventually, the potential of node A becomes higher than V. DD + V th101 and both the potential of the first output terminal 26 and the potential of the second output terminal 27 become V DD (H-level) (see Fig. 6 and Fig. 7B).

[0109] In the third period 53, the potential of CLK2 becomes H level and the eighth transistor 108 is turned on. Accordingly, the potential of node B is increased. When the potential of node B is increased, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are turned on and the potential of node A is decreased. Thus, the potential of the first output terminal 26 and the potential of the second output terminal 27 become L level (see Fig. 7C).

[0110] In the fourth period 54, the potential of CLK2 becomes L level, and the eighth transistor 108 is turned off. The potential of the fifth input terminal 25 (i.e., SROUT3) becomes H level, and the eleventh transistor 111 is turned on. Thus, the potential of node A and the potential of node B are held in the third period 53, and the potential of the first output terminal 26 and the potential of the second output terminal 27 are held at L level (see Fig. 8A).

[0111] In the fifth period 55, the potential of the fifth input terminal 25 (ie, SROUT3) becomes the L level and the potential of the node B is held. That is, the second transistor 102, the fourth transistor 104, and the sixth transistor 106 are kept on, so that the potentials of the first output terminal 26 and the second output terminal 27 are kept at the L level (see Fig. 8B).

[0112] Note that the potential of node B is generally lowered due to, for example, the off-state current of a transistor. However, a transistor with a sufficiently low off-state current (e.g., a transistor including an oxide semiconductor) does not have such a problem. To reduce the decrease in the potential of node B, a capacitor may be provided. In this case, the provided capacitor is electrically connected to the gate terminal of the second transistor 102, the gate terminal of the fourth transistor 104, the gate terminal of the sixth transistor 106, the first terminal of the eighth transistor 108, and the first terminal of the ninth transistor 109.

[0113] If the potential of CLK2 becomes H level in a subsequent period, the eighth transistor 108 is turned on and a potential is periodically supplied to node B. Thus, even if a transistor whose off-state current is relatively high is used, disturbance of the pulse signal output circuit can be prevented.

[0114] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed. [Embodiment 3]

[0115] In this embodiment, Fig. 9A to 9C describe configuration examples of a pulse signal output circuit and a shift register which are types other than the pulse signal output circuit and the shift register described in any of the above embodiments.

[0116] The configuration of the shift register described in this embodiment is similar to that of the shift register described in the above embodiment. One of the differences between them is that with a subsequent stage of the n-th pulse signal output circuit 10 _n a first dummy pulse signal output circuit 10 _D1 and a second dummy pulse signal output circuit 10 _D2 are connected (see Fig. 9A). The first dummy pulse signal output circuit 10 _D1 and the second dummy pulse signal output circuit 10 _D2 have a function of supplying a pulse signal to the fifth input terminals 25 of the (n-1)-th and the n-th pulse signal output circuit 10 _n-1 and 10 _n .

[0117] In subsequent stages of the first dummy pulse signal output circuit 10 _D1 and the second dummy pulse signal output circuit 10 _D2 no pulse signal output circuit is provided. That is, in the first dummy pulse signal output circuit 10 _D1 and into the second dummy pulse signal output circuit 10 _D2 no pulse signal is input from its subsequent stages (in this case, from the stages following their respective next stages), which is different from the first to n-th pulse signal output circuits. Thus, no terminal is provided corresponding to the fifth input terminal 25 of the first to n-th pulse signal output circuits (see Fig. 9B and Fig. 9C). Furthermore, the eleventh transistor 111, which relates to the fifth input terminal 25, is also not provided (see Fig. 9C).

[0118] The function of the dummy pulse signal output circuits (the first and second dummy pulse signal output circuits) is to output an appropriate pulse signal to the pulse signal output circuits in the normal stages (the (n-1)th and nth pulse signal output circuits); thus, the dummy pulse signal output circuits do not need to have the ability to sufficiently charge node B. Here, in the first to nth pulse signal output circuits, the sizes of the eighth transistor 108 and the tenth transistor 110 are made small (e.g., the channel width W is made small or the ratio W / L of the channel width W to the channel length L is made small), so that the charging ability by the eleventh transistor 111 is ensured to reduce power consumption due to input of the clock signal.On the other hand, the eleventh transistor 111 is not provided in the dummy pulse signal output circuits; thus, the sizes of the eighth transistor 108 and the tenth transistor 110 must be large so that the charging capability of the eleventh transistor 111 can be compensated.

[0119] More specifically, for example, each of the channel widths W (or the ratios W / L of the channel widths W to the channel lengths L) of the eighth transistors in the first and second dummy pulse signal output circuits may be made larger than each of the channel widths W (or the ratios W / L of the channel widths W to the channel lengths L) of the eighth transistors in the first to n-th pulse signal output circuits, or each of the channel widths W (or the ratios W / L of the channel widths W to the channel lengths L) of the tenth transistors in the first and second dummy pulse signal output circuits may be made larger than each of the channel widths W (or the ratios W / L of the channel widths W to the channel lengths L) of the tenth transistors in the first to n-th pulse signal output circuits.

[0120] With such a structure, the power consumption in the pulse signal output circuits in the normal stages (the (n-1)th and the nth pulse signal output circuits) can be reduced, and a shift register that operates properly can be realized.

[0121] It is noted that the basic configuration of the dummy pulse signal output circuits is similar to that of the pulse signal output circuit described in the above embodiment except for the above difference. Specifically, each of the first to n-th pulse signal output circuits 10 includes _1 up to 10 _n a dummy pulse signal generating circuit 204 including the first to fourth transistors 101 to 104; a first input signal generating circuit 205 including the fifth to seventh transistors 105 to 107; and a second input signal generating circuit 206 including the eighth to tenth transistors 108 to 110. The first to tenth transistors 101 to 110 are supplied with signals from the first power supply line 31 and the second power supply line 32.

[0122] The operation of the dummy pulse signal output circuits is also similar to that of the pulse signal output circuit described in the above embodiment, except that an output from their subsequent stages is not input. Thus, for a detailed description thereof, reference may be made to the above embodiment. Note that the tenth transistor 110 is not necessarily provided. Further, in the dummy pulse signal output circuits, at least one output to the pulse signal output circuits in the normal stages (to the (n-1)th and to the nth pulse signal output circuits) must be ensured; thus, the number of systems of output terminals is not limited to two and may be one. That is, the first output terminal 26 or the second output terminal 27 may be omitted.It is noted that in this case, a transistor connected to the output terminal to be omitted (e.g., if the second output terminal 27 is omitted, the third transistor 103 and the fourth transistor 104) may be omitted as necessary.

[0123] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed. [Embodiment 4]

[0124] In this embodiment, Fig. 10A to 10D describe examples of transistors that can be used in the pulse signal output circuit and the shift register described in the above embodiment. There is no particular limitation on the structure of the transistor. For example, a stacked type or a planar type with a top gate structure or with a bottom gate structure can be used. Alternatively, the transistor may have a single-gate structure in which one channel formation region is formed, or a multi-gate structure in which two or more channel formation regions are formed. Alternatively, the transistor may have a structure in which two gate electrode layers are formed above and below a channel region, with a gate insulating layer provided therebetween.

[0125] Fig. 10A to 10D illustrate examples of the cross-sectional structures of the transistors. Fig. The transistors shown in Figures 10A to 10D each contain an oxide semiconductor as a semiconductor. One advantage of using an oxide semiconductor is the high mobility and low off-state current that can be achieved through a simple low-temperature process.

[0126] One in Fig. Transistor 410 shown in Figure 10A is an example of a bottom-gate transistor and is also referred to as an inverted stacked transistor.

[0127] Transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b provided over a substrate 400 having an insulating surface. Further, an insulating layer 407 is provided in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is formed over the insulating layer 407.

[0128] One in Fig. Transistor 420 shown in Figure 10B is an example of a bottom-gate transistor, referred to as a channel protection transistor (channel stop transistor), and also referred to as an inverted stacked transistor.

[0129] Transistor 420 includes gate electrode layer 401, gate insulating layer 402, oxide semiconductor layer 403, an insulating layer 427 acting as a channel protection layer, source electrode layer 405a, and drain electrode layer 405b provided over substrate 400 with an insulating surface. Further, protective insulating layer 409 is provided.

[0130] One in Fig. Transistor 430 shown in Figure 10C is an example of a bottom-gate transistor. Transistor 430 includes gate electrode layer 401, gate insulating layer 402, source electrode layer 405a, drain electrode layer 405b, and oxide semiconductor layer 403 provided over substrate 400 having an insulating surface. Further, insulating layer 407 is provided in contact with oxide semiconductor layer 403. Furthermore, protective insulating layer 409 is formed over insulating layer 407.

[0131] In the transistor 430, the gate insulating layer 402 is provided on and in contact with the substrate 400 and the gate electrode layer 401, and the source electrode layer 405a and the drain electrode layer 405b are provided on and in contact with the gate insulating layer 402. Further, the oxide semiconductor layer 403 is provided over the gate insulating layer 402, the source electrode layer 405a, and the drain electrode layer 405b.

[0132] One in Fig. Transistor 440 shown in Figure 10D is an example of a top-gate transistor. Transistor 440 includes an insulating layer 437, the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 402, and the gate electrode layer 401, which are provided over the substrate 400 having an insulating surface. A wiring layer 436a and a wiring layer 436b are provided in contact with the source electrode layer 405a and the drain electrode layer 405b, respectively.

[0133] As described above, in this embodiment, the oxide semiconductor layer 403 is used as a semiconductor layer.As an oxide semiconductor used for the oxide semiconductor layer 403, a four-component metal oxide such as an In-Sn-Ga-Zn-O-based oxide semiconductor, a three-component metal oxide such as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-Al-Zn-O-based oxide semiconductor, a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, or a Sn-Al-Zn-O-based oxide semiconductor; a two-component metal oxide such as an In-Zn-O-based oxide semiconductor, an In-Ga-O-based oxide semiconductor, an Sn-Zn-O-based oxide semiconductor, an Al-Zn-O-based oxide semiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-based oxide semiconductor, or an In-Mg-O-based oxide semiconductor; or a one-component metal oxide such as an In-O-based oxide semiconductor, an Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor.Furthermore, SiO2 may be added to the oxide semiconductor. Here, for example, an In-Ga-Zn-O-based oxide semiconductor is an oxide containing at least In, Ga, and Zn, and there is no particular limitation on its composition ratio. Furthermore, the In-Ga-Zn-O-based oxide semiconductor may contain an element other than In, Ga, and Zn.

[0134] For the oxide semiconductor layer 403, an oxide semiconductor represented by a chemical formula In-MO3 (ZnO) can be used. m (m > 0 and m is not a natural number). Here, M represents one or more metal elements selected from gallium (Ga), aluminum (Al), manganese (Mn), and cobalt (Co). Further, M may be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like.

[0135] The off-state current of transistor 410, transistor 420, transistor 430, and transistor 440, which include oxide semiconductor layer 403, can be significantly reduced. Thus, when these transistors are used in the pulse signal output circuit and shift register, the potential of each node can be easily maintained, so that the possibility of disturbances to the pulse signal output circuit and shift register can be significantly reduced.

[0136] There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface. For example, a glass substrate, a quartz substrate, or the like used for a liquid crystal display device or the like can be used. Alternatively, for example, a substrate in which an insulating layer is formed over a silicon wafer can be used.

[0137] In each of the bottom-gate transistors 410, 420, and 430, an insulating layer serving as a base may be provided between the substrate and the gate electrode layer. The insulating layer has a function of preventing the diffusion of an impurity element from the substrate and may be formed to have a single-layer structure or a stacked structure including one or more layers selected from a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer.

[0138] The gate electrode layer 401 may be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as a main component. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

[0139] The gate insulating layer 402 may be formed by plasma CVD, sputtering, or the like using one or more layers selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, a hafnium oxide layer, and the like. For example, a gate insulating layer with a total thickness of about 300 nm may be formed by plasma CVD forming a silicon nitride layer (SiN y (y > 0)) with a thickness of 50 nm to 200 nm is formed as a first gate insulating layer and a silicon oxide layer (SiO x (x > 0)) with a thickness of 5 nm to 300 nm is stacked as a second gate insulation layer.

[0140] The source electrode layer 405a and the drain electrode layer 405b may be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing one of these materials as a main component. For example, the source electrode layer 405a and the drain electrode layer 405b may have a stacked structure of a metal layer containing aluminum, copper, or the like and a refractory metal layer containing titanium, molybdenum, tungsten, or the like. Heat resistance can be improved by using an aluminum material to which an element for preventing the generation of etching bumps and needle crystals (e.g., silicon, neodymium, or scandium) has been added.

[0141] Alternatively, a conductive metal oxide layer may be used as a conductive layer serving as the source electrode layer 405a and the drain electrode layer 405b (including a wiring layer formed from the same layer as the source electrode layer 405a and the drain electrode layer 405b). As a conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), an alloy of indium oxide and tin oxide (In2O3-SnO2, which is abbreviated to ITO in some cases), an alloy of indium oxide and zinc oxide (In2O3-ZnO), any of these metal oxide materials containing silicon oxide, or the like may be used.

[0142] The wiring layer 436a and the wiring layer 436b, which are in contact with the source electrode layer 405a and the drain electrode layer 405b, respectively, may be formed using a material similar to that of the source electrode layer 405a and the drain electrode layer 405b.

[0143] For each of the insulating layers 407, 427 and 437, an inorganic insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer or an aluminum oxynitride layer can typically be used.

[0144] For the protective insulating layer 409, an inorganic insulating layer such as a silicon nitride layer, an aluminum nitride layer, a silicon nitride oxide layer, or an aluminum nitride oxide layer may be used.

[0145] Furthermore, a planarization insulating layer may be formed over the protective insulating layer 409 to reduce surface unevenness due to the transistor. An organic material such as polyimide, acrylic, or benzocyclobutene may be used for the planarization insulating layer. As an alternative to such an organic material, a low-dielectric-constant material (a low-k material) or the like may be used. Note that the planarization insulating layer may be formed by stacking multiple insulating layers containing these materials.

[0146] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed. [Embodiment 5]

[0147] In this embodiment, an example of a transistor including an oxide semiconductor layer and an example of a manufacturing method thereof will be explained with reference to Fig. 11A to 11E are described in detail.

[0148] Fig. 11A to 11E are cross-sectional views illustrating a transistor manufacturing process. A transistor 510 shown here is similar to the transistor 510 shown in Fig. 10A, the transistor 410 is an inverted stacked transistor.

[0149] An oxide semiconductor used for a semiconductor layer of this embodiment is an i-oxide semiconductor (intrinsic oxide semiconductor) or substantially an i-oxide semiconductor (intrinsic oxide semiconductor). The i-oxide semiconductor (intrinsic oxide semiconductor) or substantially an i-oxide semiconductor (intrinsic oxide semiconductor) is obtained by removing hydrogen, which is an n-type impurity, from an oxide semiconductor and purifying the oxide semiconductor to contain as few impurities as possible that are not main components of the oxide semiconductor.

[0150] It is noted that the purified oxide semiconductor contains extremely few charge carriers and that the charge carrier concentration is lower than 1 10 14 cm -3 , preferably lower than 1 · 10 12 cm -3 , more preferably lower than 1 · 10 11 cm -3 , is. Such few charge carriers allow a current in an off state (off-state current) to be small enough.

[0151] More specifically, in the transistor including the oxide semiconductor layer described above, the reverse current density per channel width of 1 µm at room temperature (25 °C) under conditions where the channel length L of the transistor is 10 µm and the source-drain voltage is 3 V can be 100 zA µm -1 (1 · 10 -19 A · µm -1 ) or lower or furthermore 10 zA · µm -1 (1 · 10 -20 A · µm -1 ) or lower.

[0152] A transistor 510 containing a purified oxide semiconductor layer has little temperature dependence of the forward current and has an extremely small reverse current.

[0153] Based on Fig. 11A to 11E, a process for fabricating transistor 510 over a substrate 505 is described.

[0154] First, a conductive layer is formed over the substrate 505 having an insulating surface, and then a gate electrode layer 511 is formed by a first photolithography process. Note that a resist mask used in the photolithography process can be formed by an inkjet method. Forming the resist mask by an inkjet method does not require a photomask; thus, manufacturing costs can be reduced.

[0155] As the substrate 505 having an insulating surface, a substrate similar to the substrate 400 described in the above embodiment can be used. In this embodiment, a glass substrate is used as the substrate 505.

[0156] An insulating layer serving as a base may be provided between the substrate 505 and the gate electrode layer 511. The insulating layer has a function of preventing the diffusion of an impurity element from the substrate 505 and may be formed from one or more layers selected from a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, a silicon oxynitride layer, and the like.

[0157] The gate electrode layer 511 may be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these metal materials as a main component. The gate electrode layer 511 may have a single-layer structure or a stacked structure.

[0158] Subsequently, a gate insulating layer 507 is formed over the gate electrode layer 511. The gate insulating layer 507 may be formed by a plasma CVD method, a sputtering method, or the like. The gate insulating layer 507 may be formed from one or more layers selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, a hafnium oxide layer, and the like.

[0159] Further, in order to minimize the amount of hydrogen, hydroxyl, and moisture contained in the gate insulating layer 507 and an oxide semiconductor layer 530, it is preferable to preheat the substrate 505 over which the gate electrode layer 511 is formed, or the substrate 505 over which the gate electrode layer 511 and the gate insulating layer 507 are formed, in a preheating chamber of a sputtering apparatus as pretreatment for forming the oxide semiconductor layer 530, so that impurities such as hydrogen and moisture adsorbed in the substrate 505 are removed. A cryopump is preferably provided as an evacuation unit for the preheating chamber. This preheating step may preferably be performed on the substrate 505 over which layers up to and including a source electrode layer 515a and a drain electrode layer 515b are formed. It is noted that this preheating treatment can be omitted.

[0160] Subsequently, the oxide semiconductor layer 530 is formed over the gate insulating layer 507 with a thickness greater than or equal to 2 nm and less than or equal to 200 nm, preferably greater than or equal to 5 nm and less than or equal to 30 nm (see Fig. 11A).

[0161] For the oxide semiconductor layer 530, any of the four-component metal oxide, the three-component metal oxide, the two-component metal oxide, an In-O-based oxide semiconductor, an Sn-O-based oxide semiconductor, a Zn-O-based oxide semiconductor, and the like described in the above embodiment can be used.

[0162] It is particularly preferable to use a target having a composition ratio of In:Ga:Zn = 1:x:y (x is greater than or equal to 0, and y is greater than or equal to 0.5 and less than or equal to 5) as a target for forming the oxide semiconductor layer 530 by a sputtering method. For example, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] may be used. Alternatively, a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [molar ratio], a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:4 [molar ratio], or a target having a composition ratio of In2O3:Ga2O3:ZnO = 1:0:2 [molar ratio] may be used.

[0163] In this embodiment, an oxide semiconductor layer having an amorphous structure is formed by a sputtering method using an In-Ga-Zn-O based metal oxide target.

[0164] The relative density of a metal oxide in the metal oxide target is greater than or equal to 80%, preferably greater than or equal to 95%, and further preferably greater than or equal to 99.9%. Using a metal oxide target with a high relative density makes it possible to form an oxide semiconductor layer with a dense structure.

[0165] The atmosphere in which the oxide semiconductor layer 530 is formed is preferably a rare gas atmosphere (typically an argon atmosphere), an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically argon) and oxygen. Specifically, for example, an atmosphere of a high-purity gas from which impurities such as hydrogen, water, hydroxyl, or hydride have been removed so that the impurity concentration is 1 ppm or lower is preferably used (so that the impurity concentration is preferably 10 ppb or lower).

[0166] In the formation of the oxide semiconductor film 530, for example, a process object is held in a treatment chamber maintained under a negative pressure, and the process object may be heated such that the temperature of the process object is greater than or equal to 100°C and lower than 550°C, preferably greater than or equal to 200°C and lower than or equal to 400°C. Alternatively, the temperature of the process object in the formation of the oxide semiconductor film 530 may be room temperature (25°C ± 10°C (greater than or equal to 15°C and lower than or equal to 35°C)). Then, a sputtering gas from which hydrogen, water, or the like has been removed is introduced while removing moisture in the treatment chamber, and the above-mentioned target is used, thereby forming the oxide semiconductor film 530.The oxide semiconductor layer 530 is formed while heating the process object, so that impurities contained in the oxide semiconductor layer can be reduced. Furthermore, damage due to sputtering can be reduced. To remove moisture in the treatment chamber, a getter vacuum pump is preferably used. For example, a cryopump, an ion pump, a titanium sublimation pump, or the like can be used. Alternatively, a turbopump equipped with a cold trap can be used. By evacuating with the cryopump or the like, hydrogen, water, and the like can be removed from the treatment chamber, whereby the impurity concentration in the oxide semiconductor layer 530 can be reduced.

[0167] The oxide semiconductor layer 530 can be formed, for example, under the following conditions: the distance between the processing object and the target is 170 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is an oxygen atmosphere (the oxygen content is 100%), an argon atmosphere (the argon content is 100%), or a mixed atmosphere containing oxygen and argon. Since powdery substances (also referred to as particles or dust) generated during layer formation can be reduced and the layer thickness can be uniformed, a pulse DC power source is preferably used. The thickness of the oxide semiconductor layer 530 is greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 1 nm and less than or equal to 30 nm, more preferably greater than or equal to 1 nm and less than or equal to 10 nm.With the oxide semiconductor layer 530 having such a thickness, a short-channel effect due to miniaturization can be suppressed. Note that the appropriate thickness varies depending on the oxide semiconductor material to be used, the intended use of the semiconductor device, and the like; so the thickness can be determined in accordance with the material, the intended use, and the like.

[0168] It is noted that, before forming the oxide semiconductor layer 530 by a sputtering process, a substance attached to a surface on which the oxide semiconductor layer 530 is to be formed (e.g., a surface of the gate insulating film 507) is preferably removed by reverse sputtering, in which an argon gas is introduced and a plasma is generated. Unlike normal sputtering in which ions collide with a sputtering target, reverse sputtering is a process in which ions collide with a process surface, thereby changing the surface. As an example of a process for causing ions to collide with a process surface, there is a process in which a high-frequency voltage is applied to the process surface in an argon atmosphere, thereby generating a plasma near the process object.It is noted that instead of an argon atmosphere, an atmosphere of nitrogen, helium, oxygen or the like may be used.

[0169] Subsequently, the oxide semiconductor layer 530 is processed into an island-shaped oxide semiconductor layer through a second photolithography process. Note that a resist mask used in the photolithography process can be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the need for a photomask, thus reducing manufacturing costs.

[0170] If a contact hole is formed in the gate insulating layer 507, a step of forming the contact hole may be performed simultaneously with the processing of the oxide semiconductor layer 530.

[0171] For etching the oxide semiconductor layer 530, either wet etching or dry etching, or both, can be used. As an etchant used for wet etching the oxide semiconductor layer 530, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, or the like, can be used. An etchant such as ITO-07N (manufactured by KANTO CHEMICAL CO., INC.) can also be used.

[0172] Then, a heat treatment (first heat treatment) is carried out on the oxide semiconductor layer, so that an oxide semiconductor layer 531 is formed (see Fig. 11B). The first heat treatment removes excess hydrogen (including water and hydroxyl) in the oxide semiconductor layer and improves the structure of the oxide semiconductor layer, allowing impurity levels in the energy gap to be reduced. The temperature of the first heat treatment is, for example, greater than or equal to 300°C and less than or equal to 550°C, or greater than or equal to 400°C and less than or equal to 500°C.

[0173] The heat treatment can be performed by placing a process object into an electric furnace using a resistance heating element or the like and heating it at 450 °C for one hour under a nitrogen atmosphere. During the heat treatment, the oxide semiconductor layer is not exposed to air to prevent the ingress of water and hydrogen.

[0174] The heat treatment apparatus is not limited to an electric furnace; the heat treatment apparatus may be an apparatus that heats a process object using thermal conditions or heat radiation from a medium such as heated gas or the like. For example, an RTA (Rapid Thermal Annealing) apparatus such as an LRTA (Lamp Rapid Thermal Annealing) apparatus or a GRTA (Gas Rapid Thermal Annealing) apparatus may be used. An LRTA apparatus is an apparatus for heating a process object using light radiation (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.A GRTA device is a device for heat treatment using a high-temperature gas. The gas used is an inert gas that does not react with a process object during heat treatment, such as nitrogen or a noble gas such as argon.

[0175] For example, GRTA treatment can be performed as the initial heat treatment in the following manner. The process object is placed in a heated inert gas atmosphere, heated for several minutes, and then removed from the inert gas atmosphere. GRTA treatment enables high-temperature heat treatment in a short time. Moreover, GRTA treatment itself can utilize conditions where the temperature exceeds the upper temperature limit of the process object. It should be noted that the inert gas can be changed to a gas containing oxygen during the process. This is because impurity levels in the energy gap due to oxygen deficiency can be reduced by performing the initial heat treatment in an atmosphere containing oxygen.

[0176] Note that, as an inert gas atmosphere, it is preferable to use an atmosphere containing nitrogen or a rare gas (e.g., helium, neon, or argon) as its main component and not containing water, hydrogen, or the like. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0177] In any case, the impurities are reduced by the first heat treatment, so that the i-oxide semiconductor layer (intrinsic oxide semiconductor layer) or substantially i-oxide semiconductor layer is obtained. Accordingly, a transistor with substantially excellent characteristics can be realized.

[0178] The above heat treatment (first heat treatment) removes hydrogen, water, and the like, and thus may be referred to as a dehydration treatment, dehydrogenation treatment, or the like. The dehydration treatment or dehydrogenation treatment may be performed after the formation of the oxide semiconductor layer 530 and before the oxide semiconductor layer 530 is processed into the island-shaped oxide semiconductor layer. This dehydration treatment or dehydrogenation treatment may be performed once or multiple times.

[0179] The first heat treatment may be carried out at any of the following timings instead of the above timing: after forming a source electrode layer and a drain electrode layer, after forming an insulating layer over the source electrode layer and the drain electrode layer, and the like.

[0180] Subsequently, a conductive layer to become a source electrode layer and a drain electrode layer (including wiring formed from the same layer as the source electrode layer and the drain electrode layer) is formed over the gate insulating layer 507 and the oxide semiconductor layer 531. The conductive layer used to form the source electrode layer and the drain electrode layer can be formed using any of the materials described in the above embodiment.

[0181] In a third photolithography process, a resist mask is formed over the conductive layer and the source electrode layer 515a and the drain electrode layer 515b are formed by selective etching, after which the resist mask is removed (see Fig. 11C).

[0182] The exposure at the time of forming the resist mask in the third photolithography process can be performed using ultraviolet light, KrF laser light, or ArF laser light. Note that the channel length (L) of the transistor is determined by the distance between the source electrode layer and the drain electrode layer. Thus, when exposing to form a mask for a transistor with a channel length (L) of less than 25 nm, it is preferable to use extreme ultraviolet light whose wavelength is no longer than several nanometers to several tens of nanometers. When exposing using extreme ultraviolet light, the resolution is high and the depth of field is large. For these reasons, the channel length (L) of the subsequently completed transistor can be greater than or equal to 10 nm and less than or equal to 1000 nm (1 μm), and the circuit can operate at high speed.In addition, the power consumption of the semiconductor device can be reduced by miniaturization.

[0183] To reduce the number of photomasks and the number of photolithography processes, the etching step can be performed using a resist mask formed with a multi-tone mask. Since a resist mask formed with a multi-tone mask includes regions of multiple thicknesses and its shape can be further changed by performing etching, the resist mask can be used in multiple etching steps to provide various patterns. Thus, with a multi-tone mask, a resist mask corresponding to at least two types of different patterns can be formed. Thus, the number of exposure masks can be reduced and the number of corresponding photolithography processes can also be reduced, thereby realizing process simplification.

[0184] Note that etching conditions are preferably optimized so that the oxide semiconductor layer 531 is not etched and divided when the conductive layer is etched. However, it is difficult to obtain etching conditions in which only the conductive layer is etched and the oxide semiconductor layer 531 is not etched at all. In some cases, a part of the oxide semiconductor layer 531 is etched when the conductive layer is etched, thereby forming the oxide semiconductor layer 531 with a groove portion (a recessed portion).

[0185] For etching the conductive layer, either wet etching or dry etching can be used. Note that dry etching is preferable in view of element miniaturization. If necessary, an etching gas and an etchant can be selected in accordance with a material to be etched. In this embodiment, a titanium layer is used as the conductive layer, and an In-Ga-Zn-O-based material is used for the oxide semiconductor layer 531; accordingly, in the case of using wet etching, an ammonia-hydrogen peroxide solution (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2) can be used as an etchant.

[0186] Subsequently, plasma treatment is preferably performed using a gas such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar) so that water, hydrogen, or the like attached to a surface of an exposed portion of the oxide semiconductor layer can be removed. If plasma treatment is performed, an insulating layer 516 serving as a protective insulating layer is formed after the plasma treatment without being exposed to the air.

[0187] The insulating layer 516 is preferably formed to a thickness of at least 1 nm by a method that does not introduce impurities such as water or nitrogen into the insulating layer 516, such as a sputtering method. When hydrogen is contained in the insulating layer 516, the hydrogen causes hydrogen to be introduced into the oxide semiconductor layer or oxygen to be extracted from the oxide semiconductor layer, thereby causing the back channel of the oxide semiconductor layer to have a lower resistance (and thus an n-type conductivity), so that a parasitic channel can be formed. As the insulating layer 516, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like is preferably used.

[0188] In this embodiment, a silicon oxide layer is formed to a thickness of 200 nm as the insulating layer 516 by a sputtering process. The substrate temperature during deposition can be greater than or equal to room temperature (25°C) and less than or equal to 300°C, and is 100°C in this embodiment. The silicon oxide layer can be deposited by a sputtering process in a rare gas atmosphere (typically an argon atmosphere), an oxygen atmosphere, or a mixed atmosphere containing a rare gas and oxygen. A silicon oxide target or a silicon target can be used as a target.

[0189] To remove moisture remaining in the deposition chamber of the insulating layer 516 simultaneously with the deposition of the oxide semiconductor layer 530, a getter vacuum pump (such as a cryopump) is preferably used. When the insulating layer 516 is deposited in the deposition chamber evacuated using a cryopump, the impurity concentration in the insulating layer 516 can be reduced. A turbopump equipped with a cold trap can be used as an evacuation unit for removing moisture remaining in the deposition chamber used to form the insulating layer 516.

[0190] A sputtering gas used to form the insulating layer 516 is preferably a high-purity gas from which impurities such as hydrogen or water have been removed.

[0191] Subsequently, a second heat treatment is performed in an inert gas atmosphere or in an oxygen gas atmosphere. The second heat treatment is performed at a temperature greater than or equal to 200°C and less than or equal to 450°C, preferably greater than or equal to 250°C and less than or equal to 350°C. For example, the heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere. The second heat treatment can reduce the variation in electrical characteristics of the transistor. By supplying oxygen from the insulating layer 516 to the oxide semiconductor layer 531, oxygen vacancies in the oxide semiconductor layer 531 are reduced, whereby an i-oxide semiconductor layer (intrinsic oxide semiconductor layer) or substantially i-oxide semiconductor layer can be formed.

[0192] In this embodiment, the second heat treatment is performed after the formation of the insulating layer 516; however, the timing of the second heat treatment is not limited thereto. For example, the first heat treatment and the second heat treatment may be performed sequentially, or the first heat treatment may also function as the second heat treatment.

[0193] In the manner described above, the oxide semiconductor layer 531 is cleaned by the first heat treatment and the second heat treatment so that it contains as few impurities as possible that are not main components of the oxide semiconductor layer, whereby the oxide semiconductor layer 531 can become an i-oxide semiconductor layer (oxide intrinsic semiconductor layer).

[0194] The process described above forms the transistor 510 (see Fig. 11D).

[0195] It is preferable to further form a protective insulating layer 506 over the insulating layer 516 (see Fig. 11E). The protective insulating layer 506 prevents the introduction of hydrogen, water, and the like from the outside. For example, a silicon nitride layer, an aluminum nitride layer, or the like can be used as the protective insulating layer 506. The formation method of the protective insulating layer 506 is not particularly limited; however, an RF sputtering method is suitable for forming the protective insulating layer 506 because it achieves high productivity.

[0196] After the formation of the protective insulating layer 506, a further heat treatment may be carried out in the air for 1 hour to 30 hours at a temperature greater than or equal to 100 °C and less than or equal to 200 °C.

[0197] A transistor including a purified oxide semiconductor layer and fabricated according to the embodiment described above has a characteristic of a significantly small off-state current. Thus, the potential of a node can be easily maintained using the transistor. Using such a transistor for a pulse signal output circuit and a shift register can significantly reduce the likelihood of causing malfunctions in the pulse signal output circuit and the shift register.

[0198] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed. [Embodiment 6]

[0199] By using the shift register, the example of which is described in any one of Embodiments 1 to 3, a semiconductor device with a display function (also referred to as a display device) can be manufactured. Furthermore, part or all of a drive circuit can be formed over the same substrate as a pixel portion, thereby achieving a system on the display screen.

[0200] As a display element used for the display device, a liquid crystal element (also called a liquid crystal display element) or a light-emitting element (also called a light-emitting display element) can be used. A light-emitting element includes, in its category, an element whose brightness is controlled by a current or by a voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. In addition, a display medium whose contrast is changed by an electrical effect, such as an electronic ink, can be used.

[0201] In Fig. 12A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a first substrate 4001, wherein the pixel portion 4002 is sealed between the first substrate 4001 and a second substrate 4006. In Fig. 12A, in a region different from a region surrounded by the sealant 4005, a scanning line driving circuit 4004 and a signal line driving circuit 4003, which are separately prepared over a substrate, are mounted above the first substrate 4001. Further, a plurality of signals and potentials are supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4002 from flexible printed circuits (FPCs) 4018a and 4018b.

[0202] In Fig. 12B and Fig. 12C, the sealant 4005 is provided so as to surround the pixel portion 4002 and the scan line driver circuit 4004 provided above the first substrate 4001. The second substrate 4006 is provided above the pixel portion 4002 and the scan line driver circuit 4004. Thus, the pixel portion 4002 and the scan line driver circuit 4004 are sealed by the first substrate 4001, the sealant 4005, and the second substrate 4006 together with the display element. Fig. 12B and Fig. 12C, the signal line driver circuit 4003, which is formed over a separately prepared substrate, is mounted in a region different from a region surrounded by the sealant 4005 over the first substrate 4001. In Fig. 12B and Fig. 12C, a plurality of signals and potentials are supplied to the signal line driving circuit 4003, which is formed separately, and the scanning line driving circuit 4004 or the pixel portion 4002 from an FPC 4018.

[0203] Although Fig. 12B and Fig. 12C each illustrate an example in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, the present invention is not limited to this structure. The scanning line driving circuit may be separately formed and then mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and then mounted.

[0204] It is noted that a connection method of a separately formed driver circuit is not particularly limited, and a chip-on-glass (COG) method, a wire bonding method, a film automatic bonding (TAB) method, or the like may be used. Fig. 12A illustrates an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by a COG method. Fig. 12B illustrates an example in which the signal line driving circuit 4003 is mounted by a COG method. Fig. 12C illustrates an example in which the signal line driving circuit 4003 is mounted by a TAB method.

[0205] Furthermore, the display device includes a screen in which the display element is sealed, and a module in which an IC or the like containing a controller is attached to the screen.

[0206] Note that a display device in this specification means an image display device, a display device, or a light source (including an illumination device). Furthermore, the display device also includes the following modules in its category: a module to which a connector such as an FPC, a TAB sheet, or a TCP is attached; a module having a TAB sheet or a TCP at the tip, from which a printed circuit board is provided; and a module in which an integrated circuit (IC) is directly attached to a display element by a COG method.

[0207] Further, the pixel portion provided above the first substrate includes a plurality of transistors, and for the transistors, the transistors illustrated in the above-mentioned embodiment as an example can be used.

[0208] If a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular-weight liquid crystal, a high-molecular-weight liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like is used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on the conditions.

[0209] Alternatively, a liquid crystal exhibiting a blue phase, for which an alignment layer is unnecessary, can be used. A blue phase is one of the liquid crystal phases that is generated just before a cholesteric phase changes to an isotropic phase as the temperature of a cholesteric liquid crystal is raised. Since the blue phase only appears in a narrow temperature range, a liquid crystal composition containing a chiral agent at 5 wt% or more is used for a liquid crystal layer to improve the temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 ms or less, possesses optical isotropy, which eliminates the need for an alignment process, and has low viewing angle dependence.Furthermore, no alignment layer needs to be provided, and thus no polishing treatment is necessary. Thus, damage caused by electrostatic discharge during polishing can be prevented, and defects and damage to the liquid crystal display device during the manufacturing process can be reduced. Thus, liquid crystal display devices can be manufactured with improved productivity.

[0210] The specific resistance of the liquid crystal material is greater than or equal to 1 10 9 Ω· cm, preferably greater than or equal to 1 · 10 11 Ω· cm, more preferably greater than or equal to 1 · 10 12 Ω· cm. It is noted that the resistivity in this specification is measured at 20 °C.

[0211] The size of a storage capacitor formed in the liquid crystal display device is adjusted in consideration of the leakage current of the transistor or the like provided in the pixel portion so that the charge can be retained for a predetermined period. The size of the storage capacitor can be adjusted in consideration of the off-state current of a transistor or the like.

[0212] For the liquid crystal display device, a twisted nematic mode (TN mode), an in-plane switching mode (IPS mode), a stray field switching mode (FFS mode), an axially symmetrically aligned microcell mode (ASM mode), an optically compensated birefringence mode (OCB mode), a ferroelectric liquid crystal mode (FLC mode), an antiferroelectric liquid crystal mode (AFLC mode), or the like is used.

[0213] A normally black liquid crystal display device, such as a see-through liquid crystal display device, that utilizes a vertical alignment (VA) mode is preferable. The VA liquid crystal display device has a type of shape in which the alignment of liquid crystal molecules of a liquid crystal display panel is controlled. In the VA liquid crystal display device, liquid crystal molecules are aligned in a vertical direction with respect to a panel surface when no voltage is applied. Some examples of the vertical alignment mode are given. For example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, or the like can be used.In addition, it is possible to use a method called domain multiplication or multi-domain design, in which a pixel is divided into several regions (subpixels) and the molecules in their respective regions are aligned in different directions.

[0214] In the display device, a black matrix (a light-blocking layer), an optical element (an optical substrate) such as a polarizing element, a retarder element, or an anti-reflection element, and the like are provided as necessary. For example, circular polarization can be achieved by using a polarizing substrate and a retarder substrate. Furthermore, a backlight, a sidelight, or the like can be used as a light source.

[0215] As a display method in the pixel portion, a progressive scan method, an interlaced scan method, or the like can be used. Furthermore, the color elements controlled in one pixel at the time of color display are not limited to three colors: R, G, and B (where R, G, and B correspond to red, green, and blue, in this order). For example, R, G, B, and W (where W corresponds to white); R, G, B, and one or more of yellow, cyan, magenta, and the like can be used; or the like can be used. Furthermore, the sizes of the display areas between respective dots of color elements can be different. It is noted that the disclosed invention is not limited to application to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display.

[0216] Alternatively, a light-emitting element utilizing electroluminescence may be used as the display element included in the display device. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. Generally, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

[0217] In an organic EL element, by applying a voltage to a light-emitting element, electrons and holes are injected from a pair of electrodes separately into a layer containing an organic light-emitting compound, while a current flows. The charge carriers (electrons and holes) are allowed to recombine, exciting the organic light-emitting compound. The organic light-emitting compound returns from the excited state to a ground state, thereby emitting light. Because of this mechanism, the light-emitting element is called a current-excitation light-emitting element.

[0218] According to their element structures, inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film inorganic EL elements. A dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. Its light-emitting mechanism is donor-acceptor recombination-type light emission, which utilizes a donor level and an acceptor level. An inorganic thin-film EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes. Its light-emitting mechanism is localized-type light emission, which utilizes electron transfer between internal switching metal ions.

[0219] Furthermore, electronic paper, which uses electronic ink, can be used as the display device. Electronic paper is also called an electrophoretic display device (electrophoretic display) and has advantages in that it has the same degree of readability as ordinary paper, consumes less power than other display devices, and can be configured to have a thin and lightweight form.

[0220] An electrophoretic display device can have various operating modes. An electrophoretic display device contains multiple microcapsules dispersed in a solvent or solute, each microcapsule containing positively charged first particles and negatively charged second particles. By applying an electric field to the microcapsules, the particles within the microcapsules move in opposite directions, displaying only the color of the particles that cluster on one side. Note that the first and second particles each contain a pigment and do not move without an electric field. Furthermore, the first and second particles have different colors (which may be colorless).

[0221] Thus, an electrophoretic display device is a display device that uses a so-called dielectrophoretic effect, by which a substance with a high dielectric constant moves towards an area of high electric field.

[0222] A solution in which the above microcapsules are dispersed in a solvent is called electronic ink. This electronic ink can be printed on a surface made of glass, plastic, fabric, paper, or the like. Furthermore, color display can also be achieved using a color filter or particles containing a pigment.

[0223] It is noted that the first particles and the second particles in the microcapsules may each be formed using a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoretic material, or may be formed using a composite material of any of these.

[0224] As the electronic paper, a display device using a twisting-ball display system can be used. The twisting-ball display system refers to a method in which spherical particles, each colored black and white, are arranged between a first electrode layer and a second electrode layer, which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles to perform a display.

[0225] The pulse signal output circuit described in Embodiment 1 or Embodiment 2 is used for the display device whose example is described above, and the display device can have a variety of functions.

[0226] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed. [Embodiment 7]

[0227] A semiconductor device disclosed in this specification can be used in a variety of electronic devices (including game machines). Examples of electronic devices include a television set (also referred to as a television or television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone headset (also referred to as a mobile phone or a mobile phone device), a portable game machine, a personal digital assistant, an audio playback device, a large-scale game machine such as a pinball machine, and the like.

[0228] Fig. Figure 13A illustrates a laptop personal computer including at least the semiconductor device disclosed in this specification as a component. The laptop personal computer includes a main body 3001, a casing 3002, a display section 3003, a keyboard 3004, and the like.

[0229] Fig. 13B illustrates a personal digital assistant (PDA) including at least the semiconductor device disclosed in this specification as a component. A main body 3021 is provided with a display section 3023, an external interface 3025, operation buttons 3024, and the like. A stylus 3022 is included as an accessory for operation.

[0230] The semiconductor device disclosed in this patent can be used as an electronic paper. Fig. Figure 13C illustrates an e-book reader that includes the electronic paper as a component. Fig. 13C illustrates an example of the e-book reader. For example, an e-book reader 2700 includes two casings 2701 and 2703. The casings 2701 and 2703 are combined with a hinge 2711 so that the e-book reader 2700 can be opened and closed using the hinge 2711 as an axis. With such a structure, the e-book reader 2700 can operate like a paper book.

[0231] A display section 2705 and a display section 2707 are included in the housing 2701 and the housing 2703, respectively. The display section 2705 and the display section 2707 can display one image or different images. If the display section 2705 and the display section 2707 display different images, for example, a display section on the right side (the display section 2705 in Fig. 13C) display text and can be a display section on the left side (the display section 2707 in Fig. 13C) Display images.

[0232] Fig. 13C illustrates an example in which the housing 2701 includes an operation section and the like. For example, the housing 2701 includes a power switch 2721, operation buttons 2723, a speaker 2725, and the like. The operation buttons 2723 can be used to turn pages. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display section of the housing. In addition, a terminal for external connections (e.g., an earphone jack or a USB port), a recording medium insertion section, and the like may be provided on the back surface or on a side surface of the housing. In addition, the e-book reader 2700 can function as an electronic dictionary.

[0233] Furthermore, the e-book reader 2700 can transmit and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an e-book server.

[0234] Fig. 13D illustrates a mobile phone including at least the semiconductor device disclosed in this specification as one component. The mobile phone includes two housings 2800 and 2801. The housing 2801 includes a display screen 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, a connector 2808 for external connections, and the like. Furthermore, the housing 2800 includes a solar cell 2810 for storing electricity in a personal digital assistant, a slot 2811 for external storage, and the like. Furthermore, an antenna is incorporated into the housing 2801.

[0235] Furthermore, the display screen 2802 includes a touch panel. Fig. In Figure 13D, a plurality of operation buttons 2805, displayed as images, are indicated by dashed lines. Note that the mobile phone includes a voltage booster circuit for boosting a voltage output from the solar cell 2810 to a voltage necessary for each circuit.

[0236] The display direction of the display screen 2802 is changed as necessary depending on a usage pattern. Furthermore, since the mobile phone includes the camera lens 2807 on the same surface as the display screen 2802, it can be used as a video phone. The speaker 2803 and the microphone 2804 can be used for video phone calls, recording, playback, and the like, as well as for voice calls. In addition, the housings 2800 and 2801, which are arranged as shown in Fig. 13D overlap by sliding; thus, the size of the mobile phone can be reduced, making the mobile phone suitable for carrying.

[0237] The external connection port 2808 can be connected to an AC adapter and a variety of cables, such as a USB cable, enabling charging and data communication with a personal computer or the like. Furthermore, by inserting a storage medium into the external storage slot 2811, a large amount of data can be stored and moved.

[0238] Furthermore, in addition to the above functions, the mobile phone may have an infrared communication function, a television reception function, or the like.

[0239] Fig. Figure 13E illustrates a digital video camera incorporating at least the semiconductor device disclosed in this specification as a component. The digital video camera includes a main body 3051, a first display portion 3057, a viewfinder portion 3053, operation switches 3054, a second display portion 3055, a battery 3056, and the like.

[0240] Fig. 13F illustrates an example of a television set including at least the semiconductor device disclosed in this specification as a component. In a television set 9600, a display section 9603 is incorporated into a housing 9601. The display section 9603 can display images. Here, the housing 9601 is supported by a stand 9605.

[0241] The television 9600 can be operated by a control switch of the cabinet 9601 or by a remote control. Furthermore, the remote control may include a display section for displaying data output from the remote control.

[0242] Note that the television 9600 includes a receiver, a modem, and the like. The receiver can receive general television broadcasts. Furthermore, one-way data communication (from a transmitter to a receiver) or two-way data communication (between a transmitter and a receiver, or between receivers) can be performed when the television is connected to a communication network with wires or wirelessly via a modem.

[0243] The structures, methods, and the like described in this embodiment may be combined with any of the structures, methods, and the like described in the other embodiments as needed.

[0244] The invention further provides the following embodiments: 1. Pulse signal output circuit comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; a ninth transistor; and a tenth transistor, wherein a first terminal of the first transistor, a first terminal of the second transistor and a first output terminal are electrically connected to each other, wherein a first terminal of the third transistor, a first terminal of the fourth transistor and a second output terminal are electrically connected to each other, wherein a first terminal of the fifth transistor, a first terminal of the sixth transistor and a first terminal of the seventh transistor are electrically connected to each other, wherein a gate terminal of the first transistor, a gate terminal of the third transistor and a second terminal of the seventh transistor are electrically connected to each other, wherein a gate terminal of the second transistor, a gate terminal of the fourth transistor, a gate terminal of the sixth transistor, a first terminal of the eighth transistor and a first terminal of the ninth transistor are electrically connected to each other, wherein a second terminal of the eighth transistor and a first terminal of the tenth transistor are electrically connected to each other, wherein a ratio W / L of a channel width W to a channel length L of the first transistor and a ratio W / L of a channel width W to a channel length L of the third transistor are each greater than a ratio W / L of a channel width W to a channel length L of the sixth transistor, wherein a ratio W / L of a channel width W to a channel length L of the fifth transistor is greater than the ratio W / L of the channel width W to the channel length L of the sixth transistor, wherein the ratio W / L of the channel width W to the channel length L of the fifth transistor is equal to a ratio W / L of a channel width W to a channel length L of the seventh transistor, and wherein a ratio W / L of the channel width W to the channel length L of the third transistor is greater than a ratio W / L of a channel width W to a channel length L of the fourth transistor. 2. Pulse signal output circuit according to embodiment 1, wherein a first clock signal is input to a second terminal of the first transistor and to a second terminal of the third transistor, wherein a second clock signal is input to a gate terminal of the eighth transistor, wherein a third clock signal is input to a gate terminal of the tenth transistor, wherein a first potential is supplied to a second terminal of the second transistor, a second terminal of the fourth transistor, a second terminal of the sixth transistor and a second terminal of the ninth transistor, wherein a second terminal of the fifth transistor, a gate terminal of the seventh transistor and a second terminal of the tenth transistor are supplied with a second potential which is higher than the first potential, wherein a first pulse signal is input to a gate terminal of the fifth transistor and to a gate terminal of the ninth transistor, and wherein a second pulse signal is output from the first output terminal or from the second output terminal. 3. The pulse signal output circuit according to embodiment 1, further comprising a capacitor, wherein the capacitor is electrically connected to the gate terminal of the second transistor, to the gate terminal of the fourth transistor, to the gate terminal of the sixth transistor, to the first terminal of the eighth transistor, and to the first terminal of the ninth transistor. 4. The pulse signal output circuit according to embodiment 1, further comprising an eleventh transistor, wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, to the gate terminal of the fourth transistor, to the gate terminal of the sixth transistor, to the first terminal of the eighth transistor and to the first terminal of the ninth transistor, and wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor. 5. Pulse signal output circuit according to embodiment 4, wherein a second potential is supplied to the second terminal of the eleventh transistor, and wherein a third pulse signal is input to a gate terminal of the eleventh transistor. 6. A shift register comprising a plurality of pulse signal output circuits according to embodiment 1. 7. n-stage shift register, which includes: two pulse signal output circuits, each of the two pulse signal output circuits being the pulse signal output circuit according to Embodiment 1; and n pulse signal output circuits, each of the n pulse signal output circuits comprising an eleventh transistor, wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, to the gate terminal of the fourth transistor, to the gate terminal of the sixth transistor, to the first terminal of the eighth transistor and to the first terminal of the ninth transistor, and wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor, wherein a channel width W of the eighth transistor in the pulse signal output circuit according to embodiment 1 is larger than a channel width W of the eighth transistor in one of the n pulse signal output circuits. 8. n-stage shift register, which includes: two pulse signal output circuits, each of the two pulse signal output circuits being the pulse signal output circuit according to Embodiment 1; and n pulse signal output circuits, each of the n pulse signal output circuits comprising an eleventh transistor, wherein a first terminal of the eleventh transistor is electrically connected to the gate terminal of the second transistor, to the gate terminal of the fourth transistor, to the gate terminal of the sixth transistor, to the first terminal of the eighth transistor and to the first terminal of the ninth transistor, and wherein a channel width W of the eighth transistor and a channel width W of the tenth transistor are each smaller than a channel width W of the eleventh transistor, wherein a channel width W of the tenth transistor in the pulse signal output circuit according to embodiment 1 is larger than a channel width W of the tenth transistor in one of the n pulse signal output circuits. 9. The pulse signal output circuit according to embodiment 1, wherein the first or the second or the third or the fourth or the fifth or the sixth or the seventh or the eighth or the ninth or the tenth transistor comprises an oxide semiconductor layer. 10. The shift register according to embodiment 6, wherein the first or the second or the third or the fourth or the fifth or the sixth or the seventh or the eighth or the ninth or the tenth transistor comprises an oxide semiconductor layer. Explanation of reference symbols

[0245] 11: Signal line, 12: Signal line, 13: Signal line, 14: Signal line, 15: Wiring, 21: Input terminal, 22: Input terminal: 23: Input terminal, 24: Input terminal, 25: Input terminal, 26: Output terminal, 27: Output terminal, 31: Power supply line, 32: Power supply line, 51: Period, 52: Period, 53: Period, 54: Period, 55: Period, 56: Period, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Transistor, 109: Transistor, 110: Transistor, 111: Transistor, 200: Pulse signal generating circuit, 201: first Input signal generating circuit, 202: second input signal generating circuit, 203: second input signal generating circuit, 204: dummy pulse signal generating circuit, 205: first input signal generating circuit, 206: second input signal generating circuit, 400: substrate, 401: gate electrode layer, 402: gate insulating layer,403: Oxide semiconductor layer, 405a: Source electrode layer, 405b: Drain electrode layer, 407: Insulating layer, 409: Protective insulating layer, 410: Transistor, 420: Transistor, 427: Insulating layer, 430: Transistor, 436a: Wiring layer, 436b: Wiring layer, 437: Insulating layer, 440: Transistor, 505: Substrate, 506: Protective insulating layer, 507: Gate insulating layer, 510: Transistor, 511: Gate electrode layer, 515a: Source electrode layer, 515b: Drain electrode layer, 516: Insulating layer, 530: Oxide semiconductor layer, 531: Oxide semiconductor layer, 2700: E-book reader, 2701: Package, 2703: Housing, 2705: Display section, 2707: Display section, 2711: Hinge, 2721: Power switch, 2723: Control button, 2725: Speaker, 2800: Housing, 2801: Housing, 2802: Display screen, 2803: Speaker, 2804: Microphone, 2805: Control button, 2806: Pointing device, 2807: Camera lens, 2808: Connector for external connections, 2810: Solar cell, 2811: Slot for external memory,3001: Main body, 3002: Housing, 3003: Display section, 3004: Keyboard, 3021: Main body, 3022: Stylus, 3023: Display section, 3024: Operation knob, 3025: External interface, 3051: Main body, 3053: Viewfinder section, 3054: Operation switch, 3055: Display section, 3056: Battery, 3057: Display section, 4001: Substrate, 4002: Pixel section, 4003: Signal line driving circuit, 4004: Scanning line driving circuit, 4005: Sealant, 4006: Substrate, 4018: FPC, 4018a: FPC, 4018b: FPC, 9600: TV, 9601: Housing, 9603: Display section and 9605: Foot,< / betrieb> < / schaltungskonfiguration> < / betrieb> < / schaltungskonfiguration>

Claims

[1] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is directly connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is directly connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is directly connected to a first power supply line (31), the other of the source and drain of the second transistor (104) being directly connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is directly connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is directly connected to a second power supply line (32), wherein a gate of the third transistor (108) is directly connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is directly connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is directly connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is directly connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is directly connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is directly connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is directly connected to the first power supply line (31), the other of the source and drain of the seventh transistor being directly connected to the second wiring, wherein one of a source and a drain of the eighth transistor is directly connected to a gate of the seventh transistor, the other of the source and drain of the eighth transistor being directly connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is directly connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is directly connected to the first power supply line (31), wherein a gate of the tenth transistor is directly connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, and wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor. [2] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is directly connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is directly connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is directly connected to a first power supply line (31), the other of the source and drain of the second transistor (104) being directly connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is directly connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is directly connected to a second power supply line (32), wherein a gate of the third transistor (108) is directly connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is directly connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is directly connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is directly connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is directly connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is directly connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is directly connected to the first power supply line (31), the other of the source and drain of the seventh transistor being directly connected to the second wiring, wherein one of a source and a drain of the eighth transistor is directly connected to a gate of the seventh transistor, the other of the source and drain of the eighth transistor being directly connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is directly connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is directly connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is directly connected to the first power supply line (31), wherein a gate of the tenth transistor is directly connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor, wherein a ratio W / L of a channel width W to a channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the second transistor (104), and wherein the ratio W / L of the channel width W to the channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the fifth transistor (106). [3] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is electrically connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is electrically connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is electrically connected to a first power supply line (31), wherein the other of the source and the drain of the second transistor (104) is electrically connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is electrically connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is electrically connected to a second power supply line (32), wherein a gate of the third transistor (108) is electrically connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is electrically connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is electrically connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is electrically connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is electrically connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is electrically connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is electrically connected to the first power supply line (31), wherein the other of the source and drain of the seventh transistor is electrically connected to the second wiring, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the seventh transistor, wherein the other of the source and drain of the eighth transistor is electrically connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is electrically connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is electrically connected to the first power supply line (31), wherein a gate of the tenth transistor is electrically connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, and wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor. [4] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) is electrically connected to a first clock line (21), wherein the other of the source and the drain of the first transistor (103) is electrically connected to a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) is electrically connected to a first power supply line (31), wherein the other of the source and the drain of the second transistor (104) is electrically connected to the first wiring (27), wherein one of a source and a drain of the third transistor (108) is electrically connected to a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) is electrically connected to a second power supply line (32), wherein a gate of the third transistor (108) is electrically connected to a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) is electrically connected to a gate of the first transistor (103), wherein a gate of the fourth transistor (107) is electrically connected to the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) is electrically connected to the first power supply line (31), wherein a gate of the fifth transistor (106) is electrically connected to the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor is electrically connected to the second clock line (22), wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor is electrically connected to the first power supply line (31), wherein the other of the source and drain of the seventh transistor is electrically connected to the second wiring, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the seventh transistor, wherein the other of the source and drain of the eighth transistor is electrically connected to the second power supply line (32), wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the sixth transistor, wherein a gate of the ninth transistor is electrically connected to the second power supply line (32), wherein one of a source and a drain of the tenth transistor is electrically connected to the first power supply line (31), wherein a gate of the tenth transistor is electrically connected to the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor, wherein a ratio W / L of a channel width W to a channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the second transistor (104), and wherein the ratio W / L of the channel width W to the channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the fifth transistor (106). [5] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) has continuous electrical continuity with a first clock line (21), wherein the other of the source and the drain of the first transistor (103) has continuous electrical continuity with a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) has continuous electrical continuity with a first power supply line (31), the other of the source and drain of the second transistor (104) having continuous electrical continuity with the first wiring (27), wherein one of a source and a drain of the third transistor (108) has continuous electrical continuity with a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) has continuous electrical continuity with a second power supply line (32), wherein a gate of the third transistor (108) has continuous electrical continuity with a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) has continuous electrical continuity with a gate of the first transistor (103), wherein a gate of the fourth transistor (107) has continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) has continuous electrical continuity with the first power supply line (31), wherein a gate of the fifth transistor (106) has continuous electrical continuity with the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor has continuous electrical continuity with the second clock line (22), wherein the other of the source and the drain of the sixth transistor has continuous electrical continuity with a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor has continuous electrical continuity with the first power supply line (31), the other of the source and drain of the seventh transistor having continuous electrical continuity with the second wiring, wherein one of a source and a drain of the eighth transistor has continuous electrical continuity with a gate of the seventh transistor, the other of the source and drain of the eighth transistor having continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the ninth transistor has continuous electrical continuity with a gate of the sixth transistor, wherein a gate of the ninth transistor has continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the tenth transistor has continuous electrical continuity with the first power supply line (31), wherein a gate of the tenth transistor has continuous electrical continuity with the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, and wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor. [6] A semiconductor device comprising: a first circuit (10_2); and a second circuit (10_3) adjacent to the first circuit (10_2), wherein the first circuit (10_2) comprises a first to fifth transistor, wherein the second circuit (10_3) comprises a sixth to tenth transistor, wherein one of a source and a drain of the first transistor (103) has continuous electrical continuity with a first clock line (21), wherein the other of the source and the drain of the first transistor (103) has continuous electrical continuity with a first wiring (27) configured to output a signal, wherein one of a source and a drain of the second transistor (104) has continuous electrical continuity with a first power supply line (31), the other of the source and drain of the second transistor (104) having continuous electrical continuity with the first wiring (27), wherein one of a source and a drain of the third transistor (108) has continuous electrical continuity with a gate of the second transistor (104), wherein the other of the source and drain of the third transistor (108) has continuous electrical continuity with a second power supply line (32), wherein a gate of the third transistor (108) has continuous electrical continuity with a second clock line (22), wherein one of a source and a drain of the fourth transistor (107) has continuous electrical continuity with a gate of the first transistor (103), wherein a gate of the fourth transistor (107) has continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the fifth transistor (106) has continuous electrical continuity with the first power supply line (31), wherein a gate of the fifth transistor (106) has continuous electrical continuity with the gate of the second transistor (104), wherein one of a source and a drain of the sixth transistor has continuous electrical continuity with the second clock line (22), wherein the other of the source and the drain of the sixth transistor has continuous electrical continuity with a second wiring configured to output a signal, wherein one of a source and a drain of the seventh transistor has continuous electrical continuity with the first power supply line (31), the other of the source and drain of the seventh transistor having continuous electrical continuity with the second wiring, wherein one of a source and a drain of the eighth transistor has continuous electrical continuity with a gate of the seventh transistor, the other of the source and drain of the eighth transistor having continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the ninth transistor has continuous electrical continuity with a gate of the sixth transistor, wherein a gate of the ninth transistor has continuous electrical continuity with the second power supply line (32), wherein one of a source and a drain of the tenth transistor has continuous electrical continuity with the first power supply line (31), wherein a gate of the tenth transistor has continuous electrical continuity with the gate of the seventh transistor, wherein a potential of the first power supply line (31) is supplied to the other of the source and the drain of the fourth transistor (107) at least through a channel formation region of the fifth transistor (106) when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the fourth transistor (107) at least through the channel formation region of the fifth transistor (106), wherein the potential of the first power supply line (31) is supplied to the other of the source and the drain of the ninth transistor at least through a channel formation region of the tenth transistor when the first power supply line (31) has an electrical continuity with the other of the source and the drain of the ninth transistor at least through the channel formation region of the tenth transistor, wherein the eighth transistor is configured to control a timing when a potential of the second power supply line (32) is supplied to the gate of the seventh transistor and the gate of the tenth transistor at least through a channel formation region of the eighth transistor, wherein a ratio W / L of a channel width W to a channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the second transistor (104), and wherein the ratio W / L of the channel width W to the channel length L of the first transistor (103) is greater than a ratio W / L of a channel width W to a channel length L of the fifth transistor (106).

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