METHOD FOR DECODING PCI EXPRESS ADDRESSES

Abstract

Device and method for the rapid decoding of addresses from PCle multifunction units using a lookup table containing target function data. One or more decoding guidelines (e.g., planned function) are provided in the header of the PCle request packet, thus eliminating the need to search for the target function in the endpoint during the decoding process. This enables decoding in complex multifunction units to be performed in a single decoder in a single step.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the field of data transmission and, more particularly, to a method for fast decoding addresses of PCIe multifunctional units using a target function lookup table. BACKGROUND OF THE INVENTION

[0002] Peripheral Component Interconnect Express (PCIe) is a standard for computer expansion cards developed to replace older PCI, PCI-X, and AGP bus standards. Recent versions of the PCe standard support hardware I / O virtualization. PCe relies on a point-to-point topology with separate serial connections connecting each device to the host. A PCe bus connection supports full-duplex data transfer between any two endpoints, with no limit on simultaneous access to multiple endpoints. PCe data transfer is embedded in packets, with the work of packetizing and unpacketing data and status message traffic handled by the transaction layer of the PCIe connector.

[0003] The document US 2011 / 0 219 161 A1 relates to a system comprising: a controller, wherein the controller is configured to be communicatively coupled to a Peripheral Component Interconnect Express (PCIE) multi-root input / output virtualization (IOV) environment via an Advanced High Performance Bus (AHB) interface, wherein the controller comprises a Content Addressable Memory (CAM) interface state machine, wherein the CAM interface state machine is configured to control operations of a communicatively coupled Content Addressable Memory (CAM), wherein the controller is configured to manage Virtual Function (VF) migration requests, to provide base address decoding functionality, and to manage base address updating in the PCIE multi-root IOV environment.

[0004] The publication US 2009 / 0 006 932 A1 relates to an apparatus for modifying a Peripheral Component Interconnect (PCI) Express packet digest. The apparatus comprises: a credit-based flow control interconnect device for generating a credit-based flow control interconnect transaction layer packet in which one or more bits of a digest section carry non-end-to-end cyclic redundancy check (ECRC) data.

[0005] A user manual “TMS320C645x DSP Peripheral Component Interconnect (PCI)” from Texas Instruments describes a PCI module in TMS320C645x units, in particular base address registers of this PCI module (PCI-SIG: PCI Express Base Specification - Revision 3.0. 2010, pages 53 to 57). SUMMARY OF THE INVENTION

[0006] The invention relates to methods for decoding PCI Express (PCIe) addresses, the features of which are specified in the corresponding independent claims. Embodiments of the invention are specified in the dependent claims.

[0007] A method for decoding PCI Express (PCIe) addresses is provided, the method comprising providing a lookup table in a PCIe host, the lookup table operable to map from an address range to a target function and utilizing the lookup table, sending an address and a proposed target function to a PCIe endpoint, decoding the received address at the PCIe endpoint utilizing the proposed target function, and verifying information of proposed target functions.

[0008] Also provided is a method for decoding PCI Express (PCIe) addresses for use in a PCIe host, the method comprising receiving PCIe requests each having an address, determining a target device function according to each address, and assigning the target functions to requests issued to the PCIe endpoints.

[0009] Further provided is a method for decoding PCI Express (PCIe) addresses for use in a PCIe host, the method comprising scanning PCIe devices and functions during a PCIe bus initialization phase, assigning address ranges to functions, and building a lookup table that maps the address ranges to the target functions.

[0010] Also provided is a method for decoding PCI Express (PCIe) addresses for use in a PCIe endpoint, the method comprising receiving a read / write request packet from a PCIe host, determining whether the request packet includes recommended target function data, and if so, validating the target function data received in the packet. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention is described herein by way of example only with reference to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating an exemplary PCIe network with a PCIe fast address decoding mechanism of the present invention; Fig. 2 is a schematic diagram illustrating a first exemplary parallel approach to address decoding in a PCIe endpoint; Fig. 3 is a schematic diagram illustrating a second example sequential approach to address decoding in a PCIe endpoint; Fig. 4 is a schematic diagram illustrating a third exemplary parallel decoding data approach to decoding addresses in a PCIe endpoint; and Fig. 5 is a flowchart illustrating the method of the present invention for fast decoding of PCIe addresses. DETAILED DESCRIPTION OF THE INVENTION

[0012] Recent extensions to the PCI Express (PCIe) standard, such as Alternate RequestorID Interpretation (ARI) and Single Root I / O Virtualization (SR-IOV), enable a higher degree of integration of multifunction applications within a single PCIe unit. Such applications utilize a common PCIe connection to the host, which is shared by various functions implemented on the unit. A system diagram illustrating an exemplary PCIe network with a fast PCIe address decoding mechanism of the present invention is shown in Fig. 1 shown.

[0013] The system, generally designated 10, includes a PCI host 12, a PCIe switch 22, and a plurality of PCIe endpoints 24. The PCIe switch 22 is connected to the PCIe host and the endpoints via PCIe links 20. The PCIe host 12 includes one or more processor cores 14 and a PCIe root complex 16, which includes a table 18 with address-function mappings. The PCIe endpoints 24 include an address decoding circuit 26, a plurality of functions 0, 1, ...N 28, and a plurality of configuration spaces 29.

[0014] Each function 28 implements its own PCIe configuration 29 by providing standard means for controlling the operation of a function. A large portion of a function's configuration space logic is dedicated to configuring and controlling address regions associated with that function. Each incoming transaction passes through address decoding logic to determine the destination unit. The PCIe standard allows for considerable flexibility in address space allocation and programming, resulting in complex address decoding logic required for each function.

[0015] With the increasing degree of integration of multiple functions, logic designers face problems in implementing fast and efficient address decoding. One approach is to perform parallel decoding, as in Fig. 2. The parallel scheme, generally designated 30, comprises a plurality of configuration spaces F0, F1,..., Fn 34, BAR decoders 32 (BAR = Base Address Register), and RX address information 38 (RX = Receiver). The RX address is applied in parallel to all BAR decoders simultaneously to generate a decoded function / BAR 36.

[0016] With the parallel decoding approach, the PCI endpoint unit implements dedicated decoding logic (BAR decoder) for each function. Address decoding is performed in parallel for all functions in a single unit. This approach requires the use of numerous decoding logic instances, resulting in very large decoding logic and potential problems with signal routing control.

[0017] A second approach is to perform sequential address decoding, as in Fig. 3. The sequential scheme, generally designated 40, includes a plurality of configuration spaces F0, F1,..., Fn 46, a serial BAR selection multiplexer 44, and a BAR decoder 42. The serial BAR selection multiplexer receives data from the configuration spaces 46 and a selection controller 52. The BAR decoder circuit 42 receives the RX address information 48 received in the read / write request packet and the output of the serial BAR selection multiplexer and is operable to generate the decoded function / BAR 50. The serial BAR selection multiplexer sequentially selects all of the function's configuration space data for matching by the BAR decoder 42.

[0018] In the sequential decoding approach, the endpoint performs address decoding for each supported function until the target function is identified. Address decoding is performed using a single, shared address decoder 42. Address decoding is performed in multiple steps, with each step involving one of the functions loading its address configuration 46 into the decoder and evaluating the decoding results. The decoding flow stops when a positive decode is detected. Although this approach uses minimal logic resources, it requires significant decoding latency, resulting in bandwidth degradation.

[0019] A third approach provides one or more decoding policies (e.g., planned function) in the PCIe request header, eliminating the need to search for the target function in the endpoint during the decoding process. This allows for the implementation of decoding in a single decoder with a single step in complex multifunction devices.

[0020] A schematic diagram illustrating a third exemplary approach using parallel decoding data to decode addresses in a PCIe endpoint is shown in Fig. 4. The decode data scheme, generally designated 60, includes a plurality of configuration spaces F0, F1,..., Fn 66, a BAR selection multiplexer 64, and a BAR decoder 62. The BAR selection multiplexer receives data from the configuration spaces 66 and directly selects one of the address configurations using extended decode data 70 received from the host. The BAR decoder circuit 62 receives the RX address information 68 received in the read / write request packet and in the output of the serial BAR selection multiplexer 64 and is operable to generate the acknowledged (or validated) function / BAR 72. The BAR selection multiplexer selects the function's configuration space data for validation by the BAR decoder 62.

[0021] In one embodiment, the PCIe host (or any other requestor) includes target function data in the PCIe request packet according to the decoding data mechanism. PCIe functions in the endpoints implement configuration space capabilities that provide control over the use of target function decoding information in the requests. Note that this feature may be optional. Therefore, units implementing the decoding data mechanism simply ignore target function data in the read / write request packet and perform address decoding using either the parallel or sequential scheme described above.

[0022] A flowchart illustrating the method of the present invention for fast decoding of PCIe addresses is shown in Fig.5. The PCIe endpoint receives a PCIe read / write request (step 80). The contents of the packet are then validated as usual (step 82). The PCIe endpoint checks whether target function data is included in the request packet (step 84).

[0023] The PCIe endpoint then checks whether the use of target function data is enabled (step 86). Note that the decode data feature can be controlled by setting a flag in the device's configuration space. If no target function data is included in the request packet or the use of target function data is not enabled in the device's configuration space, the endpoint device performs an address decode sequence using the parallel or sequential scheme described above (for example, in the sequential scheme, the endpoint performs address decoding for each supported function until the target function is identified) (step 92).

[0024] If target function data is present in the request packet and the use of target function data is enabled in the device's configuration space, the endpoint device checks whether the request address matches one of the address ranges of the proposed target function (step 88). If the target function address range is positively decoded, address decoding is validated and complete (step 90). If the address range is not within the decoded configuration function address, the device endpoint can take further steps, including, for example, reporting an error for incorrect use of target function data or for attempting parallel or sequential address decoding.

[0025] It should be noted that it is not critical how the PCIe host performs the mapping between address ranges and target function data and how the target function information is transmitted to the endpoints. In one embodiment, the request initiator (e.g., the PCIe host) creates a mapping between PCIe address ranges and target units / functions during the PCIe bus initialization phase. During this initialization phase, host software searches all PCIe units and functions by querying their address ranges for demand and then allocating address ranges. During this phase, a table containing associations between address ranges and target functions is built in the host. This lookup table is then used to assign target function attributes to requests issued to PCIe endpoints.

[0026] The objective function data is embedded in the PCle request in any suitable manner, with various possible examples presented below.

[0027] In a first scheme, all or part of the target function data is contained in bits of the PCIe request header, which are normally reserved. In a second scheme, a mechanism is used to extend the PCIe header to include function decoding data. In a third scheme, target function data is contained in payload data, with a specified header field indicating the presence of target data in the payload. In a fourth scheme, ECRC (End-to-End Cyclic Redundancy Check) metadata contained at the end of the request packet is replaced with target data.

[0028] The following is a description of an exemplary method for constructing the root port's lookup table and determining the number of target functions. In one embodiment, the root port implements a fixed-size lookup table containing address-to-function-count translations for a subset of latency-critical address ranges.

[0029] Requests for other functions are sent without function decoding. Note that this may result in higher processing latencies because the sequential decoding path is followed.

[0030] First, the host software scans all PCIe device configuration spaces for address range requirements (e.g., the number of ranges for each device / function and the range size). Note that this is typically standard PCIe practice. Second, the host software creates a memory map by assigning address ranges to devices / functions and writing base address values ​​to function configuration spaces. Third, while PCIe ranges are being allocated, the host software creates a complete table of address-to-function mappings for all PCIe ranges. This table is stored in main memory.

[0031] Next, the host software initializes the root port mapping table with address-to-function-count mappings for critical performance functions. This table can be updated / reloaded during operation to support changes in system requirements. Next, the root port mapping table can serve as a local cache. For example, if a request does not find function information in the root port mapping table, its address is captured, and the software routine is called to determine if the availability of a translation is critical for this type of request. When the software or another mechanism determines that a translation is needed, function information is retrieved from the mapping table in main memory and stored in the local root port table.If a table is full, one of the existing entries can be deleted.

[0032] In one embodiment, the structure of the root port lookup table entries includes: (1) a valid bit; (2) the base address (e.g., up to 64 bits); (3) a range size, which is system-dependent and serves to indicate the log2 value of the range size (assuming that ranges are always specified as a power of two); and (4) the objective function information (e.g., up to 16 bits).

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a" and "an" and "the" include the plural forms unless the context expressly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising," when used in this specification, refer to the presence of specified features, integers, steps, sequences, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, sequences, operations, elements, components, and / or groups thereof.

[0034] The corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or act for performing the function in conjunction with other expressly claimed elements. The description of the present invention is intended to be illustrative and descriptive, but is not intended to be exhaustive or limited to the invention in the form disclosed. Since numerous modifications and changes will readily occur to those skilled in the art, it is to be understood that the invention is not limited to the limited number of embodiments described herein. Accordingly, it will be understood that all suitable variations, modifications, and equivalents made are intended to be within the scope of the present invention.The embodiments were chosen and described in order to best explain the principles and practical application of the invention and to enable others skilled in the art to understand various embodiments with various modifications for the particular use contemplated.

Claims

[1] A method for decoding PCI Express (PCIe) addresses, the method comprising in a PCIe host (12): Searching PCIe devices (24) and functions (28) during a PCIe bus initialization phase; Assigning address ranges to target functions of the PCle units; and constructing a lookup table (18) that assigns the address ranges to the target functions, the lookup table comprising a base address, an address range size and target function information corresponding to the recommended target function; Receiving PCIe requests, each with an address; for each requirement, determining a recommended target unit function according to each address by using the lookup table; and Assigning the recommended target functions to requests issued to PCIe endpoint devices (24), wherein the recommended target functions and requirements are sent in a PCIe request packet from the PCIe host to the PCIe endpoint unit (24). [2] The method of claim 1, further comprising sending the PCIe request packet to the PCIe endpoint device containing the request address and the target function information, wherein the PCIe request packet contains a read and / or write request. [3] A method for decoding PCI Express (PCIe) addresses, the method comprising in a PCle endpoint unit (24): Receiving a read / write request packet from a PCIe host (12); Determine whether the requirements package contains data of recommended objective functions; and if so, decode the received address using the recommended target function; Check whether the request address matches one of the address ranges of the proposed target function; if the address range of the target function has been positively decoded, completing the address decoding; if the address range is not within the decoded function address of the configuration, reporting an error due to incorrect use of target function data or attempts at parallel or sequential address decoding. [4] The method of claim 3, wherein the target function data is validated using contents of base address registers (BAR contents). [5] The method of claim 3, wherein the objective function information is transmitted to the endpoint unit using normally reserved header bits. [6] The method of claim 3, wherein the target function information is transmitted to the endpoint device using an extension of the PCIe header. [7] The method of claim 3, wherein the target function information is transmitted to the endpoint unit within payload data with a field in a corresponding header indicating the presence of target function information in the payload data. [8] The method of claim 3, wherein the target function information is transmitted to the endpoint device instead of ECRC (End-to-end Cyclic Redundancy Checking) metadata normally included at the end of the packet. [9] A method for decoding PCI Express (PCIe) addresses, the method comprising: Providing a lookup table (18) in a PCIe host (12), the lookup table being operable to perform a mapping from an address range to a recommended target function decoding policy, the lookup table comprising a base address, an address range size and Target function information according to the recommended target function decoding policy; using the lookup table, sending an address and a proposed target function to a PCIe endpoint device (24) as a PCIe request packet; Decoding the received address at a PCIe endpoint device using the proposed objective function; and Check whether the request address matches one of the address ranges of the proposed target function and, if so, indicate that decoding of the address is complete. [10] The method of claim 1 or 9, wherein the objective function information is transmitted to the endpoint unit using normally reserved header bits. [11] The method of claim 1 or 9, wherein the target function information is transmitted to the endpoint device using an extension of the PCIe header. [12] The method of claim 1 or 9, wherein the target function information is transmitted to the endpoint unit within payload data with a field in a corresponding header indicating the presence of target function information in the payload data. [13] The method of claim 12, wherein the target function information is transmitted to the endpoint device instead of ECRC (End-to-end Cyclic Redundancy Checking) metadata normally included at the end of the packet.

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