Data transmission system, data transmission device and sensor device for bidirectional communication

Abstract

Data transmission system (1), comprising: a master-side data transmission device (1a) configured to perform bidirectional communication with a slave side via a single-wire transmission line (L1); and a slave-side data transmission device (1b) configured to perform bidirectional communication with the master-side data transmission device (1a) via the transmission line (L1), wherein the master-side data transmission device (1a) includes: an input-clock-side transistor (MN1) connected between a reference potential and the transmission line (L1), which is configured to perform the switching according to an input clock; a first transistor (MP1) connected between a first potential and the transmission line (L1); a second transistor (MP2), one end of which is connected to a second potential which is lower than the first potential; a third transistor (MP3), one end of which is connected to the second potential; a master-side resistor (R1) connected between another end of the second transistor (MP2) and another end of the third transistor (MP3); a connection interruption circuit (1a-1) configured to interrupt an electrical connection between transistors two and three and the transmission line (L1) depending on the switching state of the first transistor (MP1); and a master-side data reproduction circuit (1a-2) configured to reproduce data sent by the slave-side data transmission device (1b) via the transmission line (L1), wherein the slave-side data transmission device (1b) includes: a fourth transistor (MP4) connected between the transmission line (L1) and a third potential which is higher than or equal to the first potential; a slave-side resistor (R2) connected between the transmission line (L1) and the reference potential; a clock reproduction circuit (1b-1) configured to reproduce a clock (ck) sent by the master-side data transmission device (1a) over the transmission line (L1); and a slave-side data reproduction circuit (1b-2) which is configured to reproduce data sent by the master-side data transmission device (1a) over the transmission line (L1).

Description

Technical field

[0001] The embodiments discussed herein relate to a data transmission system, a data transmission device and a sensor device. State of the art

[0002] Single-wire bidirectional data transmission can have a configuration in which a command is sent through a single transmission line from a master side to a slave side and a command response is sent back from the slave side to the master side.

[0003] Such a system configuration can be used for quality control at the time of product shipment, such as sending a command from a test device corresponding to a master side to a product corresponding to a slave side and receiving, on the master side, a response sent back from the slave side to check the quality of the product.

[0004] Conventional methods for single-wire bidirectional transmission include, for example, a transmission method that uses A / D and D / A conversion (PTL 1) and a transmission method that defines a logical level by timing (PTL 2). Furthermore, a method is proposed in which a first device sends a clock signal to a second device by switching between a first level and an intermediate level, and the second device sends information to the first device indicating whether a second level should be output during the duration of the intermediate level of the clock signal (PTL 3).

[0005] On the other hand, a conventional method corresponding to a slave side of a bidirectional transmission is proposed which, for example, measures a sensor output by gradually changing adjustment data, sets and stores adjustment data to set the sensor output to a desired value, and adjusts the sensor output with the stored adjustment data (PTL 4).

[0006] PTL 5 discloses a network node for a Local Interconnect Network (LIN). The network node includes a bus terminal that is operationally coupled to a data line to receive a data signal representing serial data over this data line. The data signal is a binary signal with high and low signal levels. The network node also includes a receiver circuit that uses a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a sensing circuit that receives the data signal and provides an initial voltage signal to represent the high signal level of the data signal. List of printed materials and patent literature PTL 1: Published Japanese patent no. JP 2011-055 312 A PTL 2: US Patent No. US 5,210,846 B1 PTL 3: Published Japanese patent no. JP 2012-169 746 A PTL 4: Published Japanese patent no. JP 2002-310 735 A PTL 5: US Patent Application No. US 2015 / 0039801A1 Brief description of the invention: Technical task

[0007] With the conventional single-wire bidirectional data transmission system, it was difficult to reduce the circuit size. It turns out that the circuit size increases, for example, due to a built-in A / D and D / A converter according to the aforementioned PTL 1, or the addition of a timing circuit or similar for timing according to PTL 2.

[0008] As described above, one weakness was that if bidirectional transmission, such as writing data from the master side to the slave side or reading slave-side data from the master side, is conventionally implemented, transmission devices on the master side and the slave side have a complicated circuit configuration, resulting in an increased circuit size.

[0009] The present embodiments were devised in view of the problems described above and have the objective of providing a data transmission system, a data transmission device and a sensor device for efficiently performing single-wire bidirectional data transmission with a small circuit size. Solution to the task

[0010] To solve the above tasks, a data transmission system is provided according to one aspect. The data transmission system includes a master-side data transmission device configured to perform bidirectional communication with a slave-side device over a single-wire transmission line; and a slave-side data transmission device configured to perform bidirectional communication with the master-side data transmission device over the transmission line.

[0011] The master-side data transmission device includes an input clock-side transistor, transistors one, two and three, a master-side resistor, a link break circuit and a master-side data reproduction circuit.

[0012] The input-clock-side transistor is connected between a reference potential and the transmission line and is configured to switch according to an input clock signal. The first transistor is connected between a first potential and the transmission line. One end of the second transistor is connected to a second potential, which is lower than the first potential. One end of the third transistor is connected to the second potential. The master-side resistor is connected between the other end of the second transistor and the other end of the third transistor. The interrupt circuit is configured to break the electrical connection between transistors two and three and the transmission line depending on the switching state of the first transistor.The master-side data reproduction circuit is configured to reproduce data sent by the slave-side data transmission device over the transmission line.

[0013] The slave-side data transmission device includes a fourth transistor, a slave-side resistor, a clock reproduction circuit, and a slave-side data reproduction circuit.

[0014] The fourth transistor is connected between the transmission line and a third potential that is higher than or equal to the first potential. The slave-side resistor is connected between the transmission line and the reference potential. The clock reproduction circuit is configured to reproduce a clock signal sent by the master-side data transmission device over the transmission line. The slave-side data reproduction circuit is configured to reproduce data sent by the master-side data transmission device over the transmission line.

[0015] Furthermore, according to another aspect, a data transmission device is provided which performs bidirectional communication with a slave side via a single-wire transmission line. This data transmission device includes an input clock-side transistor, transistors one, two, and three, a master-side resistor, a connection interrupt circuit, and a master-side data reproduction circuit.

[0016] The input-clock-side transistor is connected between a reference potential and the transmission line and is configured to switch according to an input clock signal. The first transistor is connected between a first potential and the transmission line. One end of the second transistor is connected to a second potential, which is lower than the first potential. One end of the third transistor is connected to the second potential. The master-side resistor is connected between the other end of the second transistor and the other end of the third transistor. The interrupt circuit is configured to break the electrical connection between transistors two and three and the transmission line depending on the switching state of the first transistor.The master-side data reproduction circuit is configured to reproduce data sent from the slave side via the transmission line.

[0017] Furthermore, according to another aspect, a data transmission device is provided which performs bidirectional communication with a master side via a single-wire transmission line. This data transmission device includes a transistor, a slave-side resistor, a clock reproduction circuit, and a slave-side data reproduction circuit.

[0018] The transistor is connected between the transmission line and a slave-side potential that is higher than or equal to a master-side potential supplied to the master side. The slave-side resistor is connected between the transmission line and a reference potential. The clock reproduction circuit is configured to reproduce a clock signal sent from the master side via the transmission line. The slave-side data reproduction circuit is configured to reproduce data sent from the master side via the transmission line.

[0019] Furthermore, according to another aspect, a sensor device is provided which performs bidirectional communication with a master device via a single-wire transmission line and detects a physical quantity. The sensor device includes an interface circuit, a sensor element, an amplification circuit, auxiliary memory, main memory, an adaptation circuit, and a control circuit.

[0020] The interface circuit includes a transistor connected between the transmission line and a slave-side potential that is higher than or equal to a master-side potential supplied to the master side; a slave-side resistor connected between the single-wire transmission line and a reference potential; a clock reproduction circuit configured to reproduce a clock signal sent from the master side via the transmission line; and a slave-side data reproduction circuit configured to reproduce data sent from the master side via the transmission line. The slave-side data reproduction circuit is configured to communicate with the master side via the transmission line. The sensor element is configured to generate an electrical signal corresponding to the detected physical quantity. The amplification circuit is configured to amplify this electrical signal.The auxiliary memory is configured to temporarily store entered calibration data. The main memory is configured to save the calibration data stored in the auxiliary memory using an electrical write operation. The adaptation circuit is configured to adjust the output characteristic of the sensor element based on the calibration data stored in the auxiliary memory or the calibration data stored in the main memory. The control circuit is configured to determine a control mode for the main memory.

[0021] Furthermore, the sensor device has, as device connections, a single output terminal for outputting an electrical signal amplified by the amplification circuit to the outside, a single input / output interface terminal which is connected to the transmission line for receiving calibration clocks to determine the calibration data to be written to main memory, and also for input and output of data, and a variety of voltage application terminals for applying a voltage when writing data to main memory. Advantageous effects of the invention

[0022] A reduction in circuit size becomes possible. The above and further problems, features and advantages of the present invention will become more readily apparent from the following description, in which preferred embodiments of the invention are presented in conjunction with the accompanying drawings. Brief description of the drawings Fig. Figure 1 illustrates an example configuration of a data transmission system. Fig. Figure 2 illustrates an example configuration of the data transmission system. Fig. Figure 3 illustrates a waveform of a transmission signal. Fig. Figure 4 illustrates an operation waveform of a write mode. Fig. Figure 5 illustrates an operation waveform of a reading mode. Fig. Figure 6 illustrates a circuit configuration in which a leakage current occurs. Fig. Figure 7 is an explanatory drawing illustrating one cause of a leakage current. Fig. Figure 8 illustrates a circuit configuration of a variant with a leakage current suppression function. Fig. Figure 9 illustrates an example configuration of the data transmission system. Fig. Figure 10 illustrates an example system configuration. Fig. Figure 11 illustrates another example system configuration. Fig. Figure 12 illustrates another example system configuration. Fig. Figure 13 illustrates another example system configuration. Fig. Figure 14 illustrates transmission formats. Fig. 15 illustrates further transmission formats. Fig. Figure 16 illustrates a state transition. Fig. Figure 17 illustrates another state transition. Fig. Figure 18 illustrates an exemplary configuration of a sensor device. Fig. Figure 19 illustrates exemplary functions of a 3-bit instruction register. Fig. Figure 20 illustrates a state transition. Fig. Figure 21 is an explanatory drawing that illustrates all states. Fig. Figure 22 is a representation of time sequences illustrating an operation in a write mode to an EPROM. Fig. Figure 23 is a representation of time sequences illustrating an operation in a reset mode. Fig. Figure 24 illustrates a configuration of a semiconductor sensor device for a physical quantity. Description of embodiments

[0023] The following describes the embodiments with reference to the drawings. Fig. Figure 1 illustrates an example configuration of a data transmission system. A data transmission system 1 includes a master-side data transmission device 1a and a slave-side data transmission device 1b.

[0024] Furthermore, a DIO port of the master-side data transmission device 1a and a OW port of the slave-side data transmission device 1b are connected by a single-wire transmission line L1, and bidirectional transmission is carried out between the master-side data transmission device 1a and the slave-side data transmission device 1b via the transmission line L1.

[0025] The master-side data transmission device 1a includes an NMOS (N-channel metal oxide semiconductor) transistor MN1, PMOS (P-channel MOS) transistors MP1 to MP3, a resistor R1 (master-side resistor), an inverter Inv1, a link interrupt circuit 1a-1 and a master-side data reproduction circuit 1a-2.

[0026] It should be noted that the NMOS transistor MN1 corresponds to an input clock-side transistor and the PMOS transistors MP1 to MP3 each correspond to transistors one to three.

[0027] The NMOS transistor MN1, connected between a reference potential (GND) and the transmission line L1, performs the switching according to a clock signal ck.

[0028] The PMOS transistor MP1 is connected between 5 V (the first potential) and the transmission line L1. One end (the source) of the PMOS transistor MP2 is connected to 3.3 V (the second potential, which is lower than the first potential). One end (the source) of the PMOS transistor MP3 is connected to 3.3 V.

[0029] The resistor R1 is connected between the other end (the drain) of the PMOS transistor MP2 and the other end (the drain) of the PMOS transistor MP3.

[0030] The interrupt circuit 1a-1 interrupts the electrical connection between the PMOS transistors MP2 and MP3 and the transmission line L1 depending on the switching state of the PMOS transistor MP1.

[0031] The master-side data reproduction circuit 1a-2 reproduces data sent by the slave-side data transmission device 1b via the transmission line L1. The slave-side data transmission device 1b, on the other hand, contains a PMOS transistor MP4, a resistor R2 (slave-side resistor), a clock reproduction circuit 1b-1, and a slave-side data reproduction circuit 1b-2. The PMOS transistor MP4 is equivalent to a fourth transistor.

[0032] It should be noted that the PMOS transistor MP4 is connected between 5 V (the third potential) and the transmission line L1. The third potential supplied to the slave-side data transmission device 1b, which is higher than or equal to the first potential of the master-side data transmission device 1a, is shown here as an example equal to the first potential (5 V).

[0033] Resistor R2 is connected between transmission line L1 and GND. The clock reproduction circuit 1b-1 reproduces and outputs a clock signal sent by the master-side data transmission device 1a via transmission line L1.

[0034] The slave-side data reproduction circuit 1b-2 reproduces and outputs data sent by the master-side data transmission device 1a via the transmission line L1.

[0035] Here, the NMOS transistor MN1 switches on when a clock signal ck to be input into the inverter Inv1 is at a low potential level (L level) in order to set the potential on the transmission line L1 to GND.

[0036] When writing data from the master side to the slave side, the PMOS transistor MP1 is switched on by a first condition signal r1, which is set to the L level when data, a master-side activation signal and the clock ck are set to a high potential level (H level), in order to set the potential on the transmission line L1 to 5 V.

[0037] When writing data from the master side to the slave side, the PMOS transistor MP2 is switched on by a second condition signal r2, which is set to the L level when data is set to the L level and the master-side activation signal and the clock ck are set to the H level, in order to set the potential on the transmission line L1 to 3.3 V.

[0038] When reading the slave-side data from the master side, the PMOS transistor MP3 is switched on by a third condition signal r3, which is set to the L level when the master-side activation signal is set to the L level, in order to pull the transmission line L1 into a 3.3 V pull-up state via the resistor R1.

[0039] When reading data sent from the slave side to the master side, the PMOS transistor MP4 is switched on by a fourth condition signal r4, which is set to the L level when data, the slave-side activation signal and the clock reproduced by the clock reproduction circuit 1b-1 are set to the H level, in order to set the potential on the transmission line L1 to 5 V.

[0040] According to the above-mentioned configuration of the data transmission system 1, it becomes possible to efficiently write data from the master side to the slave side or to read the slave-side data from the master side via the single-wire transmission line L1, and also to reduce the circuit size.

[0041] Now, a specific example configuration of data transmission system 1 will be described. Fig. Figure 2 illustrates an exemplary configuration of the data transmission system. A data transmission system 1-1 comprises a master-side data transmission device 10m and a slave-side data transmission device 10s, wherein the master-side data transmission device 10m and the slave-side data transmission device 10s are connected to each other via the single transmission line L1.

[0042] The master-side 10m data transmission device is powered by a variety of power supplies, such as a 5V and a 3.3V operating power supply, which in the example are shown in Fig. The slave-side data transmission device 10s is operated by a single power supply, such as a single 5V operating power supply (which can also be higher than 5V) in the example shown in Figure 2. Fig. 2 operated. Furthermore, the ground (GND) of the master-side data transmission device 10m and the slave-side data transmission device 10s is one and the same.

[0043] The master-side data transmission device 10m corresponds to a test device (a test instrument) which, for example, tests the slave-side data transmission device 10s, whereas the slave-side data transmission device 10s corresponds to a product (e.g., an IC (Integrated Circuit)) to be tested by the master-side data transmission device 10m.

[0044] It should be noted that the master-side data transmission device 10m and the slave-side data transmission device 10s are both transmission interface circuits which contain a control circuit at a higher level to perform such a test function or the like (as shown below based on the Fig. 10, Fig. 11, Fig. 12 to Fig. 13 described) to realize.

[0045] The master-side 10m data transmission device includes a DO port, a DE port, a CLK port, a DI port, and a DIO port. DO, DE, CLK, and DI are internal ports, while DIO is an external port. DO is used to input data (commands for tests, data to be written, etc.) to be sent from the master to the slave. DE is used to input a master-side activation signal. CLK is used to input a clock signal.

[0046] The DI port is a port from which data sent by the slave-side data transmission device for 10 seconds is output, or a port from which data sent by the master-side data transmission device for 10 seconds is fed back and output.

[0047] The DIO port is an input / output interface port which is connected to one end of the transmission line L1 to communicate with the slave-side data transmission device for 10 seconds.

[0048] Furthermore, the master-side data transmission device contains 10m logic elements Ic1 and Ic2, inverters Inv0 and Inv1, the resistor R1, the NMOS transistor MN1, PMOS transistors MP0 to MP3, a comparator Cmp1 and a reference voltage source Vr1 as components.

[0049] It should be noted that the comparator Cmp1 and the reference voltage source Vr1 perform the function of the master-side data reproduction circuit 1a-2 in Fig. 1 realize and the inverter Inv0 and the PMOS transistor MP0 perform the function of the interrupt circuit 1a-1 in Fig. 1. Implement (the interruption circuit 1a-1 is shown below based on the Fig. 6, Fig. 7 to Fig. 8 described).

[0050] The logic element Ic1 is a logic circuit with three inputs and one output, whose output (the output corresponds to the first condition signal r1) is set to the L level when an input condition, that three inputs in input ends a4 to a6 are at the H level, is met, and is set to the H level when an input condition other than the one mentioned above is met.

[0051] Furthermore, the logic element Ic2 is a logic gate with three inputs and one output. Its output (corresponding to the second condition signal r2) is set to a low level when an input condition is met: that one input to input a1 is at a low level and two inputs to inputs a2 and a3 are at a high level. It is set to a high level when any other input condition is met. Note that the activation signal input via terminal DE corresponds to the third condition signal r3.

[0052] Regarding the connection relationship of the respective elements in the master-side data transmission device 10m, terminal DO is connected to input a1 of logic element Ic2 and input a4 of logic element Ic1. Terminal DE is connected to input a2 of logic element Ic2, input a5 of logic element Ic1, and the gate of PMOS transistor MP3.

[0053] Terminal CLK is connected to input a3 of logic element Ic2, input a6 of logic element Ic1, and input Inv1 of inverter. Terminal DI is connected to output Cmp1 of comparator.

[0054] The output end of the logic element Ic2 is connected to the gate of the PMOS transistor MP2, and the output end of the logic element Ic1 is connected to the gate of the PMOS transistor MP1 and the input end of the inverter Inv0.

[0055] The source of the PMOS transistor MP1 is connected to the 5V power supply. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the positive input of the comparator Cmp1, the drain of the PMOS transistor MP0, and the DIO pin.

[0056] The gate of the NMOS transistor MN1 is connected to the output of the inverter Inv1, and the source of the NMOS transistor MN1 is connected to GND. The negative input of the comparator Cmp1 is connected to the positive terminal of the reference voltage source Vr1, and the negative terminal of the reference voltage source Vr1 is connected to GND.

[0057] The source of the PMOS transistor MP3 is connected to the 3.3V power supply and the source of the PMOS transistor MP2, and the drain of the PMOS transistor MP3 is connected to one end of the resistor R1.

[0058] The drain of the PMOS transistor MP2 is connected to the other end of the resistor R1 and the source of the PMOS transistor MP0, and the gate of the PMOS transistor MP0 is connected to the output end of the inverter Inv0.

[0059] Here, the reference voltage source Vr1, connected to the negative input end of the comparator Cmp1, is intended to generate an intermediate potential (≈ 4.2 V) between 5 V (the first potential) and 3.3 V (the second potential).

[0060] Therefore, a high (5 V) signal is output from comparator Cmp1 if the level of an input signal at the positive input end of comparator Cmp1 is higher than or equal to 4.2 V. Alternatively, a low (GND) signal is output if the level of the input signal at the positive input end of comparator Cmp1 is lower than 4.2 V.

[0061] On the other hand, the slave-side data transmission device 10s includes a connector ICDH, a connector ICDE, a connector ICCLK, a connector ICDI, and a connector OW (single-wire). The ICDH, ICDE, ICCLK, and ICDI connectors are internal, whereas the OW connector is external. The ICDH connector is used to input data (responses to commands or the like) to be sent from the slave side to the master side, and the ICDE connector is used to input a slave-side activation signal. The ICCLK connector outputs a reproduced clock signal. The ICDI connector outputs data sent by the master-side data transmission device 10m, or it feeds back data sent by the slave-side data transmission device 10s and outputs it.The OW port is an input / output interface port connected to the other end of the L1 transmission line for communication with the master-side data transmission device 10m.

[0062] Furthermore, the slave-side data transmission device 10s contains a logic element Ic3, a buffer Ic4, a resistor R2, the PMOS transistor MP4, a comparator Cmp2 and a reference voltage source Vr2 as components.

[0063] It should be noted that the comparator Cmp2 and the reference voltage source Vr2 perform the function of the slave-side data reproduction circuit 1b-2 in Fig. 1. Realize and the buffer Ic4 performs the function of the clock reproduction circuit 1b-1 in Fig. 1 realized.

[0064] The logic element Ic3 is a logic circuit with three inputs and one output, the output of which is set to the L level when an input condition, that three inputs in input ends b1 to b3 are at the H level (the output corresponds to the fourth condition signal r4), is met, or is set to the H level when an input condition other than the aforementioned one is met.

[0065] Furthermore, the relationship between the respective resistance values ​​of resistor R1 provided in the master-side data transmission device 10m and resistor R2 provided in the slave-side data transmission device 10s is R1 << R2.

[0066] Regarding the connection relationships of the respective elements in the slave-side data transmission device 10s, the ICDH terminal is connected to the input end b1 of the logic element Ic3, and the ICDE terminal is connected to the input end b2 of the logic element Ic3. The ICCLK terminal is connected to the input end b3 of the logic element Ic3 and to the output end of the buffer Ic4. The ICDI terminal is connected to the output end of the comparator Cmp2.

[0067] The gate of PMOS transistor MP4 is connected to the output of logic element Ic3, and the source of PMOS transistor MP4 is connected to the 5V power supply. The drain of PMOS transistor MP4 is connected to terminal OW, one end of resistor R2, the input of buffer Ic4, and the positive input of comparator Cmp2.

[0068] The other end of resistor R2 is connected to GND, the negative input end of comparator Cmp2 is connected to the positive terminal of reference voltage source Vr2, and the negative terminal of reference voltage source Vr2 is connected to GND.

[0069] Here, the reference voltage source Vr2, connected to the negative input end of the comparator Cmp2, is intended to generate an intermediate potential (≈ 4.2 V) between 5 V (the third potential) and 3.3 V (the second potential).

[0070] Therefore, a high (5 V) signal is output from comparator Cmp2 if the level of an input signal at the positive input end of comparator Cmp2 is higher than or equal to 4.2 V of the reference voltage. Alternatively, a low (GND) signal is output if the level of the input signal at the positive input end of comparator Cmp2 is lower than 4.2 V of the reference voltage.

[0071] Now the waveform of the transmission signal on the transmission line L1 of the data transmission system 1-1 is described. Fig. Figure 3 illustrates the waveform of the transmission signal. The master-side data transmission device 10m generates a serial transmission signal w1 by combining a clock and data and sends it through the transmission line L1. The serial transmission signal w1 has three levels: 5 V, 3.3 V, and the GND level.

[0072] Upon receiving the serial transmission signal w1 sent by the master-side data transmission device 10m, the slave-side data transmission device 10s reproduces the clock and the data.

[0073] In such a case, the high level of the clock is reproduced from the 5 V level or the 3.3 V level of the serial transmission signal w1, and the low level of the clock corresponds to the ground level of the serial transmission signal w1.

[0074] Furthermore, the H level of the data is reproduced from the 5 V level of the serial transmission signal w1, and the L level of the data corresponds to the 3.3 V level of the serial transmission signal w1 or the GND level.

[0075] Now the operation in write mode, in which the master-side data transmission device writes 10m of data to the slave-side data transmission device for 10s, is performed using the Fig. 2 and Fig. 4 described.

[0076] Fig. Figure 4 illustrates an operation waveform in write mode. The waveform in Fig. 4. A clock signal entered into the CLK port is referred to as a clock signal ckm, data entered into the DO port is referred to as data dm1, and a master-side activation signal entered into the DE port is referred to as an activation signal e1.

[0077] Furthermore, a reproduced clock output from the ICCLK port is referred to as a clock cks, reproduced data output from the ICDI port is referred to as data ds1, and a slave-side activation signal input into the ICDE port is referred to as an activation signal e2.

[0078] It should be noted that in the write mode from the master side to the slave side, the master-side activation signal e1 goes to the H level and the slave-side activation signal e2 goes to the L level.

[0079] (Time periods t1, t3, t5, t7, t9) In the master-side data transmission device 10m, the NMOS transistor MN1 switches on when the clock signal ckm is at the low level. Accordingly, the DIO terminal is connected to the ground level, and therefore the serial transmission signal w1 flowing through the transmission line L1 goes to the ground level regardless of the level of the data dm1 being transmitted.

[0080] On the other hand, in the slave-side data transmission device 10s, the OW connection goes to the GND level, causing the input of buffer Ic4 to go to the GND level and the clock cks output from buffer Ic4 to go to the L level (GND).

[0081] It should be noted that buffer Ic4 is a CMOS (Complementary MOS) element with an operating threshold voltage of approximately 2.5 V. Therefore, applying a voltage lower than 2.5 V will cause the output level of buffer Ic4 to drop to the GND level.

[0082] On the other hand, the positive input end of comparator Cmp2 goes to the GND level, which is lower than 4.2 V of the reference voltage at the negative input end, and therefore comparator Cmp2 outputs the data ds1 at the L level.

[0083] (Time periods t2, t6) In the master-side data transmission device 10m, the clock ckm, the data dm1 and the activation signal e1 have gone to the H level and the activation signal e2 of the slave-side data transmission device 10s has gone to the L level.

[0084] In this case, the switching states of the NMOS transistor MN1 and the PMOS transistors MP0 and MP4 in the system are each (MN1, MP0, MP1, MP2, MP3, MP4) = (OFF, OFF, ON, OFF, OFF, OFF). Accordingly, the DIO pin is connected to the 5V power supply, and therefore the serial transmission signal w1 is at the 5V level.

[0085] On the other hand, in the slave-side data transmission device 10s, the OW connection goes to 5 V, and therefore the input of buffer Ic4 goes to 5 V and the clock cks output from buffer Ic4 goes to the H level (5 V).

[0086] It should be noted that the operating threshold voltage of buffer Ic4 is approximately 2.5 V, and therefore, applying a voltage higher than 2.5 V will cause the output level of buffer Ic4 to drop to 5 V of the operating power supply.

[0087] On the other hand, the positive input end of comparator Cmp2 has gone to 5 V, which is higher than 4.2 V of the reference voltage of the negative input end, and therefore comparator Cmp2 outputs the data ds1 at the H level. Fig. Figure 4 shows that the H level is output after a transmission delay time Δt.

[0088] (Time periods t4, t8) In the master-side data transmission device 10m, the clock ckm has gone to the H level, the data dm1 has gone to the L level, the activation signal e1 has gone to the H level and the activation signal e2 of the slave-side data transmission device 10s has gone to the L level.

[0089] In this case, the switching states of the NMOS transistor MN1 and the PMOS transistors MP0 to MP4 in the system are each (MN1, MP0, MP1, MP2, MP3, MP4) = (OFF, ON, OFF, ON, OFF, OFF). Accordingly, the 3.3 V power supply is connected to the DIO pin, and therefore the serial transmission signal w1 is at the 3.3 V level.

[0090] On the other hand, in the slave-side data transmission device 10s, the OW connection goes to 3.3 V, and therefore the input of buffer Ic4 goes to 3.3 V and the clock cks output from buffer Ic4 goes to the H level (5 V).

[0091] It should be noted that the operating threshold voltage of buffer Ic4 is approximately 2.5 V, and therefore, applying a voltage higher than 2.5 V as described above will cause the output level of buffer Ic4 to go to 5 V of the operating power supply.

[0092] On the other hand, the positive input end of comparator Cmp2 has gone down to 3.3 V, which is lower than the 4.2 V reference voltage at the negative input end, and therefore comparator Cmp2 outputs the data ds1 at the L level.

[0093] As described above, it is evident that in the write mode from the master to the slave, the master-side clock is reproduced on the slave side and the high level of the master-side data was written to the slave side approximately in the time periods t2, t6.

[0094] Now the operation is performed in read mode, in which the master-side data transmission device reads data to be sent from the slave-side data transmission device 10m over a period of 10s, based on the Fig. 2 and Fig. 5 described.

[0095] Fig. Figure 5 illustrates an operation waveform in read mode. The difference to the one in Fig. The difference in waveform shown in Figure 4 lies in the fact that the data output from port DI is labeled as data dm2, and the data input to port ICDH is labeled as data ds2. The data input via port DO, dm1, is irrelevant (it can be either the high or low level) and is therefore not shown.

[0096] It should be noted that in the read mode from the master side to the slave side, the master-side activation signal e1 goes to the L level and the slave-side activation signal e2 goes to the H level.

[0097] (Time periods t11, t13, t15, t17, t19) In the master-side data transmission device 10m, the NMOS transistor MN1 turns on when the clock signal ckm is at the low level. Accordingly, the DIO pin is connected to GND, and therefore the serial transmission signal w1 goes to the GND level.

[0098] On the other hand, in the slave-side data transmission device 10s, the OW connection goes to the GND level, which causes the input of buffer Ic4 to go to the GND level, which is lower than the operating threshold voltage of buffer Ic4, and therefore the clock cks output from buffer Ic4 goes to the L level.

[0099] Additionally, in the master-side data transmission device 10m, the positive input end of the comparator Cmp1 goes to the GND level, which is lower than 4.2 V of the reference voltage at the negative input end, and therefore the comparator Cmp1 outputs the data dm2 at the L level.

[0100] (Time periods t12, t14) In the master-side data transmission device 10m, the clock ckm went to the H level and the activation signal e1 went to the L level, whereas in the slave-side data transmission device 10s, the data ds2 went to the L level and the activation signal e2 went to the H level.

[0101] In this case, the switching states of the NMOS transistor MN1 and the PMOS transistors MP0 to MP4 in the system are each (MN1, MP0, MP1, MP2, MP3, MP4) = (OFF, ON, OFF, OFF, ON, OFF). Accordingly, the OW terminal goes to the 3.3 V pull-up voltage via resistor R1, and therefore the serial transmission signal w1 goes to the 3.3 V level.

[0102] On the other hand, in the slave-side data transmission device 10s, the input of buffer Ic4 goes to 3.3 V, which is higher than the operating threshold voltage of buffer Ic4, and therefore the clock cks goes to the 5 V level.

[0103] Additionally, in the master-side data transmission device 10m, the positive input end of the comparator Cmp1 goes to 3.3 V, which is lower than 4.2 V of the reference voltage at the negative input end, and therefore the comparator Cmp1 outputs the data dm2 at the L level.

[0104] (Time periods t16, t18) In the master-side data transmission device 10m, the clock ckm went to the H level and the activation signal e1 went to the L level, whereas in the slave-side data transmission device 10s, the data ds2 went to the H level and the activation signal e2 went to the H level.

[0105] In this case, the switching states of the NMOS transistor MN1 and the PMOS transistors MP0 to MP3 on the master side each turn out to be (MN1, MP0, MP1, MP2, MP3) = (OFF, ON, OFF, OFF, ON).

[0106] In the slave-side data transmission device 10s, on the other hand, the input voltage of buffer Ic4 is higher than the operating threshold voltage of buffer Ic4 in this case, causing the clock signal cks to reach the 5 V level. Consequently, the PMOS transistor MP4 on the slave side turns on, connecting terminal OW to the 5 V power supply on the slave side, and therefore the serial transmission signal w1 reaches the 5 V level.

[0107] Additionally, in the master-side data transmission device 10m, the positive input end of the comparator Cmp1 goes to 5 V, which is higher than 4.2 V of the reference voltage at the negative input end, and therefore the comparator Cmp1 outputs the data dm2 at the H level.

[0108] As described above, it is evident that in the read mode from the master side to the slave side, the master-side clock is reproduced on the slave side, and also the high level of the slave-side data is read on the master side during the time periods t16 and t18.

[0109] A leakage current suppression function of the master side in the connection interruption circuit 1a-1 is now described. The master-side data transmission device 10m of the data transmission system 1-1 has a circuit configuration for controlling the leakage current that can flow from the PMOS transistors MP2 and MP3.

[0110] First, the circuit configuration that can cause a leakage current is described. Fig. Figure 6 illustrates the circuit configuration that can cause a leakage current. The data transmission system 100 includes a master-side data transmission device 100m and a slave-side data transmission device 10s.

[0111] The master-side data transmission device 100m is configured to connect the inverter Inv0 and the PMOS transistor MP0, which are located in Fig. Figure 2 does not include the components shown. Accordingly, the drain of the PMOS transistor MP2 and the other end of resistor R1 are directly connected to the DIO terminal. The other components are the same as those shown. Fig. 2.

[0112] The configuration of the master-side data transmission device 100m as in Fig. Figure 6 shows that a problem of leakage current can occur due to the PMOS transistors MP2 and MP3.

[0113] Fig. Figure 7 is an explanatory drawing illustrating the cause of the leakage current. It shows a cross-sectional structure of the PMOS transistors MP2 and MP3.

[0114] An operation is performed to set the transmission line L1 to 5 V when the PMOS transistor MP1 is in a forward state. In this case, the configuration of the master-side data transmission device is set to 100 m. Fig. 6. The drain-side potential of the PMOS transistor MP2 is higher than 3.3 V. Similarly, the drain-side potential of the PMOS transistor MP3 across resistor R1 is also higher than 3.3 V.

[0115] Accordingly, a current (leakage current) flows in the direction of the arrow as shown. Fig. 7 shown by body diodes (parasitic diodes) Db of the PMOS transistors MP2 and MP3, which can result in a fault that the signal voltage of the transmission line L1 does not reach 5 V.

[0116] To correct such an error, the following steps are necessary: Fig. 2 shown master-side data transmission device 10m the inverter Inv0 and the PMOS transistor MP0 as the connection interruption circuit 1a-1 attached.

[0117] In Fig. 2. The gate of PMOS transistor MP1 is connected to the input of inverter Inv0, and the output of inverter Inv0 is connected to the gate of PMOS transistor MP0. Additionally, the source of PMOS transistor MP0 is connected to the drain of PMOS transistor MP2 and the other end of resistor R1.

[0118] The drain of the PMOS transistor MP0 is connected to the DIO terminal, the drain of the PMOS transistor MP1, the drain of the NMOS transistor MN1 and the positive input end of the comparator Cmp1.

[0119] The configuration mentioned above puts the PMOS transistor MP0 into an off state when the PMOS transistor MP1 is in an on state, thereby breaking (high impedance) the electrical connection between the transmission line L1 and the PMOS transistors MP2 and MP3.

[0120] As a result, the body diodes Db of the PMOS transistors MP2 and MP3 do not conduct when the transmission line L1 is at 5 V, and therefore it turns out that the transmission line L1 is normally held at 5 V without any leakage current occurring (however, the back-gate voltage of the PMOS transistor MP0 is assumed to be 5 V).

[0121] A variant of a configuration with a leakage current suppression function is now described. Although the preceding description suppresses the occurrence of leakage current by using the inverter Inv0 and the PMOS transistor MP0, an equivalent effect can also be achieved by using a diode. This variant shows a case of a circuit configuration using a diode.

[0122] Fig. Figure 8 illustrates a circuit configuration of the variant with a leakage current suppression function. A data transmission system 1-2 includes a master-side data transmission device 10m-1 and the slave-side data transmission device 10s.

[0123] The master-side data transmission device 10m-1 is configured to connect the inverter Inv0 and the PMOS transistor MP0, which are located in Fig. 2 shown, does not contain, but instead contains a diode Di (whose forward voltage Vf is, for example, 0.7 V) as the interrupt circuit 1a-1.

[0124] The anode of diode Di is connected to the drain of PMOS transistor MP2 and the other end of resistor R1. The cathode of diode Di is connected to the drain of PMOS transistor MP1, the drain of NMOS transistor MN1, the positive input of comparator Cmp1, and the DIO terminal. Additionally, the sources of PMOS transistors MP2 and MP3 are connected to a 4V power supply. The other components are the same as those in [reference missing]. Fig. 2.

[0125] The configuration mentioned above causes the diode Di to be reverse-biased when the transmission line L1 is at 5 V, thus preventing leakage current from flowing through the PMOS transistors MP2 and MP3.

[0126] It should be noted that when the PMOS transistors MP2 and MP3 are in the forward state, the diode Di is forward-biased, causing a voltage drop in the forward voltage Vf (0.7 V in this example). Therefore, the PMOS transistors MP2 and MP3 are used with their source voltage set to 4.0 V, which is 0.7 V higher than 3.3 V.

[0127] Now, a data transmission system with an alarm function for reporting a fault existing on the slave side to the master side is described.

[0128] Fig. Figure 9 illustrates an example configuration of the data transmission system. A data transmission system 1-3 includes the master-side data transmission device 10m and a slave-side data transmission device 10s-1.

[0129] The slave-side data transmission device 10s-1 includes, as a new connection, an ALM connection into which a signal to report a fault of the slave (temperature deviation, supply voltage deviation or the like) is input.

[0130] Furthermore, the slave-side data transmission device 10s-1 is configured to do the in Fig. The logical element shown in point 2, Ic3, is not included, but instead contains logical elements Ic5 and Ic6 and an inverter Inv2.

[0131] The logic element Ic5 is a logic circuit with three inputs and one output, whose output goes to the L level when an input condition, that three inputs in input ends b4 to b6 are at the H level, is met, or goes to the H level when an input condition other than the one mentioned above is met.

[0132] The logic element Ic6 is a logic gate with two inputs and one output (equivalent to a two-input, one-output AND element) whose output goes to the L level if either of the two inputs is at the L level, or to the H level if both inputs are at the H level.

[0133] Here, the ALM terminal is connected to the input end of inverter Inv2. The ICDH terminal is connected to input b4 of logic element Ic5, the ICDE terminal is connected to input b5 of logic element Ic5, and the ICCLK terminal is connected to input b6 of logic element Ic5 and the output end of buffer Ic4.

[0134] The output of inverter Inv2 is connected to one of the inputs of logic element Ic6, and the output of logic element Ic5 is connected to the other input of logic element Ic6. The output of logic element Ic6 is connected to the gate of PMOS transistor MP4. The other components are the same as those in Fig. 2.

[0135] An alarm signal dalm sent by the control circuit of the slave-side data transmission device 10s-1 is entered into the ALM terminal, and if a fault occurs on the slave side, the alarm signal dalm goes to the H level.

[0136] Accordingly, the PMOS transistor MP4 switches on regardless of the levels at terminals ICDH and ICDE when the alarm signal reaches the high level, thereby setting the transmission line L1 to the 5V state. This allows the master-side data transmission device to quickly detect the fault on the slave side over a distance of 10m.

[0137] Now, based on the Fig. 10, Fig. 11, Fig. 12 to Fig. 13 describes an exemplary system configuration. Fig. Figure 10 illustrates the exemplary system configuration. A data transmission system 2-1 includes a master-side device 20a and a slave-side device 30a, wherein the master-side device 20a and the slave-side device 30a are connected to each other via the transmission line L1.

[0138] The master-side device 20a includes a master-side control circuit 22a and a master-side interface circuit 21a, which correspond to the master-side data transmission device 10m. The master-side interface circuit 21a also includes the terminals DO, DE, CLK, and DI.

[0139] The master-side control circuit 22a sends the data dm1 to terminal DO, the activation signal e1 to terminal DE, and the clock signal ckm to terminal CLK. The master-side interface circuit 21a sends the data dm2 to the master-side control circuit 22a via terminal DI.

[0140] On the other hand, the slave-side device 30a includes a slave-side control circuit 32a and a slave-side interface circuit 31a, which correspond to the slave-side data transmission device 10s. The slave-side interface circuit 31a includes the terminals ICDH, ICDE, ICCLK, and ICDI.

[0141] The slave-side control circuit 32a sends the data ds2 to the ICDH terminal and the activation signal e2 to the ICDE terminal. The slave-side interface circuit 31a sends the clock signal cks via the ICCLK terminal and the data ds1 via the ICDI terminal to the slave-side control circuit 32a.

[0142] Fig. Figure 11 illustrates another exemplary system configuration. It depicts an exemplary multi-wire system configuration in which a plurality of slave-side devices are connected via a single-wire transmission line. A data transmission system 2-2 includes the master-side device 20a and slave-side devices 30a-1 to 30a-n, wherein the master-side device 20a and the slave-side devices 30a-1 to 30a-n are interconnected via a transmission line L1a. The transmission line L1a has a multi-wire configuration on the slave side.

[0143] The slave-side device 30a-1 includes a slave-side interface circuit 31a-1 and a slave-side control circuit 32a-1. Similarly, the slave-side device 30a-n includes a slave-side interface circuit 31a-n and a slave-side control circuit 32a-n. The connection between the control circuit side and the interface circuit side is the same as that in Fig. 10.

[0144] Fig. Figure 12 illustrates another exemplary system configuration. It depicts an exemplary system configuration in a case where an alarm function is present. A data transmission system 2-3 contains the master-side device 20a and a slave-side device 30b, wherein the master-side device 20a and the slave-side device 30b are connected to each other via the transmission line L1.

[0145] The slave-side device 30b includes a slave-side interface circuit 31b and a slave-side control circuit 32b. In addition to the connections ICDH, ICDE, ICCLK and ICDI, the slave-side interface circuit 31b also includes a connection ALM.

[0146] Upon receiving a fault message from a higher level, the slave-side control circuit 32b sends the alarm signal dalm at the high level to the ALM terminal. The other components are the same as those in Fig. 10.

[0147] Fig. Figure 13 illustrates another exemplary system configuration. It shows an exemplary system configuration in which the master side is replaced by a microcomputer. A data transmission system 2-4 contains a microcomputer 20b and a slave-side device 30c, wherein the microcomputer 20b and the slave-side device 30c are connected to each other via the transmission line L1. The other components are the same as those in Fig. 12.

[0148] Here, the use of the present data transmission system for IC mass production testing and the like in a system configuration as described above, for example by providing a Fig. Figure 11 shows a multi-wire connection to efficiently perform mass production testing in a summarized manner, wherein the master-side device is the test device and the slave-side device is the IC.

[0149] Furthermore, the transmission function becomes superfluous after completion of the mass production test, and it is sufficient to simply report an abnormal output from the slave side to the master side. Therefore, it turns out that the transmission line L1 in the Fig. 12 and Fig. The configuration shown in 13 is used as a line to report a fault detection.

[0150] Now, transmission formats will be described. Fig. Figure 14 illustrates transmission formats. (a) of Fig. Figure 14 illustrates a transmission format f1 specific for an N-bit instruction cm1.

[0151] The transmission format f1 is used when the master-side data transmission device 10m only performs a setting for the slave-side data transmission device 10s, which does not require any data exchange. For example, when resetting (initializing) the slave side, the master-side data transmission device 10m sends the command cm1, which instructs the slave side to perform a reset, and the slave-side data transmission device 10s performs the reset upon receiving the cm1 command. (b) of Fig. Figure 14 illustrates a transmission format f2 which contains the N-bit instruction cm1 and M-bit instruction processing payload cm2.

[0152] The f2 transmission format is used when the master-side data transmission device 10m performs writing and reading data to and from the slave-side data transmission device 10s, which requires a data exchange.

[0153] When data is written, the master-side data transmission device 10m sends the command cm1, which orders the data to be written, and command processing payload cm2, into which the data to be written has been inserted, to the slave-side data transmission device 10s. Furthermore, when data is read, the master-side data transmission device 10m sends the command cm1, which orders the data to be read, to the slave-side device 10s, and upon receiving the command cm1, the slave-side data transmission device 10s inserts the data read based on the instruction of the command cm1 into the command processing payload cm2 and sends it back.

[0154] Fig. Figure 15 illustrates other transmission formats. (a) of Fig. Figure 15 illustrates a transmission format f1a, which contains the N-bit instruction cm1 and a K-bit address ad1. (b) of Fig. Figure 15 illustrates a transmission format f2a containing the N-bit instruction cm1, the M-bit instruction processing payload cm2 and the K-bit address ad1.

[0155] The transmission formats f1a and f2a mentioned above are used for the in Fig. 11 Data transmission system 2-2 shown is used, wherein the address ad1 contains address values ​​of slave-side devices 30a-1 to 30a-n (or address values ​​of slave-side interface circuits 31a-1 to 31a-n).

[0156] Now a state transition will be described. Fig. Figure 16 illustrates a state transition. It depicts a state transition during a transfer between the master and the slave using the transfer format, which does not contain a field for address ad1. (S1) The master-side device and the slave-side device are activated. (S2) The master-side device and the slave-side device enter an operational wait state (IDLE). (S3) The master-side device and the slave-side device enter a command setting state (CMD). In the command setting state (CMD), the setting, receiving, decoding, or similar actions of a command are performed. (S4) If the command is "reset by software", the command setting state (CMD) is changed to the operation wait state (IDLE). (S5) When the command is "Write data", the command setting state (CMD) transitions to the data write state (WT). In the data write state (WT), the data to be written is sent from the master-side data transmission device 10m to the slave-side data transmission device 10s. (S6) After the data has been written, the data write state (WT) transitions to the operation wait state (IDLE). (S7) When the command is "Read Data", the command setting state (CMD) transitions to the data read state (RD). In the data read state (RD), the data to be read is sent from the slave-side data transmission device 10s to the master-side data transmission device 10m. (S8) After the data has been read, the data read state (RD) transitions to the operation wait state (IDLE).

[0157] It should be noted that in the preceding description, the respective processing times for the instruction setting state (CMD), the data write state (WT), and the data read state (RD) were predetermined according to the number of clock cycles. Therefore, the master-side and slave-side control circuits perform a clock counting process to detect a state transition time.

[0158] Fig. Figure 17 illustrates another state transition. It depicts a state transition during communication between the master and the slave using a transmission format with a field for the address ad1. (S11) The master-side device and the slave-side device are activated. (S12) The master-side device and the slave-side device enter the operation wait state (IDLE). (S13) The master-side device and the slave-side device enter the command setting (CMD) state. (S13a) The master-side device and the slave-side device enter an address transfer state (ADR). In the address transfer state (ADR), a predetermined address is sent from the master-side device to the slave-side device. (S14) The slave-side device to which the address does not belong enters the operation wait state (IDLE). Furthermore, if the command is, for example, "reset by software", the slave-side device with the corresponding address performs the reset and enters the operation wait state (IDLE). (S15) When the command is “write data”, the slave-side device with the corresponding address enters the data write state (WT). (S16) After the data has been written, the data write state (WT) transitions to the operation wait state (IDLE). (S17) When the command is “Read Data”, the slave-side device with the corresponding address enters the data read (RD) state. (S18) After the data has been read, the data read state (RD) transitions to the operation wait state (IDLE).

[0159] It should be noted that in the preceding section, the processing time of the address transfer state (ADR) was also determined in advance based on the number of clock cycles, and the master-side and slave-side control circuits perform a clock counting process to detect the time of the transition from the processing carried out in the address transfer state (ADR) to another state.

[0160] As described above, the configuration of the data transmission system of the present disclosure makes it possible to efficiently perform single-wire bidirectional data transmission with a small circuit size.

[0161] It should be noted that the configuration described in PTL 3 of Fig. 2 is unable to perform an H-level transmission from the slave to the master, and therefore is unable to detect the power supply state on the slave side.

[0162] In contrast, in the data transmission system of the present disclosure, the slave-side data transmission device 10s is able to send the high level to the master-side data transmission device 10m when the slave-side data transmission device 10s is operating normally. However, the high level is not sent (only the ground level is output) if the power supply to the slave-side data transmission device 10s has been switched off or the operating voltage has dropped.

[0163] As described above, it becomes possible to detect the power supply state of the slave-side data transmission device 10s (or the slave-side device) by determining on the master side whether the slave-side data transmission device 10s is able to send the H level, or by checking the voltage value of the H level that was sent.

[0164] The slave-side device will now be described in detail. In the following description, the slave-side device is referred to as a sensor device, which is assumed to be, for example, a sensor for detecting a physical quantity such as temperature or pressure.

[0165] Fig. Figure 18 illustrates an exemplary configuration of a sensor device. A sensor device 30 includes a slave-side interface circuit 31, a control circuit 32, an auxiliary memory 33, a main memory 34, an adaptation circuit 35, a sensor element 36, an amplification circuit 37, and a fault detection unit 38. In addition to the Vcc and GND terminals for the device's power supply, the device also has the following terminals: OW, Vout, EV, and CG.

[0166] It should be noted that the sensor device 30 is configured only with active and passive components formed on the same semiconductor chip and manufactured using the CMOS process.

[0167] The OW port is an input / output interface connected to the L1 transmission line for communication with the master-side data transmission device over a distance of 10 m, as described above. A synthesized signal consisting of data and a clock signal is input to or output from the OW port. The Vout port is the output from which a result detected by sensor element 36 is output.

[0168] The EV and CG pins are voltage-applied pins used when writing data to main memory 34. Main memory 34 is specifically an EPROM (erasable programmable read-only memory) configured with a floating MOS array.

[0169] Accordingly, when writing data to the EPROM, a voltage higher than the operating current supply Vcc of the sensor device 30 is applied to the EV terminal, and a voltage to control the floating gate is also applied to the CG terminal.

[0170] The slave-side interface circuit 31 corresponds to the slave-side data transmission device 10s described above and communicates with the master-side device via the transmission line L1 connected to terminal OW. The control circuit 32 corresponds to the one described above. Fig. 10, Fig. 11, Fig. 12 to Fig. 13 described slave-side control circuit.

[0171] Auxiliary memory 33 temporarily stores data (calibration data) entered via the OW port. Auxiliary memory 33 is configured with a shift register, which is, for example, a 48-bit shift register.

[0172] The main memory 34, which is an EPROM, stores the alignment data stored in the auxiliary memory 33 by means of an electrical rewrite operation (the main memory 34 is referred to below as an EPROM 34).

[0173] The adaptation circuit 35 adjusts an output characteristic (sensitivity) of the sensor element 36 based on the calibration data stored in the auxiliary memory 33 or the calibration data stored in the EPROM 34. Alternatively, the adaptation circuit 35 adjusts an offset, a gain, and the like of the gain circuit 37.

[0174] The sensor element 36 generates an electrical signal corresponding to the detected physical quantity. The amplification circuit 37 amplifies the electrical signal output by the sensor element 36 and outputs it externally via the Vout terminal. The fault detection unit 38 detects a fault that has occurred in the sensor device 30 and sends an alarm signal to the slave side interface circuit 31.

[0175] Here, the auxiliary memory 33 receives the temporary calibration data sent via the OW connection via the slave-side interface circuit 31 and the control circuit 32 and stores it. The adaptation circuit 35 uses the temporary calibration data stored in the auxiliary memory 33 to adjust an output characteristic of the sensor element 36 or the offset, gain, and the like of the gain circuit 37.

[0176] In the above-mentioned case, the control circuit 32 causes the matching circuit 35 to measure the output of the sensor element 36 or the output of the amplification circuit 37 while simultaneously changing the adjustment value using a variety of temporary adjustment data, and it determines the adjustment data which provide a desired output value.

[0177] When setting the calibration data, the control circuit 32 stores the calibration data in the EPROM 34. Subsequently, in a normal operating state, the adaptation circuit 35 adjusts the outputs of the sensor element 36 and the amplification circuit 37 using the calibration data stored in the EPROM 34.

[0178] Now, an instruction analysis performed by control circuit 32 is described. Control circuit 32 contains a 3-bit instruction register (mode setting register), and the 3-bit instruction register analyzes a 3-bit instruction sent from the master side using a predetermined number of clock cycles.

[0179] Fig. Figure 19 illustrates exemplary functions of the 3-bit instruction register. Table T1 lists functions of 3-bit instruction register values. Note that fields numbered 2, 6, and 7 are empty.

[0180] In the case of No. 1, the name is "Output" and the control circuit outputs 32 serial data points when a command "000" is sent from the master side.

[0181] In the case of No. 3, the name is “reference” and the control circuit 32 writes the contents of the EPROM 34 into a shift register (SR), which is the additional memory 33, when an instruction “010” is sent from the master side.

[0182] In the case of No. 4, the name is “adjustment” and the control circuit 32 outputs the logical sum (OR) of the contents of the shift register (SR) and the EPROM 34 to a D / A converter in the sensor device 30 when a command “011” is sent from the master side.

[0183] In the case of No. 5, the name is “Write” and the control circuit 32 writes the contents of the shift register (SR) into the EPROM 34 when a command “100” is sent from the master side.

[0184] In the case of No. 8, the name is “Reset” and the control circuit 32 resets the shift register (SR) and the mode setting when a command “111” is sent from the master side.

[0185] Now, a state transition during the execution of an adjustment control on the EPROM 34 is described. Fig. Figure 20 illustrates a state transition, and Fig. 21 is an explanatory drawing illustrating the respective states. In a table T2 in Fig. 21 are the respective states in the state transition diagram of the Fig. 20 listed. Here, "No." corresponds to the in Fig. The state transition diagram “No.” shown in table T1 of the 20 Fig. 19. (S20) The sensor device 30 is switched on. (S21) After being switched on, the sensor device 30 enters an initialization state (Init) according to a reset operation performed by the control circuit 32. The initialization state (Init) is a data input wait state via the slave side interface circuit 31. (S22) Control circuit 32 enters an instruction analysis state. The instruction analysis state is a state for analyzing an instruction sent from the master side. Instruction analysis is performed using four clock cycles based on the value stored in the 3-bit instruction register in control circuit 32. (S22a) When performing a four-clock instruction analysis, the control circuit 32 uses three of the four clocks for mode setting. (S22b) When the mode is set, the control circuit 32 enters an execution state. (S22c) The execution state is a state used to determine, for the set mode, which state to transition to next. Here, the control circuit 32 uses one of the four clock cycles to determine the next state to transition to. (S23) If the mode setting is “Reset” (the case of No. 8 in Table T1), the control circuit 32 enters the initialization (Init) state after performing a software reset. (S24) If the mode setting is one of the numbers 1, 3, 4 and 5 of table T1, the control circuit 32 enters a displacement state. (S25) The shift state is a state for performing the operations of register values ​​No. 1, 3, 4 and 5 of the 3-bit instruction register, and the 48-bit shift register, which is the auxiliary memory 33, performs a shift operation using 48 input clock cycles.

[0186] In case 1 (output), serial data is output after the 48-bit shift has been performed. In case 3 (reference), the 48-bit shift operation is performed after the value of EPROM 34 has been written to the 48-bit shift register.

[0187] Additionally, in the case of No. 4 (adjustment), the logical sum of the value of EPROM 34 and the data after the 48-bit shift is output to the D / A converter.

[0188] Furthermore, in the case of No. 5 (write), the value of the 48-bit shift register is written to EPROM 34.

[0189] (S26) When the 48-bit shift operation is performed and after completion of operations in respective modes, the control circuit 32 initializes the mode setting in the next clock cycle and enters a restart state to transition to the initialization state (Init).

[0190] It should be noted that the control circuit 32 also enters the restart state if the master-side device has written data to the EPROM 34 or performed an analog measurement based on the application of a voltage to the EV and CG terminals.

[0191] Now an operation is being written to EPROM 34 in write mode. Fig. Figure 22 is a representation of time courses illustrating an operation in write mode to the EPROM. Each of the signals CK, MODE (2:0), IDENT, SFTEN and CNT6BIT (5:0) in Fig. 22 represents an internal signal in the control circuit 32. Furthermore, the symbol “?” in Fig. 22 is a data bit of the value 0 or 1, which was entered via the OW port, and the symbol “b” means that the number is binary (the same applies below).

[0192] The clock signal CK is a clock signal output from the aforementioned ICCLK pin of the slave-side interface circuit 31. The mode setting signal MODE (2:0) is a value from the 3-bit instruction register. The first data (at the left end in Fig. 23 data shown) 001b of the mode setting signal MODE (2:0) are the initial value of the mode setting signal MODE (2:0), which is shifted to the left each time an input clock signal CK is entered, and the data which was entered via the OW connection (the data bit 0 or 1 marked by “?”) is shifted to the least significant bit.

[0193] The IDENT signal is a signal that goes to the H level after completion of an operation to write 3 bits to the 3-bit instruction register, or to the L level if the 3-bit write operation was not completed.

[0194] The shift activation signal SFTEN is a signal that goes to the H level when a 48-clock shift state exists with respect to the 48-bit shift register, or goes to the L level in a state other than the one mentioned above.

[0195] The counting control signal CNT6BIT (5:0) is a value of a 6-bit counter for performing a 48-bit count.

[0196] It should be noted that the voltages EV and CG are the voltages applied to the EV terminal and the CG terminal respectively, and the voltage EV is, for example, 9 V and the voltage CG is, for example, 18 V, at the time of writing data to the EPROM 34.

[0197] (S31) During a 3-clock instruction duration, a 3-bit instruction is written to the 3-bit instruction register according to the data which was entered via the OW port.

[0198] The 3-bit write operation is not completed during the aforementioned duration, and therefore the IDENT signal is at a low level. Furthermore, for the 48-bit shift register not undergoing a shift operation, the shift activation signal SFTEN is at a low level, and since the 6-bit counter has not yet started counting, its output value is 00d (d is a symbol indicating that 00 is a decimal number. The same applies in the following). (S32) Upon entering a 1-clock-period setting time, the write operation to the 3-bit instruction register is completed, and therefore the IDENT signal goes to the H level. (S33) During the 48-clock shift duration, the 48-bit shift register is in the 48-clock shift state. The shift activation signal SFTEN went high with a 1-clock delay after the rise of the IDENT signal, following confirmation of the shift operation. Additionally, the count control signal CNT6BIT (5:0) started the counting operation with a 1-clock delay after the rise of the shift activation signal SFTEN. (S34) The count value has reached the value 48 in an EPROM write port measurement period, and therefore the voltages EV and CG are applied so that the data corresponding to the mode setting signal MODE (2:0) is written to the EPROM 34. (S35) During a 1-clock initialization period, initialization for the next instruction input is performed. In other words, a new instruction setting is performed, and therefore the 3-bit instruction register is reset and the mode setting signal MODE (2:0) assumes the initial value 001b for the next cycle.

[0199] Furthermore, the IDENT signal and the shift activation signal SFTEN will go to the L level from the next cycle, the 6-bit counter will also be reset and the counter value will be set to 00d from the next cycle.

[0200] In the above-mentioned representation of time sequences, the return from the init state back to the init state in the write mode to EPROM 34 turns out to be a 53-clock operation.

[0201] Fig. Figure 23 is a representation of time sequences illustrating an operation in reset mode. (S41) The initial value of the mode setting signal MODE (2:0) is 001b. During the 3-clock instruction duration, a 3-bit instruction 111b is written sequentially into the 3-bit instruction register according to the data which was entered via the OW pin.

[0202] The 3-bit write operation is not yet complete, and therefore the IDENT signal is at a low level. Additionally, for the 48-bit shift register that is not undergoing a shift operation, the shift activation signal SFTEN is at a low level, and since the 6-bit counter has not yet started counting, its output value is 00d. (S42) Upon entering the 1-clock-period setting time, the write operation to the 3-bit instruction register is completed, and therefore the IDENT signal goes to the high level. The reset instruction is detected during this time. (S43) This is the reset duration. The 3-bit instruction register is reset, and the mode setting signal MODE (2:0) assumes a value of 001b, which is the initial value. Also, since the IDENT signal has gone low and the 48-bit shift register has not been activated, the shift activation signal SFTEN is still low, and since the 6-bit counter has not been activated, the counter value remains 00d.

[0203] In the above-mentioned representation of temporal progressions, the return from the init state back to the init state in reset mode turns out to be a 4-clock operation.

[0204] Now, a configuration difference between the sensor device 30 and the PTL 4 mentioned above will be described. Fig. Figure 24 illustrates a configuration of a semiconductor sensor device for a physical quantity. The configuration shown is as follows: Fig. 1 of PTL 4 shows a semiconductor sensor device for a physical quantity.

[0205] The semiconductor sensor device for a physical quantity made of PTL 4 has eight connections, namely connections one through eight. When used, for example, as a pressure sensor in a motor vehicle, such a semiconductor sensor device for a physical quantity is installed in a confined space near the point to be measured, in order to reduce pressure loss or minimize piping.

[0206] Accordingly, a smaller sensor device is desirable, and since the number of connections of a housing to be molded is determined by the number of connections of a semiconductor chip, it is desirable to further reduce the number of connections to achieve miniaturization.

[0207] To fulfill such a wish, the sensor device 30 of the present disclosure attempts to reduce the number of connections by providing in an interface part the slave-side interface circuit 31 with the function of the slave-side data transmission device 10s and the control circuit 32.

[0208] In other words, there are a total of six terminals, which, in addition to Vcc and GND of the power supply connection, include the terminals OW, Vout, EV and CG as shown in Fig. Figure 18 shows that this reduced the number of connections from eight to six. Here, the slave-side interface circuit 31 and the control circuit 32 of the sensor device 30 correspond to the operation selection circuit in the Fig. 24 Semiconductor sensor device shown for a physical quantity.

[0209] Combining the data and clock signals from the DS and CLK ports of the in Fig. The semiconductor sensor device shown in 24 for a physical quantity makes the sensor device 30 controllable via a single terminal OW. Furthermore, the activation signal of terminal E of the sensor device shown in 24 is controlled in the control circuit 32. Fig. 24 semiconductor sensor device shown for a physical quantity is generated.

[0210] As described above, the sensor device 30 is configured to determine whether the logic level is H or L by means of three voltage levels (5 V, 3.3 V, GND level) resulting from the superposition of clocks and data, and additionally contains a 3-bit instruction register to receive a mode which determines how the EPROM 34 is to be controlled.

[0211] Accordingly, it will be possible to use the DS, CLK and E ports of the Fig.The semiconductor sensor device shown in Figure 24 for a physical quantity is to be removed, communication with the master side is to be carried out using the OW connection, and the number of connections is to be reduced for miniaturization. As described above, the sensor device 30 can be provided as a compact device with a reduced number of connections for performing sensitivity adjustment, temperature behavior adjustment, and offset adjustment by electrical matching using the EPROM 34.

[0212] The embodiments were described above. However, each unit illustrated in the embodiments can be replaced by an arbitrary structure with equivalent functions. Furthermore, additional arbitrary components and processes can be added.

[0213] The foregoing is to be regarded merely as illustrating the principles of the present invention. Furthermore, since every person skilled in the art will immediately think of numerous variations and modifications, it is not desirable to limit the invention to exactly the structure and applications shown and described, and accordingly, all suitable variations and equivalents can be considered to fall within the scope of the invention in the appended claims and their equivalents. Reference symbol list 1 Data transmission system 1a Master-side data transmission device 1b slave-side data transmission device L1 transmission line MN1 input clock-side transistor (NMOS transistor) MP1 to MP4 transistors one to four (PMOS transistors) R1 master-side resistor R2 slave-side resistor Inv1 Inverter 1a-1 Interruption circuit 1a-2 master-side data reproduction circuit 1b-1 Clock Reproduction Circuit 1b-2 slave-side data reproduction circuit ck Takt r1 to r4 Condition signals one to four DIO, OW connection

Claims

Data transmission system (1) comprising: a master-side data transmission device (1a) configured to perform bidirectional communication with a slave-side device via a single-wire transmission line (L1); and a slave-side data transmission device (1b) configured to perform bidirectional communication with the master-side data transmission device (1a) via the transmission line (L1), wherein the master-side data transmission device (1a) comprises: an input-clock-side transistor (MN1) connected between a reference potential and the transmission line (L1), configured to perform switching according to an input clock; a first transistor (MP1) connected between a first potential and the transmission line (L1);a second transistor (MP2), one end of which is connected to a second potential lower than the first potential; a third transistor (MP3), one end of which is connected to the second potential; a master-side resistor (R1) connected between another end of the second transistor (MP2) and another end of the third transistor (MP3); a connection interruption circuit (1a-1) configured to interrupt an electrical connection between transistors two and three and the transmission line (L1) depending on the switching state of the first transistor (MP1);and a master-side data reproduction circuit (1a-2) configured to reproduce data sent by the slave-side data transmission device (1b) over the transmission line (L1), the slave-side data transmission device (1b) comprising: a fourth transistor (MP4) connected between the transmission line (L1) and a third potential higher than or equal to the first potential; a slave-side resistor (R2) connected between the transmission line (L1) and the reference potential; a clock reproduction circuit (1b-1) configured to reproduce a clock (ck) sent by the master-side data transmission device (1a) over the transmission line (L1); and a slave-side data reproduction circuit (1b-2) configured to reproduce data sent by the master-side data transmission device (1a) over the transmission line (L1).Data transmission system (1) according to claim 1, wherein the input clock-side transistor (MN1) switches on when the clock (ck) is at a low potential level to set a potential on the transmission line (L1) to the reference potential, the first transistor (MP1) is switched on by a first condition signal at a time of data transmission from a master side to the slave side when data, a master-side activation signal and the clock (ck) are set to a high potential level, to set the potential on the transmission line (L1) to the first potential, the second transistor (MP2) is switched on by a second condition signal at a time of writing data from the master side to the slave side when the data is set to a low potential level and the master-side activation signal and the clock (ck) are set to a high potential level,to set the potential on the transmission line (L1) to the second potential, the third transistor (MP3) is switched on by a third condition signal at a time when slave-side data is read by the master side, when the master-side activation signal is set to a low potential level, to pull the transmission line (L1) into a pull-up state with the second potential via the master-side resistor (R1), and the fourth transistor (MP4) is switched on by a fourth condition signal at a time when slave-side data is read on the master side, when data, a slave-side activation signal and the clock (ck) reproduced by the clock reproduction circuit (1b-1) are set to a high potential level, to set the potential on the transmission line (L1) to the third potential. Data transmission system (1) according to claim 1, wherein the connection interruption circuit (1a-1) comprises an inverter (Inv1) and a transistor, an input end of the inverter (Inv1) is connected to a gate of the first transistor (MP1), an output end of the inverter (Inv1) is connected to a gate of the transistor, a source of the transistor is connected to an end of the master-side resistor (R1) and a drain of the second transistor (MP2), a drain of the transistor is connected to the transmission line (L1), and the transistor switches off when the first transistor (MP1) switches on in order to interrupt the electrical connection between transistors two and three and the transmission line (L1). Data transmission system (1) according to claim 1, wherein the connection interruption circuit (1a-1) includes a diode, an anode of the diode is connected to an end of the master-side resistor (R1) and a drain of the second transistor (MP2), a cathode of the diode is connected to the transmission line (L1), and the diode assumes a reverse bias state when the first transistor (MP1) turns on in order to interrupt the electrical connection between transistors two and three and the transmission line (L1). Data transmission system (1) according to claim 1, wherein the master-side data reproduction circuit (1a-2) is a first comparator, an input end of the first comparator is connected to the transmission line (L1) and an intermediate potential between the first potential and the second potential is inputted into another input end of the first comparator, and the slave-side data reproduction circuit (1b-2) is a second comparator and an input end of the second comparator is connected to the transmission line (L1) and an intermediate potential between the third potential and the second potential is inputted into another input end of the second comparator. Data transmission system (1) according to claim 1, wherein the fourth transistor (MP4), when a fault occurs in the slave-side data transmission device (1b), switches itself on in order to set the potential on the transmission line (L1) to the third potential and reports the fault to the master-side data transmission device (1a). Data transmission system (1) according to claim 1, wherein the slave-side data transmission device (1b) sends a high potential level to the master-side data transmission device (1a) when it is operating with a normal power supply, and outputs a GND level when it is not operating with a normal power supply, and the master-side data transmission device (1a) detects a power supply state of the slave-side data transmission device (1b) by determining whether the slave-side data transmission device (1b) is capable of sending the high potential level. Data transmission device (1a) which performs bidirectional communication with a slave side via a single-wire transmission line (L1), comprising: an input-clock-side transistor (MN1) connected between a reference potential and the transmission line (L1), which is configured to perform switching according to an input clock; a first transistor (MP1) connected between a first potential and the transmission line (L1); a second transistor (MP2), one end of which is connected to a second potential which is lower than the first potential; a third transistor (MP3), one end of which is connected to the second potential; a master-side resistor (R1) connected between another end of the second transistor (MP2) and another end of the third transistor (MP3);a connection interruption circuit (1a-1) configured to interrupt an electrical connection between transistors two and three and the transmission line (L1) depending on the switching state of the first transistor (MP1); and a master-side data reproduction circuit (1a-2) configured to reproduce data sent from the slave side via the transmission line (L1). Data transmission device (1b) which performs bidirectional communication with a master side via a single-wire transmission line (L1), comprising: a transistor connected between the transmission line (L1) and a slave-side potential which is higher than or equal to a master-side potential supplied to the master side; a slave-side resistor (R2) connected between the transmission line (L1) and a reference potential; a clock reproduction circuit (1b-1) which is configured to reproduce a clock (ck) sent by the master side via the transmission line (L1); and a slave-side data reproduction circuit (1b-2) which is configured to reproduce data sent by the master side via the transmission line (L1). Sensor device which performs bidirectional communication with a master side via a single-wire transmission line (L1) and detects a physical quantity, comprising: an interface circuit comprising a transistor connected between the transmission line (L1) and a slave-side potential which is higher than or equal to a master-side potential supplied to the master side, a slave-side resistor (R2) connected between the single-wire transmission line (L1) and a reference potential, a clock reproduction circuit (1b-1) which is configured to reproduce a clock (ck) sent by the master side via the transmission line (L1), and a slave-side data reproduction circuit (1b-2) which is configured to reproduce data sent by the master side via the transmission line (L1), and which is configuredthat it communicates with the master side via the transmission line (L1); a sensor element configured to generate an electrical signal corresponding to the detected physical quantity; an amplification circuit configured to amplify the electrical signal; an auxiliary memory configured to temporarily store input calibration data; a main memory configured to store the calibration data stored in the auxiliary memory by means of an electrical write operation; an adaptation circuit configured to adapt an output characteristic of the sensor element based on the calibration data stored in the auxiliary memory or the calibration data stored in the main memory; and a control circuit configured to determine a control mode of the main memory.and wherein the sensor device has as device connections: a single output terminal for outputting an electrical signal amplified by the amplification circuit to the outside; a single input / output interface terminal, which is connected to the transmission line (L1), for receiving calibration clocks to determine the calibration data to be written to main memory, and also for inputting and outputting data; and a plurality of voltage application terminals for applying a voltage when writing data to main memory.

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