Low-overhead hardware prediction element to mitigate performance reversal for core-to-core data transfer optimization instructions

Abstract

Device (102) comprising: a plurality of hardware processor cores (114), each of the hardware processor cores having a first cache (116); a second cache (116, 108) communicatively coupled to and shared by the plurality of hardware processor cores; and a prediction means (140) for tracking accesses to a plurality of monitored cache lines in the first cache and controlling activation of a cache line downgrade instruction based on the tracked accesses, wherein execution of the cache line downgrade instruction by one of the plurality of hardware processor cores results in a plurality of unmonitored cache lines in the first cache being moved to the second cache.

Description

AREA

[0001] Embodiments of the invention relate to the field of computer architecture and, in particular, data traffic. BACKGROUND INFORMATION

[0002] Access to computer networks has become a ubiquitous part of computer use. Whether accessing a local area network (LAN) in a corporate environment to access shared network resources or accessing the Internet via the LAN or another access point, users seem to be logged into at least one service accessed via a computer network at all times. The rapid proliferation of cloud-based services has led to even greater use of computer networks, and predictions indicate that these services will play an increasingly important role.

[0003] Network operations are facilitated by various types of devices, including routers, switches, bridges, gateways, and access points. Large network infrastructure typically involves the use of telecommunications-class network elements, including switches and routers, manufactured by companies such as Cisco Systems, Juniper Networks, Alcatel Lucent, IBM, and Hewlett-Packard. These telecommunications switches are highly sophisticated, operate at very high bandwidths, and provide advanced routing functionality and various levels of quality of service (QoS). Private networks, such as local area networks (LANs), are most commonly used by businesses and home users. Corporate networks also often employ hardware and / or software-based firewalls and the like.

[0004] In recent years, the virtualization of computer systems has gained considerable importance, particularly in server installations and data centers. In a traditional approach, a server runs a single operating system directly on physical hardware resources, such as CPU, RAM, storage devices (e.g., hard disk), network controllers, I / O ports, etc. In a virtualized approach using virtual machines (VMs), physical hardware resources are used to support corresponding types of virtual resources, allowing multiple VMs to run on the server's physical hardware resources, with each virtual machine comprising its own CPU allocation, memory allocation, storage devices, network controllers, I / O ports, etc. Multiple operating systems of the same or different ones then run on the various VMs.Furthermore, by using a virtual machine manager (VMM) or hypervisor, virtual resources can be dynamically allocated while the server is running, allowing VM types to be added, shut down, or repurposed without requiring a server shutdown. This allows for greater flexibility in server deployment and better utilization of server processing resources, especially for multi-core and / or multi-processor servers.

[0005] Another virtualization approach is container-based OS virtualization, which uses visualized "containers" without the need for a virtual machine (VMM) or hypervisor. Instead of hosting different types of operating systems on dedicated VMs, container-based OS virtualization allows multiple containers to share a single OS kernel, with separate system types and software libraries for each container. As with VMs, virtual resources are allocated to each container.

[0006] The use of software-defined networking (SDN) and network functions virtualization (NFV) has also gained momentum in recent years. With SDN, the system that decides where traffic is sent (the control plane) is decoupled from the underlying system that forwards traffic to the selected destination (the data plane). SDN concepts can be used to facilitate network visualization, allowing service providers to manage various aspects of their network services through software applications and application program interfaces (APIs). Within NFV, network service providers can gain flexibility in network configuration by virtualizing network functions, which brings significant benefits, including optimization of available bandwidth, cost savings, and faster time to market for new services.

[0007] Today, a large number of proprietary network devices exist, making expansion and upgrades increasingly difficult. Such network devices include routers, firewalls, and other devices that maintain the real-time state of subscriber mobility, voice and media calls, security, contextual content management, and more. NFV technology consolidates these network functions on universal x86 servers and can significantly reduce configuration and upgrade complexity.

[0008] When multiple NFVs are consolidated, e.g., running as a set of virtual machines (VMs) on a single platform, highly efficient network packet forwarding is required due to the nature of the workload and the high transmission speeds of current (10 gigabits per second (Gbps)) and future (40 Gbps and 100 Gbps) network interfaces. On a multi-core x86 server, these packets are forwarded and processed (via inter-VM communication) by NFV modules in VMs on different cores.

[0009] Recently, during testing of a conventional implementation, it was observed that the packet throughput of inter-VM communication, especially for small packets (e.g., 64 B, which is important for telecommunications companies), is far from satisfactory. Several performance bottlenecks exist, both in the form of software and hardware deficiencies.

[0010] Document US 2009 / 0006755 A1 shows a provision of application-level information for use in cache management. Document US 2009 / 0216950 A1 shows a request for split instructions. SUMMARY OF THE INVENTION

[0011] The invention provides an object as disclosed in the independent claims. Preferred embodiments are disclosed in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above-mentioned aspects and many of the attendant advantages of this invention will become apparent from the following detailed description, particularly when taken in conjunction with the accompanying drawings, in which reference numerals refer to the same parts throughout the several views unless otherwise specified: Fig. 1 is a schematic diagram of a configuration of an exemplary host platform, including platform hardware, and various software-based components, including NFV components; Fig. Figure 2 is a schematic diagram of a producer-consumer model using shared memory; Fig. Figure 3 is a diagram comparing the data transmission bandwidths of intra-socket and inter-socket communication; Fig. Figure 4a is a schematic representation of access to a cache line by a vendor application that is not currently stored at any cache level and is accessed from system memory, using a conventional approach; Fig. Figure 4b is a schematic diagram of a consumer application fetching the cache line from the L1 cache of the core executing the producer application, following a conventional approach; Fig. Figure 5 is a schematic representation of an abstracted view of a memory coherence architecture used by the Fig. 4a and Fig. 4b shown platform; Fig. 6 is a notification flow diagram showing a producer core evaluating a cache line held in an L3 cache and modifying it, and a consumer core evaluating the same cache line after the cache line has been modified, in a conventional approach; Fig. 7 is a notification flow diagram illustrating similar cache line access by the producer core and the consumer core from which cache line demotion is used, according to one embodiment; Fig. 8 is a notification flow diagram showing a producer thread accessing and modifying a cache line held in an L3 cache, and a consumer thread located in the same physical core as the producer thread, which, after the cache line is modified, accesses the same cache line and from which the cache line demotion instruction is asserted. Fig. Figure 9 is a notification flow diagram showing a similar cache line access by producer and consumer threads located in the same physical core, where the cache line demotion instruction is disabled. Fig. 10 is a schematic diagram of an exemplary hardware prediction element, including various hardware components. Fig. 11 is a flowchart illustrating operations and logic for implementing a single threshold hardware prediction element according to one embodiment. Fig. 12 is a flowchart illustrating operations and logic for implementing a dual-threshold hardware prediction element according to one embodiment. Fig. 13A is a block diagram showing both an exemplary in-order processing chain and an exemplary register renaming, out-of-order issue / execution chain according to embodiments of the invention. Fig. 13B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the invention. Fig. 14A-B are block diagrams of a more specific example in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and / or different type) in a chip. Fig. 15 is a block diagram of a processor 1500 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to an embodiment of the invention. Fig. 16-19 are block diagrams of example computer architectures. Fig. 20 is a block diagram comparatively illustrating the use of a software instruction converter to convert binary instructions in a set of source instructions to binary instructions in a set of target instructions according to embodiments of the invention. DETAILED DESCRIPTION

[0013] Embodiments of an apparatus and methods for implementing a hardware predictor to mitigate performance inversion due to intra-VM data transfer during inter-VM data transfer optimization for NFVs and other producer / consumer workloads are described herein.

[0014] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the use of the phrase "in one embodiment" in this specification does not necessarily always refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any one or more embodiments.

[0015] For convenience, the individual components in the figures may also be referred to herein by their markings in the figures rather than by a specific reference number. Reference numbers that refer to a particular type of component (as opposed to a specific component) may be provided with a reference number followed by "(typ.)" in the sense of "typical." It is to be understood that the configuration of these components is typical of similar components that may exist but are not shown in the drawings for simplicity and clarity, or of otherwise similar components that are not marked with separate reference numbers. Conversely, "(typ.)" should not be construed to mean that the component, element, etc. is typically used for its disclosed function, implementation, purpose, etc.

[0016] As used herein, the terms "virtual appliance," "virtual network appliance," "network device," or simply "appliance" may be used interchangeably. Furthermore, for purposes herein, including the claims, any software-based device related to software-defined networking or configured to implement network function virtualization may be more generally referred to as a "virtual appliance," which should be understood to include any network device and / or visualized entity configured to implement network function virtualization and / or operations related to software-defined networking.

[0017] Fig. 1 shows an exemplary host platform configuration 100 comprising platform hardware 102 and various software-based components, including NFV components. Platform hardware 102 includes a central processing unit (CPU) 104 coupled via an interconnect 112 to a memory interface 106, a last-level cache (LLC) 108, an input / output (I / O) interface 110, and a prediction element 140. In some embodiments, all or a portion of these components may be integrated on a system-on-chip (SoC). Memory interface 106 is configured to facilitate access to system memory 113, which is typically separate from the SoC.

[0018] The CPU 104 includes a core section comprising M processor cores 114, each including a local Level 1 (L1) and Level 2 (L2) cache 116. Optionally, the L2 cache may be referred to as a "mid-level cache" (MLC). As shown, each processor core 114 has a corresponding connection 118 to the interconnect 112 and operates independently of the other processor cores.

[0019] For simplicity, the interconnect 112 is shown as a single double-headed arrow, representing a single interconnect structure; in practice, however, the interconnect 112 is illustrative of one or more interconnect structures within a processor or SOC and may comprise a hierarchy of interconnect segments or domains employing separate protocols and applicable bridges for connecting the interconnect segments / domains. For example, the portion of an interconnect hierarchy to which memory and processor cores are connected may comprise a coherent memory domain that first protocol, while interconnects at a lower hierarchy level are generally used for I / O access and application of non-coherent domains. The interconnect structure on the processor or SoC can be any existing interconnect structure, such as buses, single-lane or multi-lane serial point-to-point, ring, or mesh interconnect structures.

[0020] I / O interface 110 is exemplary of numerous I / O interfaces provided by platform hardware 102. In general, I / O interface 110 may be implemented as a standalone component (such as an ICH (I / O Control Node) or the like) or it may be implemented on a SoC. In addition, I / O interface 110 may also be implemented as an I / O hierarchy, such as a Peripheral Component Interface Express (PCIe™) I / O hierarchy. I / O interface 110 further facilitates communication between various I / O resources and devices with other platform components. These include a network interface controller (NIC) 120 configured to facilitate access to network 122 and other I / O devices, including firmware memory 124, a hard disk / SSD controller 126, and a hard disk drive 128.More generally, hard disk drive 128 is representative of various types of non-volatile storage devices, including both magnetic and optical-based storage devices, as well as semiconductor storage devices such as solid-state hard drives (SSDs) or flash memory.

[0021] The multiple cores 114 of CPU 104 are used to execute numerous software components 130, such as modules and applications, stored in one or more non-volatile storage devices, such as hard disk drive 128. Optionally, all or portions of software components 130 may be stored on one or more storage devices (not shown) accessible via network 122.

[0022] During system boot or runtime operations, numerous software components 130 and firmware 132 are loaded into system memory 113 and executed on cores 114 as processes comprising execution threads or the like. Depending on the particular processor or SoC architecture, a given "physical" core may be implemented as one or more logical cores, with the processes being allocated to the different logical cores. For example, under the Intel® Hyperthreading™ architecture, each physical core is implemented as two logical cores.

[0023] During a typical system boot for platform hardware 102, firmware 132 is loaded and configured into system memory 113, and then a host operating system (OS) 138 is started. Subsequently, a hypervisor 136 (or VMM) is started, typically launching an application running on host OS 134. Hypervisor 136 can then be used to launch various virtual machines, VM1-N, each of which is configured to use different portions (i.e., address spaces) of system memory 113. In turn, each virtual machine VM1-N can be used to host a corresponding operating system 1381-N.

[0024] During runtime operations, hypervisor 136 enables the reconfiguration of various system resources, such as system memory 113, cores 114, and disk drive(s) 128. Generally, the virtual machine provides abstractions (in combination with hypervisor 136) between the host operating system and the underlying platform hardware 102, allowing hardware resources to be shared between VM1-N. From the perspective of each host operating system, that operating system "owns" the entire platform and is unaware of the presence of other operating systems running in virtual machines. In reality, each operating system only has access to the resources and / or resource portions allocated to it by hypervisor 136.

[0025] How further Fig. As illustrated in Figure 1, each operating system includes an operating system kernel memory and a user memory, both of which execute as memory in system memory 113. The operating system kernel memory is protected and used to execute operating system kernel components, including a network stack. Optionally, the network stack may be located in user memory. Meanwhile, the user memory of an operating system is used to execute user applications, as represented by devices 1, 2, and N and applications 1A-C, 2A-C, and NA-C.

[0026] In general, devices 1, 2, and N are examples of different SDN or NFV devices that can run on virtual machines on platform hardware 102. For simplicity, each VM1-N is depicted with a similar set of software applications installed; nevertheless, this is for illustrative purposes only, as the VMs for a given platform may have similar or different applications installed. Similarly, each VM1-N may have a single virtual network device (as shown), multiple virtual network devices, or no network devices installed at all.

[0027] With SDN on a virtualized platform, data is passed between VMs over a virtual network. This can generally be accomplished using virtual NICs for each VM and a virtual switch in the hypervisor or VMM. With a non-optimized traditional approach, the virtual switch actually operates similarly to a physical switch, meaning the virtual switch has input and output buffers and performs packet flow operations. As with a physical switch, latency occurs at each step of the data transfer sequence between the virtual NICs, resulting in a significant performance degradation.

[0028] In a virtual environment where multiple VMs are installed on the same physical machine, the memory subsystem represents the communication medium. Therefore, expecting high throughput performance by connecting these VMs is not unrealistic. Nevertheless, measurements of VMs on a typical modern server running a variety of virtualization software show that the communication performance between VMs does not even come close to what the memory subsystem could potentially achieve in terms of throughput. For example, cloud workloads typically achieve a packet transfer rate of approximately one million packets per second between two VMs. Telco workloads, which typically utilize highly optimized software stacks and libraries, can achieve packet transfer rates of approximately ten million packets per second between two VMs.

[0029] The most efficient inter-VM solution currently known in the field of invention is based on a shared memory as a data medium for packet communication, as described in Fig. 2, which depicts a pair of VMs 200 and 202 and a hypervisor 204 running on a host platform 206. VM 200 is a producer that writes a packet to shared memory, which includes data exchange medium 208, while VM 202 is a consumer that reads the packets from shared memory. To maintain data accuracy, there is also a "ready" status indicator (not shown) used to ensure that the producer and consumer do not interfere with each other.

[0030] As mentioned earlier, there is a lot of VM and network stack-related software management data involved in this case that prevents packet throughput from reaching the upper bandwidth limit of the host platform's memory system. To separate the pure software management data (which would eventually be addressed by the many ongoing software optimization efforts), an IPC memory metric was used to emulate packet communication between the VMs in terms of memory access behavior to investigate hardware bottlenecks.

[0031] The benchmark used for emulation is called mempipe-spin (Smith et al., Draft: Have you checked your IPC performance lately?, UNENIX 2012). Its datapath behavior mimics the previously described communication between VMs, without the VM management data, with shared circular memory for the producer thread and the consumer thread, and a ready status flag that must be checked before a read or write operation. The consumer uses a pull model to check whether the status flag is ready, which is similar to the pull model used in DPDK packet processing.

[0032] Fig. Figure 3 shows the throughput performance of mempipe-spin, with two threads running on two cores in one socket and two threads running on different sockets. Fig. Two main observations can be seen from Figure 3. First, the throughput for communication within the socket, especially for smaller packet sizes, is far from the physical bandwidth limit. Second, the throughput degrades considerably when the producer and consumer are on different sockets.

[0033] During a producer-to-consumer data transfer, a first thread running on the producer writes a block of data (also called a data object), which is then read by one or more threads (depending on the number of consumers and software architecture). If the data exchange medium is shared memory, at an abstract level this involves the producer writing data to a location in shared memory (e.g., at an address where the data object is stored) and the consumer thread(s) accessing that location in shared memory. Simple and straightforward, at least until you consider that the shared memory location can be copied across various locations in system memory and numerous caches.

[0034] To illustrate this, we will start with a simple example of a software application that involves a producer accessing data so that the software application can modify the data before it is sent to a consumer. Fig. 4a, which shows the Fig. 1 illustrates the platform hardware and software architectures in more detail.

[0035] In virtualized environments employing many VMs, it is considered preferable to allocate a physical or logical processor core to each VM. This allows multiple threads corresponding to specific guest operating system processes and applications running on the guest operating system to execute on the same core. It also significantly improves memory access for the core using L1 and L2 caches, as will become more apparent below. Accordingly, in some of the figures herein, VMs are shown running on corresponding cores, but it is recognized that there may be cases where multiple VMs may be installed on a single core. While the processes of a single VM may run on multiple cores (e.g.,a personal computer running a single VM, such as an Apple Macintosh computer running a VM with Microsoft Windows OS installed), this is not a likely usage scenario in SDN and NFV applications.

[0036] As shown, each of cores 1141 and 1142 includes a respective L1 cache 1161 and 1162 and a respective L2 cache 1181 and 1182, each including a plurality of cache lines represented as rectangular blocks. LLC 108 includes a set of LLC cache lines 430, and system memory 113 also includes a plurality of cache lines, including a set of memory cache lines 426 corresponding to a portion of shared memory 406.

[0037] Fig. Figure 5 shows an abstract view of a memory coherence architecture used by the embodiment of Fig. 4a and Fig. 4b is applied. Under this and similar architectures, as applied by many Intel® processors, the L1 and L2 caches are part of a coherent memory domain under which memory coherence is managed by coherence mechanisms in processor core 500. Each core 104 includes an L1 instruction (IL1) cache 1161, and L1 data (DL1) cache 1160, and an L2 cache 118. L2 caches 118 are represented as non-inclusive, meaning that they do not include copies of cache lines in the L1 instruction and data caches for their corresponding cores. Optionally, L2 can be inclusive of L1 or partially inclusive of L1. Additionally, L3 can sometimes be non-inclusive of L2. As a third option, L1 and L2 can be replaced by a cache that occupies a single level in the cache hierarchy.

[0038] Meanwhile, the LLC is considered part of the "Un-Core" 502, where memory coherence is extended by coherence agents, resulting in additional overhead and processor cycles. As shown, Un-Core 502 includes memory controller 106 coupled to external memory 113 and a global queue 504. Global queue 504 is also coupled to an L3 cache 108 and a QuickPath Interconnect® (QPI) interface 506. Optionally, interface 506 may include a Keizer Technology interface (KTI). L3 cache 108 (which functions as an LLC in this architecture) is inclusive, meaning it includes a copy of each cache line in the L1 and L2 caches.

[0039] As is well known, the size of cache levels increases the further away from a core, but so does the latency associated with accessing cache lines within them. L1 caches are the smallest (e.g., 32–64 kilobytes (KB)), while L2 caches are slightly larger (e.g., 256–640 KB), and LLCs are an order of magnitude larger than the typical L2 cache (e.g., 8–16 MB). Clearly, the size of these caches is dwarfed by the size of system memory (in terms of gigabytes). Generally, the size of a cache line at a given level in a memory hierarchy is consistent throughout the memory hierarchy, and for convenience and reference, memory lines in system memory are also referred to as cache lines, even though they are not, strictly speaking, in a cache.It is further noted that the size of the global queue 504 is quite small since it is intended to only temporarily cache cache lines that are transferred between the various caches, memory controller 106 and QPI interface 506.

[0040] Fig. Figure 4a further shows multiple cache agents used to exchange notifications and transfer data according to a cache coherence protocol. The agents include core agents 408 and 410, L1 cache agents 412 and 414, L2 cache agents 416 and 418, and an L3 cache agent 420.

[0041] Fig. Figure 4a illustrates a simple memory access sequence in which a cache line is accessed from system memory and copied into L1 cache 1161 of core 1141. Data in system memory is stored in memory blocks (conventionally referred to as cache lines, as mentioned above), and each memory block has an associated address, such as a 64-bit address for today's common 64-bit processors. From the perspective of applications, including both manufacturers and consumers, a specific data block (data object) resides at a location in system memory beginning with a specific memory address, and the data is accessed via the application's host operating system.In general, the memory address is actually a virtual memory address, and some software and hardware mechanisms map such virtual addresses to physical addresses behind the scenes. In addition, the application does not know whether all or part of the data block is in a cache. At an abstract level, the application asks the operating system to retrieve the data (usually via address pointers), and the operating system and hardware return the requested data to the application. Therefore, the access sequence is translated by the operating system as a request for one or more memory blocks, starting at a memory address, which is then eventually translated (as needed) into a physical address for one or more requested cache lines.

[0042] In Fig. 4a, the access sequence would begin with core 1141 sending a Read-for-Ownership (RFO) notification and an initial "snooping" (i.e., checking) of the local L1 and L2 caches to see if the requested cache line is currently located in one of these caches. In this example, vendor 200 wants to access the cache line so that the data can be modified, and therefore the RFO is used rather than a read request. The presence of a requested cache line in a cache is called a "hit," while its absence is called a "miss." This is done using well-known snooping techniques, and the determination of a hit or miss via information contained in each cache is done by identifying the addresses of the cache lines currently present in that cache.As previously discussed, the L2 cache is non-inclusive, making the L1 and L2 caches exclusive, meaning that the same cache line is not present in both the L1 and L2 caches for a given core. During an operation 1a, core agent 408 sends an RFO notification with snoop (RFO / S) 422 to L1 cache agent 412, resulting in a miss. During an operation 1b, L1 cache agent 412 forwards the RFO / Snoop notification 422 to L2 cache agent 416, resulting in another miss.

[0043] In addition to checking a local L1 and L2 cache in a core, the core also checks L3 cache 108. If the processor uses an architecture where the L3 cache is inclusive, meaning that a cache line that appears in L1 or L2 for any core also appears in L3, the core knows that the only valid copy of the cache line is in system memory if the L3 snoop ends in a miss. If the L3 cache is not inclusive, additional snoops of the L1 and L2 caches can be performed for the other cores. In the example of Fig. 4a, L2 agent 416 forwards RFO / Snoop notification 422 to L3 cache agent 420, which also results in a miss. Because L3 is inclusive, it does not forward RFO / Snoop notification 422 to cache agents for other cores.

[0044] In response to determining that the requested cache line is not present in L3 cache 108, L3 cache agent 420 sends a read request 424 to memory interface 106 to retrieve the cache line from system memory 113, as represented by access operation 1d, which accesses a cache line 426 stored at memory address 428. As represented by copy operation 2a, the read request results in cache line 426 being copied into a cache line slot 430 in L3 cache 108. Assuming that L3 is full, this results in an eviction of a cache line 432 currently occupying slot 430. In general, the selection of which cache line to evict (and therefore the determination of which slot in the cache data is evicted from where and where to write) is based on one or more cache eviction algorithms well known in the art.If cache line 432 is in a modified state, cache line 432 is written back to memory 113 (known as a cache write-back) before being evicted, as shown. As further shown, a copy of cache line 432 was in a slot 434 in L2 cache 1181, freeing that slot. Thus, cache line 426 is also copied to slot 434 during operation 2b.

[0045] Then cache line 426 should be mapped to L1 data cache 116 1D be written. However, this cache is full, necessitating an eviction of one of its cache lines, as illustrated by an eviction of cache line 436 occupying slot 438. This evicted cache line is then written to slot 434, swapping cache lines 426 and 436, as illustrated by operations 2c and 2d. At this point, cache line 426 can be accessed (i.e., consumed) by core 1141.

[0046] Often, as in relation to Fig. As described in Figure 2, a first NFV device (the producer) generates data corresponding to a first object (e.g., modify the first object), and then a second NFV device (the consumer) wants to access the object. In one case, several NFV devices may only want to read the data of this object. An illustration of an example of how this is done using conventional access is provided in Fig. 4b shown.

[0047] At the beginning of the process, there are three copies of cache line 426 - one in memory 113, one in slot 430 of L3 cache 108, and the other in slot 434 of L1 data cache 116 1DCache line 430 contains data corresponding to a data object. (For simplicity, only a single cache line is shown; in practice, the data for a data object typically spans multiple cache lines.) The consumer, executing on core 2, wants to access the data object, which it knows to be located at memory address 428 (through corresponding software object code running on core 2).

[0048] How to continue in Fig. As shown in Figure 4b, L3 cache agent 420 maintains information from each cache line stored regarding the state of the cache line and which cores have copies of the cache line. In one embodiment, core valid (CV) bits are used to indicate which core(s) have a valid copy of the cache line. When cache line 426 is copied to L3 cache 108, its cache line state data is set to indicate that cache line 426 is in the exclusive state, and the CV bits indicate that core 1 has the only valid copy of the cache line, as determined by cache line state data 440. S1 Afterwards, manufacturer 200 modifies the data object, which results in the state of cache line 426 becoming a (M)odified state 426 S1is updated. According to conventional cache coherence schemes and cache ejection policies, the modified copy of the cache line is not written to L3 cache 108 at this time.

[0049] Core 2 agent 410 sends a read request 442 along with a cache snoop to determine whether cache line 426 is in either its L1 data cache 116 2D or in its L2 cache 1182, or L3 cache 108. As shown by operations 1a and 1b, core agent 410 sends a first cache snoop to L1 cache agent 414 requesting access to cache line 426 (e.g., read request 422), resulting in a miss, and the snoop is forwarded to L2 cache agent 418, resulting in a second miss. As before, the read request notification with snoop is forwarded from the L2 cache agent (418) to the L3 cache agent 420.

[0050] L3 cache agent 420 checks whether a copy of cache line 426 exists in L3 cache 108, resulting in a hit. L3 cache agent 420 then checks cache line state data 440 S1 and specifies that core 1 has exclusive ownership of cache line 426. Since a cache line in an exclusive state can be modified by its user, it is possible that cache line 426 has been modified (in this case, it has), and therefore the copy of cache line 426 in L3 cache 108 is not current. Accordingly, L3 cache agent 420 sends the read request to the L1 and L2 cache agents for core 1, as depicted by operations 2a and 2b, which is ultimately processed by L1 cache agent 412.

[0051] In response to receiving the read request 442, a copy of the modified cache line 426 is fetched from L1 data cache 116 1D to L1 data cache 116 2Dforwarded via interconnect 112 and written to a slot 444 as mapped by operation 3. In addition, each copy of cache line 426 in L1 data cache 116 1D and L1 data cache 116 2D marked as (S)hared, as determined by cache line state 426 S2 For simplicity, cache lines that are in one or more of L1 data cache 116 2D and L2 cache 1182 and can be thrown out as a result of copying cache line 426, but similar results to those shown in Fig. 4a and already discussed, can be expected when L1 data cache 116 2D and L2 cache 1182 are full.

[0052] In connection with operation 3, the copy of cache line 426 in L3 cache 108 is also updated to reflect the modified data in cache line 426. In addition, the cache line 426 state data is updated to reflect that cache line 426 is now shared by core 1 and core 2, as indicated by cache line state data 440. S2 shown.

[0053] Each snoop has an associated, costly latency that consumes bandwidth on the processor's interconnects. Furthermore, while a processor core waits to access its requested data, the processing of the thread requesting the access is delayed.

[0054] A more complex memory access sequence is described in Fig. 6, which shows a notification flow diagram 600 executing on a computing platform that includes a producer core 602, including a producer's L1 cache 604, an L3 cache (e.g., LLC) 606, and a consumer core 608 with a consumer's L1 cache 610. Each of these components has a corresponding agent, as represented by agents 602A, 604A, 606A, 608A, and 610A. Fig. 6, the L2 caches are not shown because in this example the copies of the cache line are located in the L1 caches.

[0055] In an initial state, there are three copies of a cache line 612 currently cached in the producer's L1 cache 604, in the L3 cache 606, and in the consumer's L1 cache 610, respectively represented by cache lines 612 P , 612 L3 , and 612c. Each of the cache lines 612 P and 612 Cis marked as (S)hared, with cache line 612 L3 Includes cache line state data identifying that cache line 612 is shared and both the producer core and the consumer core have a valid copy of the cache line.

[0056] As shown, manufacturer core 602 wants to acquire ownership of a shared cache line 602 in order to modify it. For example, if manufacturer core 602 wants to modify its copy (cache line 612 P) of cache line 612 by writing to it, it must first acquire ownership of the cache line. To acquire ownership of cache line 612, agent 602A of the producer core sends a read-for-ownership (RFO) write request 614 to agent 604A for the producer's L1 cache 604. RFO 614 is forwarded from agent 604A to agent 606A for L3 cache 606. In response to receiving RFO 614, agent 606A sends an invalidation notification 616 to the consumer's L1 cache agent 610A and updates its cache line 612. L3 -State data to indicate that the cache line is now in the (E)xclusive state and vendor core 602 is identified as the exclusive owner of cache line 612. Upon receiving invalidation notification 616, agent 610A marks cache line 612c as invalid (not shown).

[0057] Agent 606A for L3 cache 606 sends a completion notification 618 back to agent 604A for the manufacturer's L1 cache 604. Upon receipt, cache line 612 P marked as (E)xclusive. Data is then transferred to cache line 612 P written (as represented by a letter 620) and cache line 612 P is marked as (M)odified. Agent 604A then returns a completed notification 622 to agent 602A of processor core 602, thus completing the write operation.

[0058] Asynchronously, agent 608A for consumer core 608 periodically queries the state of the cache lines in consumer L1 cache 610, as represented by poll loop 624. Agent 608A then attempts to read its copy of cache line 612 (cache line 612c) using poll loop read 626. Since cache line 612c is marked invalid at this time, this results in an L1 cache miss, and agent 610A for consumer L1 cache 610 sends a notification 628 to agent 606A identifying producer core 602 as the owner of the valid cache line, as identified by a corresponding CV bit. Agent 606A then sends a snoop 630 with the read request to agent 604A. In response, the state of cache line 612 P changed from (M)odified to (Shared) and a snoop response 632 including a copy of cache line 612 P is returned to Agent 606A.

[0059] Upon receiving the snoop response 632, agent 606A performs a memory writeback (WB) of the cache line and restores the state of its copy (612 L3 ) is reset to (S)hared, and appropriate CV bits are set to again determine that producer core 602 and consumer core 608 have valid copies of the cache line. A cache line miss response 634, including the modified copy of cache line 612, is then received by agent 610A, which is used to overwrite the data in cache line 612c and mark cache line 612c as (S)hared. Once in the consumer's L1 cache, consumer core 608 consumes the cache line, as represented by consumer operation 636.

[0060] When the previous cache line access sequence was tested as a producer / consumer output transaction on a processor class, 112 processor cycles were required to complete the read request alone. This represents a significant amount of overhead, with a large amount of traffic being sent between the numerous agents to facilitate the operation while maintaining cache coherence. These operations cause longer latency for each memory access from producer-consumer workloads, such as in inter-VM communication. As a result, tests showed that the processor was stalled for more than 50% of its cycles (i.e., >50% of CPU cycles are performed without reorder instructions).

[0061] Ideally, the manufacturer could use a push store command to push the data to a consumer MLC to reduce latency. However, this approach requires the software to always know the target MLC, which can be impractical, especially with frequent VM migrations. Furthermore, the push operation can throw out useful data in the consumer MLC due to the limited capacity of the MLC.

[0062] To achieve a significant performance increase without incurring additional complexity, a new memory instruction called cache line LLC allocation (CLLA) is proposed. The CLLA instruction allocates the cache line directly into the LLC of the producer MLC, allowing the consumer to directly access the data from the LLC to reduce memory reference latency. Note that a CLLA instruction is typically a cache line demotation instruction, causing a cache line from a lower cache level to be moved to a higher cache level. The discussion regarding L1-to-LLC moves is applicable to other moves, such as L1-to-L2, L2-to-L3, MLC-to-LLC, etc. The CLLA instruction allows software to provide application-level knowledge to the hardware for optimization.By actively pushing data to the LLC closer to the consumer, communication latency is reduced by more than 2x, thus increasing performance, and reducing the number of coherence notifications (avoiding querying SF) to save energy.

[0063] Fig. 7 shows a notification flow diagram 700 corresponding to a similar pair of write and read transactions originating from the producer core 602 and consumer core 608, respectively, and which are shown in notification flow diagram 600 of Fig. 6. Notifications are passed between the same agents in both notification flow diagrams. As an initial condition, there is a copy of cache line 612 in L3 cache 606, as requested by cache line 612. L3 The original state of cache line 612 L3is either (M)odified if the consumer copy of cache line 612 has been updated, or (E)xclusive if the consumer copy has been cache-line demoted unmodified. The CV is none, indicating that no copy of the cache line exists in the producer L1 (or L2) cache 604 or the consumer L1 (or L2) cache 610.

[0064] As before, agent 602A for vendor core 602 sends an RFO / write notification 702 to agent 604A, resulting in an L1 miss. In response, agent 604A forwards the RFO / write notification 702 to agent 606A for L3 cache 606, which creates a copy of the requested cache line (cache line 612 L3 ). Depending on the initial state, the state for cache line 612 L3either changed from (M)odified to (E)xclusive or remains (E)xclusive. The CV bits are updated to determine that vendor core 602 has the only valid copy of the cache line. A copy of cache line 612 L3 is returned by agent 606A to agent 604A via a notification 704, as indicated by cache line 612 P This copy is then updated by the manufacturer write process and marked as (M)odified, with a completed notification 706 being returned to agent 602A.

[0065] In a conventional approach, cache line 612 would P remain in the vendor L1 cache 604 until it is evicted. However, with this new approach, the application that modified the cache line includes a CLLA instruction to cache line 612 PAccordingly, in connection with the execution of the CLLA instruction, a cache line demotion notification 708 is sent from agent 602A to agent 604A to demote cache line 612 P to L3 cache 606. In response to receiving cache line demotion notification 708, agent 604A throws cache line 612 P and forwards the cache line to agent 606A, which stores the existing data in cache line 612 L3 overwrites (updates) the cache line and marks it as (M)odified. The CV bit for the vendor core is reset to indicate that no cores have a valid copy of the cache line.

[0066] In a similar manner as before, agent 608A from consumer core 608 sends a read request 712 to agent 610A to identify cache line 612. The query for cache line 612 results in a miss (for both the consumer L1 and L2 caches), and agent 610A forwards read request 712 to agent 606A. Since the modified version of cache line 612 P was downgraded using the CLLA instruction, the modified copy of the requested cache line 612 is already in cache line 612 L3 This results in snoop notification 630 and snoop response 632 being eliminated, as represented by block 714.

[0067] In response to read request 712, agent 606A sends a copy of modified cache line 612 L3in a miss response notification 716 to agent 610A. This copy of the modified cache line is then written to a cache line slot in consumer L1 cache 610, as represented by a cache line 612c whose state is marked as (M)odified. Cache line 612c is then retrieved from consumer L1 cache 610 to be consumed by consumer core 608, as represented by a consumer operation 718. If the application running on consumer core 608 knows that it is only reading a cache line, it can actively demote it with the CLLA instruction, as represented by a cache line demote notification 720.

[0068] Referring to cache line 612 L3 , which in the embodiment of Fig. 7, there is no write back to memory, although the data in cache line 612 L3 modified. The state of cache line 612 L3is marked as (E)xclusive with the CV set for the consumer, which transfers ownership of the cache line to the consumer L1 cache 610 instead of performing a write back to memory.

[0069] By actively promoting cache lines with the CLLA instruction, latency associated with memory transactions can be significantly reduced. For example, below notification flow diagram 700, the number of processor cycles for consumer read memory access is reduced to 48 cycles. Nevertheless, while actively promoting cache lines with a CLLA instruction provides benefits in most situations, a performance reversal may occur in edge cases where producer and consumer threads that share data reside on the same physical core, e.g., two SMT threads on a single core. In these cases, instead of directly retrieving the shared data from the L1 or L2 cache (MLC), the core most likely must contact the L3 cache (LLC) to retrieve the data promoted by the CLLA instruction. Note that promotion can occur from any cache level.For example, from L1 to L2, or L1 to L3, or L2 to L4, L1 to L4, etc. This affects performance because accesses to LLC (~44 cycles) have higher latencies than accesses to MLC (~14 cycles).

[0070] This performance reversal can be minimized by a hardware predictor that monitors the access pattern to a set of sample cache lines and adaptively determines whether to enable the CLLA instruction based on the behavior in real time. The predictor first randomly selects N sample cache lines from the candidates for cache line demotion and continuously monitors them. For behavior tracking purposes, the selected sample cache lines are never demoted to an LLC. A counter is used to track the number of accesses to the sample cache lines by local core requests versus those by remote snoops. For example, if a cache line access is made by a remote snoop, the hardware predictor decrements the counter by 1. If the cache line access is made by a local core request, the counter is incremented by 1.Over time, the counter indicates whether the remote cores or local threads are accessing the sample cache lines. This, in turn, provides a good prediction of whether the CLLA instruction should be enabled or disabled.

[0071] If the counter value exceeds a selected threshold, indicating that most cache line accesses are being made by a local core, the producer and consumer threads are on the same physical core. To minimize the performance reversal caused by the core having to fetch data from the LLC instead of the MLC, the CLLA instruction should be disabled for all cache line demotion candidates for that core. However, if the counter is below the selected threshold, indicating that most accesses are being made by remote core(s), the CLLA instruction should be enabled to allow all cache line demotion candidates, except those being monitored, to be actively demoted.For simplicity, in the following example embodiments where producer and consumer threads reside on the same physical core, memory coherence protocols are omitted and the L1 / L2 cache is collectively referred to as the L1 cache.

[0072] Fig. 8 shows an example notification flow diagram 800 corresponding to a pair of write and read transactions originating from a producer thread and a consumer thread residing in the same physical core 802 with the CLLA instruction enabled, according to one embodiment. Fig. Figure 8 includes a producer / consumer core 802, which includes a producer / consumer L1 cache and an L3 cache (LLC). Each of these components has a corresponding agent, as represented by agents 802A, 804A, and 806A. Notifications are passed between these agents in the notification flow diagram. Note that different cache levels could have been used, but L1 and L3 are shown, while L2 has been explicitly omitted for simplicity.

[0073] As an initial state, there is a copy of cache line 840 in the L3 cache. A producer thread in the producer / consumer core 802 wishes to acquire ownership of cache line 840 so that it can modify it. To acquire ownership, the producer / consumer core agent 802A sends an RFO / write request 808 to agent 804A of the producer / consumer L1 cache. This request results in an L1 miss. In response, agent 804A forwards the RFO request to agent 806A of the L3 cache 806 in notification 810.

[0074] In response to receiving RFO notification 810, agent 806A returns a copy of cache line 840 to agent 804A via notification 812. Agent 804A then updates the copy of cache line 840 according to the producer thread write request and sends a completion notification 814A to agent 802A. Thereafter, because the CLLA instruction is enabled, upon its execution, a cache line demote notification 816 is sent from agent 802A to agent 804A to demote cache line 840 to L3 cache 806. In response to receiving cache line demote notification 816, agent 804A evicts cache line 840 and forwards it to agent 806A. Agent 806A then overwrites the existing data in its copy of cache line 840 with the updated version.

[0075] Next, a consumer thread residing in the same core as the producer thread wishes to access cache line 840. Accordingly, agent 802A sends a read request 820 to agent 804A, which identifies cache line 840. The query for cache line 840 results in a miss in the L1 cache because cache line 840 has already been demoted to the L3 cache. As a result of this miss, agent 804A forwards the read request to agent 806A in notification 822. Upon receiving notification 822, agent 806A responds back to agent 804A with its copy of cache line 840 in notification 824. Agent 804A then updates the received cache line 840A according to the consumer thread's instructions. A completion notification 826 is sent from agent 804A to agent 802A to confirm the execution of the read notification by the consumer thread.Because the CLLA instruction is enabled, upon execution, a notification 828 is again sent from agent 802A to agent 804A to demote cache line 840 to the L3 cache. Accordingly, agent 804A evicts cache line 840 and forwards it to agent 806A. Agent 806A then overwrites the existing data in its copy of cache line 840 with the updated version.

[0076] Fig. 9 shows an example notification flow diagram 900 corresponding to a similar pair of write and read transactions shown in the notification flow diagram 800 of Fig. 8, where, according to one embodiment, both the producer thread and the consumer thread are located in the same physical core. In contrast to Fig. 8, however, the CLLA command is in Fig. 9 disabled. It should also be noted that different cache levels could have been used, but L1 and L3 are shown for purely illustrative purposes.

[0077] As before, agent 902A for producer / consumer core 902 sends an RFO / write notification 908 to agent 904A, resulting in an L1 miss. In response, agent 904A forwards the RFO / write request in notification 910 to agent 906A for L3 cache 906. A copy of cache line 940 is returned from agent 906A to agent 904A via notification 912. Upon receiving a copy of cache line 940, agent 904A updates it according to the producer thread write request and then returns a completed notification 914 to agent 902A to indicate that the task has been executed. This time, because the CLLA instruction is disabled, cache line 840 is not demoted from the L1 cache to the L3 cache. Cache line demotion notifications 916 and 918 are therefore eliminated, as shown by the corresponding dotted lines.

[0078] Then, as before, a consumer thread residing in the same core as the producer thread wants access to cache line 940. Accordingly, agent 902A sends a read request 920 to agent 904A. Since 940 has not been demoted from L1 to L3 cache by the CLLA instruction, producer consumer L1 cache 904 has a valid copy of cache line 940. Agent 904A does not need to fetch cache line 904A from L3 cache 906 and therefore eliminates memory access notifications 922 and 924. Instead, agent 904A responds directly to agent 902A's read request with its copy of cache line 940 in notification 926. Again, because the CLLA instruction is disabled, cache line demotion notifications 928 and 930 are also eliminated.

[0079] Fig. 10 shows an example hardware configuration of a predictor including a CPU core 1010, an L3 cache (LLC) 1050, and a predictor 1060. The CPU core 1010 further includes processing thread(s) 1020, an L1 cache 1022, and an L2 cache (MLC) 1030. Cache lines 1032-N are shown as individual blocks in the L2 cache (MLC). The prediction element 1060 includes a counter 1070, a first threshold 1072, a second threshold 1074, and a cache line demotion command activation module 1080. The prediction element monitors a number of randomly selected sample cache lines in the L2 cache (MLC) and tracks their accesses, for example, through an inbound snoop 1090. These monitored cache lines are stored as cache lines 1062-1068 in the prediction element 1060 in Fig. 10 shown.

[0080] Fig. 11 is a flowchart illustrating operations and logic for implementing the hardware prediction element with a threshold, according to one embodiment. In block 1102, the prediction element selects one or more random sample cache lines from a group of cache line demotion candidates in the first cache. The selected sample cache lines are continuously monitored by the prediction element and are excluded from demotion by the cache line demotion instruction. The number of selected sample cache lines may depend on factors such as the size of the various caches, e.g., MLC and L. The selected sample cache lines may be replaced with new sample cache lines at regular intervals. The prediction element also starts a counter in block 1102 to track the number of local core requests versus the number of remote snoops accessing the sample cache lines.The initial value of the counter can depend on factors such as the selected threshold and the size of the caches. The counter should always be reset when the selected sample cache lines are replaced with new cache lines.

[0081] In block 1104, the predictor tracks each access to the sample cache lines. In block 1106, the predictor determines for each access whether the access is from a local core or a remote core. This determination may be made by determining whether the access is a remote snoop or not. If the access to a sample cache line is a remote snoop, indicating an access from a remote core, the counter is decremented by 1, as illustrated in block 1110. Conversely, if the access is not a remote snoop, indicating a local access, the counter is incremented by 1, as illustrated by block 1108.

[0082] In block 1112, the predictor checks whether the counter exceeds a selected threshold. If the counter exceeds the threshold, there are more local accesses to the sample cache lines than remote accesses. The predictor then checks the enable status of the CLLA instruction in block 1114. If the CLLA instruction is enabled, the predictor disables it in block 1116. If the CLLA instruction is already disabled, the predictor makes no changes to the enable status of the CLLA instruction in block 1118 and returns to monitoring sample cache line accesses.

[0083] On the other hand, if the predictor determines in block 1112 that the counter is below the selected threshold, indicating more remote accesses to the sample cache lines than local accesses, the predictor enables the CLLA instruction. In block 1120, the predictor checks for the CLLA instruction's enablement. If the CLLA instruction is disabled, the predictor enables it in block 1122. If the CLLA instruction is already enabled, the predictor makes no changes to the enable status of the cache line demotion instructions in block 1118 and returns to monitoring the sample cache line accesses.

[0084] Fig. 12 shows a similar flowchart illustrating operations and logic for implementing the dual-threshold hardware prediction element, according to another embodiment. In block 1202, the prediction element selects one or more random sample cache lines from a group of cache line demotion candidates in the first cache. The selected sample cache lines are continuously monitored by the prediction element and, for behavior tracking purposes, excluded from demotion by the cache line demotion instruction. The number of selected sample cache lines may depend on the size of the caches. Also, in block 1202, the prediction element starts a counter to compare the number of local core requests to the number of remote snoops accessing the sample cache lines. The initial value of the counter may depend on the selected threshold and / or the size of the caches.

[0085] In block 1204, the predictor tracks each access to the sample cache lines. In block 1206, the predictor determines for each access whether it is from a local core or a remote core. This determination is made by determining whether the access is a remote snoop or not. A remote snoop indicates an access by a remote core, and the counter is decremented by 1, as shown in block 1210. On the other hand, if the access is not a remote snoop, indicating an access in the local core, the counter is incremented by 1, as shown in block 1208.

[0086] In block 1212, the predictor checks whether the counter exceeds the first selected threshold. If the counter exceeds the first threshold, there are more local accesses to the sample cache lines than remote accesses. Therefore, this disables the CLLA instruction in block 1214 and returns to monitoring sample cache line accesses.

[0087] If the counter in block 1212 is not greater than the first selected threshold, the predictor next checks in block 1216 whether the counter is lower than a second selected threshold. If the counter is lower than the second threshold, the predictor enables the CLLA instruction in block 1218 because there are more remote accesses to the sample cache lines than local accesses. The predictor then returns to monitoring the sample cache lines. If the counter is neither higher than the first threshold nor lower than the second, the predictor makes no change to the enable status of the CLLA instruction at block 1220 and returns to monitoring accesses to the sample cache lines.

[0088] Described in detail below are embodiments of processing systems that may utilize the above embodiments.

[0089] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core for general-purpose computing; 2) an out-of-order high-performance general-purpose core for general-purpose computing; 3) a special-purpose core primarily intended for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general-purpose in-order cores for general-purpose computing and / or one or more general-purpose out-of-order cores for general-purpose computing; and 2) a coprocessor including one or more special-purpose cores primarily intended for graphics and / or scientific (throughput).Such different processors result in different computer system architectures, which may include: 1) the coprocessor on a separate die from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as integrated graphics logic and / or scientific (throughput) logic, or as special-purpose cores); and 4) a single-chip system that may include the described CPU (sometimes referred to as application core(s) or application processor(s)), the coprocessor described above, and additional functionality on the same die. Example core architectures are described below, followed by descriptions of example processors and computer architectures. Example core architecturesIn-order and out-of-order core block diagram

[0090] Fig. 13A is a block diagram showing both an example in-order pipeline and an example register renaming, out-of-order issue / execution pipeline according to embodiments of the invention. Fig. 13B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the invention. The solid-line frames in Fig. Figures 13A-B show the in-order pipeline and the in-order core, while the optionally added dashed-line frames show the register renaming and out-of-order issue / execution pipeline and the associated core. Since the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect is described.

[0091] In Fig. 13A, a processor pipeline 1300 includes a fetch stage 1302, a length decode stage 1304, a decode stage 1306, an allocation stage 1308, a rename stage 1310, a scheduling stage (also known as an allocation or issue stage) 1312, a register fetch / memory fetch stage 1314, an execution stage 1316, a write-back / memory write stage 1318, an exception handling stage 1322, and a commit stage 1324.

[0092] Fig. 13B shows a processor core 1390 including a front-end unit 1330 coupled to an execution engine unit 1350, both coupled to a memory unit 1370. Core 1390 may be a reduced instruction set computer (RISC) core, a complex instruction set computer (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As a further option, core 1390 may be a special-purpose core, such as a network or communications core, a compression engine, a coprocessor core, a general-purpose compute on graphics processing unit (GPGPU) core, a graphics core, or the like.

[0093] The front-end unit 1330 includes a branch prediction unit 1332 coupled to an instruction cache unit 1334, which is coupled to an instruction translation lookaside buffer (TLB) 1336, which is coupled to an instruction fetch unit 1338, which is coupled to a decode unit 1340. The decode unit 1340 (or decoder) may decode instructions and produce as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from, or otherwise reflecting or derived from, the original instructions. The decode unit 1340 may be implemented using various mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc.In one embodiment, core 1390 includes a microcode ROM or other medium that stores microcode for specific macroinstructions (e.g., in decode unit 1340 or otherwise within front-end unit 1330). Decode unit 1340 is coupled to a rename / allocation unit 1352 in execution engine unit 1350.

[0094] The execution engine unit 1350 includes the rename / allocation unit 1352, which is coupled to a reorder unit 1354 and a set of one or more scheduling units 1356. The scheduling unit(s) 1356 represent any number of different schedulers, including reservation stations, a central instruction window, etc. The scheduling unit(s) 1356 are coupled to the physical register file unit(s) 1358. Each of the physical register file units 1358 represents one or more physical register files, various of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc.In one embodiment, the physical register file unit 1358 includes a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The physical register file unit 1358 overlaps with the reorder unit 1354 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using one or more reorder buffers and one or more reorder register files; using one or more future files, one or more history buffers, and one or more reorder register files; using tabs and a pool of registers, etc.). The reorder unit 1354 and the physical register file unit(s) 1358 are coupled to the execution cluster(s) 1360.The execution cluster(s) 1360 includes a set of one or more execution units 1362 and a set of one or more memory access units 1364. The execution units 1362 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units all performing the same functions.Scheduling unit(s) 1356, physical register file unit(s) 1358, and execution cluster(s) 1360 are depicted as possibly plural because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipeline, and / or a memory access pipeline, each having its own scheduling unit, its own physical register file unit, and / or its own execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented where only that pipeline's execution cluster includes memory access unit(s) 1364). It should also be understood that when using separate pipelines, one or more of these pipelines may be out-of-order issue / execution, and the rest may be in-order.

[0095] The set of memory access units 1364 is coupled to memory unit 1370, which includes a data TLB unit 1372 coupled to a data cache unit 1374 coupled to a Level 2 (L2) cache unit 1376. In an exemplary embodiment, memory access units 1364 may include a load unit, a memory address unit, and a memory data unit, each coupled to the data TLB unit 1372 in memory unit 1370. Instruction cache unit 1334 is further coupled to a Level 2 (L2) cache unit 1376 in memory unit 1370. L2 cache unit 1376 is coupled to one or more cache levels and ultimately to main memory.

[0096] As an example, the exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 1300 as follows: 1) instruction fetch 1338 executes fetch and length decode stages 1302 and 1304; 2) decode unit 1340 executes decode stage 1306; 3) rename / allocation unit 1352 executes allocation stage 1308 and rename stage 1310; 4) scheduling unit(s) 1356 executes scheduling stage 1312; 5) physical register file unit(s) 1358 and memory unit 1370 execute register fetch / memory fetch stage 1314; the execution cluster 1360 executes the execution stage 1316; 6) the memory unit 1370 and the physical register file unit(s) 1358 execute the write-back / memory write stage 1318; 7) various units may participate in the exception handling stage 1322;and 8) the reorder unit 1354 and the physical register file unit(s) 1358 execute the instruction stage 1324.;

[0097] The core 1390 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions); the MIPS instruction set from MIPS Technologies in Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) from ARM Holdings in Sunnyvale, CA), including the instruction(s) described herein. In one embodiment, the core 1390 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), enabling the operations used by numerous multimedia applications to be performed using packed data.

[0098] It should be noted that the core supports multipathing (execution of two or more parallel sets of operations or paths) and can do so in several ways, including timed multipathing, simultaneous multipathing (when a single physical core provides a logical core for each of the paths, that physical core exhibits simultaneous multipathing), or a combination thereof (e.g., timed fetch and decode and simultaneous multipathing thereafter, as with Intel® Hyperthreading Technology).

[0099] While register renaming has been described in the context of out-of-order execution, it should be understood that register renaming may also be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 1334 / 1374 and a shared L2 cache unit 1376, alternative embodiments may have a single internal cache for both instructions and data, such as an internal Level 1 (L1) cache or multiple levels of internal caches. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or the processor. Alternatively, the entire cache may be external to the core and / or the processor. Specific exemplary in-order core architecture

[0100] Fig. 14A-B shows a block diagram of a more specific example in-order core architecture, where the core is one of several logic blocks (including other cores of the same type and / or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed-function logical memory I / O interfaces and other necessary I / O logic, depending on the application.

[0101] Fig. 14A is a block diagram of a single processor core along with its connection to the on-chip interconnect network 1402 and its local subset of the Level 2 (L2) cache 1404, according to some embodiments of the invention. In one embodiment, an instruction decoder 1400 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 1406 enables low-latency accesses to cache memory in the scalar and vector units. While in one embodiment (to simplify the design) a scalar unit 1408 and a vector unit 1410 use separate register sets (scalar registers 1412 and vector registers 1414, respectively) and data transferred therebetween is written to memory and then read back from a Level 1 (L1) cache 1406, alternative embodiments of the invention may use a different approach (e.g.,use a single register set or include a communication path that allows data to be transferred between two register files without being written and read).

[0102] The local subset of the L2 cache 1404 is part of a global L2 cache, which is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 1404. Data read by a processor core is stored in its L2 cache subset 1404 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1404 and flushed from other subsets as needed. The ring network ensures coherence for shared data. The ring network is bidirectional, allowing agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide per direction.

[0103] Fig. 14B is an expanded view of a portion of the processor core in Fig. 14A according to an embodiment of the invention. Fig. Figure 14B includes an L1 data cache portion 1406A of L1 cache 1404, as well as more details regarding the vector unit 1410 and the vector registers 1414. Specifically, the vector unit 1410 is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 1428) that executes one or more of integer, single-precision equal-point, and double-precision floating-point instructions. The VPU supports swizzling of register inputs with a swizzle unit 1420, numeric conversion with numeric conversion units 1422A-B, and replication with a replication unit 1424 at the memory input. Write mask registers 1426 enable the assertion of resulting vector writes. Processor with integrated memory control and graphics

[0104] Fig. Figure 15 is a block diagram of a processor 1500 that may include one or more cores, an integrated memory controller, and integrated graphics according to embodiments of the invention. The solid-line frames in Fig. 15 illustrates a processor 1500 having a single core 1502A, a system agent 1510, a set of one or more bus control units 1516, while the optionally added dashed line frames illustrate an alternative processor 1500 having multiple cores 1502AN, a set of one or more memory control units 1514 integrated within the system agent unit 1510, and special purpose logic 1508.

[0105] Thus, various implementations of processor 1500 may include: 1) a CPU, where special-purpose logic 1508 is integrated graphics and / or scientific (throughput) logic (which may comprise one or more cores), and cores 1502A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, out-of-order general-purpose cores, a combination of the two); 2) a coprocessor, where cores 1502A-N are a large number of special-purpose cores primarily dedicated to graphics and / or scientific (throughput); and 3) a coprocessor, where cores 1502A-N are a large number of in-order general-purpose cores. Thus, processor 1500 may be a general-purpose processor, coprocessor, or special-purpose processor, such as, for example, a processor 1500A-N.a network or communications processor, a compression engine, a graphics processor, GPGPU (general-purpose compute on graphics processing unit), a high-throughput multi-core (MIC) coprocessor (with 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1500 may be part of or implemented on one or more substrates using any of a variety of process technologies, such as BiCMOS, CMOS, or NMOS.

[0106] The memory hierarchy includes one or more cache levels within the cores, a set of one or more shared cache units 1506, and external memory (not shown) coupled to the set of integrated memory control units 1514. The set of shared cache units 1506 may include one or more mid-level caches, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other cache levels, a last-level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 1512 connects the integrated graphics logic 1508, the set of shared cache units 1506, and the system agent unit 1510 / integrated memory control unit(s) 1514, alternative embodiments may include any number of well-known techniques for interconnecting such units.In one embodiment, coherency is maintained between one or more cache units 1506 and cores 1502-AN.

[0107] In some embodiments, one or more of cores 1502A-N is / are capable of multi-path operation. System agent 1510 includes those components that coordinate and operate cores 1502A-N. System agent unit 1510 may, for example, include a power control unit (PCU) and a display unit. The PCU may be or include logic and components necessary to regulate the power state of cores 1502A-N and integrated graphics logic 1508. The display unit is for operating one or more externally connected displays.

[0108] The cores 1502A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of the cores 1502A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set. Example computer architectures

[0109] Fig. 16-19 are block diagrams of example computer architectures. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, tabletop devices, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of incorporating a processor and / or other execution logic as disclosed herein are generally suitable.

[0110] With reference to Fig. 16 illustrates a block diagram of a system 1600 according to an embodiment of the present invention. System 1600 may include one or more processors 1610, 1615 coupled to a control node 1620. In one embodiment, control node 1620 includes a graphics memory control node (GMCH) 1690 and an input / output node (IOH) 1650 (which are on separate chips); GMCH 1690 includes memory and graphics controllers, to which memory 1640 and coprocessor 1645 are coupled. the IOH 1650 couples input / output (I / O) devices 1660 to the GMCH 1690. Alternatively, one or both of the memory and graphics controllers are integrated into the processor (as described herein), the memory 1640 and the coprocessor 1645 are directly coupled to the processor 1610, and the control node 1620 is present in a single chip with the IOH 1650.

[0111] The optional type of additional processors 1615 is in Fig. 16 is represented by dashed lines. Each processor 1610, 1615 may include one or more of the processing cores described herein and may be a version of processor 1500.

[0112] Memory 1640 may be, for example, dynamic random access memory (DRAM), phase-change memory (PCM), or a combination of the two. In at least one embodiment, control node 1620 communicates with processor(s) 1610, 1615 via a multi-drop bus, such as a front-side bus (FSB), a point-to-point interface, such as a QuickPath interconnect (QPI), or a similar interconnect 1695.

[0113] In one embodiment, coprocessor 1645 is a special-purpose processor, such as a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, GPGPU, an embedded processor, or the like. In one embodiment, control node 1620 may include an integrated graphics accelerator.

[0114] There may be various differences between the physical resources 1610, 1615 with respect to a spectrum of performance metrics including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

[0115] In one embodiment, processor 1610 executes instructions that control data processing operations of a general nature. Coprocessor instructions may be embedded within the instructions. Processor 1610 recognizes these coprocessor instructions as being of the type that should be executed by the attached coprocessor 1645. Accordingly, processor 1610 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1645 on a coprocessor bus or via another interconnect. Coprocessor(s) 1645 accept and execute the received coprocessor instructions.

[0116] With reference to Fig. 17 is a block diagram of a first, more specific, exemplary system 1700 according to an embodiment of the present invention. As shown in Fig. 17, a multiprocessor system 1700 is a point-to-point interconnect system and includes a first processor 1770 and a second processor 1780 connected via a point-to-point interconnect 1750. Each of processors 1770 and 1780 may be a version of processor 1500. In one embodiment of the invention, processors 1770 and 1780 are processors 1610 and 1615, respectively, while coprocessor 1738 is coprocessor 1645. In another embodiment, processors 1770 and 1780 are processor 1610 and coprocessor 1645, respectively.

[0117] Processors 1770 and 1780 are shown with integrated memory control (IMC) units 1772 and 1782, respectively. Processor 1770 further includes, as part of its bus control unit, point-to-point (PP) interfaces 1776 and 1778; similarly, the second processor 1780 includes PP interfaces 1786 and 1788. Processors 1770, 1780 may exchange information via a point-to-point (PP) interface 1750 using PP interface circuits 1778, 1788. As shown in Fig. 17, IMCs 1772 and 1782 couple the processors to corresponding memory, namely a memory 1732 and a memory 1734, which may be parts of a main memory locally attached to the corresponding processors.

[0118] Processors 1770, 1780 may exchange information with a chipset 1790 via individual PP interfaces 1752, 1754 using point-to-point interface circuits 1776, 1794, 1786, 1798. Chipset 1790 may optionally exchange information with coprocessor 1738 via a high-performance interface 1739. In one embodiment, coprocessor 1738 is a special-purpose processor, such as a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, GPGPU, an embedded processor, or the like.

[0119] A shared cache (not shown) may be included in one of the processors or external to both processors, but still connected to the processors via a PP interconnect, so that local cache information from one or both of the processors can be stored in the shared cache when one processor is switched to a low-power mode.

[0120] Chipset 1790 may be coupled to a first bus 1716 via an interface 1796. In one embodiment, first bus 1716 may be a peripheral component interconnect (PCI) bus or a bus such as a PCI Express bus or other third-generation I / O interconnect bus, although the scope of the present invention is not so limited.

[0121] As in Fig. 17, various I / O devices 1714 may be coupled to the first bus 1716, along with a bus bridge 1718 coupling the first bus 1716 to a second bus 1720. In one embodiment, one or more additional processors 1715, such as coprocessors, high-throughput MIC processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field-programmable gate arrays, or any other processor, may be coupled to the first bus 1716. In one embodiment, the second bus 1720 may be a low line count (LPC) bus. Various devices may be coupled to a second bus 1720, including, for example, a keyboard and / or mouse 1722, communication devices 1727, and a memory unit 1728, such asa disk drive or other mass storage device that may contain instructions / code and data 1730, in one embodiment. Furthermore, an audio I / O 1724 may be coupled to the second bus 1720. It should be noted that other architectures are also possible. For example, instead of the point-to-point architecture of . Fig. 17 a system may implement a multidrop bus or other such architecture.

[0122] With reference to Fig. 18 is a block diagram of a second, more specific exemplary system 1800 according to an embodiment of the present invention. Similar elements in Fig. 17 and Fig. 18 have similar reference numbers, and certain aspects of Fig. 17 were in Fig. 18 omitted to avoid obscuring other aspects of Fig. 18 to be avoided.

[0123] Fig. Figure 18 shows that processors 1770, 1780 include integrated memory and I / O control logic ("CL") 1772, 1782, respectively. Thus, CL 1772, 1782 includes integrated memory control units and I / O control logic. Fig. Figure 18 shows that not only are the memory 1732, 1734 coupled to the CL 1772, 1782, but also that the I / O devices 1814 are also coupled to the control logic 1772, 1782. Legacy system I / O devices 1815 are coupled to the chipset 1790.

[0124] With reference to Fig. 19 is a block diagram of an SoC 1900 according to an embodiment of the present invention. Similar elements in Fig. 15 have similar reference numbers. Furthermore, dashed-line frames are optional elements on more advanced SoCs. Fig. 19, one or more interconnect units 1902 are coupled to: an application processor 1910 including a set of one or more cores 202A-N and one or more shared cache units 1506; a system agent unit 1510; one or more bus control units 1516; one or more integrated memory control units 1514; a set of one or more coprocessors 1920, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1930; a direct memory access (DMA) unit 1932; and a display unit 1940 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 1920 include a special-purpose processor, such as aa network or communications processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.

[0125] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a memory system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0126] A program code, such as code 1730, which is in Fig.17, may be used to input instructions to perform the functions described herein and to generate output information. The output information may be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system that includes a processor, such as a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0127] The program code may be implemented in a high-order procedural language or an object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

[0128] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor, which, when read by a machine, cause the machine to generate logic to perform the techniques described herein. Such representations, known as "IP cores," may be stored on a physical, machine-readable medium and provided to various customers or manufacturing facilities for loading into the manufacturing machines that actually manufacture the logic or processor.

[0129] Such machine-readable storage media include, without limitation, non-transitory, physical arrangements of objects formed by a machine or device, including storage media such as hard disks, any other type of storage disk, including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs), e.g., dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memory, electrically erasable programmable read-only memories (EEPROMs), phase-change memories (PCMs), magnetic or optical cards, or other types of media suitable for storing electronic instructions.

[0130] Accordingly, embodiments of the invention also include non-transitory, tangible, machine-readable media containing instructions or design data, such as Hardware Description Language (HDL), that describe structures, circuits, devices, processors, and / or system features discussed herein. Such embodiments may also be referred to as program products.

[0131] In some cases, an instruction converter can be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter can translate (e.g., using static binary translation, where dynamic binary translation includes dynamic compilation), morph, emulate, or otherwise convert an instruction into one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on a processor, off a processor, or partly on and partly off a processor.

[0132] In any system illustrated in a figure, the elements may, in some cases, have the same reference number or a different reference number to indicate that the illustrated elements may be different and / or similar. However, an element may be flexible enough to have various implementations and function with some or all of the systems illustrated or described herein. The various elements illustrated in the figures may be the same or different. Which element is referred to as the first element and which is referred to as the second element is arbitrary.

[0133] Throughout the description and claims, the terms "coupled" and "connected" may be used with their associated derivatives. It is understood that these terms are not used synonymously. In certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

Claims

[1] Device (102) comprising: a plurality of hardware processor cores (114), each of the hardware processor cores having a first cache (116); a second cache (116, 108) communicatively coupled to and shared by the plurality of hardware processor cores; and a prediction means (140) for tracking accesses to a plurality of monitored cache lines in the first cache and controlling activation of a cache line downgrade instruction based on the tracked accesses, wherein execution of the cache line downgrade instruction by one of the plurality of hardware processor cores results in a plurality of unmonitored cache lines in the first cache being moved to the second cache. [2] The apparatus of claim 1, wherein the first cache is a level 1 cache and the second cache is a level 2 cache. [3] The apparatus of claim 1, wherein the first cache is a middle-level cache and the second cache is a last-level cache. [4] The apparatus of any of claims 1-3, wherein the tracked accesses include intra-core accesses and inter-core accesses. [5] The apparatus of claim 4, wherein the inter-core accesses comprise snoop requests. [6] The apparatus of any of claims 1-5, wherein the prediction means comprises a counter for tracking the number of intra-core accesses compared to the number of inter-core accesses. [7] The apparatus of claim 6, wherein the prediction means is to store a first threshold and a second threshold for controlling activation of the cache line demotion instruction by one of the plurality of hardware processor cores. [8] Apparatus according to claim 7, wherein the prediction means is for: to store addresses of a plurality of cache lines in the first cache; increment the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; decrement the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; disable the cache line demotion command when the counter exceeds the first threshold; and to enable the cache line demotion command when the counter falls below the second threshold. [9] Apparatus according to claim 7, wherein the prediction means is for: to store addresses of a plurality of cache lines in the first cache; decrement the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; increment the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; to activate the cache line demotion command when the counter exceeds the first threshold; and to disable the cache line demotion command when the counter falls below the second threshold. [10] The apparatus of any of claims 1-9, wherein each of the plurality of hardware processor cores comprises a decoder for decoding the cache line downgrade instruction and execution hardware for executing a decoded cache line downgrade instruction to move a cache line from the first cache to the second cache. [11] The apparatus of any of claims 1-10, wherein the plurality of monitored cache lines in the first cache are randomly selected. [12] A method implemented in a hardware processor (114), the method comprising: Tracking accesses to a plurality of monitored cache lines in a first cache (116) of the hardware processor; Controlling activation of a cache line downgrade instruction based on the tracked accesses, wherein execution of the cache line downgrade instruction results in a plurality of unmonitored cache lines in the first cache being moved to the second cache (116, 108). [13] The method of claim 12, further comprising: Storing addresses of the plurality of cache lines in the first cache; Maintaining a counter to track the number of intra-core accesses compared to the number of inter-core accesses; Increasing the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; Decrementing the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; Disabling the cache line demotion instruction when the counter exceeds a first threshold; and Enable the cache line demotion command when the counter falls below a second threshold. [14] The method of claim 12, further comprising Storing addresses of a plurality of cache lines in the first cache; Maintaining a counter to track the number of intra-core accesses compared to the number of inter-core accesses; Decrementing a counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; Increasing the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; Enabling the cache line demotion instruction when the counter exceeds a first threshold; and Disable the cache line demotion command when the count falls below a second threshold. [15] A method according to any one of claims 12-14, further comprising: Decoding cache line downgrade instructions; Executing a decoded cache line demotion instruction; and Move a cache line from the first cache to the second cache. [16] A method according to any one of claims 12-15, further comprising: randomly selecting the plurality of monitored cache lines in the first cache. [17] Device (102) comprising: a plurality of hardware processor cores (114), each of the hardware processor cores having a first cache (116); a second cache (116, 108) communicatively coupled to and shared by the plurality of hardware processor cores; and a prediction circuit (140) for tracking accesses to a plurality of monitored cache lines in the first cache and controlling activation of a cache line downgrade instruction based on the tracked accesses, wherein execution of the cache line downgrade instruction by one of the plurality of hardware processor cores results in a plurality of unmonitored cache lines in the first cache being moved to the second cache. [18] The apparatus of claim 17, wherein the first cache is a level 1 cache and the second cache is a level 2 cache. [19] The apparatus of claim 17, wherein the first cache is a middle-level cache and the second cache is a last-level cache. [20] The apparatus of any of claims 17-19, wherein the tracked accesses comprise intra-core accesses and inter-core accesses. [21] The apparatus of claim 20, wherein the inter-core accesses comprise snoop requests. [22] The apparatus of any of claims 17-21, wherein the prediction circuit comprises a counter for tracking the number of intra-core accesses compared to the number of inter-core accesses. [23] The apparatus of claim 22, wherein the prediction circuit is to store a first threshold and a second threshold for controlling activation of the cache line demotion instruction by one of the plurality of hardware processor cores. [24] The apparatus of claim 23, wherein the prediction circuit is arranged to: to store addresses of a plurality of cache lines in the first cache; increment the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; decrement the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; disable the cache line demotion command when the counter exceeds the first threshold; and to enable the cache line demotion command when the counter falls below the second threshold. [25] The apparatus of claim 23, wherein the prediction circuit is arranged to: to store addresses of a plurality of cache lines in the first cache; decrement the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache; increment the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache; to activate the cache line demotion command when the counter exceeds the first threshold; and to disable the cache line demotion command when the counter falls below the second threshold.

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