Substrate-free system in housing design, method for producing such a system and computer device with such a system

Abstract

System-in-Package (1000), SIP, comprehensive: a redistribution layer (104) with a first and a second side opposite the first side; one or more components (111) coupled to the first side, wherein the one or more components (111) have a combined total Z-height above the first side of the redistribution layer (104), the Z-height being measured in a direction perpendicular to the first side or the second side; and one or more electrical intermediate connections (112a-b) coupled to the first side, wherein the electrical intermediate connections (112ab) are solder balls and have a Z-height greater than the combined total Z-height of the one or more components (111); wherein the one or more components (111), the one or more electrical interconnects (112a-b) and the redistribution layer (104) are embedded in a molding compound (114b), wherein the molding compound (114b) has one or more openings to expose the electrical interconnects (112a-b), wherein the exposure of the one or more electrical interconnects (112a-b) comprises the removal of a partial section (114a) of the molding compound together with an upper section of the electrical interconnects (112a-b), such that upper surfaces of the electrical interconnects (112a-b) are partially exposed, wherein the one or more components are a first set of one or more components (111) and the SIP (1000) further comprises a second set of components (106) coupled to the second side of the redistribution layer (104), wherein a component of the first set of components (111) for coupling with the redistribution layer (104) has one or more solder balls on one side of the component, the side of the component facing the first side of the redistribution layer (104).

Description

Technical area

[0001] The present disclosure relates generally to the field of system-in-package (SIP) manufacturing and further relates to the implementation of SIPs with substrate-free designs. background

[0002] In legacy implementations for manufacturing a SIP, a film-assisted molding process and laser ablation processes may be used to define a through-via (TMV) structure within the SIP, which is built using a stripe-level bismaleimide triazine (BT) substrate. These legacy implementations may result in a result that is not entirely reliable and can be a major source of assembly costs. For example, in legacy implementations, wafer- or board-level molding on the secondary side may be implemented using a thin-film material placed over components and solder ball mounts, and a vacuum process used to secure the components during the molding process.

[0003] US 2013 / 0 343 022 A1 describes a system in package (SiP) that includes several device components with different form factors that are embedded in a molding compound.

[0004] US 2016 / 0 027 753 A1 describes a semiconductor device comprising a single-layer substrate with an insulating layer and conductive patterns on a first surface of the insulating layer. Brief description of the drawings

[0005] Embodiments will be readily apparent from the following detailed description when taken in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated in the figures of the accompanying drawings by way of example and not by way of limitation. Fig. 1 shows an example of a wafer or board level carrier with conductive traces according to some embodiments. Fig. 2 shows an example of surface mount components on a primary side of the carrier according to some embodiments. Fig. 3 shows an example of applying wafer or plate level top forming to the primary side of the carrier according to some embodiments. Fig. 4 shows an example of the removal of a portion of a molding compound according to some embodiments, Fig. 5 shows an example of removing the wafer or plate level carrier to expose a second side of the conductive traces according to some embodiments. Fig. 6 shows an example placement of components, solder ball holders, and subsequent reflow to the secondary side 15 of the conductive traces according to some embodiments. Fig. 7 shows an example of wafer or plate level forming onto the second side of the conductive lines according to some embodiments. Fig. 8 shows an example of at least partial exposure of the solder balls according to some embodiments. Fig. 9 shows an example of additional solder on the exposed partial solder balls according to some embodiments. Fig. 10 shows an exemplary substrate-free SIP with TMVs according to some embodiments. Fig. 11 shows an example of dicing wafer or 25 board level packages and removing the completed SIP components according to some embodiments. Fig. 12 shows an exemplary process for creating a substrate-free SIP according to some embodiments. Fig. 13 schematically illustrates an example 30 computing device according to some embodiments. Detailed description

[0006] In embodiments of this disclosure, a system-in-package (SIP) may be built using a wafer carrier or board carrier without the use of a substrate. This may be referred to as a substrate-free SIP. The carrier may have predefined conductive traces deposited thereon. In embodiments, these predefined conductive traces may be fabricated, in non-limiting examples, using lithography processing or redistribution layer (RDL) technology. Interconnects such as TMV interconnects may be built by coupling solder balls to the conductive traces. The side of the conductive traces with the coupled solder balls may be embedded in the molded part. The top surfaces of the embedded solder balls may then be removed by wafer-level or board-level grinding, resulting in TMV interconnects.In embodiments, additional amounts of solder may be applied to the top surface of the TMV interconnects.

[0007] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like reference characters designate like parts throughout, and in which is shown by way of illustration embodiments in which the subject matter of the present disclosure may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure.

[0008] For the purposes of this disclosure, the term "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0009] The description may use the terms "in one embodiment" or "in 30 embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0010] The term "coupled with" and its derivatives may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, yet still cooperate or interact with each other, and that one or more other elements are coupled or connected between the elements that are said to be coupled with each other.

[0011] In various embodiments, the phrase "a first layer formed on a second layer" may mean that the first layer is formed over the second layer and at least a portion of the first layer is formed in direct contact (e.g., direct physical and / or electrical contact) or indirect contact (e.g., with one or more other layers between the first layer and the second layer) with at least a portion of the second layer.

[0012] Embodiments of the present disclosure may result in a significant combined Z-height reduction of the SIP compared to legacy techniques because a wafer- or plate-level carrier is used to create the SIP. In embodiments, the carrier may be thinned below 100 micrometers (µm). The substrate thickness of legacy packages may be approximately 280 micrometers with six metal layers.

[0013] Embodiments of the present disclosure may result in mass production manufacturing / test throughput increases, for example, by adopting a wafer-level and board-level manufacturing process to create SIPs. Older SIP implementations based on the strip-level BT substrate design may accommodate fewer than 50 units per strip. In embodiments, the wafer-level or board-level SIP process may produce hundreds of units per wafer or thousands of units per board. Because many critical integrated circuits (ICs), for example, central processing units (CPUs), application-specific integrated circuits (ASICs), and other complex ICs can be tested during wafer- or board-level assembly, embodiments of this present disclosure may result in significant test time savings over legacy implementations.

[0014] Embodiments of the wafer- or board-level interconnect process may also provide increased component integration. In non-limiting examples, embodiments may accommodate more components in a component Z-height and may achieve a smaller combined SIP Z-height compared to legacy implementations. In embodiments, embedded solder interconnects within a mold compound may be exposed through a wafer- or board-level polishing process. In embodiments, the solder interconnects may also serve as TMVs. The process of exposing the embedded solder interconnects may result in further thinning of unnecessary mold cap clearance into which the solder interconnects and other components may be embedded. In legacy implementations, it may be difficult to reduce the mold cap clearance below 150 micrometers (µm).For example, in some legacy implementations, a film-assisted molding process followed by laser ablation may be used to expose TMV interconnects in legacy implementations, and as a result, an approximately 150 µm thick mold cap clearance may remain between the top of the chip and the top surface of the mold.

[0015] Additionally, the housing thickness can be controlled by grinding the upper mold, eliminating the need for a new mold lock for different housing thicknesses. This can lead to savings in assembly tooling costs compared to outdated systems. Obsolete housings that require the purchase of new mold locks can cost up to $300,000 per mold or more.

[0016] In embodiments, the actions described below may be performed in the order described, in a different order, or in an order in which not all of the described actions may be performed.

[0017] Fig. 1 shows an example of a wafer- or board-level carrier with conductive traces according to some embodiments. The diagram 100 shows a carrier 102 with conductive traces 104 attached to the first side of the carrier 102. In embodiments, non-limiting examples of the material of the carrier 102 may include silicon, stainless steel, and / or glass. The carrier 102 may be a wafer- or board-level carrier. In embodiments, the conductive traces 104 may be specific circuitry that may be placed on one side of the carrier 102. In embodiments, the specific circuitry may be fabricated using a lithography process, an RDL technology, or another process. In embodiments, the conductive traces 104 are constructed to carry electrical signals between various surface-mounted components and other components that may be located within the package and / or two others.In embodiments, the conductive traces 104 may include a plurality of levels of conductive material separated by a dielectric, and may include paths for electrical conduction connecting the plurality of levels at one or more locations.

[0018] Fig. Fig. Figure 2 shows an example of surface-mount components on a primary side of the carrier according to some embodiments. In this disclosure, a primary side is to be distinguished from a secondary side of a carrier, but does not necessarily indicate a preferred side. The diagram 200 shows a non-limiting example of surface-mount components 106 arranged on the primary side of the carrier 102 and coupled to a first side of the conductive traces 104. In embodiments where a silicon or stainless steel carrier is used due to the high thermal conduction properties, the components 106 may be assembled by heating the carrier above the melting temperature of the solder, which in non-limiting examples may be above about 230°C. In other embodiments, the surface-mount components 106 may be assembled using a convection reflow process.

[0019] In embodiments, the surface-mount components 106 may include resistive components 106a, such as a resistor, and / or capacitance components 106b, such as a capacitor. Other embodiments may also include other components, in one non-limiting example, a transistor. These components may be coupled to the conductive traces 104 by the solder 106g.

[0020] In embodiments, the surface-mount components 106 may also include integrated circuit components 106c, 106d. In non-limiting examples, an integrated circuit may be a combination of one or more integrated circuits, such as a first integrated circuit 106c coupled to a second integrated circuit 106d via a coupling layer 106e. In non-limiting examples, the first integrated circuit 106c may be coupled to the conductive traces 104 through one or more solder balls 106h. In embodiments, wires 106f may be used to directly couple the second integrated circuit 106d to the conductive traces 104. In other embodiments, a single chip, more than two chips, a plurality of chips side by side, and the like may be coupled to the conductive traces 104.

[0021] Fig. Figure 3 shows an example application of applying a wafer- or plate-level top mold to the primary side of the carrier according to some embodiments. Diagram 300 shows a mold 108 being applied to the primary side of the carrier 102. In embodiments, the mold 108 may encapsulate the surface-mount components 106 on the primary side of the carrier 102. In embodiments, a molding compound may be made of a polymer-based material, and transfer or compression molding may be used to encapsulate components, such as surface-mount components 106.

[0022] Fig. 4 shows an example of the removal of a portion of a molding compound according to some embodiments. The diagram 400 shows a top portion 108a that has been removed, leaving the remaining mold part 108b. In embodiments, the surface-mount components 106 may still be embedded in the remaining mold part 108b. In embodiments, the top portion 108a may be removed from the molding compound 108 by wafer- or plate-level grinding. In embodiments, this may be conventional mechanical grinding using polishing papers or sandpaper. In embodiments, a narrow mold cap clearance 110 may be achieved by grinding the portion of the molding compound 108a to a point proximate the surface-mount components 106.

[0023] Fig. 5 shows an example of the removal of a wafer or board-level carrier on a second side of the conductive traces, according to some embodiments. Diagram 500 shows the package of diagram 400 flipped over and with the carrier 102 removed. In embodiments, the removal may be performed through a grinding process that exposes the second side of the conductive traces 104. In embodiments, this may expose the metal bond pad (not shown for clarity), which may be used for component placement on the second side of the conductive traces 104. In embodiments, a very uniform grinding may be achieved.

[0024] Fig. Figure 6 shows an example placement of the components, solder ball supports, and subsequent reflow to the second side of the conductive traces according to some embodiments. In embodiments, an air convection or infrared reflow system may be used. In one example of a wafer-level SiP, the reflow may be performed using a rotating reflow machine. In another example, a conveyor-type reflow machine may be used for the board-level SiP.

[0025] Diagram 600 shows surface-mount components 111 coupled to the second side of conductive traces 104. In embodiments, surface-mount components 111 may include a single IC, more than two ICs, adjacent ICs, capacitors, resistors, and / or another surface-mount component. In embodiments, solder balls 112a, 112b are coupled to the second side of conductive traces 104. In embodiments, solder balls 112a and 112b may serve as TMVs, as described later in Fig. 9 is described.

[0026] Fig. Figure 7 shows an example of wafer- or plate-level molding onto the second side of the conductive lines according to some embodiments. Diagram 700 shows a mold part 114 being introduced onto the second side of the conductive lines 104. In embodiments, the mold part 114 may be applied in a manner similar to the mold part 108 or in a different manner. In embodiments, the mold part 114 may completely enclose the components 111 and the solder balls 112a, 112b.

[0027] Fig. 8 shows an example of at least partially exposing solder balls according to some embodiments. Diagram 800 shows an upper portion of the mold part 114 that has been removed 114a to leave the remaining mold part 114b. In embodiments, the top surfaces of the solder balls 112a, 112b may be exposed to provide electrical conductivity to the conductive traces 104. In embodiments, the components 111 may still be enclosed in the remaining mold part 114b. In embodiments, the removal process may be a wafer- or board-level grinding or polishing process. Using such a process may result in a significant reduction of unpredictable expansions and deformations that may occur when using laser drills to expose the top surfaces of the solder balls.

[0028] Fig. Figure 9 illustrates the addition of additional solder to the exposed partial solder balls according to some embodiments. Diagram 900 illustrates additional solder 116a, 116b being added to the solder balls 112a, 112b. In embodiments, a solder bump may be defined by printing solder pastes using a solder stamping process or by individually picking and placing micro solder balls. In embodiments, this may enable easier electrical coupling between the SIP and the components to which the SIP may be attached.

[0029] Fig. 10 shows an exemplary substrate-less SIP with TMVs according to some embodiments. The diagram 1000 shows a first set of components 106 electrically coupled to a first side of the conductive traces 104. A second set of components 111 is electrically connected to a second side of the conductive traces 104. The remaining mold part 108b encloses the first set of components 106 and at least a portion of the first side of the conductive traces 104. A second mold part 114b encloses the second set of components 111 and may surround, but not completely enclose, the solder balls 112a, 112b, which may serve as TMVs. An additional solder paste stencil or the solder balls 116a, 116b may be attached to the exposed portion of the solder balls 112a, 112b, which may form TMVs.

[0030] Fig. Figure 11 shows an example of dicing wafer or plate-level packages and removing the finished SIP components according to some embodiments. Diagram 1100 shows a wafer 120 having a plurality of substrate-free SIPs 1000, and also a plate 122 having a plurality of substrate-free SIPs 1000. In embodiments, one or more processes as in Fig. 1 to Fig. 9, to create wafer 120 or plate 122, which may include multiple substrate-free SIPs. Once wafer 120 or plate 122 has been created, it may be diced to separate the individual SIPs 1000. In embodiments, this may be achieved using a diamond blade sawing process, laser cutting process, or plasma etching process.

[0031] Fig. 12 illustrates an exemplary process for creating a substrate-free SIP according to some embodiments. Process 1200 may be used to create a substrate-free SIP, such as package assembly 1000, according to some embodiments.

[0032] At block 1202, the process may include providing a conductive trace layer on a first side of a carrier. In embodiments, the conductive trace layer may be similar to the conductive traces 104 shown in Fig. 1. In embodiments, the conductive layer may be formed by a lithography processing or redistribution layer (RDL) technology applied to the first side of the carrier. In embodiments, the carrier may be a wafer carrier, a plate-level carrier, or another carrier, and may be similar to the carrier 102 of Fig. 1. In embodiments, the carrier may be made of a material that may include silicon, stainless steel, and / or glass.

[0033] At block 1204, the process may include coupling a first set of one or more surface-mount components to a first side of the conductive trace layer opposite the carrier. As explained above, the first set of one or more surface-mount components may be similar to the surface-mount components 106 of Fig. 1. The components may include integrated circuits 106c, 106d, resistance components 106a, capacitance components 106b, and / or some other components. In embodiments, the components may be coupled to the conductive trace layer that corresponds to the conductive trace layer 104 of Fig. 2 may resemble.

[0034] At block 1206, the process may include embedding the first set of one or more surface-mounted components in a molding compound. In embodiments, the one or more surface-mounted components may be similar to the surface-mounted components 106 of Fig. 1. The molding compound can be similar to Fig. 3 are similar to the molding compound 108 shown.

[0035] At block 1208, the process may include exposing a second side of the conductive trace layer from the first side of the conductive trace layer. In embodiments, this may be similar to the top side of the conductive trace layer 104, as shown in Fig. 5 after the carrier 102 has been removed.

[0036] At block 1210, the process may include coupling one or more electrical interconnects to the second side of the conductive trace layer. In embodiments, the electrical interconnects may be solder balls 112a, 112b, as shown in Fig. 6. As explained above, in embodiments, the electrical interconnections may be coupled to a second side of the conductive traces 104.

[0037] Fig. 13 schematically illustrates a computing device 1300 according to some embodiments, which may include one or more housing assemblies 1000, which in Fig. 10 are shown.

[0038] Embodiments of the present disclosure may be implemented in a system using any suitable hardware and / or software for configuration as desired. Fig. 13 schematically illustrates a computing device 1300 according to one embodiment. Computing device 1300 may include a circuit board such as motherboard 1302 (i.e., housing 1351). Motherboard 1302 may include a number of components, including, but not limited to, a processor 1304 and at least one communication chip 1306. Processor 1304 may be physically and electrically coupled to motherboard 1302. In some implementations, at least one communication chip 1306 may also be physically and electrically coupled to motherboard 1302. In further implementations, communication chip 1306 may be part of processor 1304.

[0039] Depending on its applications, the computing device 1300 may include other components that may or may not be physically and electrically coupled to the motherboard 1302. These other components may include volatile memory (e.g., dynamic read-only memory (DRAM)) 1320, non-volatile memory (e.g.,Read-only memory (ROM) 1324, flash memory 1322, a graphics processor 1330, a digital signal processor (not shown), a cryptoprocessor (not shown), a chipset 1326, an antenna 1328, a display (not shown), a touchscreen display 1332, a touchscreen controller 1346, a battery 1336, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP) 1341, a global positioning system (GPS) device 1340, a compass 1342, an accelerometer (not shown), a gyroscope (not shown), a speaker 1350, a camera 1352, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so on) (not shown). Other components described in . Fig. 13, may include a microphone, a filter, an oscillator, a pressure sensor, or an RFID (Radio Frequency Identification) chip. In embodiments, one or more of the housing assembly components 1355 may be a housing assembly such as the housing assembly 1000 as shown in Fig. 10 shown.

[0040] The communication chip 1306 may enable wireless communication for transferring data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, processes, techniques, communication channels, etc., that can transfer data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although this may not be the case in some embodiments. The communication chip 1306 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) Project, along with any amendments, updates, and / or testing (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) Project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that demonstrate conformance and interoperability testing for the IEEE 802.16 standards. The communication chip 1306 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.The communication chip 1306 may also be configured to operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1306 may operate according to CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocol referred to as 3G, 4G, 5G, and beyond. The communication chip 306 may operate according to other wireless protocols in other embodiments.

[0041] Computing device 1300 may include a plurality of communication chips 1306. For example, a first communication chip 1306 may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 1306 may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

[0042] The processor 1304 of the computing device 1300 may include a chip in a package assembly, such as the package assembly 1000, which may be Fig. 10 and described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that may be stored in registers and / or memory.

[0043] In various implementations, computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.

[0044] The following paragraphs provide examples of various embodiments disclosed herein.

[0045] Example 1 may be a system-in-package (SIP) comprising: a redistribution layer having a first and a second side opposite the first side; one or more components coupled to the first side, the one or more components having an aggregate total Z-height above the first side of the redistribution layer, the Z-height being measured in a direction perpendicular to the first side or the second side; and one or more electrical interconnections coupled to the first side, the electrical interconnections having a Z-height greater than the aggregate total Z-height of the one or more components.wherein the one or more components, the one or more electrical interconnections, and the redistribution layer are embedded in a molding compound, the molding compound having one or more openings to expose the electrical interconnections;

[0046] Example 2 may comprise the subject matter of Example 1, wherein the electrical interconnections are solder balls.

[0047] Example 3 may include the subject matter of Example 1, wherein having one or more openings for exposing the electrical interconnections further comprises exposing the electrical interconnections through a grinding process.

[0048] Example 4 may include the subject matter of Example 1, wherein the electrical interconnections are vias, TMV.

[0049] Example 5 may include the subject matter of Example 1, wherein the one or more components are a first set of one or more components, and the SIP further comprises a second set of components coupled to the second side of the redistribution layer.

[0050] Example 6 may comprise the article of Example 5, wherein the second set of components is within a mold layer.

[0051] Example 7 may include the subject matter of any of Examples 1 to 6, wherein the one or more components are integrated circuit components or resistance and capacitance components.

[0052] Example 8 may be a method of creating a substrate-free system-in-package, SIP, the method comprising: providing a conductive trace layer on top of a first side of a carrier, coupling a first set of one or more surface-mounted components to a first side of the conductive trace layer opposite the carrier, embedding the first set of one or more surface-mounted components in a molding compound, exposing a second side of the conductive trace layer opposite the first side of the conductive trace layer, and coupling one or more electrical interconnects to the second side of the conductive trace layer.

[0053] Example 9 may include the subject matter of Example 8, wherein the electrical interconnections are solder balls.

[0054] Example 10 may include the subject matter of Example 8, further comprising coupling a second set of one or more surface mount components to the second side of the conductive trace layer.

[0055] Example 11 may include the article of any of Examples 9 to 10, further comprising embedding the one or more electrical interconnects coupled to the second side of the conductive trace layer in a molding compound.

[0056] Example 12 may include the subject matter of Example 11, further comprising exposing a surface of the one or more electrical interconnections.

[0057] Example 13 may include the subject matter of Example 12, wherein exposing a surface of the one or more electrical interconnections comprises exposing a surface of the one or more electrical interconnections by grinding.

[0058] Example 14 may include the subject matter of any of Examples 11 to 12, wherein the electrical interconnections are vias, TMVs.

[0059] Example 15 may include the subject matter of any of Examples 8 to 10, wherein exposing a second side of the conductive layer opposite the first side of the conductive layer further comprises removing the carrier to expose the second side of the conductive layer.

[0060] Example 16 may include the article of Example 15, wherein removing the carrier further comprises removing the carrier using an abrasive process.

[0061] Example 17 may include the subject matter of any of Examples 8 to 10, wherein the conductive layer further comprises a redistribution layer.

[0062] Example 18 may include the subject matter of any of Examples 8 to 10, wherein the carrier further comprises a wafer carrier or a plate-level carrier.

[0063] Example 19 may comprise the article of any of Examples 8 to 10, wherein the support is made of silicon, glass, or stainless steel.

[0064] Example 20 may include the subject matter of any of Examples 8 to 10, wherein the one or more surface mount components are integrated circuit components or resistance and capacitance components.

[0065] Example 21 may be a computing device comprising: a substrate; and a system-in-package, SIP, coupled to the substrate, the SIP comprising: a redistribution layer having first and second sides opposite the first side; one or more components coupled to the first side, the one or more components having an aggregate total Z-height above the first side of the redistribution layer, the Z-height measured in a direction perpendicular to the first side or the second side; and one or more electrical interconnections coupled to the first side, the electrical interconnections having a Z-height that is greater than the aggregate total Z-height of the one or more components.wherein the one or more components, the one or more electrical interconnections, and the redistribution layer are embedded in a molding compound, the molding compound having one or more openings to expose the electrical interconnections;

[0066] Example 22 may include the subject matter of Example 21, wherein the electrical interconnections are solder balls.

[0067] Example 23 may include the subject matter of Example 21, wherein having one or more openings for exposing the electrical interconnections further comprises exposing the electrical interconnections through a grinding process.

[0068] Example 24 may include the subject matter of any of Examples 21 to 23, wherein the electrical interconnections are vias, TMV.

[0069] Example 25 may include the subject matter of Example 21, wherein the one or more components are a first set of one or more components, and the SIP further comprises a second set of components coupled to the second side of the redistribution layer.

[0070] Example 26 may comprise the subject matter of Example 25, wherein the second set of components is within a mold layer.

[0071] Example 27 may include the subject matter of any of Examples 21 to 23, wherein the one or more components are integrated circuit components or resistance and capacitance components.

Claims

[1] System-in-Package (1000), SIP, comprising: a redistribution layer (104) having a first and a second side opposite the first side; one or more components (111) coupled to the first side, wherein the one or more components (111) have a combined total Z-height above the first side of the redistribution layer (104), the Z-height being measured in a direction perpendicular to the first side or the second side; and one or more electrical interconnections (112a-b) coupled to the first side, the electrical interconnections (112ab) being solder balls and having a Z-height greater than the combined total Z-height of the one or more components (111); wherein the one or more components (111), the one or more electrical interconnections (112a-b), and the redistribution layer (104) are embedded in a molding compound (114b), the molding compound (114b) having one or more openings to expose the electrical interconnections (112a-b), wherein exposing the one or more electrical interconnections (112a-b) comprises removing a portion (114a) of the molding compound together with an upper portion of the electrical interconnections (112a-b), such that upper surfaces of the electrical interconnections (112a-b) are partially exposed, wherein the one or more components are a first set of one or more components (111) and the SIP (1000) further comprises a second set of components (106) coupled to the second side of the redistribution layer (104), wherein a component of the first set of components (111) for coupling to the redistribution layer (104) has one or more solder balls on a side of the component, the side of the component facing the first side of the redistribution layer (104). [2] The SIP of claim 1, wherein having one or more openings for exposing the electrical interconnections (112a-b) further comprises exposing the electrical interconnections by a grinding process. [3] The SIP of claim 1, wherein the electrical interconnections (112a-b) are vias, TMV. [4] The SIP of claim 1, wherein the second set of components (106) is within a mold layer (108b). [5] The SIP of any one of claims 1 to 4, wherein the one or more components (106, 111) are integrated circuit components or resistance and capacitance components. [6] A method (1200) for producing a substrate-free system-in-package, SIP, the method comprising: Providing (1202) a conductive layer on a first side of a carrier; coupling (1204) a first set of one or more surface-mounted components to a first side of the conductive layer opposite the carrier; embedding (1206) the first set of one or more surface-mounted components in a molding compound; Exposing (1208) a second side of the conductive layer from the first side of the conductive layer; coupling (1210) one or more electrical interconnects to the second side of the conductive layer, wherein the electrical interconnects are solder balls, coupling a second set of one or more surface-mounted components to the second side of the conductive layer, Embedding the one or more electrical interconnects coupled to the second side of the conductive layer in a molding compound and Exposing a surface of the one or more electrical interconnections. [7] The method (1200) of claim 6, wherein exposing a surface of the one or more electrical interconnections comprises exposing a surface of the one or more electrical interconnections by grinding. [8] The method (1200) of any of claims 6 or 7, wherein the electrical interconnections are vias, TMV. [9] The method (1200) of any one of claims 6 to 8, wherein exposing a second side of the conductive layer from the first side of the conductive layer further comprises removing the carrier to expose the second side of the conductive layer. [10] The method (1200) of claim 9, wherein removing the carrier further comprises removing the carrier using a grinding process. [11] The method (1200) of any one of claims 6 to 10, wherein the conductive layer further comprises a redistribution layer. [12] The method (1200) of any one of claims 6 to 11, wherein the carrier further comprises a wafer carrier or a plate-level carrier. [13] The method (1200) of any one of claims 6 to 12, wherein the support is made of silicon, glass or stainless steel. [14] The method (1200) of any one of claims 6 to 13, wherein the one or more surface-mounted components are integrated circuit components or resistance and capacitance components. [15] A computer device (1300) comprising: a substrate; and a system-in-package (1000), SIP, coupled to the substrate, the SIP comprising: a redistribution layer (104) having a first and a second side opposite the first side; one or more components (111) coupled to the first side, wherein the one or more components (111) have a combined total Z-height above the first side of the redistribution layer (104), the Z-height being measured in a direction perpendicular to the first side or the second side; and one or more electrical interconnections (112a-b) coupled to the first side, wherein the electrical interconnections (112a-b) are solder balls and have a Z-height greater than the combined total Z-height of the one or more components (111); wherein the one or more components (111), the one or more electrical interconnections (112a-b), and the redistribution layer (104) are embedded in a molding compound (114b), the molding compound (114b) having one or more openings to expose the electrical interconnections (112a-b), wherein exposing the one or more electrical interconnections (112a-b) comprises removing a portion (114a) of the molding compound together with an upper portion of the electrical interconnections (112a-b), such that upper surfaces of the electrical interconnections (112a-b) are partially exposed, wherein the one or more components are a first set of one or more components and the SIP (1000) further comprises a second set of components (106) coupled to the second side of the redistribution layer (104), wherein a component of the first set of components (111) for coupling to the redistribution layer (104) has one or more solder balls on a side of the component, the side of the component facing the first side of the redistribution layer (104). [16] The computing device (1300) of claim 15, wherein having one or more openings for exposing the electrical interconnections (112a-b) further comprises exposing the electrical interconnections through a grinding process. [17] The computer device (1300) of claim 15 or 16, wherein the electrical interconnections (112a-b) are vias, TMV.

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