Hash table in a pipeline with reduced collisions

Abstract

Network device (100, 200) for performing a pipeline hash function, comprising: a first memory (110, 210) for storing a first plurality of bucket records, a second memory (140, 240) for storing a plurality of entry records; a third memory (150, 250) for storing a second plurality of bucket records; and a hash circuit (120, 220) for receiving a key and performing a pipeline hash function using the key to provide a hash value, wherein the hash circuit (120, 220) further selects a first bucket record of the first plurality of bucket records from the first memory (110, 210) based on a first subset of bits of the hash value, wherein the hash circuit (120, 220) further provides an indication of a position of a particular entry of an entry record of the plurality of entry records based on the content of the first bucket record and a second subset of bits of the hash value, and an output logic circuit (160, 260) for providing a hit indication in response to a hit in an entry of a bucket record of the second plurality of bucket records or in response to a match between the key and a key value stored in the respective entry of the entry record.

Description

BACKGROUND OF THE INVENTION

[0001] Modern switching hardware supports complex packets that stack multiple protocols, such as Multiprotocol Label Switching (MPLS), Stacked Virtual Local Area Network (VLAN), and Internet Protocol (IP)-in-IP. To process a packet, hardware can classify each packet by comparing a key extracted from the packet against a table of flow entries. Virtualization, tunneling, OpenFlow, and Network Address Translation (NAT) applications can require a flow table of more than 100,000 entries, each 64 or more bytes in size. Some protocols require the classification process for a packet to occur within a single clock cycle, with low latency and low power consumption.

[0002] Some memory architectures, such as content-addressable memory (CAM), can incorporate deterministic table structures for low-latency classification, but they can also consume significantly more power (e.g., ten times more) and require significantly more area (e.g., four times more or more) than a random-access memory (RAM) of the same size. In some examples, hash tables can be used in a RAM architecture due to the limitations of a CAM architecture; however, RAM architectures also have limitations, such as the inability to fill a RAM architecture to capacity (e.g., only 60% capacity) due to collision and latency issues.

[0003] US 5 920 900 A shows a hash-based translation method and apparatus with multi-stage collision resolution, wherein a translation is performed by applying a programmable hash method to an input number to generate a hashed number.

[0004] The stated object is achieved according to the invention by the features of patent claims 1 and 9. Further embodiments of the invention are presented in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In the drawings, which are not necessarily to scale, like reference numerals may refer to similar components in different views. Like reference numerals with different suffix letters may represent different instances of similar components. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in this document. Fig. 1 illustrates components of an apparatus including a pipelined hash circuit according to some embodiments. Fig. 2 illustrates components of an apparatus including a pipelined hash circuit according to some embodiments. Fig. 3 illustrates components of an example implementation of a pipelined hash circuit according to some embodiments. Fig. 4 illustrates a method for performing a pipelined hashing operation according to some embodiments. Fig. 5 illustrates a method for performing a pipelined hashing operation according to some embodiments. Fig. 6 illustrates a method for generating a mask value for colliding hash values ​​according to some embodiments. Fig. 7 illustrates components of a network device having a pipelined hash circuit according to some embodiments. DETAILED DESCRIPTION

[0006] Some network-based packet processing solutions have so far focused on the application of various hash functions, such as d-left, cuckoo hashing, binary search tree (BST) functions, and dynamic perfect hashing. However, all of these functions suffer from some combination of latency and collision issues, requiring a significant CAM architecture to complement the RAM architecture, which can drastically increase memory overhead, e.g., by 40% or more.

[0007] The described embodiments provide a way to utilize the full capacity of a RAM architecture device while avoiding the latency problems of previous solutions. The ability to utilize the full capacity of the RAM architecture device can reduce the memory overhead to 1% or less. Furthermore, since the memory overhead can be approximately 1% or less, the power consumption required to access a memory device with significantly lower overhead in response to a miss attempt can also be reduced.

[0008] Embodiments provide methods, systems, and apparatus in the control plane for performing pipelined hash table processing to determine a process flow for packet processing. Pipelined hash table processing may be performed on data plane components, including, as non-limiting examples, Data Plane Development Kit (DPDK) components, Field Programmable Gate Array (FPGA) components, and switching components available from Intel® of Santa Clara, California, among other components. Methods according to various embodiments may coordinate the use of these and other components in a dynamic and flexible manner based on user-defined and user-configured actions to reduce or minimize power consumption or improve speed and performance.In embodiments, a control plane may offload a simple, fast packet processing pipeline from software-based switches or virtual switches to switching hardware, while providing more sophisticated processing at the data plane to CPU-based software.

[0009] Fig. Figure 1 illustrates components of an apparatus 100 for performing pipelined hashing methods according to some embodiments. The illustration of the embodiments includes only those components necessary for evaluating the illustrated embodiments, so that other components can be anticipated without departing from the teachings of the present specification.

[0010] The device 100 may include a receiver 104 to receive a packet and provide a process flow key KEY to a hash circuit 120 and a memory 150. The hash circuit 120 may perform a pipelined hash function using the key KEY to provide a hash value and may provide an entry pointer ENTRY_POINT to indicate a position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means for identifying a particular position in the memory 140) of an entry of an entry record of a plurality of entry records stored in a memory 140, based on the hash value and a plurality of bucket records stored in a memory 110. An output logic circuit 160 may receive the entry (e.g., M2 KEY / ACTION) from memory 2 140 and provide an output (e.g.,HIT-NUMBER / ACTION) from an entry of an entry record of a plurality of entry records stored in memory 3 150 to provide an output hit indication HIT-NUMBER and an output action ACTION to an output.

[0011] Receiver 104 may include circuitry to receive a packet and generate the KEY based on the contents of the packet. The KEY may be used by device 100 to determine a process flow for the packet. This means that each key may be associated with an action used to process a packet. The KEY may be based on a source IP address, a destination IP address, applications or protocols associated with the packet, and other data included in the packet. For complex packet architectures, the number of process flows may be 100,000 or more. Accordingly, the KEY may be sufficiently large (e.g., 424 bits or more) to cover the large number of process flows.

[0012] Hash circuit 120 may process the KEY to provide the ENTRY_ZGR to indicate the position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular position of Memory 2 140) of an entry in a bucket of Memory 2 140. Hash circuit 120 may include a hash module 124 to perform a hash function on the KEY to provide a hash value, which may have two parts, e.g., a HASH1 value (e.g., a first subset of bits) and a HASH2 value (e.g., a second subset of bits). The value HASH1 may indicate a location (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular location of memory 1 110) to a bucket record BR1 stored in memory 1 110.Hash circuit 120 may further include bucket logic circuitry 128 that processes the HASH2 value and data stored in BR1 to provide the EINTR-ZGR. In some examples, the hash value is 30 bits long, with the HASH1 value comprising 14 bits and the HASH2 value comprising 16 bits, although embodiments are not so limited.

[0013] Memory 2 140 may provide a key / action pair M2 KEY / ACTION stored in an entry of an entry record referenced by the ENTRY_ZGR to output logic circuit 160. Memory 3 150 may receive the KEY from receiver 104 and may provide a hit indication (Hit, e.g., an indication of whether memory 3 150 contains an entry record with a key that matches the KEY received from receiver 104) and the action pair M3 HIT_NUMBER / ACTION. If no entry record is found, M3 HIT_NUMBER may indicate a miss, and no action may be provided by memory 3 150. In some examples, memory 1 110 and / or memory 2 140 may have a RAM architecture, and memory 3 150 may have a CAM architecture.

[0014] Output logic circuitry 160 may include circuitry to receive the M3 TREF-NUMBER / ACTION pair as provided by Memory 3 150 and the M2 KEY / ACTION pair as provided by Memory 2 140, and may provide the TREF-NUMBER and the ACTION. The ACTION may define the process flow for the packet. The packet may be processed by other circuitry (not shown) of device 100 based on the ACTION.

[0015] In operation, the receiver 104 may receive a packet. The packet may be a complex packet in which multiple protocols are stacked, for example, MPLS, Stacked VLAN, IP-in-IP, etc. It will be appreciated that usages other than processing a packet may be realized and that the device 100 may also be used for content other than packet processing. The receiver 104 may generate the KEY based on the content of the packet, which is used to determine a process flow for the packet. Due to the complexity and diverse possibilities of packet construction, the number of possible process flows that must be evaluated for a given packet may be 100,000 or more. The memory 2 140 and the memory 3 150 may store process flow entries in entry records for each process flow under consideration, and if a non-existent process flow is detected (e.g.,a failed attempt), the entry records of Memory 2 140 and / or Memory 3 150 may be updated to reflect the new process flow. Instead of performing a time-consuming sequential comparison of keys stored in each entry record of Memory 2 140 with the KEY, the hash circuit 120 and Memory 1 110 may perform a pipelined hash function using the KEY to indicate a location (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular location of Memory 2 140) of a likely matching entry in an entry record of Memory 2 140.

[0016] The idea behind hashing may be to distribute entries (e.g., key / action pairs) across an array of entry records stored in a memory such as memory 2 140. Ideally, given a key, a hash function generates a hash value that is used to provide a pointer to indicate the location of an entry record containing the target key / action pair. However, hashing often leads to collisions where the distribution of entries is imperfect because it is impractical or impossible to consider every possible combination of bits in the key values. Therefore, a hash function may generate the same hash value for two different keys, leading to collisions. In these cases, an entry record stored in a memory may contain two or more different entries.Furthermore, it is often unknown which entry record(s) must contain more than one entry, or how many entries each entry record requires. One way to deal with the possibility of more than one entry per entry record is to allocate storage space for a predetermined number of entries for each entry record, where the predetermined number is chosen based on a likely maximum number of entries necessary for a given entry record. However, since many of the entry records will use fewer than the predetermined number, a large amount of storage may remain unused.

[0017] The combination of memory 1 110 and hash circuit 120 may provide or enable a method for uniquely identifying and pointing to a specific entry of a bucket record stored in memory 2 140 based on the key in a single clock cycle (e.g., because the hash function in the pipeline is designed to execute once during a clock cycle). Furthermore, for each received key value, memory 1 110 and memory 2 140 are only accessed (e.g., read) once each (e.g., a single lookup operation per received key value). The combination of memory 1 110 and hash circuit 120 may also enable efficient use of memory 2 140 such that each entry record is allocated memory only for the actually stored entries, rather than being allocated based on the number of possible entries.This means that if an entry record stored in memory 2 140 only has three entries out of a possible 32 entries stored, these three entries can be stored consecutively and the next entry record can begin immediately after the last of the three entries.

[0018] Hash module 124 may perform a hash function on the KEY to provide the value HASH1 and the value HASH2. The value HASH1 may be provided to Memory 1 110 to retrieve BR1 from Memory 1 110. BR1 may include three fields that may be used with the value HASH2 to provide the ENTRY_ZGR to Memory 2 140. The first field may include a bucket pointer. The bucket pointer may identify a starting address position of a first entry of an entry record of Memory 2 140 containing the entry corresponding to the KEY.

[0019] The second field may comprise a mask field. The mask field may identify which of the possible entries for the entry record of memory 2 140 are currently stored in memory 2 140. For example, it may be possible to store up to 32 entries for an entry record of memory 2 140, but only a subset of these entries are actually used (e.g., the 2nd, 4th, and 30th entries may actually be used). The mask field may be a group of bits equal to a number of possible assigned entries (e.g., 32 bits in the example), with only the bits set for the entries actually stored in the entry record in memory 2 140 (e.g., bits 2, 4, and 30 in the example).

[0020] The third field may include a selection field. The selection field may contain a series of values ​​(e.g., selection values) that identify a subset of individual bits of the HASH2 value, which can be used to uniquely identify which entry of the entry data set stored in memory 2 140 is associated with the key. The order of the entries and the respective selection values ​​may be algorithmically determined such that a subset of the HASH2 bits is selected that results in a different aggregate value for each entry of an entry data set.

[0021] To determine the EINTR_AUSW value, the bucket logic circuitry 128 may first apply the selection values ​​to the HASH2 value to provide an EINTR_AUSW value. The EINTR_AUSW value may identify a particular entry of the entry record stored in Memory 2 140 associated with the key. The number of bits in the EINTR_AUSW value may be based on a number of possible entries for a given entry record. For example, if an entry record may contain up to 32 entries, the EINTR_AUSW value may include at least five bits selected from the HASH2 value based on the selection values ​​from BR1. The hash circuitry 120 may then determine how many of the possible previous entries (e.g., sequentially prior to the particular entry to be identified by the EINTR_AUSW value) of the entry record are actually stored with the entry record in Memory 2 140.In the example, if the entry in question identified by EINTR_AUSW is the 30th entry, and the only other entries actually stored in the entry record are the second and fourth entries, only two previous entries exist. Finally, hash circuit 120 can insert the number of stored previous entries multiplied by an entry size of each entry into the bucket pointer to provide the EINTR_ZGR.

[0022] At an output, Memory 2 140 may provide the M2 key / action pair to output logic circuitry 160 selected based on the entry count. Occasionally, the use of hash functions may result in situations where it is impossible to distinguish between collisions (e.g., distinguishing between two keys based on the hash values). In other examples, an entry record may be filled beyond the allocated number of entries (e.g., more than 32 entries in the examples discussed above). For these special cases, Memory 3 150 may store key / action pairs as entry records to supplement the entry records stored in Memory 2 140.In parallel with the provision of M2 KEY / ACTION from Memory 2 140, Memory 3 150 can compare the KEY with entries stored in Memory 3 150 and, based on the comparison, provide the M3 MATCH COUNT / ACTION pair to output logic circuit 160. For example, if there is a hit, the M3 MATCH COUNT will indicate the hit, and the corresponding ACTION can be provided. If the comparison results in a miss (e.g., none of the keys stored in Memory 3 150 correspond to the KEY), the M3 MATCH COUNT indicates a miss, and no ACTION can be provided.

[0023] Output logic circuitry 160 may provide the HIT COUNT and the ACTION based on the outputs received from Memory 2 140 and Memory 3 150. In one example, a hit from M3 takes precedence over a matching key from Memory 2 140. For example, if the M3 HIT COUNT from Memory 3 150 indicates a hit, output logic circuitry 160 may provide the M3 ACTION as the ACTION on an output, regardless of the M2 KEY / ACTION pair from Memory 2 140. If the M3 HIT COUNT indicates a miss, output logic circuitry 160 may compare the M2 KEY to the KEY, and if a hit (e.g., a match) is detected, output logic circuitry 160 may indicate a hit via the HIT COUNT and may provide the M2 ACTION as the ACTION. If no hit is detected, the HIT COUNT may indicate a miss and no action may be provided as ACTION.The device 100 may process the packet based on the ACTION provided by the output logic circuit 160.

[0024] By allocating only the required amount of memory for each entry record in memory 2 140, 100% of memory 2 140 can be available for use, compared to conventional solutions that reserve potential use for each entry record and therefore only utilize 60% or less of the available memory. Because 100% of memory 2 140 is available for use, more entries can be stored in memory 2 140, which can lead to a reduction in the size of memory 3 150 compared to a design in which only 60% of a RAM device is usably available.Furthermore, the use of memory 1 110 and hash circuit 120 may provide an efficient means for uniquely identifying and providing an indication of a location of a record of an entry record of memory 2 140 in a single clock cycle using a single hash function and a small amount of overhead memory in memory 1 110. In combination, memory 1 110 and memory 3 150 may represent less than 1% of the total memory of memory 2 140. In one embodiment, memory 2 140 may be 8 megabytes (MB), memory 3 150 may be 2 kilobytes (KB), and memory 1 110 may be 144 KB.

[0025] Fig. Figure 2 illustrates components of an apparatus 200 for performing pipelined hashing methods, including a specific implementation of bucket logic circuits 228 according to some embodiments. The illustration of the embodiments shows only the components necessary for evaluating the illustrated embodiments, so that other components can be anticipated without departing from the teachings of the present specification.

[0026] The device 200 may receive a process flow key KEY in a hash circuit 220 and a memory 3 250. The hash circuit 220 may perform a pipeline hash function using the KEY to provide a hash value and may provide an entry pointer to indicate a position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means for identifying a particular position in memory 2 140) of an entry of an entry record in memory 2 140 based on the hash value and bucket records stored in memory 1 210. An output logic circuit 260 may process the entry from memory 2 240 and an output of memory 3 250 to provide an output hit indication HIT_NUMBER and an output action ACTION to an output. The hash circuit 120 of Fig. 1 may comprise the hash circuit 220, the memory 1 110 of Fig. 1 may comprise the memory 1 210, the memory 2 140 of Fig. 1 may comprise the memory 2 240, the memory 3 150 of Fig. 1 may include the memory 3 250, the output logic circuit 160 of Fig. 1 may include the output logic circuit 260, or combinations thereof.

[0027] Hash circuit 220 may process the KEY to provide the ENTRY_ZGR to indicate the position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means for identifying a particular position of Memory 2 140) of an entry in a bucket of Memory 2 240. Hash circuit 220 may include a hash module 224 to perform a hash function on the KEY to provide a hash value, which may have two parts, e.g., a value HASH1 and a value HASH2. The value HASH1 may indicate a position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means for identifying a particular position of Memory 2 140) of a bucket record BR1 stored in Memory 1 210. The BR1 can have three fields: a selection field BR1.AUSW, which contains a series of values ​​(e.g.selection values) that identify a subset of individual bits of the value HASH2 that can be used to uniquely identify which entry of the entry record stored in memory 2 140 is associated with the key; a mask field BR1.MSK to identify which of the possible entries for the entry record of memory 2 140 are currently stored in memory 2 140; and a bucket pointer field BR1.ZGR to indicate a position (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular location of memory 2 140) from a starting address of the entry record in memory 2 140.

[0028] Hash circuitry 220 may further include bucket logic circuitry 228 that processes the HASH2 value and data stored in BR1 to provide the EINTR_ZGR. In some examples, the hash value is 30 bits long, with the HASH1 value comprising 14 bits and the HASH2 value comprising 16 bits. Bucket logic circuitry 228 may include an entry selection module 232 to provide an entry selection value EINTR_AUSW identifying a particular entry of a corresponding entry record based on the BR1.AUSW field values. The EINTR_AUSW value may be based on individual bits selected from the HASH2 value based on BR1.AUSW. For example, BR1.AUSW may include m+1 selection values. Entry selection module 232 may iteratively select a bit of the HASH2 value corresponding to each of the m+1 selection values ​​to provide the EINTR_AUSW value.

[0029] The bucket logic circuit 228 may further include a previous entry identifier 234 configured to use BR1.MSK to determine which of the possible entries of the entry record that sequentially precede the EINTR_AUSW entry are actually stored in memory 2 240. The BR1.MSK values ​​may include a bit for each possible entry, with the bits set for entries that are actually stored in memory 2 240. The previous entry identifier 234 may step through each bit of BR1.MSK and set a corresponding bit of a previous array PREV to 1 if the BR1.MSK bit is set and the count (h) is less than EINTR_AUSW.

[0030] Bucket logic circuitry 228 may further include a previous entry identifier 234 configured to provide the entry pointer based on the BR1.ZGR and the PREVIOUS array. BR1.PTS may include a starting address of a target bucket record stored in memory 2 240. Previous entry identifier 234 may add a number of set bits multiplied by an entry size to the BR1.ZGR address to provide the EINTR-ZGR with a value indicating the position of a target entry of the entry record.

[0031] Memory 2 240 may provide to output logic circuit 260 a key M2 KEY and action M2 ACTION pair stored in the target entry of the entry record referenced by the ENTRY_PITCH. Memory 3 250 may receive the KEY and may provide a hit indication M3 HIT_NUMBER (e.g., an indication of whether Memory 3 250 contains an entry record with a key matching the KEY received from 204) and the action pair M3 ACTION. If no entry record is found, the M3 HIT_NUMBER may indicate a miss, and no action may be provided by Memory 3 250. In some examples, Memory 1 210 and / or Memory 2 240 may comprise a RAM architecture, and Memory 3 250 may comprise a CAM architecture.

[0032] Output logic circuitry 260 may include circuitry to receive the M3 HIT COUNT and the M3 ACTION as provided by Memory 3 250 and the M2 KEY and the M2 ACTION as provided by Memory 2 240, and may provide the HIT COUNT and the ACTION. The ACTION may define the process flow for the packet. Output logic circuitry 260 may include a comparator 262 configured to compare the KEY and the M2 KEY and provide a hit indication to an OR logic gate 264. The OR logic gate 264 may further receive the M3 HIT COUNT from Memory 3 250 and may provide the HIT COUNT with a value based on OR logic between the hit indication from comparator 262 and the M3 HIT COUNT. The output logic circuit 260 may further include a multiplexer 266 to receive the M3 ACTION and the M2 ACTION.The multiplexer 266 may provide either the M3 ACTION or the M2 ACTION as the ACTION based on the M3 TREF-ANZ received from the memory 3 250. The packet may be processed by other circuitry (not shown) of the device 200 based on the ACTION.

[0033] In operation, device 200 may provide the KEY generated based on the contents of a received packet to hash circuit 220 and memory 3 250. It will be appreciated that use cases other than processing a packet may be realized, and that device 100 may also be employed in contexts other than packet processing. The KEY may be used to determine a process flow for the received packet. Due to the complexity and diverse configurations of packets, the number of possible process flows that must be evaluated for a given packet may be 100,000 or more. Memory 2 240 and memory 3 250 may store process flow entries in an entry record for known process flows, and if no existing process flow is detected (e.g.,a failed attempt), the entry record of Memory 2 240 and / or Memory 3 250 may be updated to reflect the new process flow. Instead of performing a time-consuming sequential comparison of keys stored in each entry record of Memory 2 240 with the KEY, the hash circuit 220 and Memory 1 210 may perform a pipelined hash function using the KEY to indicate a location (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular location of Memory 2 240) of a likely matching entry in an entry record of Memory 2 240.

[0034] The combination of memory 1 210 and hash circuit 220 can provide or enable a method for uniquely identifying and pointing to a specific entry of an entry record stored in memory 2 240 based on the key. The combination of memory 1 210 and hash circuit 220 can also enable efficient use of memory 2 240 such that each bucket record is only allocated storage for the actually stored entries, rather than being allocated based on the number of possible entries. This means that if an entry record stored in memory 2 240 only stores three entries out of a possible 32 entries, those three entries can be stored consecutively, and the next entry record can begin immediately after the last of the three entries.

[0035] Hash module 224 may perform a hash function on the key to provide the value HASH1 and the value HASH2. The value HASH1 may be provided to memory 1 210 to retrieve the BR1 from memory 1 210.

[0036] To determine the EINTR_ZGR, the entry selection module 232 may iteratively apply the selection values ​​to the HASH2 value to provide an EINTR_AUSW value. The EINTR_AUSW value may identify a particular entry of the entry record stored in memory 2 240 that is associated with the key. The number of bits m+1 in the EINTR_AUSW value may be based on a number of possible entries for a given entry record. For example, if an entry record can have up to 32 entries, m+1 may be greater than or equal to five.

[0037] The previous entry identifier 234 can then determine which of the possible sequentially previous entries (e.g., sequentially before the entry in question to be identified with the EINTR_AUSW value) of the entry record are actually stored with the entry record in memory 2 240, based on the BR1.MSK field to provide the VORH array. The BR1.MSK field can have n+1 bits, which is set based on a number of possible entries to be stored in a given entry record. For example, if an entry record is designed for 32 entries, then n+1 can be equal to 32. In the example, if the entry in question identified with the EINTR_AUSW is the 30th entry and the only other entries actually stored in the entry record are the second and fourth entries, only two previous entries are present, and only the second and fourth bits are set in the VORH array.The previous entry identifier 234 may then insert the number of set bits in the VORH array multiplied by an entry size EINTR_GROE (e.g., number of bits per entry) into the BR1.ZGR to provide the EINTR_ZGR.

[0038] At an output, memory 2 240 may provide M2 ​​KEY and M2 ACTION to output logic circuitry 260 selected based on the ENTRY NUMBER. Occasionally, the use of hash functions may result in situations where it is impossible to distinguish between collisions (e.g., distinguishing between two keys based on the hash values). In other examples, an entry record may be filled beyond the allocated number of entries (e.g., more than 32 entries in the examples discussed above). For these special cases, memory 3 250 may store key / action pairs to supplement the entry record stored in memory 2 240.In parallel with providing the M2 KEY and M2 ACTION from Memory 2 240, Memory 3 250 may compare the KEY with entries stored in Memory 3 250 and, based on the comparison, provide the M3 HIT COUNT and the corresponding M3 ACTION to Output Logic Circuitry 260. For example, if there is a hit, the M3 HIT COUNT will indicate the hit and the corresponding M3 ACTION may be provided to Output Logic Circuitry 260. If the comparison results in a miss (e.g., none of the keys stored in Memory 3 250 correspond to the KEY), the M3 HIT COUNT indicates a miss and no M3 ACTION may be provided.

[0039] Output logic circuitry 260 may provide the TREF COUNT and the ACTION based on the outputs received from Memory 2 240 and Memory 3 250. Due to collision issues as discussed above, the entry pointed to by the ENTRY COUNT may not necessarily be the correct entry associated with the KEY. Thus, comparator 262 may compare the KEY to the M2 KEY to determine if a hit is indicated (e.g., if the two keys match) and provide a comparison result to OR logic gate 264. OR logic gate 264 may provide / set the TREF COUNT to indicate a hit if either the M3 TREF COUNT or the output of comparator 262 indicates a hit. Otherwise, OR logic gate 264 may set the TREF COUNT to indicate a miss.The output logic circuit 260 may further include a multiplexer 266 to receive the M3 ACTION and the M2 ACTION. The multiplexer 266 may provide either the M3 ACTION or the M2 ACTION as the ACTION based on the M3 HIT COUNT received from Memory 3 250. In one example, a hit from M3 may take precedence over a matching key from Memory 2 240. Thus, for example, if the M3 HIT COUNT from Memory 3 250 indicates a hit, the output logic circuit 260 may provide the M3 ACTION as the ACTION at an output, regardless of the M2 KEY / ACTION from Memory 2 240. Otherwise, the multiplexer 266 may provide the M2 ACTION at an output. The device 200 may process the packet based on the ACTION provided by the output logic circuit 260.

[0040] By allocating only the required amount of memory for each entry record in memory 2240, 100% of memory 2240 can be available for use, compared to conventional solutions that allow for potential use for each entry record and therefore utilize only 60% or less of the available memory. Since 100% of memory 2240 is available for use, more entries can be stored in memory 2240, which can result in a reduction in the size of memory 3250 compared to a design in which only 60% of a RAM device is usably available.Furthermore, the use of memory 1 210 and hash circuit 220 may provide an efficient means for uniquely identifying and providing an indication of a location of a record of an entry record of memory 2 240 in a single clock cycle using a single hash function and a small amount of overhead memory in memory 1 210. In combination, memory 1 210 and memory 3 250 may represent less than 1% of the total memory of memory 2 240. In one embodiment, memory 2 210 may be 8 megabytes (MB) in size, memory 3 250 may be 2 kilobytes (KB) in size, and memory 1 210 may be 144 KB in size.

[0041] Fig. 3 illustrates an apparatus 300 that includes an exemplary implementation of pipelined hash function methods according to some embodiments, for example, the embodiments of Fig. 1 and Fig. 2. The illustration of the embodiments shows only the components necessary for the evaluation of the illustrated embodiments, so that other components can be foreseen without deviating from the teachings of the present patent specification.

[0042] Device 300 may receive a process flow key KEY at a hash module 324. Hash module 324 may perform a hash function on the received key to provide a HASH1 value with a value of 21 and a HASH2 value with a value of 0x341e. A HASH1 value of 21 may indicate a location (e.g., an index value, a pointer value, a physical address value, a logical address value, or some means of identifying a particular location of memory 2 140) of bucket record 21 of memory 1 310. Bucket record 21 may include a BR1.ZGR field with a value of 10, a BR1.AUSW field with values ​​of 4, 3, 2, 1, and 0, and a BR1.MSK field with bits 1, 3, and 30 set. Entry selection module 332 may select bits from the HASH2 value to generate the EINTR_AUSW value. In this particular example, the bits of the HASH2 value that are selected are bits 0 through 4. Thus, EINTR_AUSW has a value of 0x1e (e.g., 30).The EINTR_AUSW value therefore identifies the 30th entry as the target entry. The bucket logic (e.g., the entry pointer generator 236 of . Fig. 2) can then count the number of set bits in the mask before the 30th bit, which in this example is 2 (e.g., bits 1 and 3), and add the number multiplied by an entry size of an entry in memory 2 340 to BR1.ZGR to indicate a position of entry 12. Entry 12 can provide KEY4 to comparator 362. Comparator 362 can compare KEY4 with KEY to provide a hit indication HIT-NUM. Memory 1 310 can store in memory 1 110 of Fig. 1 and / or in memory 1 210 of Fig. 2. The memory 2 340 can be in the memory 2 140 of Fig. 1 and / or in memory 2 240 of Fig. 2. The hash module 324 can be included in the hash module 124 of Fig. 1 and / or in hash modulo 224 of Fig. 2. The comparator 362 may be included in the output logic circuit 160 of Fig. 1 and / or in the comparator 262 of Fig. 2 must be included. Fig. Figure 3 is a representation of a specific example of a pipelined hash function. It should be noted that other values, field lengths, and orderings are considered.

[0043] Fig. 4 illustrates a method 400 for performing a pipelined hash function according to some embodiments. The method 400, implemented as executable instructions represented by one or more modules or circuits, may be executed by one or more hardware processors from a non-transitory, machine-readable storage medium. In one embodiment, the executable instructions representing the pipelined hash function are stored on a non-transitory, machine-readable storage medium that, when executed by one or more computing devices, performs the processing of the method 400. The method 400 may be implemented in the device 100 of Fig. 1, the device 200 of Fig. 2, the device 300 of Fig. 3 or combinations thereof can be implemented.

[0044] The method 400 may include receiving a key associated with a packet at 410. The key may be stored in a hash circuit, such as the hash circuit 120 of Fig. 1, the hash circuit 220 of Fig. 2, the hash modulo 324 of Fig. 3 or combinations thereof. The key can be received by a receiver circuit, such as the receiver 104 of Fig. 1, are generated.

[0045] The method 400 may further include, at 420, performing a hash function using the key to provide a first hash value and a second hash value. The hash function may be implemented by a hash module, such as the hash module 124 of Fig. 1, the hash modulo 224 of Fig. 2, the hash modulo 324 of Fig. 3 or combinations thereof.

[0046] The method 400 may further include selecting, at 430, a first bucket record of a first plurality of bucket records based on the first hash value. The first bucket record may be stored in a memory, such as memory 1110 of Fig. 1, the memory 1 210 of Fig. 2, the memory 1 310 of Fig. 3 or combinations thereof.

[0047] The method 400 may further include providing, at 440, an indication of a position of a particular entry of an entry record from among a plurality of entry records based on the contents of the first bucket record and the second hash value. The entry record may be stored in a memory, such as memory 2 140 of Fig. 1, the memory 2 240 of Fig. 2, the memory 2 340 of Fig. 3 or combinations thereof.

[0048] In some examples, providing an indication of a position of a particular entry of the entry record of the plurality of entry records may include selecting a single bit of the second hash value corresponding to each of a plurality of selection values ​​included in the first bucket record to provide an entry selection value. The selection of the single bit of the second hash value corresponding to each of the plurality of selection values ​​included in the first bucket record to provide the entry selection value may be performed by an entry selection module, such as the entry selection module 232 of Fig. 2. The method 400 may further include identifying, up to a bit corresponding to the bucket hash value, which bits of a mask field of the first bucket data set have a high logic value to provide a previously set array. Identifying which bits of a mask field of the first bucket data set have a high logic value to provide a previously set array may be performed based on a previous entry identifier, such as the previous entry identifier 234 of Fig. 2, be carried out.

[0049] The method 400 may further include identifying the respective entry by adding a number of set values ​​in the previous set array multiplied by an entry size to a bucket pointer of the first bucket record. Adding the number of set values ​​in the previous set array multiplied by the entry size to the bucket pointer of the first bucket record may be performed by an entry pointer generator, such as the previous entry identifier 234 of Fig. 2. The method 400 may further include providing a hit indication in response to a hit associated with an entry of a second plurality of entry records or a match between a key value stored in the respective entry of the entry record and the key. The entry of the second plurality of entry records may be stored in a memory, such as memory 3 150 of Fig. 1 and / or the memory 3 250 of Fig. 2. The hit display can be controlled by an output logic circuit, such as the output logic circuit 160 of Fig. 1 and / or the output logic circuit 260 of Fig. 2, are provided.

[0050] Fig. 5 illustrates a method 500 for performing a pipeline hash function according to some embodiments. The method 500 is implemented as executable instructions represented by one or more software modules and executed by one or more hardware processors from a non-transitory, machine-readable storage medium. In one embodiment, the executable instructions representing the pipeline hash function are stored on a non-transitory, machine-readable storage medium that, when executed by one or more computing devices, performs the processing of the method 500. The method 500 may be implemented in the device 100 of Fig. 1, the device 200 of Fig. 2, the device 300 of Fig. 3 or combinations thereof can be implemented.

[0051] The method 500 may include performing a hash function on a key to generate a hash value at 510. The key may be hashed on a hash circuit, such as hash circuit 120 of Fig. 1, the hash circuit 220 of Fig. 2, the hash modulo 324 of Fig. 3 or combinations thereof. The key can be received by a receiver circuit, such as the receiver 104 of Fig. 1. The hash function can be generated by a hash module, such as the hash module 124 of Fig. 1, the hash modulo 224 of Fig. 2, the hash modulo 324 of Fig. 3 or combinations thereof.

[0052] The method 500 may further include, after performing the hash function to generate the hash value, providing at 520 a pointer to an entry of a particular entry record stored in a first memory based on the hash value and a bucket record stored in the second memory. Providing the pointer to an entry of a particular entry record stored in a first memory based on the hash value and the bucket record stored in the second memory may be performed by bucket logic, such as the hash circuit 120 of Fig. 1 and / or the hash circuit 220 of Fig. 2, can be performed. The first memory can be the memory 2 140 of Fig. 1, the memory 2 240 of Fig. 2, the memory 2 340 of Fig. 3 or combinations thereof. The second memory may comprise the memory 1 110 of Fig. 1, the memory 1 210 of Fig. 2, the memory 1 310 of Fig. 3 or combinations thereof. Providing the pointer to an entry of a particular entry record stored in the first memory may include retrieving the entry record from the second memory based on a first subset of bits of the hash value, and providing a pointer to the particular entry of the entry record based on information stored in the bucket record and a second subset of bits of the hash value.

[0053] The method 500 may further provide a hit indication at 530 in response to a match between a key value stored in the entry of the respective bucket record and the key. The hit indication may be determined by a comparator, such as the comparator 262 of Fig. 2 and / or the comparator 362 of Fig. 3. The method 500 may further include comparing the key value stored in the entry of the respective bucket record with the key. The entry record may be stored in a memory, such as the memory 110 of Fig. 1, the memory 1 210 of Fig. 2, the memory 1 310 of Fig. 3 or combinations thereof. The method 500 may further include providing the hit indication in response to detecting a hit between the key and an entry of a second entry data set stored in a third memory. The third memory may include the memory 3 150 of Fig. 1 and / or the memory 3 250 of Fig. 2.

[0054] The method 500 may further include providing an action stored in the respective entry of the bucket record at 540. The action may be executed by an output logic circuit, such as the output logic circuit 160 of Fig. 1 and / or the output logic circuit 260 of Fig. 2. The method 500 may further include providing an action stored in the entry of the third bucket record based on detecting a match between the key and the entry of the third bucket record.

[0055] Fig. 6 illustrates a method 600 for generating a mask value for colliding hash values, according to some embodiments. The method 600 is implemented as executable instructions represented by one or more software modules and executed by one or more hardware processors from a non-transitory, machine-readable storage medium. In one embodiment, the executable instructions representing the mask generator are stored on a non-transitory, machine-readable storage medium that, when executed by one or more computing devices, performs the processing of the method 600. The method 600 may use the mask field implemented in the device 100 of Fig. 1, the device 200 of Fig. 2, the device 300 of Fig. 3, the mask field used in methods 400 and / or 500, or combinations thereof.

[0056] The method 600 may include generating a list of mask values ​​at 610. Each mask value of the list of mask values ​​may have a predetermined number of bits. The predetermined number of bits set may be based on a total number of bits in a hash value of the group of hash values. For example, if the number of bits is 16, the number of bits in the mask value may be 5 bits. In some examples, the number of bits in the mask value may be equal to a number of values ​​in the BR1.AUSW field of Fig. 1-3. In some examples, generating the list of mask values ​​may involve randomizing a group of mask values ​​to provide the list of mask values.

[0057] The method 600 may further include receiving a group of hash values ​​at 620. In one example, the group of hash values ​​may be the group of HASH2 values ​​corresponding to the HASH1 values ​​that are included in a single bucket record of Fig. 1-3 collided.

[0058] The method 600 may further include, at 630, determining a respective number of collisions for a mask value of the list of mask values ​​using the set of hash values. The method 600 may further include, at 640, selecting a mask value from the list of mask values ​​that has the respective fewest number of collisions. In some examples, the method 600 may include selecting the mask value in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is zero. That is, if no collisions are detected, the method 600 may end.In some examples, method 600 may include, in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is a non-zero value, determining a respective number of collisions for a next mask value of the list of mask values ​​using the set of hash values. Method 600 may continue to traverse the list of mask values ​​until a value of zero collisions is detected for a mask value or the end of the list is reached.

[0059] In some examples, determining the respective number of collisions for the mask value of the list of mask values ​​using the group of hash values ​​may include applying the mask value to a first hash value of the group of hash values ​​to generate a first value and applying the mask value to a second hash value of the group of hash values ​​to generate a second value. The first value may be compared to the second value, and in response to the first value matching the second value, the respective number of collisions for the mask value may be incremented.

[0060] Fig. 7 is a block diagram of a network device 700 according to some embodiments. The network device 700 includes a communication port 710 that can be used to exchange information packets with other devices. Note that more than one communication port 710 can be associated with the network device 700. The network device 700 also includes a controller 720. The controller 720 can include one or more processor units, such as a control plane processor, that performs control and system management functions and executes real-time applications. The network device 700 further includes a packet forwarding engine 730 that can be used to determine routing information based on a destination address associated with an information packet.The packet forwarding engine 730 can also facilitate flow categorization and congestion management and sets queue priorities.

[0061] The packet forwarding engine 730 may also access a hashing unit 250, such as a hash circuit 750, that supports a pipelined hash function and a memory 740. The hash circuit may include the hash circuit 120 of Fig. 1, the hash circuit 220 of Fig. 2, the hash modulo 324 of Fig. 3 or combinations thereof. Furthermore, the hash module 324, in combination with the controller 720 and the memory 740, may perform the method 400, the method 500, the method 600, or combinations thereof. The memory 740 may implement the memory 1 110, the memory 2 140, and / or the memory 3 150 of Fig. 1, memory 1 210, memory 2 240 and / or memory 3 250 of Fig. 2, the memory 1 310 and / or the memory 2 340 of Fig. 3 or combinations thereof. Even if in Fig. 7 illustrates a particular network device 700, according to other embodiments, the network device 700 may include fewer and / or different components.

[0062] Examples as described in this specification may include or operate on logic or a number of components, modules, circuits, or mechanisms. Modules are physical units (e.g., hardware) capable of performing specific operations and may be designed or arranged in a particular manner. In one example, circuits may be arranged in a specific manner to form a module (e.g., internally or in relation to external units such as other circuits). In one example, the software may be located on at least one machine-readable medium.

[0063] The terms "module" and "circuits" are to be understood as referring to a tangible unit, whether one that is physically constructed, specially configured (e.g., hard-wired), or temporarily (e.g., temporarily) configured (e.g., programmed) to function in a specified manner or to perform at least part of any operation described herein. With respect to examples in which modules or circuits are temporarily configured, a module or circuit need not necessarily be implemented at any one time. For example, where the modules or circuits comprise a general-purpose hardware processor configured to operate with software, the general-purpose hardware processor may be configured as different modules or circuits at different times.Accordingly, software may, for example, configure a hardware processor to constitute a particular module or circuit at one time and a different module or circuit at another time. The terms "application, process, or service," and variations thereof, are used broadly herein to include routines, program modules, programs, components, circuits, and the like, and may be implemented in various system configurations, including single-processor or multi-processor systems, microprocessor-based electronics, single-core or multi-core systems, combinations thereof, or the like. Thus, the terms "application, process, or service" may be used to refer to an embodiment of software or hardware arranged to perform at least part of an operation described herein.

[0064] Although a machine-readable medium may include a single medium, the term "machine-readable medium" may include both a single medium and multiple media (e.g., a centralized or distributed database and / or linked caches and servers). Additional notes and examples:

[0065] Example 1 includes subject matter (such as a device, apparatus, network device, or machine) for performing a pipelined hash function, comprising: a first memory for storing a plurality of bucket records, a second memory for storing a plurality of entry records; and a hash circuit for receiving a key and performing a pipelined hash function using the key to provide a hash value, wherein the hash circuit is further to select a first bucket record of the plurality of bucket records from the first memory based on a first subset of bits of the hash value, wherein the hash circuit is further to provide an indication of a position of a particular entry of an entry record of the plurality of entry records based on the contents of the first bucket record and a second subset of bits of the hash value.

[0066] In Example 2, the subject matter of Example 1 may include, wherein the hash circuit comprises a bucket logic circuit to generate an entry pointer based on the first hash bucket record and the second subset of bits of the hash value, the entry pointer providing the indication of the position of the respective entry of the entry record.

[0067] In Example 3, the subject matter of any of Examples 1 to 2 may include, wherein the first bucket record comprises a selection field having a plurality of selection values, wherein the bucket logic circuitry comprises an entry selection module to select a single bit of the second subset of bits of the hash value corresponding to each of the plurality of selection values ​​to provide an entry selection value.

[0068] In Example 4, the subject matter of any of Examples 1 to 3 may include, wherein the first bucket record includes a mask field to identify one or more entries currently stored in the entry record, wherein the bucket logic circuitry further includes a previous array identifier to identify which of the mask field bits lower than the entry selection value have a high logic value to provide a previous set array.

[0069] In Example 5, the subject matter of any one of Examples 1 to 4 may include, wherein the first bucket record includes a bucket pointer field to indicate a position of a first entry of the entry record, wherein the bucket logic circuitry further comprises an entry pointer generator to identify the particular entry of the one or more entries of the entry record by adding a number of high logic values ​​in the previously set array multiplied by an entry size to the bucket pointer to provide the entry pointer.

[0070] In Example 6, the subject matter of any of Examples 1 to 5 may include a third memory to store a third plurality of bucket records.

[0071] In Example 7, the subject matter of any one of Examples 1 to 6 may include, wherein the first memory and the second memory are each random access memories and the third memory is an associative memory.

[0072] In Example 8, the subject matter of any of Examples 1 to 7 may include output logic circuitry to provide a hit indication in response to a hit in an entry of a bucket record of the third plurality of bucket records or in response to a match between the key and a key value stored in the respective entry of the entry record.

[0073] In Example 9, the subject matter of any of Examples 1 to 8 may include, wherein the output logic circuitry further provides an output action stored in an entry of a bucket record of the third plurality of bucket records in response to a hit associated with the entry of the bucket record of the third plurality of bucket records, wherein the output logic circuitry further provides an output action stored in the respective entry of the entry record in response to a miss associated with the entry of the bucket record of the third plurality of bucket records.

[0074] In Example 10, the subject matter of any of Examples 1 to 9 may include a receiving circuit to receive a packet and generate the key based on the data in the packet.

[0075] Example 11 includes subject matter (such as a method, a means for performing actions, a machine-readable medium having instructions that, when executed by a machine, cause the machine to perform actions, or an apparatus for performing) for performing a pipelined hash function, comprising: receiving a key associated with a packet; performing a hash function using the key to provide a first hash value and a second hash value; selecting a first bucket record from among a plurality of bucket records based on the contents of the first hash value; and providing an indication of a location of a particular entry of an entry record from among a plurality of entry records based on the contents of the first bucket record and the second hash value.

[0076] In Example 12, the subject matter of Example 11 may include, wherein providing the indication of the position of the particular entry of the entry record of the plurality of entry records comprises selecting a single bit of the second hash value corresponding to each of a plurality of selection values ​​included in the first bucket record to provide an entry selection value.

[0077] In Example 13, the subject matter of any of Examples 11 to 12 may include identifying, up to a bit corresponding to the entry selection value, which bits of a mask field of the first bucket record have a high logic value to provide a previously set array.

[0078] In Example 14, the subject matter of any of Examples 11 to 13 may include identifying the entry in question by adding a number of set values ​​in the previous set array multiplied by an entry size to a bucket pointer of the first bucket record.

[0079] In Example 15, the subject matter of any of Examples 11 to 14 may include providing a hit indication in response to a hit associated with an entry of a third plurality of bucket records or a match between a key value stored in the respective entry of the entry record and the key.

[0080] Example 16 includes at least one machine-readable medium having instructions that, when executed on a machine, cause the machine to perform any of Examples 11-15.

[0081] Example 17 features an apparatus comprising means for performing any of Examples 11-15.

[0082] Example 18 includes subject matter (such as a method, a means for performing actions, a machine-readable medium having instructions that, when executed by a machine, cause the machine to perform actions, or an apparatus for performing) a pipelined hash function, comprising: performing a hash function on a key to generate a hash value; after performing the hash function to generate the hash value, providing a pointer to indicate a location of an entry of a particular entry record stored in a first memory based on the hash value and the contents of a bucket record stored in a second memory; providing a hit indicator in response to a match between a key value stored in the entry of the particular entry record and the key;and providing an action stored in the respective entry of the entry record;

[0083] In Example 19, the subject matter of Example 18 may include, wherein providing the pointer to indicate the position of the entry of the respective entry record comprises: retrieving the bucket record from the second memory based on a first subset of bits of the hash value; and providing a pointer to indicate the position of the respective entry of the respective entry record based on information included in the respective entry record and a second subset of bits of the hash value.

[0084] In Example 20, the subject matter of any of Examples 18 to 19 may include comparing the key value stored in the entry of the respective entry record to the key.

[0085] In Example 21, the subject matter of any of Examples 18 to 20 may include providing the hit indication in response to detecting a hit between the key and an entry of a second entry record stored in a third memory.

[0086] In Example 22, the subject matter of any of Examples 18 to 21 may include providing an action stored in the entry of the second entry record based on detecting a match between the key and the entry of the second entry record.

[0087] Example 23 includes at least one machine-readable medium having instructions that, when executed on a machine, cause the machine to perform any of Examples 18-23.

[0088] Example 24 features an apparatus comprising means for performing any of Examples 18-23.

[0089] Example 25 includes subject matter (such as a device, apparatus, or machine) for performing a pipelined hash function, comprising: the plurality of memories; and the processor configured to: receive a packet; provide a key based on the data in the packet; perform a hash function on the key to generate a hash value; provide a pointer to indicate a location of an entry of a particular entry record stored in a first memory of the plurality of memories based on the hash value and the contents of a bucket record stored in a second memory of the plurality of memories; provide a hit indicator in response to a match between a key value stored in the entry of the particular entry record and the key;and provide to an output an action stored in the respective entry of the entry record;

[0090] In Example 26, the subject matter of Example 25 may include, wherein the processor configured to provide a pointer to indicate the position of the entry of an entry of a particular entry record stored in a first memory of the plurality of memories based on the hash value and the contents of a bucket record stored in a second memory of the plurality of memories, comprises the processor configured to: retrieve the bucket record from the second memory based on a first subset of bits of the hash value; and provide the pointer to indicate the position of the particular entry of the entry record based on information included in the particular entry record and a second subset of bits of the hash value.

[0091] In Example 27, the subject matter of any of Examples 25 to 26 may include, wherein the processor is further configured to compare the key value stored in the entry of the respective entry record to the key.

[0092] In Example 28, the subject matter of any of Examples 25 to 27 may include, wherein the processor is further configured to provide the hit indication in response to detecting a hit between the key and an entry of a second entry record stored in a third memory of the plurality of memories.

[0093] In Example 29, the subject matter of any of Examples 25 to 28 may include, wherein the processor is further configured to provide an action stored in the entry of the second entry record based on detecting a match between the key and the entry of the second entry record.

[0094] In Example 30, the subject matter of any of Examples 25 to 29 may include, wherein the third memory is a different memory type than the first memory and the second memory.

[0095] Example 31 includes subject matter (such as a device, apparatus, or machine) for performing a pipelined hash function, comprising: means for performing a hash function on a key to generate a hash value; after performing the hash function to generate the hash value, means for providing a pointer indicating a location of an entry of a particular entry record stored in a first memory based on the hash value and the contents of a bucket record stored in a second memory; means for providing a hit indication in response to a match between a key value stored in the entry of the particular entry record and the key; and means for providing an action stored in the particular entry of the entry record.

[0096] In Example 32, the subject matter of Example 31 may include, wherein the means for providing the pointer to indicate the position of the entry of the respective entry record comprises: means for retrieving the bucket record from the second memory based on a first subset of bits of the hash value; and means for providing a pointer to indicate the position of the respective entry of the respective entry record based on information included in the respective entry record and a second subset of bits of the hash value.

[0097] In Example 33, the subject matter of any of Examples 31 to 32 may include means for comparing the key value stored in the entry of the respective entry record with the key.

[0098] In Example 34, the subject matter of any of Examples 31 to 33 may include means for providing the hit indication in response to detecting a hit between the key and an entry of a second entry record stored in a third memory.

[0099] In Example 35, the subject matter of any of Examples 31 to 34 may include means for providing an action stored in the entry of the second entry record based on detecting a match between the key and the entry of the second entry record.

[0100] Example 36 includes subject matter (such as a method, a means for performing actions, a machine-readable medium having instructions that, when executed by a machine, cause the machine to perform actions, or an apparatus for performing) for generating a mask for colliding hash values, comprising: generating a list of mask values, each mask value of the list of mask values ​​having a predetermined number of bits set; receiving a group of hash values; determining a respective number of collisions for a mask value of the list of mask values ​​using the group of hash values; and selecting a mask value from the list of mask values ​​having the respective fewest number of collisions.

[0101] In Example 37, the subject matter of Example 36 may include, wherein the predetermined number of set bits is based on a total number of bits in a hash value of the group of hash values.

[0102] In Example 38, the subject matter of any of Examples 36 to 37 may include, in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is equal to zero, selecting the mask value.

[0103] In Example 39, the subject matter of any of Examples 36 to 38 can include, in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is a non-zero value, determining a respective number of collisions for a next mask value of the list of mask values ​​using the set of hash values.

[0104] In Example 40, the subject matter of any of Examples 36 to 39 can include, wherein determining the respective number of collisions for the mask value of the list of mask values ​​using the group of hash values ​​comprises: applying the mask value to a first hash value of the group of hash values ​​to generate a first value; applying the mask value to a second hash value of the group of hash values ​​to generate a second value; comparing the first value to the second value; and in response to the first value matching the second value, incrementing the respective number of collisions for the mask value.

[0105] In Example 41, the subject matter of any of Examples 31 to 40 can include, wherein generating the list of mask values ​​comprises randomizing a group of mask values ​​to provide the list of mask values.

[0106] Example 42 includes at least one machine-readable medium having instructions that, when executed on a machine, cause the machine to perform any of Examples 36-41.

[0107] Example 43 features an apparatus comprising means for performing any of Examples 36-41.

[0108] Example 44 includes subject matter (such as a device, apparatus, or machine) for performing a pipelined hash function, comprising: means for generating a list of mask values, each mask value of the list of mask values ​​having a predetermined number of bits set; means for receiving a group of hash values; means for determining a respective number of collisions for a mask value of the list of mask values ​​using the group of hash values; and means for selecting a mask value from the list of mask values ​​having the respective fewest number of collisions.

[0109] In Example 45, the subject matter of Example 44 may include, wherein the predetermined number of set bits is based on a total number of bits in a hash value of the group of hash values.

[0110] In Example 46, the subject matter of any of Examples 44 to 45 may include means for selecting the mask value in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is equal to zero.

[0111] In Example 47, the subject matter of any of Examples 44 to 46 may include means for, in response to a determination that the respective number of collisions for the mask value of the list of mask values ​​is a non-zero value, determining a respective number of collisions for a next mask value of the list of mask values ​​using the set of hash values.

[0112] In Example 48, the subject matter of any of Examples 44 to 47 can include, wherein the means for determining the respective number of collisions for the mask value of the list of mask values ​​using the group of hash values ​​comprises: means for applying the mask value to a first hash value of the group of hash values ​​to generate a first value; means for applying the mask value to a second hash value of the group of hash values ​​to generate a second value; means for comparing the first value to the second value; and means for incrementing the respective number of collisions for the mask value in response to the first value matching the second value.

[0113] In Example 49, the subject matter of any of Examples 44 to 48 can include, wherein the means for generating the list of mask values ​​comprises means for randomizing a group of mask values ​​to provide the list of mask values.

[0114] Example 50 includes subject matter (such as a device, apparatus, or machine) for performing a pipelined hash function, comprising: means for performing a hash function on a key to generate a hash value; after performing the hash function to generate the hash value, means for providing a pointer indicating a location of an entry of a particular entry record stored in a first memory based on the hash value and the contents of a bucket record stored in a second memory; means for providing a hit indication in response to a match between a key value stored in the entry of the particular entry record and the key; and means for providing an action stored in the particular entry of the entry record.

[0115] In Example 51, the subject matter of Example 50 may include, wherein the means for providing the pointer to indicate the position of the entry of the respective entry record comprises: means for retrieving the bucket record from the second memory based on a first subset of bits of the hash value; and means for providing a pointer to indicate the position of the respective entry of the respective entry record based on information included in the respective entry record and a second subset of bits of the hash value.

[0116] In Example 52, the subject matter of any of Examples 50 to 51 may include means for comparing the key value stored in the entry of the respective entry record with the key.

[0117] In Example 53, the subject matter of any of Examples 50 to 52 may include means for providing the hit indication in response to detecting a hit between the key and an entry of a second entry record stored in a third memory.

[0118] In Example 54, the subject matter of any of Examples 50 to 53 may include means for providing an action stored in the entry of the second entry record based on detecting a match between the key and the entry of the second entry record.

Claims

[1] A network device (100, 200) for performing a pipeline hash function, comprising: a first memory (110, 210) for storing a first plurality of bucket records, a second memory (140, 240) for storing a plurality of entry records; a third memory (150, 250) for storing a second plurality of bucket records; and a hash circuit (120, 220) for receiving a key and performing a pipeline hash function using the key to provide a hash value, wherein the hash circuit (120, 220) further selects a first bucket record of the first plurality of bucket records from the first memory (110, 210) based on a first subset of bits of the hash value, wherein the hash circuit (120, 220) further provides an indication of a position of a particular entry of an entry record of the plurality of entry records based on the content of the first bucket record and a second subset of bits of the hash value, and an output logic circuit (160, 260) for providing a hit indication in response to a hit in an entry of a bucket record of the second plurality of bucket records or in response to a match between the key and a key value stored in the respective entry of the entry record. [2] The network device (100, 200) of claim 1, wherein the hash circuit (120, 220) comprises a bucket logic circuit (128, 228) to generate an entry pointer based on the first hash bucket record and the second subset of bits of the hash value, the entry pointer providing the indication of the position of the respective entry of the entry record. [3] The network device (100, 200) of claim 2, wherein the first bucket record comprises a selection field having a plurality of selection values, wherein the bucket logic circuit (128, 228) comprises an entry selection module (232) to select a single bit of the second subset of bits of the hash value corresponding to each of the plurality of selection values ​​to provide an entry selection value. [4] The network device (100, 200) of claim 3, wherein the first bucket record comprises a mask field to identify one or more entries currently stored in the entry record, wherein the bucket logic circuit (128, 228) further comprises a previous array identifier to identify which of the mask field bits lower than the entry selection value have a high logic value to provide a previous set array. [5] The network device (100, 200) of claim 4, wherein the first bucket record comprises a bucket pointer field to indicate a position of a first entry of the entry record, the bucket logic circuit (128, 228) further comprising an entry pointer generator to identify the respective one of the one or more entries of the entry record by adding a number of high logic values ​​in the previously set array multiplied by an entry size to the bucket pointer to provide the entry pointer. [6] The network device (100, 200) of claim 1, wherein the first memory (110, 210) and the second memory (140, 240) are each random access memories and the third memory (150, 250) is an associative memory. [7] The network device (100, 200) of claim 1, wherein the output logic circuit (160, 260) further provides an output action stored in an entry of a bucket record of the second plurality of bucket records in response to a hit associated with the entry of the bucket record of the second plurality of bucket records, wherein the output logic circuit (160, 260) further provides an output action stored in the respective entry of the entry record in response to a miss associated with the entry of the bucket record of the second plurality of bucket records. [8] The network device (100, 200) of claim 1, further comprising a receiving circuit to receive a packet and generate the key based on the data in the packet. [9] A method (500) for performing a pipeline hash function, comprising: performing (510) a hash function on a key to generate a hash value; after performing (520) the hash function to generate the hash value, providing a pointer to indicate a position of an entry of a particular entry record stored in a first memory based on the hash value and the contents of a bucket record stored in a second memory; Providing (530) a hit indication in response to a match between a key value stored in the entry of the respective entry data record and the key, and detecting a hit between the key and an entry of a second entry data record stored in a third memory; and Providing an action (540) stored in the respective entry of the entry record and stored in the entry of the second entry record based on detecting a match between the key and the entry of the second entry record. [10] The method (500) of claim 9, wherein providing the pointer for indicating the position of the entry of the entry record in question comprises: Retrieving the bucket record from the second memory based on a first subset of bits of the hash value; and Providing a pointer to indicate the position of the respective entry of the respective entry record based on information contained in the respective entry record and a second subset of bits of the hash value. [11] The method (500) of claim 9, further comprising comparing the key value stored in the entry of the respective entry record with the key. [12] At least one machine-readable medium having instructions which, when executed on a machine, cause the machine to perform one of the methods of claims 10-12. [13] Apparatus comprising means for performing any of the methods according to claims 10-12.

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