Systems and techniques for remote bus release

Abstract

Communication system (100) comprising: a master transceiver (102, 120-1) coupled to a downstream connection of a two-wire bus (106), the master transceiver (102, 120-1) being configured to periodically transmit a synchronization control frame on the downstream connection of the two-wire bus (106); a voltage regulator (111) having a voltage output and an enable input, the voltage regulator being coupled to the master transceiver (102, 120-1) via the voltage output, the enable input enabling operation of the voltage regulator in response to a predetermined voltage at the enable input; and a switch (113, 115, 117) coupled to the enable input of the voltage regulator (111).

Description

background

[0001] As electronic components shrink in size and performance expectations increase, more components are being incorporated into previously uninstrumented or less instrumented devices. In some environments, the communications infrastructure used to exchange signals between these components (for example, in a vehicle) has required thick and heavy cable bundles.

[0002] US 2013 / 0124763 A1 discloses methods for detecting, configuring and coordinating data communication between master and slave devices in a communication system.

[0003] Application note AN1278, “LIN (Local Interconnect Network) Solutions” by ST Microelectronics, 2002, describes solutions for local network connections.

[0004] US 2015 / 0270777 A1 discloses digital voltage regulators with master-slave function.

[0005] US 9,887,710 B1 discloses impedance and swing control for voltage mode driving.

[0006] Furthermore, US 2002 / 0175820 A1 discloses a tracking device.

[0007] DE 10 2015 117 673 A1 discloses systems and techniques for diagnosing and controlling peripheral devices via a two-wire communication bus.In some embodiments, a slave device may, for example, include circuitry for receiving a synchronization control frame from an upstream device; receiving audio data from the upstream device upon receipt of the synchronization control frame; providing a synchronization response frame to the upstream device; and providing first data representing an operating characteristic of an audio device coupled to the slave device upon provision of the synchronization response frame; circuitry for deriving timing information from the synchronization control frame; circuitry for providing the audio data to the audio device; and receiving, from a sensor coupled to the slave device, second data representing the operating characteristic of the audio device. Brief description of the invention

[0008] The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims. Brief description of the drawings

[0009] Embodiments can be readily understood from the following detailed description taken in conjunction with the accompanying drawings. To facilitate description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings. In the figures: Fig. 1 is a block diagram of an illustrative two-wire communication system according to various embodiments, Fig. 2 a block diagram of a node transceiver used in a node of the system Fig. 1 may be included, according to various embodiments, Fig. 3 a diagram of a section of a communication module for the system Fig. 1 used synchronization control frame according to various embodiments, Fig. 4 a diagram of a communication module for the system Fig. 1 used superframe according to various embodiments, Fig. 5 example formats for a synchronization control frame in different operating modes of the system Fig. 1 according to various embodiments, Fig. 6 example formats for a synchronization response frame in different operating modes of the system Fig. 1 according to various embodiments, Fig. 7 is a block diagram of various components of the bus protocol circuitry of Fig. 2 according to various embodiments, the Fig. 8 - 11 Examples of information exchange along a two-wire bus according to various embodiments of the bus protocols described here, Fig. 12 shows a ring topology for the two-wire bus and a unidirectional communication scheme therefor according to various embodiments, Fig. 13 schematically shows a device that acts as a node or host in the system of Fig. 1 can serve, according to various embodiments and the Fig. 14 - 28 Orders for a remote bus release in the system from Fig. 1 according to various embodiments. Detailed description

[0010] Systems and techniques for remote bus enablement are disclosed below. According to some embodiments, a communication system with remote enablement functionality may include: a master transceiver coupled to a downstream connection of a bus; a voltage regulator, the voltage regulator having a voltage output and an enable input, the voltage output coupled to the master transceiver; and a switch coupled to the enable input of the voltage regulator.

[0011] Here, "remote bus enable" may refer to the use of a non-master device on a bus to enable communications over the bus. For example, when a master device on a bus is in a power-down mode, a low-power mode, a sleep mode, or other standby mode (and, accordingly, normal communications over the bus are disabled), the remote bus enablement systems and techniques disclosed herein may enable a non-master device (e.g., a slave device or another device along the bus, such as a switch) to "wake up" the master device and thereby enable communications over the bus. Once woken up, the master device may execute its discovery and initialization protocols, after which the bus may be used as a high-speed communications link.Accordingly, various systems and techniques disclosed herein may enable power savings (e.g., by allowing the master device to place the entire communications system into a low-power mode when active communications are not required) and a flexible and rapid return to full communications (e.g., by allowing a slave or other device on the bus to wake up the master). Various remote bus enablement systems and techniques disclosed herein may be relatively low-power even in the sense that they do not require conventional bus communication to wake up the master device, and may instead use other mechanisms that use less power than conventional bus communication to initiate wake-up of the master device.

[0012] In some conventional communication systems, a communication bus can only be released by a command issued by the master device. If the master device is in sleep mode or otherwise in a low-power mode, it must be powered up directly before communications can be restored. This type of direct power-up may require additional wires or possibly an entirely separate bus system that remains "on" at all times (and thus constantly consumes power).

[0013] Any of the embodiments disclosed herein may be used in a suitable environment. According to some embodiments, as discussed below, the communication systems disclosed herein may be used in a vehicle, and the remote bus enabling techniques may be used to allow a non-master component in a vehicle to activate the communication system when it is in a sleep or other dormant mode. For example, pressing a roadside assist button or an emergency call button in a vehicle (e.g., on the rearview mirror) may trigger the awakening of a master device on a communication bus to which the button is coupled (e.g., as a slave device or in another manner, as described below).In another example, a microphone coupled to a communications bus can trigger the wake-up of a master device when voice commands are detected or when an increased noise level is detected.

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, wherein like reference numerals designate like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be interpreted in a limiting sense.

[0015] Various operations may, in turn, be described as a plurality of discrete actions or operations in a manner most useful for understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order of presentation. Described operations may be performed in a different order than the described embodiment. Various additional operations may be performed, and / or described operations may be omitted from additional embodiments.

[0016] For the purposes of this disclosure, the term "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0017] Various components may be referred to or discussed herein in the singular (e.g., a "processor," a "peripheral device," etc.), but this is for convenience of discussion only, and each element referred to in the singular may include multiple such elements in accordance with the teachings presented herein.

[0018] The description uses the terms "according to an embodiment" or "according to embodiments," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "having," "with," and the like, as used with respect to embodiments of the present disclosure, are synonymous. Herein, the term "circuitry" may refer to, be part of, or include an application-specific integrated circuit (ASIC), an electronic circuit and an optical circuit, a processor (shared, dedicated, or group) and / or a memory (shared, dedicated, or group) executing one or more software or firmware programs, a combinational logic circuit, and / or other suitable hardware, thereby providing the described functionality.A master node may also be referred to here as a master “device,” and similarly, a slave node may be referred to here as a slave “device.”

[0019] Fig. Figure 1 is a block diagram of an illustrative half-duplex two-wire communication system 100 according to various embodiments. The system 100 includes a host 110, a master node 102, and at least one slave node 104. Fig. 1 shows three slave nodes (0, 1 and 2). The representation of the three slave nodes 104 in Fig. 1 is for illustrative purposes only, and the system 100 may include one, two, or more slave nodes 104 as desired.

[0020] The master node 102 may communicate with the slave nodes 104 via a two-wire bus 106. The bus 106 may include various two-wire bus connections between adjacent nodes along the bus 106 to connect the nodes along the bus 106 in a daisy-chain manner. For example, the bus 106 may be Fig. 1, a connection coupling master node 102 to slave node 0, a connection coupling slave node 0 to slave node 1, and a connection coupling slave node 1 to slave node 2. According to some embodiments, the connections of bus 106 may each be formed from a single pair of twisted wires (e.g., an unshielded twisted pair). According to some embodiments, the connections of bus 106 may each be formed from a coaxial cable (e.g., with the core providing the "positive" wire and the shield providing the "negative" wire, or vice versa).

[0021] The host 110 may include a processor that programs the master node 102, and it acts as the originator and receiver of various payloads transmitted along the bus 106. According to some embodiments, the host 110 may be or include, for example, a microcontroller. In particular, the host 110 may be the master of inter-integrated circuit tone (I2S) communications that occur along the bus 106. The host 110 may communicate with the master node 102 via an I2S / time division multiplexed (TDM) bus and / or an inter-integrated circuit (I2C) bus. According to some embodiments, the master node 102 may be a transceiver (e.g., the one described below with reference to Fig. 2) located within a chassis of the host 110. The master node 102 may be programmable by the host 110 via the I2C bus for configuration and readback, and may be configured to generate clock, synchronization, and framing signals for all slave nodes 104. According to some embodiments, an extension of the I2C control bus between the host 110 and the master node 102 may be embedded in the data streams transmitted over the bus 106, allowing the host 110 to directly access registers and status information for the one or more slave nodes 104, as well as enabling I2C-to-I2C communication over a distance to allow the host 110 to control the peripherals 108.

[0022] The master node 102 may generate "downstream" signals (e.g., data signals, power signals, etc., sent along bus 106 from the master node 102) and receive "upstream" signals (e.g., sent along bus 106 to the master node 102). The master node 102 may provide a clock signal for synchronous data transmission over the bus 106. "Synchronous data" herein may include data (e.g., audio signals) continuously streamed along the bus 106 with a fixed time interval between two consecutive transmissions to / from the same node. According to some embodiments, the clock signal provided by the master node 102 may be derived from an I2S input provided to the master node 102 by the host 110. A slave node 104 may be an addressable network connection point that represents a possible destination for data frames transmitted downstream or upstream on the bus 106.A slave node 104 may also represent a possible source of downstream or upstream data frames. System 100 may allow control information and other data to be transmitted in both directions from one node to the next via bus 106. One or more of the slave nodes 104 may be served by signals transmitted via bus 106.

[0023] In particular, the master node 102 and the slave nodes 104 may each have a positive upstream terminal (referred to as "AP"), a negative upstream terminal (referred to as "AN"), a positive downstream terminal (referred to as "BP"), and a negative downstream terminal (referred to as "BN"). The positive and negative downstream terminals of a node may be coupled to the positive and negative upstream terminals of the neighboring downstream node, respectively. As shown in Fig. 1, the master node 102 may have positive and negative upstream terminals, but these terminals may not be used. According to other embodiments, the master node 102 may not have positive and negative upstream terminals. The last slave node 104 along the bus 106 (the slave node 2 in Fig. 1) may have positive and negative downstream terminals, but these terminals may not be used. According to other embodiments, the last slave node 104 along the bus may not have positive and negative downstream terminals.

[0024] As discussed in detail below, the master node 102 may periodically send a synchronization control frame downstream, optionally along with data intended for one or more of the slave nodes 104. For example, the master node 102 may transmit a synchronization control frame every 1024 bits (representing one superframe) at a frequency of 48 kHz, resulting in an effective bit rate of 49.152 Mbps on the bus 106. Other rates may also be supported, including, for example, 44.1 kHz. The synchronization control frame may allow the slave nodes 104 to identify the beginning of each superframe and, in combination with physical layer coding / signaling, may also allow each slave node 104 to derive its internal operating clock from the bus 106.The synchronization control frame may include a preamble to signal the start of synchronization, as well as control fields that enable various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing to registers of the slave nodes 104), the transmission of I2C information, the remote control of certain general-purpose input / output pins (GPIO pins) on the slave node 104, and other services. A portion of the synchronization control frame following the preamble and the payload data may be scrambled to reduce the likelihood of information in the synchronization control frame being confused with a new preamble and to flatten the spectrum of the corresponding electromagnetic emissions.

[0025] The synchronization control frame may be transmitted between slave nodes 104 (optionally together with other data that may come from the master node 102, but may additionally or alternatively come from one or more upstream slave nodes 104 or from a slave node 104 itself) until it reaches the last slave node 104 (i.e., slave node 2 in Fig. 1) that has been interpreted by the master node 102 as the last slave node 104 or has identified itself as the last slave node 104. Upon receiving the synchronization control frame, the last slave node 104 may transmit a synchronization response frame followed by any data it is authorized to transmit (e.g., a 24-bit audio sample in an assigned time slot). The synchronization response frame may be transmitted upstream between slave nodes 104 (optionally along with data from downstream slave nodes 104), and each slave node 104 may be able to identify, based on the synchronization response frame, a time slot, if any, in which the slave node 104 is authorized to transmit.

[0026] According to some embodiments, one or more of the slave nodes 104 in system 100 may be coupled to and communicate with a peripheral device 108. For example, a slave node 104 may be configured to read and / or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, and / or I2C protocols, as discussed below. Although reference may be made to "peripheral device 108" in the singular, this is for convenience of discussion only, and a single slave node 104 may be coupled to zero, one, or more peripheral devices.Examples of peripheral devices that may be included in peripheral device 108 may include a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a codec, a microphone, a microphone array, a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an environmental condition sensor (e.g., a temperature, humidity, and / or gas sensor), a wired or wireless communication transceiver, a display device (e.g., a touchscreen display), a user interface component (e.g., a button, dial, or other control), a camera (e.g., a video camera), a storage device, or other suitable device that sends and / or receives data.A number of examples of different peripheral device configurations are discussed in detail here.

[0027] According to some embodiments, the peripheral device 108 may include a device configured for inter-integrated circuit (I2S) communication, wherein the peripheral device 108 may communicate with the associated slave node 104 via the I2S protocol. According to some embodiments, the peripheral device 108 may include a device configured for inter-integrated circuit (I2C) communication, wherein the peripheral device 108 may communicate with the associated slave node 104 via the I2C protocol. According to some embodiments, a slave node 104 may not be coupled to any peripheral device 108.

[0028] A slave node 104 and its associated peripheral device 108 may be contained in separate housings and coupled by a wired or wireless communication link, or may be contained in a common housing. For example, a loudspeaker connected as peripheral device 108 may be connected to the hardware for an associated slave node 104 (e.g., the node transceiver 120, described below with reference to Fig. 2) so that the hardware for the associated slave node 104 is contained within a housing that includes other speaker components. The same can apply to any type of peripheral device 108.

[0029] As discussed above, host 110 can communicate with and control master node 102 using multi-channel I2S and I2C communication protocols. Specifically, host 110 can transfer data through I2S to a frame buffer (not shown) in master node 102, and master node 102 can read data from the frame buffer and transfer the data along bus 106. Similarly, master node 102 can store data received over bus 106 in the frame buffer and then transfer the data through I2S to host 110.

[0030] Each slave node 104 may have internal control registers that may be configured through communications from the master node 102. A number of such registers are discussed in detail below. Each slave node 104 may receive downstream data and retransmit the data further downstream. Each slave node 104 may receive and / or generate upstream data and / or retransmit data upstream and / or add data to an upstream transaction.

[0031] Communications along bus 106 may occur in periodic superframes. Each superframe may begin with a downstream synchronization control frame, be divided into periods of one downstream transmission (also referred to as "downstream frames"), one upstream transmission (also referred to as "upstream frames"), and no transmission (where bus 106 is not driven), and end shortly before the transmission of another downstream synchronization control frame. Master node 102 may be programmed (by host 110) with a number of downstream frames to transmit to one or more of slave nodes 104 and a number of upstream frames to receive from one or more of slave nodes 104.Each slave node 104 can be programmed (by the master node 102) with a number of downstream sections for retransmitting down the bus 106, a number of downstream sections for consuming, a number of upstream sections for retransmitting up the bus 106, and a number of upstream sections in which the slave node 104 can transmit data received by the slave node 104 from the associated peripheral device 108. Communication along the bus 106 is described in more detail below with reference to FIG. Fig. 2 - 12 discussed.

[0032] The master node 102 and the slave nodes 104 may each include a transceiver to handle communication between components of the system 100. Fig. 2 is a block diagram of a node transceiver 120 included in a node (e.g., master node 102 or slave node 104) of the system 100 of Fig. 1, according to various embodiments. According to some embodiments, a node transceiver 120 may be included in each of the nodes of system 100, and a control signal may be provided to the node transceiver 120 via a master (MSTR) pin to indicate whether the node transceiver 120 should act as a master (e.g., when the MSTR pin is high) or a slave (e.g., when the MSTR pin is low).

[0033] The node transceiver 120 may include an upstream differential signaling (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be configured with the features described above with reference to Fig. 1, and the downstream DS transceiver 124 may be coupled to the positive and negative upstream terminals discussed above with reference to Fig. 1. According to some embodiments, upstream DS transceiver 122 may be a low-voltage DS (LVDS) transceiver, and downstream DS transceiver 124 may be an LVDS transceiver. Each node in system 100 may be AC-coupled to bus 106, and data signals may be communicated along bus 106 (e.g., via upstream DS transceiver 122 and / or downstream DS transceiver 124) using a predetermined form of DS (e.g., LVDS or multidrop LVDS (MLVDS) or similar signaling) with a suitable encoding for providing timing information over bus 106 (e.g., differential Manchester encoding, two-phase mark encoding, Manchester encoding, non-zero return inverted (NRZI) encoding with run-length limitation, or other suitable encoding).

[0034] The upstream DS transceiver 122 and the downstream DS transceiver 124 may communicate with the bus protocol circuitry 126, and the bus protocol circuitry 126 may communicate with a phase-locked loop (PLL) 128 and a voltage regulator circuitry 130, among other components. When the node transceiver 120 powers up, the voltage regulator circuitry 130 may generate a "power good" signal that the PLL 128 uses as a power-on reset.

[0035] As mentioned above, one or more of the slave nodes 104 in system 100 may receive power transmitted over bus 106 concurrently with data. This mode of operation may be referred to herein as "phantom power." For power sharing (which is optional because some of the slave nodes 104 may be configured to provide only local power), the master node 102 may provide a DC bias voltage to the bus connection between the master node 102 and the slave nodes (for example, by connecting one of the downstream terminals to a voltage source provided by a voltage regulator and the other downstream terminal to ground). The DC bias voltage may be a predetermined voltage, such as 5 V, 8 V, the voltage of a car battery, or higher.Each successive slave node 104 can selectively tap its upstream bus connection to reclaim power (e.g., using voltage regulator circuitry 130). This power can be used to power the slave node 104 itself (and optionally one or more peripheral devices 108 coupled to the slave node 104). A slave node 104 can also selectively bias the downstream bus connection for the next downstream slave node 104 with either power reclaimed from the upstream bus connection or power from a local power supply.For example, slave node 0 may use the DC bias on upstream bus connection 106 to reclaim power for slave node 0 itself and / or one or more associated peripheral devices 108, and / or slave node 0 may reclaim power from its upstream bus connection 106 to bias its downstream bus connection 106.

[0036] Accordingly, according to some embodiments, each node in system 100 may provide power to the following downstream node via a downstream bus connection. Powering the nodes may occur sequentially. For example, after discovering and configuring slave node 0 via bus 106, master node 102 may instruct slave node 0 to provide power to its downstream bus connection 106 to provide power to slave node 1, and after discovering and configuring slave node 1, master node 102 may instruct slave node 1 to provide power to its downstream bus connection 106 to provide power to slave node 2 (and so on for additional slave nodes 104 coupled to bus 106). According to some embodiments, one or more of the slave nodes 104 may be powered locally instead of being powered from its upstream bus connection, or this may occur in addition to being powered.According to some such embodiments, the local power source for a given slave node 104 may be used to provide power to one or more downstream slave nodes.

[0037] According to some embodiments, upstream filter circuitry 132 may be disposed between upstream DS transceiver 122 and voltage regulator circuitry 130, and downstream filter circuitry 131 may be disposed between downstream DS transceiver 124 and voltage regulator circuitry 130. Because each connection of bus 106 may carry AC (signal) and DC (power) components, upstream filter circuitry 132 and downstream filter circuitry 131 may separate the AC and DC components, provide the AC components to upstream DS transceiver 122 and downstream DS transceiver 124, and provide the DC components to voltage regulator 130. AC couplings on the line side of the upstream DS transceiver 122 and the downstream DS transceiver 124 substantially isolate the transceivers 122 and 124 from the DC component on the line to enable high-speed bidirectional communications.As discussed above, current may be diverted from the DC component, and the upstream filter circuitry 132 and the downstream filter circuitry 131 may include, for example, a ferrite core, a common-mode choke, or an inductor to reduce the AC component provided to the voltage regulator circuitry 130. According to some embodiments, the upstream filter circuitry 132 may be included in the upstream DS transceiver 122 and / or the downstream filter circuitry 131 may be included in the downstream DS transceiver 124. According to other embodiments, the filter circuitry may be external to the transceivers 122 and 124.

[0038] Node transceiver 120 may include a transceiver 127 for I2S, TDM, and PDM communication between node transceiver 120 and an external device 155. Although reference is made herein to "external device 155" in the singular, this is for convenience of explanation only, and multiple external devices may communicate with node transceiver 120 via I2S / TDM / PDM transceiver 127. As is known in the art, the I2S protocol is used to transmit pulse code modulated (PCM) information (for example, between audio chips on a printed circuit board (PCB)). Here, "I2S / TDM" may refer to an extension of I2S stereo (2-channel) content to multiple channels using TDM. As is known in the art, PDM can be used in sigma-delta converters and, in particular, the PDM format can represent an oversampled 1-bit sigma-delta ADC signal before decimation.The PDM format is often used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 can communicate with the bus protocol circuitry 126 and pins for communication with the external device 155. Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0], are shown in . Fig. 2. The BCLK pin can be used for an I2S bit clock, the SYNC pin can be used for an I2S frame synchronization signal, and the DTX[1:0] and DRX[1:0] pins are used for transmit and receive data channels, respectively. Although two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are used in Fig. 2, any number of receive and / or transmit pins can be used.

[0039] When the node transceiver 120 is included in the master node 102, the external device 155 may include the host 110, and the I2S / TDM / PDM transceiver 127 may provide an I2S slave (with respect to BCLK and SYNC) that can receive and transmit data to the host 110 in synchronization with an I2S interface clock of the host 110. Specifically, an I2S frame synchronization signal may be received as input from the host 110 at the SYNC pin, and the PLL 128 may use this signal to generate clocks. When the node transceiver 120 is included in a slave node 104, the external device 155 may include one or more peripheral devices 108, and the I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BLCK and SYNC) that may control I2S communication with the peripheral device 108. In particular, the I2S / TDM / PDM transceiver 127 may provide an I2S frame synchronization signal on the SYNC pin as an output.Registers in node transceiver 120 can determine which and how many I2S / TDM channels are transmitted as data slots over bus 106. A TDM mode (TDMMODE) register in node transceiver 120 can store a value indicating how many TDM channels fit between consecutive SYNC pulses on a TDM transmit or receive pin. Together with the knowledge of the channel size, node transceiver 120 can automatically set the BCLK rate to match the number of bits within the sample time (e.g., 48 kHz).

[0040] The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. Although reference is made herein to the "external device 157" in the singular, this is for convenience of explanation only, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As is known in the art, the I2C protocol uses clock (SCL) and data (SDA) lines to provide data transmission. The I2C transceiver 129 may be in communication with the bus protocol circuitry 126 and pins for communication with the external device 157. Four pins ADR1, ADR2, SDA, and SCL are in Fig. 2, where ADR1 and ADR2 can be used to modify I2C addresses used by node transceiver 120 when node transceiver 120 acts as an I2C slave (e.g., when included in master node 102), and SDA and SCL are used for the I2C serial data and serial clock signals, respectively. When node transceiver 120 is included in master node 102, external device 157 can include host 110, and I2C transceiver 129 can provide an I2C slave that can receive programming instructions from host 110. In particular, a serial I2C clock signal can be received at the SCL pin as input from host 110 for register accesses.When node transceiver 120 is included in a slave node 104, external device 157 may include a peripheral device 108, and I2C transceiver 129 may provide an I2C master to enable the I2C transceiver to program one or more peripheral devices according to commands provided by host 110 and sent to node transceiver 120 over bus 106. In particular, I2C transceiver 129 may provide the I2C serial clock signal as an output at the SCL pin.

[0041] Node transceiver 120 may have an interrupt request (IRQ) pin in communication with bus protocol circuitry 126. When node transceiver 120 is included in master node 102 via I2C transceiver 129, bus protocol circuitry 126 may provide event-triggered interrupt requests to host 110 via the IRQ pin. When node transceiver 120 is included in a slave node 104 (e.g., when the MSTR pin is low), the IRQ pin may serve as a GPIO pin with interrupt request capability. Node transceiver 120 may, in addition to the Fig. 2 shown other pins (for example those described below with reference to Fig. 14 - 28 discussed DETECTION and VSSN pins).

[0042] System 100 may operate in any of a number of different operating modes. The nodes on bus 106 may each have a register indicating which operating mode is currently enabled. Descriptions of examples of various operating modes that may be implemented follow. In a standby operating mode, bus activity is reduced to enable global power savings, with the only necessary traffic being a minimal downstream preamble to maintain synchronization of each node's PLL (e.g., PLL 128). In standby operating mode, reading and writing across bus 106 are not supported. In a discovery operating mode, master node 102 may broadcast predetermined signals along bus 106 and wait for appropriate responses to expose the topology of slave nodes 104 distributed along bus 106.In a normal operating mode, full register access to and from slave nodes 104, as well as access to and from peripheral devices 108 via bus 106, may be available. Normal mode can be globally configured by host 110 with or without synchronous upstream data and with or without synchronous downstream data.

[0043] Fig. 3 is a diagram of a portion of a synchronization control frame 180 used for communication in system 100 according to various embodiments. In particular, the synchronization control frame 180 may be used for data clock recovery and PLL synchronization, as discussed below. As mentioned above, because communications over bus 106 may occur in both directions, communications may be time-multiplexed into downstream sections and upstream sections. In a downstream section, a synchronization control frame and downstream data may be sent from the master node 102, while in an upstream section, a synchronization response frame and upstream data may be sent from each of the slave nodes 104 to the master node 102. The synchronization control frame 180 may include a preamble 182 and control data 184.Each slave node 104 may be configured to use the preamble 182 of the received synchronization control frame 180 as a time base for feeding to the PLL 128. To facilitate this, a preamble 182 does not follow the "rules" of valid control data 184 and can thus be easily distinguished from the control data 184.

[0044] For example, according to some embodiments, communication along bus 106 may be encoded using a differential clock-first transition-at-zero Manchester coding scheme. According to such a coding scheme, each bit time begins with a clock transition. If the data value is zero, the encoded signal undergoes another transition in the middle of the bit time. If the data value is one, the encoded signal does not undergo another transition. Fig. The preamble 182 shown in Figure 5 may violate the coding protocol (for example, by having clock transitions that do not occur at the beginning of bit times 5, 7, and 8), meaning that the preamble 182 may not match any legal (for example, correctly encoded) pattern for the control data 184. In addition, the preamble 182 cannot be reproduced by taking a legal pattern for the control data 184 and forcing the bus 106 high or low for a single bit time or for a multi-bit period. Fig. 5 is for illustrative purposes only, and the synchronization control frame 180 may include various preambles 182 that may violate the encoding used by the control data 184 in a suitable manner.

[0045] Bus protocol circuitry 126 may include differential Manchester decoding circuitry that operates on a clock recovered from bus 106 and detects synchronization control frame 180 to send a frame synchronization indicator to PLL 128. In this way, synchronization control frame 180 may be detected without the use of a system clock or a faster oversampling clock. Consequently, slave nodes 104 may receive a PLL synchronization signal from bus 106 without requiring a crystal clock source at slave nodes 104.

[0046] As mentioned above, communications along bus 106 may occur in periodic superframes. Fig. 4 is a diagram of a superframe 190 according to various embodiments. As shown in Fig. 6, a superframe may begin with a synchronization control frame 180. When the synchronization control frame 180 is used as the timing source for the PLL 128, the frequency at which superframes are transmitted ("the superframe frequency") may be equal to the frequency of the synchronization signal. According to some embodiments where audio data is transmitted along the bus 106, the superframe frequency may be equal to the audio sampling frequency used in the system 100 (e.g., either 48 kHz or 44.1 kHz), but any suitable superframe frequency may be used. Each superframe 190 may be divided into downstream transmission periods 192, upstream transmission periods 194, and non-transmission periods 196 (when the bus 106 is not driven).

[0047] In Fig. 4, superframe 190 is illustrated as having an initial period of downstream transmission 192 and a later period of upstream transmission 194. The downstream transmission period 192 may include a synchronization control frame 180 and X downstream data slots 198, where X may be zero. Substantially all signals on bus 106 may be line-encoded and may be a synchronization signal passed downstream from master node 102 to the last slave node 104 (e.g., slave node 104C) in the form of synchronization preamble 182 in synchronization control frame 180, as discussed above. Downstream, synchronous TDM data may be included in the X downstream data slots 198 following synchronization control frame 180. The downstream data slots 198 may have the same width.As discussed above, PLL 128 may provide the clock a node uses to time communications over bus 106. In some embodiments where bus 106 is used to transmit audio data, PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe).

[0048] The upstream transmission period 194 may include a synchronization response frame 197 and Y upstream data slots 199, where Y may be zero. According to some embodiments, each slave node 104 may consume a portion of the downstream data slots 198. The last slave node (e.g., slave node 2 in Fig. 1) may respond (after a predetermined response time stored in a register of the last slave node) with a synchronization response frame 197. Upstream, synchronous TDM data may be added by each slave node 104 in the upstream data slots 199 directly following the synchronization response frame 197. The upstream data slots 199 may have the same width. A slave node 104 that is not the last slave node (for example, slave nodes 0 and 1 in Fig. 1), may replace the received synchronization response frame 197 with its own upstream response if a read of one of its registers was requested in the synchronization control frame 180 of the superframe 190 or if a remote I2C read was requested in the synchronization control frame 180 of the superframe 190.

[0049] As discussed above, the synchronization control frame 180 may initiate any downstream transmission. According to some embodiments, the synchronization control frame 180 may be 64 bits long, but any other suitable length may be used. The synchronization control frame 180 may begin with the preamble 182, as mentioned above. According to some embodiments, when the synchronization control frame 180 is retransmitted by a slave node 104 to a downstream slave node 104, the preamble 182 may be generated by the transmitting slave node 104 rather than retransmitted.

[0050] The control data 184 of the synchronization control frame 180 may include fields containing data used to control transactions over the bus 106. Examples of these fields are discussed below, and some embodiments are described in Fig. 5. In particular, Fig. 5 illustrates example formats for the synchronization control frame 180 in normal mode, I2C mode, and discovery mode, according to various embodiments. According to some embodiments, a different preamble 182 or synchronization control frame 180 may be used exclusively in standby mode, so that the slave nodes 104 do not need to receive the entire synchronization control frame 180 until a transition to normal mode is transmitted.

[0051] According to some embodiments, synchronization control frame 180 may include a count (CNT) field. The CNT field may have a suitable length (e.g., 2 bits) and may be incremented from the value used in the previous superframe (modulo the field length). A slave node 104 receiving an unexpected CNT value may be programmed to return an interrupt.

[0052] According to some embodiments, synchronization control frame 180 may include a node addressing mode (NAM) field. The NAM field may have a suitable length (e.g., 2 bits) and may be used to control access to registers of a slave node 104 via bus 106. In normal mode, registers of a slave node 104 may be read and / or written based on the slave node 104's identifier and the register's address. Broadcast transactions are write operations that should be taken by every slave node 104.According to some embodiments, the NAM field may provide four node addressing modes, including "none" (e.g., data is not addressed to a particular slave node 104), "normal" (e.g., data is transmitted to a specific slave node 104 specified in the address field discussed below), "broadcast" (e.g., addressed to all slave nodes 104), and "discovery."

[0053] According to some embodiments, the synchronization control frame 180 may include an I2C field. The I2C field may have a suitable length (e.g., 1 bit) and may be used to indicate that the period of the downstream transmission 192 includes an I2C transaction. The I2C field may indicate that the host 110 has provided instructions to remotely access a peripheral device 108 acting as an I2C slave with respect to an associated slave node 104.

[0054] According to some embodiments, the synchronization control frame 180 may include a node field. The node field may be of a suitable length (e.g., 4 bits) and may be used to indicate which slave node is addressed for normal and I2C accesses. In discovery mode, this field may be used to program an identifier for a newly discovered slave node 104 into a node identifier register of the slave node 104. Each slave node 104 in the system 100 may be assigned a unique identifier when the slave node 104 is discovered by the master node 102, as discussed below. According to some embodiments, the master node 102 does not have a node identifier, while according to other embodiments, the master node 102 may have a node identifier. According to some embodiments, the slave node 104 connected to the master node 102 on the bus 106 (e.g., slave node 0 in Fig. 1) Slave node 0, and each subsequent slave node 104 has a number 1 higher than that of the previous slave node. However, this is for illustrative purposes only, and any suitable slave node identification system may be used.

[0055] According to some embodiments, synchronization control frame 180 may include a read / write (RW) field. The RW field may have an appropriate length (e.g., 1 bit) and may be used to control whether normal accesses are read accesses (e.g., RW == 1) or write accesses (e.g., RW == 0).

[0056] According to some embodiments, the synchronization control frame 180 may include an address field. The address field may have a suitable length (e.g., 8 bits) and may be used to address specific registers of a slave node 104 through the bus 106. For I2C transactions, the address field may be replaced by I2C control values, such as START / STOP, WAIT, RW, and DATA VALID. For discovery transactions, the address field may have a predetermined value (such as in Fig. 5).

[0057] According to some embodiments, the synchronization control frame 180 may include a data field. The data field may be of any suitable length (e.g., 8 bits) and may be used for normal, I2C, and broadcast write operations. The RESPCYCS value multiplied by 4 may be used to determine how many cycles a newly discovered node should allow to elapse between the beginning of the received synchronization control frame 180 and the beginning of the transmitted synchronization response frame 197. If the NAM field indicates the discovery mode, the node address and data fields discussed below may be encoded as a RESPCYCS value, which, when multiplied by a suitable optional multiplier (e.g., 4), indicates the time in bits from the end of the synchronization control frame 180 to the beginning of the synchronization response frame 197.This allows a newly discovered slave node 104 to determine the appropriate time slot for an upstream transmission.

[0058] According to some embodiments, the synchronization control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have a suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the control data 184 of the synchronization control frame 180 following the preamble 182. According to some embodiments, the CRC value may be calculated according to the CCITT CRC error detection scheme.

[0059] According to some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and the CRC field may be scrambled to reduce the likelihood that a bit sequence in that interval will periodically match the preamble 182 (and thus be misinterpreted by the slave node 104 as the beginning of a new superframe 190) and to reduce the aforementioned electromagnetic emissions. According to some of these embodiments, the CNT field of the synchronization control frame 180 may be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. In various embodiments of the system 100 described herein, scrambling may be omitted.

[0060] Other techniques may be used to ensure that the preamble 182 can be uniquely identified by the slave nodes 104, or to reduce the likelihood that the preamble 182 will appear elsewhere in the synchronization control frame 180, in addition to or instead of techniques such as scrambling and / or error coding, as discussed above. For example, a longer synchronization sequence may be used to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 180 will match it. Additionally or alternatively, the remainder of the synchronization control frame may be structured so that the synchronization sequence cannot occur, for example, by placing fixed "0" or "1" values ​​on appropriate bits.

[0061] The master node 102 may send read and write requests to the slave nodes 104, including both requests specific to communication on the bus 106 and I2C requests. For example, the master node 102 may send read and write requests (indicated using the RW field) to one or more designated slave nodes 104 (using the NAM and Node fields) and indicate whether the request is a bus 106-specific request for the slave node 104, an I2C request for the slave node 104, or an I2C request to be transmitted to an I2C-compatible peripheral device 108 coupled to the slave node 104 at one or more I2C ports of the slave node 104.

[0062] Turning now to upstream communication, note that the synchronization response frame 197 may begin any upstream transmission. According to some embodiments, the synchronization response frame 197 may be 64 bits long, but any other suitable length may be used. The synchronization response frame 197 may also include a preamble, as discussed above with respect to the preamble 182 of the synchronization control frame 180, followed by a data portion. At the end of a downstream transmission, the last slave node 104 on the bus 106 may wait until the RESPCYCS counter expires and then begin the upstream transmission of a synchronization response frame 197. If an upstream slave node 104 was the target of a normal read or write transaction, a slave node 104 may generate its own synchronization response frame 197 and replace the one received from downstream.If a slave node 104 does not see a synchronization response frame 197 from a downstream slave node 104 at the expected time, the slave node 104 generates its own synchronization response frame 197 and begins transmitting it upstream.

[0063] The data portion of the synchronization response frame 197 may include fields used to convey response information back to the master node 102. Examples of these fields are discussed below, and some embodiments are described in Fig. 6. In particular, Fig. 6 Example formats for the synchronization response frame 197 in normal mode, I2C mode, and discovery mode according to various embodiments.

[0064] According to some embodiments, the synchronization response frame 197 may include a count (CNT) field. The CNT field may have a suitable length (e.g., 2 bits) and may be used to transmit the value of the CNT field in the previously received synchronization control frame 180.

[0065] According to some embodiments, the synchronization response frame 197 may include an acknowledgment (ACK) field. The ACK field may have a suitable length (e.g., 2 bits) and may be inserted by a slave node 104 to acknowledge a command received in the previous synchronization control frame 180 when that slave node 104 generates the synchronization response frame 197. Example indicators that may be conveyed in the ACK field include wait, acknowledge, non-acknowledge (NACK), and retry. According to some embodiments, the size of the ACK field may be set to convey an acknowledgment by a slave node 104 that it has received and processed a broadcast message (e.g., by sending a broadcast acknowledgment to the master node 102).According to some such embodiments, a slave node 104 may also indicate whether it has data to transmit (which could be used, for example, for on-demand upstream transmissions such as non-TDM inputs from a keypad or touchscreen, or for prioritized upstream transmissions, for example, when the slave node 104 wants to communicate a fault or emergency).

[0066] According to some embodiments, the synchronization response frame 197 may include an I2C field. The I2C field may have a suitable length (e.g., 1 bit) and may be used to transmit the value of the I2C field in the previously received synchronization control frame 180.

[0067] According to some embodiments, the synchronization response frame 197 may include a node field. The node field may have a suitable length (e.g., 4 bits) and may be used to transmit the identifier of the slave node 104 that generated the synchronization response frame 197.

[0068] According to some embodiments, the synchronization response frame 197 may include a data field. The data field may have a suitable length (e.g., 8 bits), and its value may depend on the transaction type and the ACK response of the slave node 104 generating the synchronization response frame 197. For discovery transactions, the data field may include the value of the RESPCYCS field in the previously received synchronization control frame 180.If the ACK field indicates NACK or if the synchronization response frame 197 responds to a broadcast transaction, the data field may include a broadcast acknowledgement (BA) indicator (in which the last slave node 104 can indicate whether the broadcast letter was received without error), a discovery error (DER) indicator (indicating whether a newly discovered slave node 104 matches an existing slave node 104 in a discovery transaction), and a CRC error (CER) indicator (indicating whether a NACK was caused by a CRC error).

[0069] According to some embodiments, the synchronization response frame 197 may include a CRC field. The CRC field may have a suitable length (e.g., 16 bits) and may be used to transmit a CRC value for the portion of the synchronization response frame 197 between the preamble and the CRC field.

[0070] According to some embodiments, the synchronization response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have a suitable length (e.g., 1 bit) and may be used to indicate that an interrupt has been signaled by a slave node 104.

[0071] According to some embodiments, the synchronization response frame 197 may include an IRQ Node (IRQNODE) ​​field. The IRQNODE field may have a suitable length (e.g., 4 bits) and may be used to transmit the identifier of the slave node 104 that signaled the interrupt presented by the IRQ field. According to some embodiments, the slave node 104 inserts its own identifier into the IRQNODE field to generate the IRQ field.

[0072] According to some embodiments, the synchronization response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have a suitable length (e.g., 4 bits) and may be used to transmit a CRC value for the IRQ and IRQNODE fields.

[0073] According to some embodiments, the synchronization response frame 197 may include an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits of the synchronization response frame 197 (e.g., the last 10 bits). As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (and thus may not be protected by the preceding CRC field). Each slave node 104 that needs to signal an interrupt to the master node 102 inserts its interrupt information into these fields. According to some embodiments, a slave node 104 with a pending interrupt may have a higher priority than any slave node 104 further downstream that also has a pending interrupt. The last slave node 104 along the bus 106 (e.g., slave node 2 in Fig. 1) can always populate these interrupt fields. If the last slave node 104 has no pending interrupt, it can set the IRQ bit to 0 and the IRQNODE field to its own node ID, and provide the correct CRC-4 value. For convenience, a synchronization response frame 197 conveying an interrupt may be referred to herein as an "interrupt frame."

[0074] According to some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce emissions. According to some of these embodiments, the CNT field of the synchronization response frame 197 may be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. In various embodiments of the system 100 described herein, scrambling may be omitted.

[0075] Other techniques may be used to ensure that the preamble 182 can be uniquely identified by the slave nodes 104, or to reduce the likelihood that the preamble 182 will appear elsewhere in the synchronization response frame 197, in addition to or instead of techniques such as scrambling and / or error coding, as discussed above. For example, a longer synchronization sequence may be used to reduce the likelihood that a particular encoding of the remainder of the synchronization response frame 180 will match it. Additionally or alternatively, the remainder of the synchronization response frame may be structured so that the synchronization sequence cannot occur, for example, by placing fixed "0" or "1" values ​​on appropriate bits.

[0076] Fig. 7 is a block diagram of the bus protocol circuitry 126 of Fig. 2 according to various embodiments. The bus protocol circuitry 126 may include control circuitry 154 for controlling the operation of the node transceiver 120 according to the protocol described herein for the bus 106. In particular, the control circuitry 154 may control the generation of synchronization frames for transmission (e.g., synchronization control frames or synchronization response frames, as discussed above), the processing of received synchronization frames, and the execution of control operations specified in received synchronization control frames. The control circuitry 154 may include programmable registers, as discussed below.The control circuitry 154 may generate and receive synchronization control frames, respond appropriately to received messages (e.g., in connection with a synchronization control frame if the bus protocol circuitry 126 is included in a slave node 104, or from an I2C device if the bus protocol circuitry 126 is included in a master node 102), and adapt the framing to the various operating modes (e.g., normal, discovery, standby, etc.).

[0077] When node transceiver 120 prepares data for transmission along bus 106, preamble circuitry 156 may be configured to generate preambles for synchronization frames for transmission and receive preambles from received synchronization frames. According to some embodiments, a downstream synchronization control frame preamble may be transmitted every 1024 bits by master node 102. As discussed above, one or more slave nodes 104 may synchronize to the downstream synchronization control frame preamble and generate local phase-aligned master clocks based on the preamble.

[0078] Cyclic redundancy check (CRC) insertion circuitry 158 may be configured to generate one or more CRCs for synchronization frames for transmission. Frame / compression circuitry 160 may be configured to take incoming data from the I2S / TDM / PDM transceiver 127 (e.g., from a frame buffer associated with the transceiver 127) and / or the I2C transceiver 129, optionally compress the data, and optionally generate parity check bits or error correction codes (ECC) for the data. A multiplexer (MUX) 162 may multiplex a preamble from the preamble circuitry 156, synchronization frames, and data into a stream for transmission. According to some embodiments, the transmit stream may be scrambled by scrambling circuitry 164 prior to transmission.

[0079] For example, according to some embodiments, framing / compression circuitry 160 may employ a floating-point compression scheme. According to such an embodiment, control circuitry 154 may transmit 3 bits indicating how many repeated sign bits are in the number, followed by a sign bit and N-4 data bits, where N is the size of the data to be transmitted over bus 106. The use of data compression may be configured by master node 102, if desired.

[0080] According to some embodiments, the receive stream entering node transceiver 120 may be descrambled by descrambling circuitry 166. A demultiplexer (DEMUX) 168 may demultiplex the preamble, synchronization frames, and data from the receive stream. CRC checking circuitry 159 on the receive side may check received synchronization frames for the correct CRC. If CRC checking circuitry 159 identifies a CRC error in an incoming synchronization control frame 180, control circuitry 154 may be notified of the error and will not execute any control commands in the control data 184 of the synchronization control frame 180.If CRC checking circuitry 159 identifies a CRC error in an incoming synchronization response frame 197, control circuitry 154 may be notified of the error and generate an interrupt for transmission to host 110 in an interrupt frame. Frame extraction / decompression circuitry 170 may accept received data, optionally check its priority, optionally perform error detection and correction (e.g., single error correction - double error detection (SECDED)), optionally decompress the data, and write the received data to I2S / TDM / PDM transceiver 127 (e.g., a frame buffer associated with transceiver 127) and / or I2C transceiver 129.

[0081] As discussed above, upstream and downstream data may be transmitted along bus 106 in TDM data slots within a superframe 190. Control circuitry 154 may include registers dedicated to handling these data slots on bus 106, a number of examples of which are discussed below. If control circuitry 154 is included in a master node 102, the values ​​in these registers may be programmed into control circuitry 154 by host 110. If control circuitry 154 is included in a slave node 104, the values ​​in these registers may be programmed into control circuitry 154 by master node 102.

[0082] According to some embodiments, control circuitry 154 may include a downstream slots (DNSLOTS) register. If node transceiver 120 is included in master node 102, this register may hold the value of the total number of downstream data slots. This register may also define the number of data slots used for combined I2S / TDM / PDM receive operations by I2S / TDM / PDM transceiver 127 in master node 102. In a slave node 104, this register may define the number of data slots forwarded downstream to the next slave node 104 before or after the addition of locally generated downstream slots, as discussed in further detail below with reference to LDNSLOTS.

[0083] According to some embodiments, control circuitry 154 may include a local downstream slots (LDNSLOTS) register. This register may remain unused in master node 102. In a slave node 104, this register may define the number of data slots that slave node 104 uses and does not retransmit. Alternatively, this register may define the number of slots that slave node 104 can contribute to downstream bus connection 106.

[0084] According to some embodiments, control circuitry 154 may include an upstream slots (UPSLOTS) register. In master node 102, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots used for I2S / TDM transmissions by I2S / TDM / PDM transceiver 127 in master node 102. In a slave node 104, this register may define the number of data slots forwarded upstream before slave node 104 begins adding its own data.

[0085] According to some embodiments, control circuitry 154 may include a local upstream slots (LUPSLOTS) register. This register may remain unused in master node 102. In a slave node 104, this register may define the number of data slots that slave node 104 adds to the data received from downstream before sending it upstream. This register may also define the number of data slots used for combined I2S / TDM / PDM receive operations by I2S / TDM / PDM transceiver 127 in slave node 104.

[0086] According to some embodiments, control circuitry 154 may include a broadcast downstream slots (BCDNSLOTS) register. This register may remain unused in master node 102. In a slave node 104, this register may define the number of broadcast data slots. According to some embodiments, broadcast data slots may always appear at the beginning of the data field. The data in the broadcast data slots may be used by multiple slave nodes 104 and may be forwarded downstream by all slave nodes 104, regardless of whether they are used.

[0087] According to some embodiments, control circuitry 154 may include a slot format (SLOTFMT) register. This register may define the data format for upstream and downstream transmissions. The data size for the I2S / TDM / PDM transceiver 127 may also be determined by this register. According to some embodiments, valid data sizes include 8, 12, 16, 20, 24, 28, and 32 bits. This register may also include bits to enable floating-point compression for downstream and upstream traffic. When floating-point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size over bus 106. All nodes of system 100 may have the same values ​​for SLOTFMT when data slots are enabled, and the nodes may be broadcast-programmed so that all nodes are updated with the same value.

[0088] The Fig. 8-11 show examples of information exchange along bus 106 according to various embodiments of the bus protocols described herein. In particular, Fig. 8-11 illustrate embodiments in which each slave node 104 is coupled to one or more speakers and / or one or more microphones as a peripheral device 108. This is for illustrative purposes only, as any desired arrangement of a peripheral device 108 may be coupled to a particular slave node 104 in accordance with the techniques described herein.

[0089] First, Fig. 8 Signaling and timing considerations for bidirectional communication on bus 106 according to various embodiments. Fig. The slave nodes 104 shown in Figure 8 have different numbers of sensor / actuator elements, so that different amounts of data can be sent to or received from different slave nodes 104. In particular, slave node 1 has two elements, slave node 4 has four elements, and slave node 5 has three elements, so that the data sent from slave node 102 has two time slots for slave node 1, four time slots for slave node 4, and three time slots for slave node 5. Similarly, slave node 0 has three elements, slave node 2 has three elements, slave node 3 has three elements, slave node 6 has one element, and slave node 7 has four elements, so that the data transmitted upstream from these slave nodes 104 has the corresponding number of time slots. Note that there does not have to be a one-to-one correlation between elements and time slots.For example, a microphone array including three microphones included in peripheral device 108 may include a digital signal processor that combines signals from the three microphones (and possibly also information received from master node 102 or other slave nodes 104) to generate a single data sample that could correspond to a single time slot or multiple time slots, depending on the type of processing.

[0090] In Fig. 8, the master node 102 transmits a synchronization control frame (SCF), followed by data for loudspeakers coupled to specific slave nodes 104 (SD). Each subsequent slave node 104 forwards the synchronization control frame and also at least data intended for downstream slave nodes 104. A particular slave node 104 can forward all data or discard data intended for that slave node 104. When the last slave node 104 receives the synchronization control frame, that slave node 104 transmits the synchronization response frame (SRF), optionally followed by data that the slave node 104 is authorized to transmit. Each subsequent slave node 104 forwards the synchronization response frame along with data from downstream slave nodes 104 and optionally inserts data from one or more microphones coupled to the particular slave node 104 (MD). In the example from Fig. 8, the master node 102 sends data to slave nodes 1, 4 and 5 (in Fig. 8 shown as active speakers) and receives data from the slave nodes 7, 6, 3, 2 and 0 (in Fig. 8 shown as microphone fields).

[0091] Fig. Figure 9 schematically illustrates the dynamic removal of data from a downstream transmission and the insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124 according to various embodiments. Fig. 9, the master node 102 sends as in Fig. 8 a synchronization control frame (SCF), followed by data for slave nodes 1, 4, and 5 (SD) in reverse order (e.g., data for slave node 5 is followed by data for slave node 4, which is followed by data for slave node 1, and so on) (see line labeled MASTER). When slave node 1 receives this transmission, it removes its own data and forwards to slave node 2 only the synchronization control frame followed by the data for slave nodes 5 and 4. Slave nodes 2 and 3 forward the unchanged data (see line labeled SLAVE 2), so that the data forwarded by slave node 1 is received by slave node 4 (see line labeled SLAVE 3).Slave node 4 removes its own data and forwards only the synchronization control frame, followed by the data for slave node 5, to slave node 5. Similarly, slave node 5 removes its own data and forwards only the synchronization control frame to slave node 6. Slave node 6 forwards the synchronization control frame to slave node 7 (see the line labeled SLAVE 6).

[0092] At this point, slave node 7 sends the synchronization response frame (SRF), followed by its data, to slave node 6 (see the line labeled SLAVE 6). Slave node 6 forwards the synchronization response frame, along with the data from slave node 7 and its own data, to slave node 5, and slave node 5, in turn, forwards the synchronization response frame, along with the data from slave nodes 7 and 6, to slave node 4. Slave node 4 has no data to add, so it simply forwards the data to slave node 3 (see the line labeled SLAVE 3), which forwards the data, along with its own data, to slave node 2 (see the line labeled SLAVE 2), which in turn forwards the data, along with its own data, to slave node 1.Slave node 1 has no data to add, so it forwards the data to slave node 0, which forwards the data along with its own data. As a result, master node 102 receives the synchronization response frame followed by the data from slave nodes 7, 6, 3, 2, and 0 (see the line labeled MASTER).

[0093] Fig. Figure 10 shows another example of dynamic removal of data from a downstream transmission and insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124, as in Fig. 9, although in Fig. 10, the slave nodes 104 are coupled to both sensors and actuators as peripheral devices 108, so that the master node 102 sends data downstream to all slave nodes 104 and receives data back from all slave nodes 104. Also, the data in Fig. 10 are ordered based on the node address to which they are addressed or from which they originate. The data slot labeled "Y" can be used for data integrity checking or data correction.

[0094] Fig. Figure 11 shows another example of dynamic removal of data from a downstream transmission and insertion of data into an upstream transmission from the perspective of the downstream DS transceiver 124, as in Fig. 9, although in Fig. 11, the data is transmitted downstream and upstream in sequential order rather than in reverse. Buffering at each slave node 104 allows for selective addition, removal, and / or forwarding of data.

[0095] As discussed above, each slave node 104 can remove data from downstream or upstream transmissions and / or add data to downstream or upstream transmissions. Accordingly, for example, the master node 102 can send a separate data sample to each of a number of slave nodes 104, and each such slave node 104 can remove its data sample and forward only data intended for downstream slaves. Conversely, a slave node 104 can receive data from a downstream slave node 104 and forward the data along with additional data. One benefit of transmitting as little information as possible is to reduce the overall amount of power consumed by the system 100.

[0096] The system 100 may also support broadcast transmissions (and multicast transmissions) from the master node 102 to the slave nodes 104, particularly by configuring the downstream slot usage of the slave nodes 104. Each slave node 104 may process the broadcast transmission and forward it to the next slave node 104, although a particular slave node 104 may "consume" the broadcast message (ie, not forward the broadcast transmission to the next slave node 104).

[0097] System 100 may also support upstream transmissions (e.g., from a particular slave node 104 to one or more other slave nodes 104). These upstream transmissions may include unicast, multicast, and / or broadcast upstream transmissions. With upstream addressing, as discussed above with respect to downstream transmissions, a slave node 104 may determine, based on the upstream slot usage configuration of the slave nodes 104, whether to remove data from an upstream transmission and / or whether to forward an upstream transmission to the next upstream slave node 104. Accordingly, for example, data may be forwarded by a particular slave node 104 to one or more other slave nodes 104 in addition to, or instead of, forwarding the data to the master node 102. Such slave-slave relationships can be configured, for example, via the master node 102.

[0098] Accordingly, according to various embodiments, the slave nodes 104 may operate as active / intelligent repeater nodes, having the ability to selectively forward, drop, and add information. The slave nodes 104 can generally perform such functions without necessarily decoding / examining all data because each slave node 104 knows the one or more relevant time slots with which it receives / transmits data and can therefore remove data from or add data to a time slot. While the slave nodes 104 may not need to decode / examine all data, the slave nodes 104 can typically retime the data they transmit / forward. This can improve the robustness of the system 100.

[0099] According to some embodiments, the bus 106 may be configured for unidirectional communications in a ring topology. For example, Fig. 12 illustrates an arrangement 1200 of the master node 102 and four slave nodes 104 in a ring topology, and shows signaling and timing considerations for unidirectional communication in the arrangement 1200 according to various embodiments. According to these embodiments, the transceivers 120 in the nodes may comprise a receive-only transceiver (MASTER IN) and a transmit-only transceiver (MASTER OUT) instead of two bidirectional transceivers for upstream and downstream communication. Fig. 12, the master node 102 sends a synchronization control frame (SCF) 180, optionally followed by downstream data 1202 for the three loudspeakers coupled to different slave nodes 104 (the data for the different loudspeakers may be arranged in a suitable order as described above with reference to the Fig. 8-11), and each subsequent slave node 104 forwards the synchronization control frame 180 along with upstream data from previous slave nodes 104 and upstream data from itself to provide upstream data 1204 (for example, the data from the eight different microphones may be arranged in a suitable order as discussed above with reference to the Fig. 8 - 11).

[0100] As described herein, data may be communicated between elements of system 100 in a number of ways. According to some embodiments, data may be sent as part of a set of synchronous data slots by a slave node 104 upstream (e.g., using data slots 199) or by a slave node 104 or a master node 102 downstream (e.g., using data slots 198). The amount of this data may be adjusted by changing the number of bits in a data slot or by including additional data slots. Data may also be communicated in system 100 by inclusion in a synchronization control frame 180 or a synchronization response frame 197.Data communicated in this manner may include I2C control data from host 110 (with a response from a peripheral device 108 associated with a slave node 104), accesses to registers of the slave nodes 104 (e.g., for discovering and configuring slots and interfaces), which may include a write access from the host 110 / master node 102 to a slave node 104 and a read access from a slave node 104 to the host 110 / master node 102, and event signaling through interrupts from a peripheral device 108 to the host 110.According to some embodiments, GPIO pins may be used to communicate information from a slave node 104 to the master node 102 (e.g., by causing the master node 102 to drive the GPIO pins over I2C or by causing a node transceiver 120 of a slave node 104 to generate an interrupt on an interrupt request pin). For example, according to some such embodiments, a host 110 may send information over I2C to the master node 102, and the master node 102 may then send that information over the GPIO pins to the slave. Any of the data types transferred over bus 106 as discussed herein may be transferred using one or more of these communication paths. Other data types and data communication techniques within the system 100 may be disclosed herein.

[0101] Embodiments of the present disclosure may be implemented in a system using suitable hardware and / or software for configuration as desired. Fig. 13 schematically shows a device 1300 that may serve as a host or node (e.g., a host 110, a master node 102, or a slave node 104) in the system 100, according to various embodiments. In Fig. 13, a number of components are shown as being included in the device 1300, however, one or more of these components may be omitted or duplicated as appropriate for the application.

[0102] In addition, according to various embodiments, the device 1300 may include one or more of the Fig. 13, but may include interface circuitry for coupling to the one or more components. For example, device 1300 may not include a display device 1306, but may include display device interface circuitry (e.g., connector and driver circuitry) to which a display device 1306 may be coupled. In another set of examples, device 1300 may not include an audio input device 1324 or an audio output device 1308, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which an audio input device 1324 or an audio output device 1308 may be coupled.

[0103] The device 1300 may include a node transceiver 120 according to any embodiment disclosed herein for handling communication along the bus 106 when the device 1300 is coupled to the bus 106. The device 1300 may include a processing device 1302 (e.g., one or more processing devices) that may be included in the node transceiver 120 or separate from the node transceiver 120. Herein, the term "processing device" may refer to a device or a portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that may be stored in registers and / or memory.Processing device 1302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors, or other suitable processing devices. Device 1300 may include a memory 1304, which may itself include one or more storage devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard disk.

[0104] According to some embodiments, memory 1304 may be used to store a working copy and a permanent copy of programming instructions for causing device 1300 to perform suitable techniques disclosed herein. According to some embodiments, machine-readable media (including non-transitory computer-readable storage media), methods, systems, and apparatus for performing the techniques described above are illustrative examples of embodiments disclosed herein for communication over a two-wire bus. For example, a computer-readable medium (e.g., memory 1304) may store instructions that, when executed by one or more of the processing devices included in processing device 1302, cause device 1300 to perform techniques disclosed herein.

[0105] According to some embodiments, device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, communication chip 1312 may be configured to handle wireless communications for transmitting data to and from device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include wires, although this could be the case according to some embodiments.

[0106] The communication chip 1312 may implement any of a number of wireless standards or protocols, including, but not limited to, the following: Institute for Electrical and Electronic Engineers (IEEE) standards, including WiFi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), the Long Term Evolution (LTE) project along with any extensions, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformance and interoperability tests for the IEEE 802.16 standards.The one or more communication chips 1312 may operate according to a Global System for Mobile Communications (GSM) network, a General Packet Radio Service (GPRS) network, a Universal Mobile Communications System (UMTS) network, a High-Speed ​​Packet Access (HSPA) network, an Evolved HSPA (E-HSPA) network, or an LTE network. The one or more communication chips 1312 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The one or more communication chips 1312 may operate according to a code division multiple access (CDMA) protocol, a time division multiple access (TDMA) protocol, a digital enhanced cordless telecommunications (DECT) protocol, an evolution data optimized (EV-DO) protocol and derivatives thereof, as well as other wireless protocols referred to as 3G, 4G, 5G, etc.The communication chip 1312 may, according to other embodiments, operate according to other wireless protocols. The device 1300 may include an antenna 1322 for enabling wireless communications and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0107] According to some embodiments, communication chip 1312 may handle wired communications using a different protocol than the protocol described herein for bus 106. Wired communications may include electrical, optical, or other suitable communication protocols. Examples of wired communication protocols that may be enabled by communication chip 1312 include Ethernet, Controller Area Network (CAN), I2C, Media Oriented Systems Transport (MOST), or another suitable wired communication protocol.

[0108] As mentioned above, the communication chip 1312 may include multiple communication chips. For example, a first communication chip 1312 may be provided for shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1312 may be provided for longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. According to some embodiments, a first communication chip 1312 may be provided for wireless communication, and a second communication chip 1312 may be provided for hard-wired communication.

[0109] The device 1300 may include a battery / power supply circuitry 1314. The battery / power supply circuitry 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the device 1300 to a separate power source from the device 1300 (e.g., AC mains power, voltage provided by a car battery, etc.). For example, the battery / power supply circuitry 1314 may include the upstream filter circuitry 132 and the downstream filter circuitry 131, as described above with reference to Fig. 2, and charged by the bias voltage on bus 106.

[0110] Device 1300 may include a display device 1306 (or corresponding interface circuitry, as discussed above). Display device 1306 may include visual indicators such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat-panel display.

[0111] Device 1300 may include an audio output device 1308 (or corresponding interface circuitry, as discussed above). Audio output device 1308 may include any device that generates an audible indicator, such as speakers, headsets, or earphones.

[0112] Device 1300 may include an audio input device 1324 (or corresponding interface circuitry, as discussed above). Audio input device 1324 may include any device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI) output).

[0113] Device 1300 may include a Global Positioning System (GPS) device 1318 (or corresponding interface circuitry, as discussed above). GPS device 1318 may be in communication with a satellite-based system and receive the location of device 1300, as is known in the art.

[0114] Device 1300 may include another output device 1310 (or corresponding interface circuitry, as discussed above). Examples of another output device 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. Additionally, suitable peripheral devices 108 discussed herein may be incorporated into another output device 1310.

[0115] Device 1300 may include another input device 1320 (or corresponding interface circuitry, as discussed above). Examples of another input device 1320 may include an accelerometer, a gyroscope, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. Additionally, suitable sensors or peripheral devices 108 discussed herein may be incorporated into another input device 1320.

[0116] Suitable display, input, output, communication, or storage devices described above with reference to device 1300 may serve as peripheral device 108 in system 100. Alternatively or additionally, suitable display, input, output, communication, or storage devices described above with reference to device 1300 may be incorporated into a host (e.g., host 110) or a node (e.g., a master node 102 or a slave node 104).

[0117] The Fig. 14 - 28 show various systems and techniques for remote bus release in the system 100 from Fig. 1. These systems and techniques may be used with any of the embodiments of system 100 disclosed herein, including any of the embodiments of master node 102 and slave node 104. Remarks on the operation and components of various of the Fig. The embodiments illustrated in Figures 14-28 accompany the drawings. According to these embodiments, a voltage regulator 111-1 associated with the master node 102 may include an "enable" input (e.g., a pin) that enables operation of the voltage regulator 111-1 in response to a high (or low, as specified) voltage at the enable input. When the voltage regulator 111-1 is enabled, it may provide an operating voltage to the master node 102 to enable it to control normal bus operations described herein. When the voltage regulator 111-1 is not enabled, it may not provide an operating voltage to the master node 102, and the master node 102 may be in a low-power mode (e.g., a standby mode, a sleep mode, a sleep mode, etc.).Enabling master node 102 to control communications along bus 106 may be referred to herein as “enabling bus 106.”

[0118] Certain circuits and operating details may be disclosed with respect to various of the embodiments of the Fig. 14 - 28, and they can be used for other of the embodiments from the Fig. 14 - 28 apply, but for reasons of economic explanation they cannot be repeated. According to the Fig. 14-28, the master node 102 may include a node transceiver 120-1 and associated downstream filter circuitry 131, and the slave node 104 may include a node transceiver 120-1 and associated upstream filter circuitry 132. The Fig. 14-28 also show the slave node 104 having the downstream filter circuitry 131, which is suitable when there are other downstream slave nodes 104 (not shown) in the system 100. Power may be provided to the master node 102 by a power supply 119 (e.g., a battery or other power supply device), and a voltage regulator 111-1 may be arranged between the power supply 119 and the master node 102 such that the output of the power supply 119 is input to the voltage regulator 111-1. In various of the Fig. Diodes included in the embodiments illustrated in Figures 14-28 may help protect against unintended current flow, and they may or may not be included as needed. The embodiments of Figures Fig. 14 - 28 have a number of high-pass filters (HPF) and low-pass filters (LPF) arranged in various ways, and any suitable HPF and LPF circuits can be used.

[0119] According to some embodiments, the voltage regulator 111-1 and the power supply 119 may be integrated into a single voltage-regulated power supply. Accordingly, the "voltage regulators 111" disclosed herein may be understood to represent a suitable power supply. The voltage regulators 111-1 and the power supply 119 disclosed in any of the Fig. The switches illustrated in Figures 14-28 may be provided by mechanically actuated switches or electronic switches that close / open in response to a control signal (e.g., a sound level above a threshold, a wireless communication received from a smartphone or remote control, etc.). For example, a switch may be a push-button switch, a dial, a field-effect transistor (FET) switch controlled by a microcontroller, etc.

[0120] Although this is in the Fig. 14-28, according to some embodiments, an additional voltage regulator or a Zener diode may be used at the enable input of the voltage regulator 111-1 to achieve a more tightly controlled enable voltage. Although this is not shown in the Fig. 14-28, according to some embodiments, an additional voltage regulator or Zener diode may be used on the I / O pins of the host 110 and / or the node transceivers 120 (e.g., to protect these pins by limiting the maximum voltage that can be applied).

[0121] Fig. Figure 14 shows an embodiment of system 100 in which slave node 104 may have its own local power source (indicated by its associated voltage regulator 111-2 coupled to power supply 119). A switch 113 coupled to an output pin of voltage regulator 111-2 may apply a DC voltage to bus 106 (through resistor R5) when switch 113 is closed, which may then enable voltage regulator 111-1 (through resistor R4). The output of voltage regulator 111-1 may be coupled to the enable input of voltage regulator 111-1 through a resistor R1. This loop may maintain voltage regulator 111-1 in an enabled mode if switch 113 on slave node 104 is a momentary switch (and thus opens shortly after it is initially closed).According to some embodiments, the diode connected between resistor R4 and the enable input of voltage regulator 111-1 may not be included, as mentioned above. Host 110 (which may be or include a microcontroller, as mentioned above) may have an I / O pin coupled through a resistor R2 to the enable input of voltage regulator 111-1, which host 110 may use to disable voltage regulator 111-1 when master node 102 is to enter a low-power mode. According to some embodiments, the I / O pin of host 110 may maintain the enable input on voltage regulator 111-1 after switch 113 initiates bus enable (e.g., by momentarily closing).An I / O pin of slave node 104 may be coupled to one side of switch 113 to detect the closure of switch 113, and according to some embodiments, when slave node 104 detects that switch 113 has been closed, slave node 104 may generate an interrupt (e.g., sent over I2C). The resistance of resistor R5 may be chosen to provide a high impedance between slave node 104 and master node 102 so as not to interfere with line diagnostics that would identify a fault if bus 106 were to appear shorted to voltage regulator 111-2 of slave node 104. Resistor R5 may act as a current-limiting resistor and may be part of a voltage divider with resistor R6 or resistor R3. In the system 100 of FIG. Fig. 14, the slave node 104 can draw power for the voltage regulator 111-2 and quiescent power for the node transceiver 120-2 when the bus 106 is inactive.

[0122] Fig. 15 shows an embodiment of system 100 in which node transceiver 120-1 itself may have an I / O pin coupled to the enable input of voltage regulator 111-1 through resistor R2, wherein master node 102 may use this I / O pin to disable voltage regulator 111-1 when master node 102 is to enter a low-power mode. According to some embodiments, the I / O pin of node transceiver 120-1 may maintain the enable input on voltage regulator 111-1 after switch 113 initiates bus enable (e.g., by momentarily closing). Such an embodiment may be particularly suitable, for example, when host 110 does not have an available I / O pin for disabling voltage regulator 111-1. In the system 100 of Fig. 15, the slave node 104 can draw power for the voltage regulator 111-2 and quiescent power for the node transceiver 120-2 when the bus 106 is inactive. The voltage regulator 111-2 in the system 100 from Fig. 15 (and other embodiments of system 100) may be a voltage divider, other voltage limiting circuitry, or a direct connection to power supply 119 (as discussed below).

[0123] Fig. 16 shows an embodiment of system 100 in which slave node 104 may be "phantom powered" by the voltage provided by master node 102 via bus 106. In particular, as discussed above, upstream filter circuitry 132 of slave node 104 may low-pass filter the signals provided via bus 106 and use the low-frequency components (e.g., DC components) to power node transceiver 120-2, as shown. Voltage regulator 111-2 associated with slave node 104, as shown in Fig. 16 is an optional component that may be included to allow the slave node 104 to provide power to the bus 106 to enable signaling through the switch 113, as discussed above, but it may not be used to power the slave node 104 (unlike the embodiments of FIGS. Fig. 14 and Fig. 15). The system 100 from Fig. 16 may include an I / O pin of the host 110 coupled to the enable input of the voltage regulator 111-1 (as described above with reference to Fig. 14) or an I / O pin of the node transceiver 120-1 coupled to the enable input of the voltage regulator 111-1 through the resistor R2 (as discussed above with reference to Fig. 15). According to the embodiment of Fig. 16 (and the Fig. 17 - 20), the quiescent current drawn by the node transceiver 120-2 may be limited.

[0124] According to the Fig. 17, a switch 115 having its own voltage regulator 111-3 (e.g., a battery) may be coupled to the bus 106 (e.g., through a resistor R8), as shown, and this switch 115 may be used to enable the master node 102, as described above with reference to Fig. 14. According to some embodiments, the resistance of resistor R8 may be equal to the resistance of resistor R5. Fig. 17 accordingly shows an embodiment in which a non-slave switch such as switch 115 (or other device) may be coupled to bus 106 and used to enable bus communications. Fig. Figure 17 also shows a switch 113 associated with the slave node 104, which may also be used to enable bus communications (for example, as described above with reference to Fig. 14), such that actuation of either switch 115 or switch 113 may enable communications along bus 106. For example, slave node 104 may be a microphone device mounted in the roof of a vehicle, and switch 115 may be a roadside emergency assist button located near the upper light pickup assembly or in the instrument panel, with communications along bus 106 being enabled by pressing the roadside emergency assist button (associated with switch 115) or issuing a voice command that is received and interpreted by slave node 104 (associated with switch 113). According to some embodiments, switch 113 (and its associated circuitry for enabling bus 106) may not be included in system 100 of Fig. 17. According to the embodiment of Fig. 17, the slave node 104 is also phantom powered (as described above with reference to Fig. 16), the voltage regulator 111-3 and the switch 115 (and their associated circuitry) may also be used in combination with the Fig. 14 and Fig. 15 illustrated systems 100 (in which the slave node 104 is supplied locally).

[0125] Fig. 18 shows an embodiment of system 100 wherein a switch 117 and an associated voltage regulator 111-4 may be used "behind" the slave node 104 on bus 106 to enable bus 106. Specifically, the slave node 104 may be located between the point where the switch 117 / voltage regulator 111-4 contacts bus 106 (through a resistor R9) and the master node 102 along bus 106. According to some embodiments, the resistance of resistor R9 may be equal to the resistance of resistor R5. Fig. 18 also includes the switch 115 and the switch 113 as described above with reference to Fig. 17, wherein, according to some embodiments, switch 115 and / or switch 113 (and their associated circuitry for enabling bus 106) from the embodiment of system 100 of Fig. 18 may be omitted. In Fig. 18, the switches within the master node 102 and the slave node 104 are shown as NMOS / PMOS FETs, whereby during operation, the voltage applied to the bus 106 by the switch 117 can "drop back" via these internal NMOS / PMOS FETs all the way to the master node 102. According to the embodiment of Fig. 18, the slave node 104 is also phantom powered (as described above with reference to Fig. 16), the voltage regulator 111-4 and the switch 117 (and their associated circuitry) may also be used in combination with the Fig. 14 and Fig. 15 illustrated systems 100 (in which the slave node 104 is supplied locally). Fig. 18 accordingly shows another embodiment in which a non-slave switch such as switch 117 (or other device) may be coupled to bus 106 and used to enable bus communications. For example, slave node 104 may be a microphone device mounted in the roof of a vehicle, and switch 117 may be a roadside emergency assistance button, as described above with reference to Fig. 17 was discussed.

[0126] Fig. Figure 19 shows an embodiment of the system 100 that shares a number of features with the Fig. 18 illustrated embodiment, in Fig. 19, however, there is no diode between resistor R4 and the enable input of voltage regulator 111-1. Adequate reverse bias protection can be provided by the PMOS FET (labeled "PMOS1") in master node 102 (e.g., represented by the diode symbol of PMOS1). According to the embodiment of Fig. 19 (and Fig. 20), resistors R5 and R6 may provide a voltage divider for the voltage at the enable input of voltage regulator 111-1. One or more of switches 113, 115, and 117 (and their associated circuitry for enabling bus 106) may, if desired, be derived from the embodiment of Fig. 19 may be omitted. Similarly, the provisions of any of the Fig. 14-28 may be modified by omitting the diode between resistor R4 and the enable input of voltage regulator 111-1.

[0127] Fig. Figure 20 shows an embodiment of the system 100 that shares a number of features with the Fig. 18 illustrated embodiment, wherein in Fig. 20, however, switches 113, 115, and 117 are coupled to power supply 119 without intervening voltage regulators 111-2, 111-3, and 111-4, respectively. According to some embodiments, switches 113, 115, and / or 117 may be directly coupled to power supply 119 as shown. One or more of switches 113, 115, and 117 (and their associated circuitry for enabling bus 106) may, if desired, be derived from the embodiment of Fig. 20 may be omitted. Similarly, the Fig. 14-28 may be modified by omitting the voltage regulators 111 between the power supply 119 and the switches 113, 115 and / or 117. According to the embodiment of Fig. 20, the slave node 104 is also phantom powered (as described above with reference to Fig. 16), and switches 113, 115 and 117 (and their associated circuitry) may also be used in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

[0128] The Fig. Figures 14-20 show a resistor R6 between resistor R4 and ground. This specific location for resistor R6 is for illustrative purposes only, and resistor R6 can be placed at a number of locations in system 100. Fig. Figure 21 shows exemplary locations for the resistor R6 in connection with the system 100 from Fig. 14, wherein the system 100 may include a resistor R6 in any of the positions indicated by a dotted line. More generally, any of the Fig. The positions illustrated in Figure 21 may be used for resistor R6 according to any embodiments disclosed herein. Resistor R6, along with one or more other resistors in system 100, may provide a voltage divider for generating the voltage provided to the enable input of voltage regulator 111-1. Resistor R6 may not be included in some embodiments. Resistor R7 may be similarly repositioned according to other embodiments.

[0129] When a power supply (e.g., a voltage regulator) located locally at a switch provides the power (e.g., voltage) required to initiate the enable of bus 106 by actuating a switch (e.g., as described above with reference to Fig. 14-21), an exemplary enable sequence may be as provided below. The master node 102 may begin in a low-power mode in which its associated voltage regulator 111-1 is disabled. The switch (e.g., switch 113, 115, or 117 according to suitable embodiments) may be closed, completing a connection to the power supply (e.g., a voltage regulator 111-2, 111-3, 111-4, and / or the power supply 119). The power supply may provide a bias voltage on the bus 106 through the switch (according to some embodiments, through a reverse current protection diode and a resistor used to provide high impedance, thereby mitigating interference with cable diagnostics).The bias voltage on bus 106 may be applied to the enable input of voltage regulator 111-1, which is "local" to master node 102 (e.g., through a forward diode and a resistor). Accordingly, voltage regulator 111-1 may initially be enabled by the bias voltage on bus 106 (provided by the power supply), and voltage regulator 111-1 may be maintained in the enabled state (e.g., through a feedback loop from the output of voltage regulator 111-1 to the enable input of voltage regulator 111-1, as described in various of the . Fig. 14-28). Node transceiver 120-1 can receive and ramp up the voltage output from voltage regulator 111-1.

[0130] According to some embodiments, the host 110 may also be connected to the voltage regulator 111-1, where the host 110 may, for example, be powered by the voltage regulator 111-1 and boot in response to the voltage output by the voltage regulator 111-1. In another example, the host 110 may receive a signal (at an input pin) representing the enable of the voltage regulator 111-1 (for example, the output signal from the voltage regulator 111-1 or the signal at the enable input of the voltage regulator 111-1). This latter embodiment may be particularly suitable when the host 110 is not powered by the voltage regulator 111-1, but instead has another power supply. After detecting that the master node 102 is powered up, the host 110 may initiate the programming of the node transceiver 120-1 and the discovery of slave nodes 104 on the bus 106.Node transceiver 120-1 may assume control of the bias on bus 106 (e.g., through a bus bias switch and line diagnostic functions of node transceiver 120-1). Upon discovery of a slave node 104, slave node 104 may monitor the status of an I / O pin reflecting the state of the switch that initiated the bus enable. When the state of this switch changes (e.g., the switch is opened or closed), slave node 104 may send an interrupt to host 110 or generate a GPIO-to-GPIO transmission of this information over bus 106 to host 110. The particular state of the switch may determine subsequent events (e.g., the master node 102 may return to its low-power mode, the host 110 may perform some predetermined "cleanup" procedures before the bus 106 is disabled, etc.).Communications along bus 106 may be disabled when the I / O pin to node transceiver 120-1 is pulled low. According to some embodiments, removing power to node transceiver 120-1 (e.g., from voltage regulator 111-1) may disable all data registers in node transceiver 120-1.

[0131] According to the provisions referred to above with reference to Fig. In the embodiments discussed in Figures 14-21, bus 106 was enabled by applying a reference voltage different from ground. Fig. Figure 22 shows an embodiment of system 100 wherein bus communications can be enabled by grounding bus 106 instead of a reference voltage other than ground. In particular, Fig. 22 illustrates an embodiment of system 100 wherein any of three switches 113, 115, and 117 may be closed to temporarily short bus 106 to ground (through associated resistors R8, R5, and R9, respectively), thereby enabling communications over bus 106, as discussed above. In Fig. 22 (and Fig. 23), resistors RB and RC provide a voltage divider for positioning the turn-off level and the enable input level (e.g., together with resistor R8). According to some embodiments, resistor RB may be used instead of PMOS1 to provide a weak bias to bus 106. Resistors RB and RC are optional. According to the embodiments of Fig. 22 and Fig. 23, a signal from the I / O pin of host 110 can be used to disable voltage regulator 111-1. One or more of switches 113, 115, and 117 (and their associated circuitry for enabling bus 106) can, if desired, be derived from the embodiment of Fig. 22 may be omitted. According to the embodiment of Fig. 22, the slave node 104 is also phantom powered (as described above with reference to Fig. 16) and the switches 113, 115 and / or 117 (and their associated circuitry) of the embodiment of Fig. 23 also in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

[0132] Fig. Figure 23 shows an embodiment of the system 100 that incorporates a number of features with the Fig. 22 shown embodiment, wherein in Fig. 23, however, the voltage regulator 111-1 may use a low voltage input to enable operation (instead of a high voltage input). According to the embodiment of Fig. 23, switches 113, 115 and 117 are shown as being arranged between bus 106 and ground, as described above with reference to Fig. 22, so that these switches 113, 115 and 117 connect the bus 106 to ground instead of a voltage derived from the power supply 119, as in the Fig. 14 - 21. One or more of the switches 113, 115 and 117 (and their associated circuitry for enabling the bus 106) may, if desired, be removed from the embodiment of Fig. 23 may be omitted. According to the embodiment of Fig. 23, the slave node 104 is also phantom powered (as described above with reference to Fig. 16) and the switches 113, 115 and / or 117 (and their associated circuitry) of the embodiment of Fig. 23 also in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

[0133] When an actuation of a switch disconnects the bus 106 by connecting the bus 106 to a local ground (for example, as described above with reference to the Fig. 22-23), an exemplary enable sequence may be as follows. The master node 102 may begin in a low-power mode in which its associated voltage regulator 111-1 is disabled. A small amount of current may be used to maintain PMOS1 in an enabled state (while the illustrated NMOS FET is disabled). The switch (e.g., switch 113, 115, or 117 according to suitable embodiments) may be closed, thereby shorting bus 106 to ground. The DETECT pin of node transceiver 120-1 may detect the voltage drop on bus 106, and node transceiver 120-1 may generate an interrupt request in response. In response to the interrupt request, host 110 may cause master node 102 to power up and initiate programming of node transceiver 120-1 and discovery of slave nodes 104 on bus 106.Node transceiver 120-1 may assume control of the bias on bus 106 (e.g., through a bus bias switch and line diagnostic functions of node transceiver 120-1). Upon discovery of a slave node 104, slave node 104 may monitor the status of an I / O pin reflecting the state of the switch that initiated the bus enable. When the state of this switch changes (e.g., the switch is opened or closed), slave node 104 may send an interrupt to host 110 or generate a GPIO-to-GPIO transmission of this information over bus 106 to host 110. The particular state of the switch may determine subsequent events (e.g., the master node 102 may return to its low-power mode, the host 110 may perform some predetermined "cleanup" procedures before the bus 106 is disabled, etc.).

[0134] According to some embodiments, the phantom power provided by a bus 106 may itself be used to enable communications along the bus 106. Fig. Figure 24 shows an embodiment of system 100 in which slave node 104 may be phantom powered, and the phantom power itself may be used to initiate a bus release. In particular, bus 106 may be weakly shorted when switch 113 is closed. Master node 102 may provide a small bias to bus 106 during its low-power mode, as discussed below (although no communication may occur over bus 106), and this small bias may be used to send the "wake-up" signal back to master node 102. According to some embodiments, a slave node 104 further down bus 106 (not shown) may detect a remote bus release if its upstream circuitry is configured to do so.One or more of the switches 113, 115 and 117 (and their associated circuitry for enabling the bus 106) may, if desired, be removed from the embodiment of FIG. Fig. 24 may be omitted. According to the embodiment of Fig. 24 (and the Fig. 25 - 26), the resistor R6 can be provided by the on-resistance of the NMOS-FET or another internal resistor. In contrast to the Fig. In the embodiment shown in Figure 17, for example, no separate voltage regulator 111 can be assigned to the switches 113, 115 or 117.

[0135] Switches may be incorporated into any of the embodiments disclosed herein to achieve a desired logic function. For example, Fig. 25 illustrates an embodiment of system 100 wherein four switches 113-1, 113-2, 115, and 117 are included (along with additional resistors RA). Switches 113-1 and 113-2 are arranged such that bus 106 can be enabled by closing switch 113-1 or switch 113-2. According to some embodiments, switches 113-1 and 113-2 (or a different number and arrangement of switches) can be connected to unique I / O pins of node transceiver 120-2, which can trigger various events during operation. According to some embodiments, the two switches 113-1 and 113-2 can be connected to Fig. 25 resistors labeled R5 have the same resistance values. A number of switches may be used in any desired arrangement with any of the embodiments disclosed herein. One or more of the switches 113, 115, and 117 (and their associated circuitry for enabling bus 106) may, if desired, be derived from the embodiment of Fig. 25 may be omitted. According to the embodiment of Fig. 25, the slave node 104 is also phantom powered (as described above with reference to Fig. 16) and the switches 113-1, 113-2, 115 and / or 117 (and their associated circuitry) of the embodiment of Fig. 25 also in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

[0136] As mentioned above, the various methods used in the Fig. 14-25 may be suitably combined with a remote bus enabling functionality in additional embodiments of the system 100. For example, Fig. 26 an embodiment of the system 100, which shows the arrangement of the switches 113-1, 113-2, 115 and 117 of Fig. 25 and the “active-low” arrangement around the voltage regulator 111-1 from Fig. 23. According to the embodiment of Fig. 26, an NMOS FET inside or outside of node transceiver 120-1 can be controlled to turn on during the low-power mode of master node 102 and turn off prior to line diagnostics and discovery. The value of resistor RC and / or resistor R6 can be selected to appropriately set a voltage across node transceiver 120-1.

[0137] If the bias voltage on the bus 106 itself is for a remote bus enable (for example, as described above with reference to the Fig. 24-26), an exemplary enable sequence may be as follows. The host 110 may be in a low-power mode. The master node 102 may be in a low-power mode in which the master node 102 biases the bus 106 (e.g., by controlling the PMOS1 or the SENSE pin) and measures the voltage at the VSSN pin. The voltage at the VSSN pin may be low if none of the remote enable switches are actuated. According to some embodiments, instead of measuring the voltage at the VSSN pin, the master node 102 may measure the voltage change at the SENSE pin or measure the current on the bus 106 (e.g., at the VSSN pin or the SENSE pin). When communication on bus 106 is not enabled, the current on bus 106 may be low (e.g., equal to the quiescent current drawn by one or more slave nodes 104).The switch (e.g., switch 113, 115, or 117 according to suitable embodiments) may be closed, thereby shunting the lines on both sides by high-impedance resistors (R5, R8, or R9, respectively) and increasing the current flow on bus 106 to a predictable value (which may be selected to be different from other current levels that may be detected during line diagnostics). The voltage at the VSSN pin of node transceiver 120-1 may also increase. Node transceiver 120-1 may detect this current or voltage change and signal the event to host 110 (e.g., with an interrupt request sent to host 110 via an IRQ pin). Host 110 may respond by initiating programming of node transceiver 120-1 and the discovery of slave nodes 104 on bus 106.Node transceiver 120-1 may assume control of the bias on bus 106 (e.g., through a bus bias switch and line diagnostic functions of node transceiver 120-1). Upon discovery of a slave node 104, slave node 104 may monitor the status of an I / O pin reflecting the state of the switch that initiated the bus enable. When the state of this switch changes (e.g., the switch is opened or closed), slave node 104 may send an interrupt to host 110 or generate a GPIO-to-GPIO transfer of this information over bus 106 to host 110. The particular state of the switch may determine subsequent events (e.g., the master node 102 may return to its low-power mode, the host 110 may perform some predetermined "cleanup" procedures before the bus 106 is disabled, etc.).

[0138] A “phantom-powered release system” (of the type used in the Fig. 24-26) may be particularly advantageous when the switch is located "close" to the master node 102 (e.g., the next in line along bus 106 or between the first two slave nodes 104 on bus 106). If the switch is located "further" downstream along bus 106, additional components may be included in system 100 so that the actuation of the switch at the master node 102 can be detected.

[0139] As mentioned above, any arrangement of switches may be used in any of the embodiments disclosed herein to achieve remote bus enabling functionality. For example, Fig. 27 illustrates an embodiment of system 100 wherein bus 106 may be enabled by a switch 121 connected between power supply 119 (e.g., a system battery) and the enable input of voltage regulator 111-1. Switch 121 may be used in conjunction with, or in place of, any of the switch arrangements 113, 115, and / or 117 discussed herein. According to the embodiment of Fig. 27, the slave node 104 is also phantom powered (as described above with reference to Fig. 16), and the switch 121 (and its associated circuitry) may also be used in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

[0140] Fig. 28 shows an embodiment of the system 100 that is compatible with the Fig. 27 has a number of common features, with the bus 106 in Fig. 28, however, can be enabled by one or more switches 125 coupled to one or more local batteries 123. According to some embodiments, the system 100 may be Fig. 28 draw less power than the versions from the Fig. 24-26 while the bus 106 is disabled. According to some embodiments, the batteries 123 may be charged during normal active operation of the system 100 by a voltage regulator (not shown) in the node transceiver 120-2 (the output of which is determined by the Fig. 28) with small amounts. The switch 125 may be used in conjunction with or in place of any of the switch arrangements 113, 115, 117, and / or 121 discussed herein. According to the embodiment of Fig. 28, the slave node 104 is also phantom powered (as described above with reference to Fig. 16), and the switch 125 (and its associated circuitry) may also be used in combination with the Fig. 14 and Fig. 15 shown systems 100 (where the slave node 104 is supplied locally).

Claims

[1] Communication system (100) comprising: a master transceiver (102, 120-1) coupled to a downstream connection of a two-wire bus (106), the master transceiver (102, 120-1) being configured to periodically transmit a synchronization control frame on the downstream connection of the two-wire bus (106); a voltage regulator (111) having a voltage output and an enable input, the voltage regulator being coupled to the master transceiver (102, 120-1) via the voltage output, the enable input enabling operation of the voltage regulator in response to a predetermined voltage at the enable input; and a switch (113, 115, 117) coupled to the enable input of the voltage regulator (111). [2] A communication system according to claim 1, further comprising: a slave transceiver (104, 120-2) coupled to the downstream connection of the two-wire bus (106). [3] Communication system according to claim 2, wherein the switch (113, 115, 117) is connected between the downstream connection of the two-wire bus (106) and a second voltage regulator (111-2) associated with the slave transceiver (104, 120-2). [4] The communication system of claim 3, wherein the second voltage regulator (111-2) is configured to provide power to the slave transceiver (104, 120-2). [5] The communication system of claim 3, wherein the second voltage regulator (111-2) is configured not to provide power to the slave transceiver (104, 120-2). [6] Communication system according to one of the preceding claims, further comprising: a second voltage regulator (111-2), a second downstream connection of the two-wire bus (106) located downstream of the slave transceiver (104, 120-2), wherein the switch (113, 115, 117) is connected between the second downstream connection of the two-wire bus (106) and the second voltage regulator (111-2). [7] Communication system according to one of the preceding claims, further comprising: a second voltage regulator (111-2), wherein the switch (113, 115, 117) is connected between the downstream connection of the two-wire bus (106) and the second voltage regulator (111-2). [8] Communication system according to one of the preceding claims, further comprising: a downstream filter circuit arrangement (131) between the master transceiver (102, 120-1) and the downstream connection of the two-wire bus (106) and a diode between the downstream filter circuitry (131) and the enable input of the voltage regulator (111). [9] A communication system according to claim 8, wherein the diode is provided by a PMOS field effect transistor. [10] Communication system according to one of the preceding claims, further comprising: a power supply, wherein an output of the power supply is coupled to the voltage regulator (111) and the switch (113, 115, 117) is connected between the output of the power supply and the downstream connection of the two-wire bus (106). [11] A communication system according to claim 10, wherein the switch (113, 115, 117) is directly coupled to the output of the power supply. [12] A communication system according to any one of the preceding claims, wherein the switch (113, 115, 117) is connected between the ground and the downstream connection of the two-wire bus (106). [13] Communication system according to one of the preceding claims, wherein the downstream connection of the two-wire bus (106) comprises two lines and the switch (113, 115, 117) is connected between the two lines. [14] Communication system according to one of the preceding claims, further comprising: a second switch (113, 115, 117) coupled to the enable input of the voltage regulator (111). [15] Communication system according to one of the preceding claims, further comprising: a rechargeable battery, wherein the rechargeable battery is connected between the switch (113, 115, 117) and the downstream connection of the two-wire bus (106). [16] Communication system according to one of the preceding claims, further comprising: a host (110) coupled to the master transceiver (102, 120-1), the host (110) having an output coupled to the enable input of the voltage regulator (111). [17] The communication system of claim 16, wherein the host (110) is coupled to the master transceiver (102, 120-1) via an inter-integrated circuit (I2C) protocol. [18] Communication system according to one of the preceding claims, wherein the master transceiver (102, 120-1) has an output coupled to the enable input of the voltage regulator (111). [19] A communication system according to any one of the preceding claims, wherein the master transceiver (102, 120-1) is further configured to: Receiving a synchronization response frame from the downstream connection of the two-wire bus (106), wherein the Synchronization response frame originates from a last downstream device on the two-wire bus (106). [20] Communication system with remote release functionality, comprising: a master transceiver (102, 120-1) coupled to a downstream connection of a two-wire bus (106), the master transceiver (102, 120-1) being configured to periodically transmit a synchronization control frame on the downstream connection of the two-wire bus (106); and a switch (113, 115, 117) connected between the downstream connection of the two-wire bus (106) and ground, the switch (113, 115, 117) further coupled to an enable input of a voltage regulator (111), the enable input enabling operation of the voltage regulator (111) in response to a predetermined voltage at the enable input. [21] A communication system according to claim 20, further comprising: a host (110) coupled to the master transceiver (102, 120-1), wherein the master transceiver (102, 120-1) is configured to detect a short circuit between the downstream connection of the two-wire bus (106) and ground and to send an interrupt to the host (110) in response to detecting the short circuit. [22] The communication system of claim 21, wherein the host (110) is configured to initialize the master transceiver (102, 120-1) in response to receiving the interrupt. [23] Method comprising: Entering a low-power mode by a master transceiver (102, 120-1) in a communication system with remote enable functionality, the communication system comprising a two-wire communication bus (106) and the master transceiver (102, 120-1) being configured to periodically transmit a synchronization control frame downstream on the two-wire communication bus (106), Detecting a signal representing an actuation of a switch (113, 115, 117) in the communication system, wherein the switch (113, 115, 117) is remote from the master transceiver (102, 120-1) and is coupled to an enable input of a voltage regulator (111), the enable input enabling operation of the voltage regulator (111) in response to a predetermined voltage at the enable input, and in response to detecting the signal, causing the master transceiver (102, 120-1) to exit the low power mode. [24] A method according to claim 23 or a communication system according to any one of claims 1 to 22, wherein the switch (113, 115, 117) is associated with an emergency button. [25] A method according to any one of claims 23-24 or a communication system according to any one of claims 1 to 22, wherein the communication system is contained in a vehicle.

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