Conversion buffer for decoupling normative and implementation datapath interleaving of video coefficients

Abstract

A computer-implemented method (1400) for video coding, comprising: Receiving (1405) a plurality of blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame for coding in a normative coding order, the normative coding order comprising two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks; Interleaving (1406) the plurality of blocks of quantized residual transform coefficients from the normative encoding order into a processing order (422), the processing order (422) comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks; and performing (1407) inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order (422) to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients.

Description

GENERAL STATE OF THE ART

[0001] In compression / decompression (codec) systems, compression efficiency, video quality, and computational efficiency are important performance criteria. It is also advantageous for bitstreams or other data representations of encoded videos based on the H.264 / MPEG-4 Advanced Video Coding (AVC) standard, the High Efficiency Video Coding (HEVC) standard, the VP9 coding standard, the Alliance for Open Media (AOM) standard, the MPEG-4 standards, and their extensions.

[0002] Therefore, it can be advantageous to increase the computational efficiency of encoders and decoders while maintaining standards based on bitstreams or other data representations of encoded video data. These and other considerations necessitated the need for these improvements. Such improvements could become critical as the desire to compress and transmit video data becomes more common.

[0003] In US 2014 / 0169479 A1, an image processing apparatus capable of reducing the capacity of a storage element includes: a first variable-length decoding unit that sequentially outputs, for each first processing unit, one or more components included in the first processing unit by performing a first process on an encoded stream; a reordering unit that sequentially outputs, for each second processing unit different from the first processing unit, one or more components included in the second processing unit by reordering the components output from the first variable-length decoding unit; and a second inverse quantization unit that performs a second process on the components output from the reordering unit for each second processing unit.US 2013 / 0301712 A1 describes systems and methods for interleaving video sub-blocks in video coding. In one aspect, an apparatus comprises a memory and a video encoder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video encoder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video encoder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.

[0004] US 2012 / 0027087 discloses an image decoding apparatus for processing an input bitstream containing coded data obtained by encoding a moving image using intraframe prediction, comprising a stream divider configured to divide the input bitstream into a plurality of substreams, and a plurality of image decoders each configured to decode the corresponding substream from the plurality of substreams, thereby outputting images. The stream divider divides the input bitstream so that the plurality of substreams each contain the coded data corresponding to one or more prediction units, wherein macroblocks of the moving image each contain a plurality of the prediction units for the intraframe prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The material described herein is illustrated in the accompanying figures by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where deemed appropriate, reference designations have been repeated among the figures to indicate corresponding or analogous elements. In the figures: Fig. 1 is an illustration of an exemplary prediction unit and corresponding transformer units; Fig. Figure 2 is an illustration of example intra-prediction loop dependencies; Fig. 3 is an illustration of exemplary transformer unit pipeline processing; Fig. Figure 4 is an illustration of an example encoder; Fig. 5 is an illustration of an example encoder conversion buffer; Fig. 6 is an illustration of an exemplary decoder; Fig. 7 is an illustration of an exemplary decoder conversion buffer; Fig. Figure 8 is an illustration of exemplary processing sequences including color interleaving; Fig. Figure 9 is an illustration of exemplary processing sequences including color interleaving; Fig. 10A to 10C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide a coding order; Fig. 11A and Fig. 11B illustrates an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order; Fig. 12A to 12C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order; Fig. 13A to 13C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order; Fig. 14 is a flowchart providing an exemplary process for video encoding, including interleaving transformer blocks by color into a processing order; Fig. 15 is an illustrative diagram of an exemplary system for video coding, including interleaving transformer blocks by color into a processing order; Fig. 16 is an illustrative diagram of an exemplary system; and Fig. 17 illustrates an exemplary device fully arranged according to at least some implementations of the present disclosure. DETAILED DESCRIPTION

[0006] One or more embodiments or implementations will now be described with reference to the accompanying figures. While specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the art that techniques and / or arrangements described herein may also be employed in a variety of systems and applications other than those described herein.

[0007] While the following description specifies various implementations that may be manifested in architectures such as system-on-a-chip (SoC) architectures, the implementations of the techniques and / or arrangements described herein are not limited to any particular architecture and / or computing system and may be implemented by any architecture and / or computing system for similar purposes. For example, various architectures including, for example, multiple integrated circuit (IC) chips and / or packages, and / or various computing devices and / or consumer electronics (CE) devices such as set-top boxes, smartphones, etc., may implement the techniques and / or arrangements described herein. Furthermore, while the following description may specify numerous specific details such as logic implementations, types and relationships between system components, logic partitioning / integration decisions, etc.may specify, the claimed content may be practiced without these specific details. In other cases, some material, such as control structures and full software instruction sequences, may not be shown in detail in order not to obscure the material disclosed herein.

[0008] The material disclosed herein may be implemented in hardware, firmware, software, or a combination thereof. The material disclosed herein may also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any medium and / or mechanism for storing or transmitting information in a form that is readable by a machine (e.g., by a computing device). For example, a machine-readable medium may include, but is not limited to, read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; or electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), among others.

[0009] References in this specification to "an implementation," "an example implementation," etc., indicate that the described implementation may include a particular feature, structure, or property, but not every implementation necessarily includes the particular feature, structure, or property. Furthermore, such terms do not necessarily refer to the same implementation. Furthermore, where a particular feature, structure, or property is described in connection with an embodiment, it is understood that it is within the scope of one skilled in the art to use those features, structures, or properties in connection with other implementations, whether or not expressly described herein.

[0010] Methods, devices, apparatus, computing platforms, and articles are described herein with reference to video coding, and in particular, decoupling a normative data path or sequence from a processing data path or sequence for improved throughput.

[0011] The discussed techniques and systems can provide a conversion buffer to decouple normative and implementation datapath interleaving of the video codec coefficients and interleaving technique schemes to be used in conjunction with such a conversion buffer to improve the throughput of an encoder and / or decoder. For example, the conversion buffer and associated techniques can decouple how coefficients of the various colors are interleaved in the actual bitstream of the video codecs from the interleaving of the same coefficients in the implementation of such video codecs. The discussed techniques can be used in any suitable coding context, such as in implementations of codecs based on H.264 / MPEG-4 Advanced Video Coding (AVC) standards, High Efficiency Video Coding (H.265 / HEVC) standards-based codecs, Alliance for Open Media (AOM) standards-based codecs such as the AVI standard, MPEG standards-based codecs such as the MPEG-4 standard, VP9 standards-based codecs, or any other suitable codec or extension or profile thereof implemented via an encoder or decoder.

[0012] As discussed further herein, one or more buffers may be provided in the implementation of one or more video codecs such that the order in which the coefficients of different colors are interleaved in the actual bitstream of the video codec(s) may differ from the interleaving of the same coefficients in sections of the pipeline processing the video codec(s). The different order in the processing pipeline provides improved video throughput and performance while generating or processing one or more bitstreams that conform to the specifications for the video codec(s). Therefore, the techniques discussed improve throughput and performance while generating or processing standards-based bitstreams that do not require normative changes.

[0013] For example, a conversion buffer can be implemented to change the order in which the luma (Y) and chroma (Cb and Cr or U and V) coefficients are interleaved to reduce the impact of intra-prediction loop delay and increase the throughput of reconstructed pixel processing. The following explanation applies to intra-prediction in the pixel domain (e.g., as in HEVC and its extensions and profiles, VP9 and its extensions and profiles, AV1 and its extensions and profiles). However, the following techniques and systems can also be applied to codecs where intra-prediction occurs in the transform domain (e.g., MPEG-4 Part 1). Furthermore, the techniques can be provided with an encoder and / or decoder to improve throughput and efficiency.

[0014] Fig. 1 is an illustration of an exemplary prediction unit 101 and corresponding transformer units arranged according to at least some implementations of the present disclosure. As shown in Fig. 1, the prediction unit (PU) 101 may include four corresponding luma transformer units (TUs) 111, 112, 113, 114 and two corresponding chroma transformer units 121, 122. In the illustrated example, the prediction unit 101 is a square block corresponding to four square luma transformer units 111, 112, 113, 114 (denoted Y0, Y1, Y2, Y3) and two square chroma transformer units 121, 122 (denoted Cb, Cr). Such an example may correspond to 4:2:0 color sampling in the Y-Cb-Cr color space. However, the prediction unit 101 may have any suitable shape, such as rectangular, and any suitable size. Furthermore, the prediction unit 101 may include any number of corresponding luma transformer units and chroma transformer units of any suitable size. The techniques discussed herein can be applied to any color sampling structure such as 4:2:2 color sampling or 4:4:4 color sampling.Examples of such structures are discussed further herein. Furthermore, any suitable color space may be used, such as a YUV color space. Hereinafter, Y-Cb-Cr and YUV color spaces are used interchangeably. The terms prediction unit and transformer unit are used herein. Such units of pixel samples, residual samples, transform coefficients, or the like may be characterized as blocks or the like. In codec systems, intrapredictions may be performed across transformer units, so that a transformer unit represents samples processed by a frequency-domain transformation.

[0015] Fig. 2 is an illustration of exemplary intra-prediction loop dependencies arranged according to at least some implementations of the present disclosure. As in Fig. 2 with respect to the prediction unit 101, intra-prediction loop dependencies 201 exist between transformer units of the prediction unit 101, such that reconstructed samples of the transformer unit Y0 are used in the intra-prediction reconstruction of the transformer units Y1 and Y2, and the reconstructed samples of transformer units Y0, Y1, and Y2 are used in the intra-prediction reconstruction of the transformer unit Y3. Furthermore, the reconstruction of the prediction unit 101 is supported by the previously reconstructed pixels 202, 203, 204. Such intra-prediction loop dependencies 201 require that, before processing a dependent transformer unit, the prediction reconstruction of the transformer unit(s) on which the dependent transformer unit depends must be processed beforehand.

[0016] With reference to Fig. 1, the normative or standards-based order of quantized transform coefficients of transformer units for prediction unit 101 is as follows: Y0-Y1-Y2-Y3-Cb-Cr. When processed in this order, the reconstruction of transformer units 121, 122 (Cb and Cr samples) must wait until all luma transformer units 111, 112, 113, 114 (Y0, Y1, Y2, Y3) have been processed, resulting in a delay. Furthermore, the smaller the transformer unit, the longer the idle time.

[0017] Fig. 3 is an illustration of an exemplary transformer unit pipeline processing 300 arranged according to at least some implementations of the present disclosure. Fig. Figure 3 provides an illustration of inserting chroma processing between luma processing, as discussed further herein. As in Fig. 3, a first sample 311 of the luma transformer unit 111 (Y0) may be inserted into stage A of a first pipeline 301 of the pipeline processing 300. Thereafter, a final luma sample 312 of the transformer unit 111 (Y0) may be inserted into stage A of a second pipeline 302, and a chroma sample 321 (Cb) may be inserted into stage A of the first pipeline 301, since the first sample 311 is located in stage B of the first pipeline 301. Furthermore, although not shown, chroma sample 322 (Cr) of a second color channel may be inserted into stage A of the second pipeline 302 since the first luma sample 311 is in stage C of the first pipeline 301, the chroma sample 321 is in stage B of the first pipeline 301, and the last luma sample 312 is in stage B of the second pipeline 302.As shown, during further processing, chroma sample 322 is in stage Y of the second pipeline 302, the first luma sample 311 is in stage Z of the first pipeline 301, the chroma sample 321 is in stage Y of the first pipeline 301, and the last luma sample 312 is in stage Z of the second pipeline 302. At the next processing stage, the first luma sample 311 has completed processing, and another sample from a subsequent luma sample can be introduced. As shown, during the idle time 311, processing of at least chroma samples 321, 322 can be provided to increase throughput.

[0018] Fig. 4 is an illustration of an exemplary encoder 400 arranged according to at least some implementations of the present disclosure. As in Fig. As shown in Figure 4, encoder 400 may include a residue generation module 401, a forward transformation and quantification module 402, an inverse transformation and quantification module 403, an intra-prediction module 404, an encoder conversion buffer 405, and an entropy encoder 406. The residue generation module 401, forward transformation and quantification module 402, inverse transformation and quantification module 403, and the intra-prediction module 404 may be labeled as an intra-prediction loop 409 or the like.

[0019] As illustrated, encoder 400 may receive source video (YUV) 411 for encoding and provide an encoded bitstream 413 of encoded video data. Source video 411 may be in any suitable format, such as YUV or YCbCr, or the like, and may have any suitable resolution, bit depth, etc. Encoded bitstream 413 may include any suitable data format. For example, encoded bitstream 413 may be a standards-compliant bitstream conforming to any standard discussed herein. Residual generation module 401 may differentiate source video 411, or portions thereof, and intra-prediction signal 412 to provide prediction residuals for intra-coded prediction units.The intra-coded prediction unit residuals are forward-transformed and forward-quantized by the forward transform and quantization module 402 to obtain quantized transform coefficients, which can be inverse-quantized and inverse-transformed by the inverse transform and quantization module 403 to generate the reconstructed prediction residuals. The reconstructed prediction residuals are combined with corresponding prediction data (e.g., using the intra-prediction based on previously decoded pixel samples) by the intra-prediction module 404 to generate the intra-prediction signal 412. This processing can be repeated for any number of prediction units or coding units, or the like, of the video frames of the source video 411.

[0020] Furthermore, the discussed forward transformations, forward quantization, inverse quantization, and inverse transformation processing can be performed on transformer units in such a way that the transformer units can be subunits of a prediction unit (or a transformer unit can be an entire prediction unit). As in Fig. 4, an exemplary prediction unit 421 processed by an intra-prediction loop 409 may be in a processing order 422. The processing order 422 may also be characterized as an intra-processing order, a hardware pipeline order, internal color interleaving, or the like. As illustrated, the processing order 422 includes transformer units (labeled Y0, U0, V0, Y1, U1, V1) along with a header (H) in an interleaved order for more efficient processing by the intra-prediction loop 409. For example, in an intra-prediction loop 409, color coefficients on a transform color unit are interleaved with the transform color unit color basis (e.g., based on TU.Color by TU.Color) so that the transform color unit is used for intra-prediction by the components of the intra-prediction loop 409.The example of processing sequence 422 represents a prediction unit 421 comprising two transformer units of equal size: TU0 and TU1. Furthermore, each transformer unit comprises three color coefficient blocks: TU.Y, TU.U, and TU.V. For example, prediction unit 421 may be a rectangular prediction unit comprising two square transformer units implemented with 4:4:4 color sampling.

[0021] As also illustrated, the encoder conversion buffer 405 may be implemented to change the order of transformer units of the prediction unit 421 into a normative encoding order 423. For example, the encoder conversion buffer 405 decouples how coefficients of different colors are interleaved in a standards-compliant bitstream (encoded bitstream 413) from interleaving the same coefficients in a conversion (processing order 422). In one embodiment, the encoder conversion buffer 405 translates coefficients of transformer units from an internal color interleaving (processing order 422) to an external color interleaving (normative encoding order 423). The normative encoding order 423 may also be characterized as a standards-based order, output encoding order, external color interleaving, or the like.For example, the entropy encoder 406 may process the prediction unit 421 to generate a standards-compliant encoded bitstream 413 in which the prediction units are represented in the normative encoding order 423. The entropy encoder 406 may generate the encoded bitstream 413 using one or more suitable techniques. For example, the entropy encoder 406 may use samples-to-bin / bit processing such as multilevel or binary entropy / arithmetic coding or the like. The techniques discussed herein may provide for performing such entropy coding using standards or normatively based techniques by providing the prediction unit 421 in the normative encoding order 423 to generate a standards-compliant encoded bitstream 413.

[0022] As illustrated, the processing order 422 may be provided in the following order: Header (H) - TU0.Y (Y0) - TU0.U (U0) - TU0.V (V0) - TU1.Y (Y1) - TU1.U (U1) - TU1.V (V1), and the normative encoding order 423 may be provided as Header (H) - TU0.Y (Y0) - TU1.Y (Y1) - TU0.U (U0) - TU1.U (U1) - TU0.V (V0) - TU1.V (V1). Example processing orders are described in more detail below. As can be seen, the normative coding order 423 and the processing order 422 differ in how the coefficient units or blocks are interleaved so that the processing by the intra-prediction loop 409 can be performed more efficiently.

[0023] As discussed, processing order 422 can reduce the processing time required to process prediction unit 421 by eliminating delays relative to processing in normative coding order 423. For example, processing U0 immediately after Y0 can reduce the delay because U0 does not wait for Y1 to complete (which, in turn, may have to wait for Y0). Similarly, processing V0 immediately after U0 can reduce the delay because V0 does not wait for Y1 to complete.

[0024] Fig. 5 is an illustration of an exemplary encoder conversion buffer 405 arranged according to at least some implementations of the present disclosure. As in Fig. 5, the encoder conversion buffer 405 may receive transformer units of the prediction unit 421 in the processing order 422 (TU0.Y, TU0.U, TU0.V, TU1.Y, TU1.U, TU1.V) and retrieve transformer units of the prediction unit 421 in the normative encoding order 423 (TU0.Y, TU1.Y, TU0.U, TU1.U, TU0.V, TU1.V). For example, a processor (not shown) such as a central processor or a video processor or the like may store blocks of quantized residual transform coefficients corresponding to the transformer units of the prediction unit 421 in the processing order 422 (or another processing order discussed herein), and the processor or another processor may retrieve the blocks of quantized residual transform coefficients corresponding to the transformer units of the prediction unit 421 in the normative encoding order 423.

[0025] As discussed, encoder conversion buffer 405 can be used to convert from TU-level color interleaving to PU-level color interleaving on a PU by PU basis. Encoder conversion buffer 405 can store the input TU color blocks by color in the input sequence. Further, encoder conversion buffer 405 can store and / or track the transform units in a prediction unit and the transform color units in a transform unit. For example, encoder conversion buffer 405 can detect that all transform units of a prediction unit are received and output all transform luma units (e.g., all transform unit luma blocks), followed by all transform U units (e.g., all transform unit U or Cb blocks), followed by all transform V units (e.g., all transform unit V or Cr blocks).

[0026] Fig. 6 is an illustration of an exemplary decoder 600 arranged according to at least some implementations of the present disclosure. As in Fig. 6, decoder 600 may include an entropy decoder 606, a decoder conversion buffer 605, an inverse transform and quantization module 603, an intra-prediction module 604, and a reconstruction module 601. As illustrated, decoder 600 may include an encoded bitstream 613 for decoding and may provide reconstructed video (YUV) 611 for storage or display, or the like. Encoded bitstream 613 may include any suitable data format. For example, encoded bitstream 613 may be a standards-compliant bitstream conforming to any standard discussed herein.

[0027] As illustrated, entropy decoder 606 may receive encoded bitstream 613 and process encoded bitstream 613 to generate prediction unit 621, which includes transformer unit data in a normative encoding order 623. For example, entropy decoder 606 may decode encoded bitstream 613 to generate prediction unit 621. Entropy decoder 606 may decode encoded bitstream 613 using one or more suitable techniques for generating prediction unit 621. The techniques discussed herein for decoder conversion buffer 605 may not affect the processing of entropy decoder 606. For example, the entropy decoder may provide bin / bit-to-sample processing or the like.In one embodiment, the prediction unit 621 may provide transformed and quantized residual coefficients for transformer units such that the transformer units are in the normative encoding order 623. Analogous to the example of . Fig. 4 and Fig. 5, the example processing sequence 624 illustrates a prediction unit 621 comprising two transformer units of equal size: TU0 and TU1. Furthermore, each transformer unit comprises three color coefficient blocks: TU.Y, TU.U, and TU.V. For example, prediction unit 421 may be a rectangular prediction unit comprising two square transformer units implemented with 4:4:4 color sampling.

[0028] As also illustrated, the decoder conversion buffer 605 may be implemented to change the order of transformer units of the prediction unit 621 into a processing order 622. For example, as discussed with respect to the encoder conversion buffer 405, the decoder conversion buffer 605 decouples how coefficients of different colors are interleaved in a standards-compliant bitstream (encoded bitstream 613) from an interleaving of the same coefficients in a conversion (processing order 622). The decoder conversion buffer 605 may translate coefficients of transformer units from an internal color interleaving (processing order 622) to an external color interleaving (normative encoding order 623). The normative encoding order 623 may also be characterized as a standards-based order, output encoding order, external color interleaving, or the like.As illustrated, a normative coding order 623 may be provided as Header (H) - TU0.Y (Y0) - TU1.Y (Y1) - TU0.U (U0) - TU1.U (U1) - TU0.V (V0) - TU1.V (V1), and the processing order 622 may be provided as Header (H) - TU0.Y (Y0) - TU0.U (U0) - TU0.V (V0) - TU1.Y (Y1) - TU1.U (U1) - TU1.V (V1). Example processing orders are described in more detail below. As can be seen, the normative coding order 623 and the processing order 622 differ in how the coefficient units or blocks are interleaved so that processing by the decoders 600 can be performed more efficiently.

[0029] When processing a prediction unit in processing sequence 622, quantized transform coefficients of transform units of prediction unit 621 may be inversely quantized and inversely transformed by inverse transform and quantization module 603 to generate reconstructed prediction residuals for the transform units. The reconstructed prediction residuals are combined with corresponding prediction data (e.g., using the intraprediction based on previously decoded pixel samples) by intraprediction module 604 to generate intraprediction signal 612. These intrapredicted prediction units may be processed by reconstruction module 601 to generate output frames or images of reconstructed video 611, which may be stored, displayed, or the like.

[0030] Fig. 7 is an illustration of an exemplary decoder conversion buffer 605 arranged according to at least some implementations of the present disclosure. As in Fig. 7, the decoder conversion buffer may receive transformer units of the prediction unit 621 in the normative encoding order 623 (TU0.Y, TU1.Y, TU0.U, TU1.U, TU0.V, TU1.V), and transformer units of the prediction unit 621 may be retrieved in the processing order 622 (TU0.Y, TU0.U, TU0.V, TU1.Y, TU1.U, TU1.V). For example, a processor (not shown), such as a central processor or a video processor or the like, may store blocks of quantized residual transform coefficients corresponding to transformer units of the prediction unit 621 in the normative encoding order 623 (or other processing order discussed herein), and the processor or another processor may retrieve the blocks of quantized residual transform coefficients corresponding to transformer units of the prediction unit 621 in the processing order 622.As discussed, decoder conversion buffer 605 can be used to convert from PU-level color interleaving based on PU by PU to TU-level color interleaving. Decoder conversion buffer 605 can provide the reverse of the conversion described with respect to encoder conversion buffer 405, converting from PU-level color interleaving to internal color interleaving. In one embodiment, decoder conversion buffer 605 stores incoming TU color blocks by color, and once all TU color blocks of a TU have been received, decoder conversion buffer 605 can provide these blocks in the order Y, followed by U and V, or another processing order as discussed herein.

[0031] As discussed, encoder 400 may implement an encoder conversion buffer 405, and decoder 600 may implement a corresponding decoder conversion buffer 605 to translate between the normative encoding orders and processing orders for the transformer units of a prediction unit. The processing orders discussed herein may interleave Y and Cb / Cr on a per-transformer-unit basis, such that a transformer unit represents a block (e.g., a square block) of samples processed by a transform. Because intra-prediction reconstruction is performed across the boundaries of the transformer unit, such interleaving may allow intra-prediction reconstruction of Y, Cb, and Cr samples in parallel, reducing intra-prediction loop delay. Such color interleaving schemes are discussed below for use with the discussed encoder and decoder conversion buffers.Such color interleaving techniques can reduce intra-prediction throughput and increase processing efficiency.

[0032] Fig. 8 is an illustration of example processing sequences including color interleaving according to at least some implementations of the present disclosure. Fig. 8 illustrates example processing sequences 801, 802, 803, each for a prediction unit 800 having four luma transformer units (Y0, Y1, Y2, Y3), two chroma channel one transformer units (U0, U1), and two chroma channel two transformer units (V0, V1). As used herein, the terms chroma channel one and chroma channel two refer to first and second chroma channels, such as channels U and V, channels Cb and Cr, or the like. The illustrated example may provide transformer units for 4:2:2 color sampling. The illustrated transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Furthermore, as discussed herein, the illustrated transformer units may have a normative coding order or standards-based coding order or the like in the following order: Y0, Y1, Y2, Y3, U0, U1, V0, V1.

[0033] In one embodiment, the processing order 801 for the prediction unit 800 may be provided with the processing order that follows the normative encoding order, such that the transformer units of the prediction unit 800 pack all luma transformer units (e.g., Y0, Y1, Y2, Y3), then all chroma channel one transformer units (e.g., U0, U1), then all chroma channel two transformer units (e.g., V0, V1).

[0034] As illustrated, in one embodiment, the processing order 802 for the prediction unit 800 may be provided by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units. For example, the processing order 802 may sort the transformer units with a first luma transformer unit directly followed by a first chroma channel one transformer unit, which in turn is directly followed by a first chroma channel two transformer unit (e.g., Y0, U0, V0). As used herein, the term directly followed or similar terms is intended to indicate that there are no intermediate units between the units in the order.Consecutive groups of a subsequent luma transformer unit, immediately followed by a subsequent chroma channel one transformer unit, immediately followed by a subsequent chroma channel two transformer unit, may also be provided until, in this example, the chroma transformer units run out. Then, the remaining luma transformer units may be packed into processing order 802. For example, as shown, processing order 802 provides a subset Y0, U0, V0, followed by a continuous subset of Y1, U1, V1 that exhausts all chroma transformer units, and then the remaining luma transformer units: Y2, Y3.

[0035] In one embodiment, the processing order 803 for the prediction unit 800 may be provided by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, a luma transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units or all available chroma transformer units. For example, the processing order 803 may sort the transformer units with a first luma transformer unit directly followed by a first chroma channel one transformer unit, which in turn is directly followed by a second luma transformer unit, which in turn is directly followed by a first chroma channel two transformer unit (e.g., Y0, U0, Y1, V0).Consecutive groups of a subsequent luma transformer unit, immediately followed by a subsequent chroma channel one transformer unit, immediately followed by another subsequent luma transformer unit, immediately followed by a subsequent chroma channel two transformer unit, may also be provided until, in this example, the chroma transformer units run out. Then, the remaining luma transformer units may be packed into processing order 803. For example, as shown, processing order 803 provides a subset of Y0, U0, Y1, V0, followed by a continuous subset of Y2, U1, Y3, V1 that consumes all transformer units.

[0036] In the examples from Fig. 8, the processing sequences 801, 802, 803 do not change the processing sequence of the luma transformer units with respect to the normative coding sequence of these transformer units used in multiple video codecs. Further illustrated Fig. 8 the importance of the processing sequences 802, 803 with respect to the processing sequence 801 in terms of throughput, since processing delays caused by waiting for the luma transformer units Y0, Y1, Y2, Y3 to complete processing in the processing sequence 801 are used to process chroma channel one and two transformer units, thus saving overall processing time.

[0037] Fig. 9 is an illustration of example processing sequences including color interleaving according to at least some implementations of the present disclosure. Fig. 9 illustrates example processing orders 901, 902, 903, each for a prediction unit 00 having four luma transformer units (Y0, Y1, Y2, Y3), two chroma channel one transformer units (U0, U1), and two chroma channel two transformer units (V0, V1). The illustrated example may provide transformer units for 4:2:0 color sampling. The illustrated transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Furthermore, as discussed herein, the illustrated transformer units may have a normative encoding order or standards-based encoding order or the like in the following order: Y0, Y1, Y2, Y3, U0, V0.

[0038] In one embodiment, the processing order 901 for the prediction unit 900 may be provided with the processing order that follows the normative encoding order, such that the transformer units of the prediction unit 900 pack all luma transformer units (e.g., Y0, Y1, Y2, Y3), then all chroma channel one transformer units (e.g., U0), then all chroma channel two transformer units (e.g., V0).

[0039] In another embodiment, the processing order 902 may be provided to the prediction unit 900 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units. This sorting follows a similar packing technique as explained with respect to processing order 802. For example, the processing order 902 may sort the transformer units with a first luma transformer unit immediately followed by a first chroma channel one transformer unit, which in turn is immediately followed by a first chroma channel two transformer unit (e.g., Y0, U0, V0).Consecutive groups of a subsequent luma transformer unit, immediately followed by a subsequent chroma channel one transformer unit, immediately followed by a subsequent chroma channel two transformer unit, may also be provided. However, in this example, the chroma transformer units run out after the first grouping. Subsequently, the remaining luma transformer units may be packed into processing order 902. For example, as shown, processing order 902 provides a subgroup Y0, U0, V0 that exhausts all chroma transformer units, followed by the remaining luma transformer units: Y1, Y2, Y3.

[0040] In one embodiment, processing order 903 may be provided to prediction unit 900 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, a luma transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units or all available chroma transformer units. This sorting follows a similar packing technique as explained with respect to processing order 803. For example, processing order 903 may sort the transformer units with a first luma transformer unit directly followed by a first chroma channel one transformer unit, which in turn is directly followed by a second luma transformer unit, which in turn is directly followed by a first chroma channel two transformer unit (e.g., Y0, U0, Y1, V0).Consecutive groups of a subsequent luma transformer unit, immediately followed by a subsequent chroma channel one transformer unit, immediately followed by another subsequent luma transformer unit, immediately followed by a subsequent chroma channel two transformer unit, may also be provided. However, in this example, the chroma transformer units after the first subgroup run out of Y0, U0, Y1, V1. Subsequently, the remaining luma transformer units may be packed into processing order 903. For example, as shown, processing order 903 provides a subgroup Y0, U0, V0 that exhausts all chroma transformer units, and then the remaining luma transformer units: Y2, Y3.

[0041] As with the examples from Fig. 8 change the examples from Fig. 9 does not illustrate the processing order of the luma transformer units with respect to the normative coding order used in several video codecs. Fig. 9 again illustrates the importance of processing sequences 902, 903 relative to processing sequence 901 in terms of throughput, since processing delays caused by waiting for luma transformer units Y0, Y1, Y2, Y3 to complete processing in processing sequence 901 are used to process chroma channel one and two transformer units, thus saving overall processing time.

[0042] As explained, the examples from Fig. 8 with 4:2:2 color sampling and the examples from Fig. 9 with 4:2:0 color sampling. In the context of 4:4:4 color sampling, the techniques discussed for transformer unit packing can be used. For example, the techniques discussed with respect to processing orders 802, 902 can be used to interleave a normative encoding order of Y0, Y1, Y2, Y3, U0, U1, U2, U3, V0, V1, V2, V3 into a processing encoding order of Y0, U0, V0, Y1, U1, V1, Y2, U2, V2, Y3, U3, V3 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available.Furthermore, the techniques discussed with respect to the processing orders 803, 903 can be used to interleave a normative encoding order of Y0, Y1, Y2, Y3, U0, U1, U2, U3, V0, V1, V2, V3 into a processing encoding order of Y0, U0, Y1, V0, Y2, U1, Y3, U1, U2, V2, U3, V3 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit until one of these transformer units is used up, and then packing all available luma transformer units or other available chroma transformer units.

[0043] In addition, as explained, the examples from Fig. 8 and Fig. 9, the processing order of the luma transformer units is not related to the normative encoding order of such luma transformer units. In other examples, the processing order of the luma transformer units may be changed.

[0044] Fig. 10A to 10C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order arranged according to at least some implementations of the present disclosure. For example, the processing order may be Fig. 10A to 10C should be compatible with intra-prediction modes that do not use upper-right samples. As described in Fig. 10A, an example prediction unit 1000 may include 16 transformer units (Y0-Y15), four chroma channel one transformer units (U0-U4), and four chroma channel two transformer units (V0-V4). The illustrated example may provide transformer units for 4:2:0 color sampling. The illustrated transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Further, as discussed herein, the illustrated transformer units may have a normative encoding order or standards-based encoding order, or the like, in the following order: Y0-Y15, U0-U4, V0-V4.

[0045] In addition, as in Fig. 10A, luma transformer units of prediction unit 1000 are scanned in a wavefront order to provide a propagation order 1001. For example, luma transformer units of prediction unit 1000 may be scanned in the following order. A first wave may scan from an upper left transformer unit (Y0) to the right and then down to a lower right transformer unit (Y15), such that the first scan reaches the following luma transformer units in the order: Y0, Y1, Y2, Y3, Y7, Y11, Y15, as shown in wave 1 (W1) of propagation order 1001.A second wave can again scan the remaining transformer units from an (available) upper left transformer unit (Y4) to the right and then down to a lower right transformer unit (Y14), so that the second scan reaches the following luma transformer units in the order: Y4, Y5, Y6, Y10, Y14, as shown in wave 1 (W1). Third and fourth waves can again scan the remaining transformer units from an (available) upper left transformer unit (Y8) to the right and then down to a lower right transformer unit (Y13), so that the third scan reaches the following luma transformer units in the order: Y8, Y9, Y13 and then the last available transformer unit (Y12), so that the fourth scan reaches the Y12 luma transformer unit.

[0046] As in Fig. 10B, luma transformer units of prediction unit 1000 in propagation order 1001 may then be translated to a luma processing order 1002 such that luma processing order 1002 provides a time order for processing as discussed herein with provided time gaps, such as time gap 1011, to satisfy neighbor dependencies. For example, luma processing order 1002 may be generated from propagation order 1001 by scanning propagation order 1001 starting at the left side of propagation order 1001, then scanning each column vertically from top to bottom, moving from left to right to the next column (along a row), scanning the column vertically, and so on.For example, a scan of the first column may provide luma transformer unit Y0, the scan of the second column may provide luma transformer units Y1, Y4, the scan of the third column may provide luma transformer units Y2, Y5, Y8, and so on, as shown in luma processing order 1002. This wavefront scanning, followed by column-wise scanning of the luma transformer units, may provide sorting that does not violate the dependencies between the luma transformer units based on the intra-prediction modes that upper-right samples do not use. Furthermore, as shown in . Fig. 10B, chroma channel one transformer units may be provided in a chroma channel one transformer unit order 1003 that corresponds to the normative encoding order. Similarly, chroma channel two transformer units may be provided in a chroma channel two transformer unit order 1004 that corresponds to the normative encoding order.

[0047] The processing carried out with regard to Fig. 10A and Fig. 10B to generate the luma processing order 1002 can be generated by performing multiple spatially downward-left oriented scans, each starting at a subsequent luma transformer unit of the wavefront of the transformer units including Y0, Y1, Y2, Y3, Y7, Y11, Y15. For example, a first downward-left oriented scan can start in luma transformer unit Y0 and reach only luma transformer unit Y0. A second downward-left oriented scan can start in luma transformer unit Y1 (e.g., the transformer unit in the top row and directly to the left of the previously starting luma transformer unit) and can reach luma transformer units Y1, Y4 by scanning downward-left. Similarly, a third downward-left oriented scan can start in luma transformer unit Y2 (e.g.,The transformer unit in the top row and directly to the left of the previously starting luma transformer unit Y1) and can reach luma transformer units Y2, Y5, and Y8 by scanning downwards to the left. A similar fourth scan can reach luma transformer units Y3, Y6, Y9, and Y12. The scan starting luma transformer unit can now move downwards in wavefront sequence to luma transformer unit Y7, and the fifth scan oriented downwards to the left can reach luma transformer units Y7, Y10, and Y13. Similarly, the sixth and seventh scans can reach luma transformer units Y11, Y14, and Y15, respectively.

[0048] Now, with a view to Fig. 10C, a processing order 1005 for the transformer units of the prediction unit 1000 is provided based on the techniques discussed with respect to the processing orders 802, 902. For example, the processing order 1005 may be formed by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units. In the discussed context, this sorting may provide the processing order 1005 as follows: Y0, U0, V0, Y1, U1, V1, Y4, U2, V2, Y2, U3, V3, Y5, Y8, Y3, Y6, Y9, Y12, Y7, Y10, Y13, Y11, Y14, Y15. Fig. 10C also illustrates a translation from processing order 1005 to normative encoding order 1006, which occurs in the order discussed above: Y0-Y15, U0-U3, V0-V3. As can be seen, performing intra-prediction in processing order 1005 results in less idle time and more efficient processing. As discussed, this processing order 1005 may be used at one or both of the encoder and decoder elements, based on the implementation of an encoding buffer as discussed herein. For example, the transformer units or blocks in processing order 1005 may be input to an encoder conversion buffer 405 (after intra-processing) and retrieved from the encoder conversion buffer 405 in normative encoding order 1006 for entropy encoding in a standards-compliant bitstream.Similarly, transformer units or blocks may be input to the decoder conversion buffer 605 in the normative encoding order 1006 (after entropy decoding) and retrieved from the decoder conversion buffer 605 in the processing order 1005 for intraprocessing as discussed herein.

[0049] In another embodiment, an encoding order may be generated based on the techniques discussed with respect to processing orders 803, 903. For example, a processing order may be formed by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, a luma transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units or all available chroma transformer units. In the context discussed, this sorting may provide an encoding order as follows: Y0, U0, Y1, V0, Y4, U1, Y2, V1, Y5, U2, Y8, V2, Y3, U3, Y6, V3, Y9, Y12, Y7, Y10, Y13, Y11, Y14, Y15.

[0050] Fig. 11A and Fig. 11B illustrates an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order arranged according to at least some implementations of the present disclosure. For example, the processing order may be Fig. 11A and Fig. 11B should be compatible with intra-prediction modes that do not use upper-right samples and provide an example of 4:4:4 color sampling. With reference to Fig. 10A, an exemplary prediction unit may include 16 transformer units (Y0-Y15). Further, for 4:4:4 color sampling, the prediction unit may include the 16 chroma channel one transformer units (U0-U15) and 16 chroma channel two transformer units (V0-V15) arranged as illustrated with respect to the luma transformer units of the prediction unit 1000. The transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Further, as discussed herein, the illustrated transformer units may have a normative encoding order or standards-based encoding order, or the like, in the following order: Y0-Y15, U0-U15, V0-V15.

[0051] With further reference to Fig. 10A, luma transformer units can be scanned in a wavefront order to provide a propagation order 1001, as explained. Similarly, chroma channel one transformer units and chroma channel two transformer units can be scanned in the wavefront order to provide chroma channel propagation orders analogous to propagation order 1001. For example, the chroma channel one propagation order can be U0, U1, U4, U2, U5, U8, U3, U6, U9, U12, U7, U10, U13, U11, U14, U15, and the chroma channel two propagation order can be V0, V1, V4, V2, V5, V8, V3, V6, V9, V12, V7, V10, V13, V11, V14, V15. The propagation order 1001 and the analog chroma channel propagation orders are in Fig. 11A as luma processing sequence 1102, chroma channel one transformer unit sequence 1103, and chroma channel two transformer unit sequence 1104. As with respect Fig. As discussed in Figures 10A to 10C, this transformer unit sorting can provide a sorting that does not violate the dependencies between the transformer units based on the intra-prediction modes that upper-right samples do not use.

[0052] Now, with a view to Fig. 11B provides a processing order 1105 for the transformer units of the discussed prediction unit (i.e., with 4:4:4 color sampling with 16 luma blocks, 16 chroma one blocks, and 16 chroma two blocks) based on the techniques discussed with respect to the processing orders 802, 902. For example, the processing order 1105 may be formed by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out). In the illustrated example with equal numbers of luma and chroma transformer units, the transformer units are used up simultaneously via such grouping techniques.In the context discussed, this sorting may provide the processing order 1005 as follows: Y0, U0, V0, Y1, U1, V1, Y4, U4, V4, Y2, U2, V2, Y5, U5, V5, Y8, U8, V8, Y3, U3, V3, Y6, U6, V6, Y9, U9, V9, Y12, U12, V12, Y7, U7, V7, Y10, U10, V10, Y13, U13, V13, Y11, U11, V11, Y14, U14, V14, Y15, U15, V15. It is noted that the transformer units V9 and Y12 are located directly next to each other, although they are illustrated separately for clarity. As with respect to . Fig. 10C, a translation of the processing order 1105 to a normative encoding order of Y0-Y15, U0-U15, V0-V15 may be provided by an encoder and / or decoder using the conversion buffers discussed herein.

[0053] As discussed, the Fig. The processing sequences discussed in 10A to 10C and 11A and 11B are compatible with intra-prediction modes that do not use upper-right samples. The explanation now turns to processing sequences compatible with intra-prediction modes that use upper-right samples.

[0054] Fig. 12A to 12C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order arranged according to at least some implementations of the present disclosure. For example, the processing order may be Fig. 12A to 12C should be compatible with intra-prediction modes that use upper right samples. As in Fig. 12A, an example prediction unit 1000 may include 16 transformer units (Y0-Y15), four chroma channel one transformer units (U0-U4), and four chroma channel two transformer units (V0-V4). The illustrated example may provide transformer units for 4:2:0 color sampling. The illustrated transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Further, as discussed herein, the illustrated transformer units may have a normative encoding order or standards-based encoding order, or the like, in the following order: Y0-Y15, U0-U4, V0-V4.

[0055] In addition, as in Fig. 12A, luma transformer units of prediction unit 1000 may be scanned in a modified wavefront order to provide propagation order 1201. For example, luma transformer units of prediction unit 1000 may be scanned in a wavefront order modified to include dependencies for upper-right samples, as illustrated by dependencies 1210. Dependencies 1210 are illustrated by arrows within prediction unit 1000, such that solid arrows of dependencies 1210 indicate dependencies of the transformer unit, and dashed lines indicate independent transformer units (e.g., those with no dependencies). For example, luma transformer units of prediction unit 1000 may be scanned in the following order.The scan can start from an upper left transformer unit (Y0) and move to the right in wavefront fashion until a dependency is reached (i.e., Y5 dependent on Y2), then the dependency is followed (to provide Y5 in the scan). The scan then returns to the wavefront sequence at Y3, follows the dependency to Y6 and Y9, returns to the wavefront scan at Y7, follows the dependency to Y10, returns to the wavefront scan at Y11, follows the dependency to Y14, and returns to the wavefront scan at Y15. A second modified wavefront scan is then performed starting in Y4 and continues with the next available transformer units, in the order: Y8, Y12, Y13. For example, the first modified wavefront scan reaches the following luma transformer units in the order: Y0, Y1, Y2, Y5, Y3, Y6, Y9, Y7, Y10, Y11, Y14, Y15 as in scan 1 (S1) of the propagation order 1201 shown.The second modified wavefront scan reaches the following luma transformer units in order: Y4, Y8, Y12, Y13 as shown in scan 2 (S2). Furthermore, the luma transformer units of S2 are aligned with those of S1 so that the luma transformer units from S2 are provided as early as possible, with the constraint that they cannot violate dependencies 1210. For example, luma transformer unit Y4 depends on Y0 and Y1, but can be processed concurrently like Y2 because there is no dependency between them. Similarly, luma transformer unit Y8 must be processed after Y5 but can be processed concurrently like Y3, luma transformer unit Y12 must be processed after Y9 but can be processed concurrently with Y7, and luma transformer unit Y13 must be processed after Y10 but can be processed concurrently with Y3.

[0056] As in Fig. 12B, luma transformer units of prediction unit 1000 in propagation order 1201 may then be translated to a luma processing order 1202 such that luma processing order 1202 provides a time order for processing as discussed herein with time gaps provided to satisfy neighbor dependencies. For example, luma processing order 1202 may be generated from propagation order 1201 by scanning propagation order 1201 starting at the left side of propagation order 1201, then scanning each column vertically from top to bottom, moving from left to right to the next column (along a row), scanning the column vertically, and so on.For example, a scan of the first column may provide luma transformer unit Y0, the scan of the second column may provide luma transformer unit Y1, the scan of the third column may provide luma transformer units Y2, Y4, and so on, as shown in luma processing order 1202. This modified wavefront scanning, followed by column-wise scanning of the luma transformer units, may provide sorting that does not violate the dependencies between the luma transformer units based on the intra-prediction modes using upper-right samples. Furthermore, as shown in . Fig. 12B, chroma channel one transformer units may be provided in a chroma channel one transformer unit order 1203 that corresponds to the normative encoding order. Similarly, chroma channel two transformer units may be provided in a chroma channel two transformer unit order 1204 that corresponds to the normative encoding order.

[0057] Now, with a view to Fig. 12C, a processing order 1205 is provided for the transformer units of the prediction unit 1000 based on the techniques discussed with respect to the processing orders 802, 902. For example, the processing order 1205 may be formed by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out) and then packing all available luma transformer units. In the discussed context, this sorting may provide the processing order 1205 as follows: Y0, U0, V0, Y1, U1, V1, Y2, U2, V2, Y4, Y5, U3, V3, Y3, Y8, Y6, Y9, Y7, Y12, Y10, Y11, Y13, Y14, Y15. As with respect to Fig. As discussed in Figure 10C, the processing order 1205 can be translated to or from a normative encoding order 1206 (Y0-Y15, U0-U3, V0-V3) so that intraprocessing can occur with less idle time. This processing order 1205 can be used at one or both of the encoder and decoder elements based on the implementation of an encoding buffer.

[0058] In another embodiment, an encoding order may be generated based on the techniques discussed with respect to processing orders 803, 903. For example, a processing order may be formed from orders 1202, 1203, 1204 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, a luma transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out) and then packing all available luma transformer units or all available chroma transformer units. In the context discussed, this sorting can provide a coding order as follows: Y0, U0, Y1, V0, Y2, U1, Y4, V1, Y5, U2, Y3, V2, Y8, U3, Y6, V3, Y6, Y9, Y7, Y12, Y10, Y11, Y13, Y14, Y15.

[0059] Fig. 13A to 13C illustrate an exemplary scanning and sorting of transformer units of a prediction unit to provide an encoding order, arranged according to at least some implementations of the present disclosure. For example, the processing order may be Fig. 13A to 13C may be compatible with intra-prediction modes that do not use upper-right samples and may provide a further optimized processing order by minimizing gaps and optimizing processing compaction. As described in Fig. 13A, an exemplary prediction unit 1000 may include 16 transformer units (Y0-Y15), four chroma channel one transformer units (U0-U4), and four chroma channel two transformer units (V0-V4). The illustrated example may provide transformer units for 4:2:0 color sampling. The illustrated transformer units may have any suitable size, such as a size of 4x4 pixel samples or transform coefficients. Further, as discussed herein, the illustrated transformer units may have a normative encoding order or standards-based encoding order, or the like, in the following order: Y0-Y15, U0-U4, V0-V4.

[0060] In addition, as in Fig. 13A, luma transformer units of prediction unit 1000 may be scanned in a modified wavefront order to provide propagation order 1201. For example, luma transformer units of prediction unit 1000 may be scanned in a wavefront order modified to increase efficiency. For example, luma transformer units of prediction unit 1000 may be scanned in the following order. The scan may start at an upper left transformer unit (Y0) and move rightward in a wavefront manner through an upper right transformer unit (Y3), and then move diagonally to the lower left to improve efficiency for transformer unit Y6, and then repeatedly to the right and lower left.A second scan can then be performed, starting at the top left available transformer unit (Y4) and repeatedly moving to the right and bottom left until all transformer units are scanned. For example, the first scan reaches the following luma transformer units in order: Y0, Y1, Y2, Y3, Y6, Y7, Y10, Y11, Y14, as shown in scan 1 (S1) of propagation sequence 1301. The second scan reaches the following luma transformer units in order: Y4, Y5, Y8, Y9, Y12, Y13, as shown in scan 2 (S2).

[0061] As in Fig. 13B, luma transformer units of prediction unit 1000 in propagation order 1201 may then be translated to a luma processing order 1302 such that luma processing order 1302 provides a time order for processing as discussed herein with time gaps provided to satisfy neighbor dependencies. For example, luma processing order 1302 may be generated from propagation order 1301 by scanning propagation order 1301 starting at the left side of propagation order 1301, then scanning each column vertically from top to bottom, moving from left to right to the next column (along a row), scanning the column vertically, and so on.For example, a scan of the first column may provide luma transformer unit Y0, the scan of the second column may provide luma transformer unit Y1, the scan of the third column may provide luma transformer units Y2, Y4, and so on, as shown in luma processing order 1302. Such a modified wavefront scan, followed by the column-wise scan of the luma transformer units, may provide sorting that is efficient for maximizing processing compaction. Furthermore, as shown in . Fig. 13B, chroma channel one transformer units may be provided in a chroma channel one transformer unit order 1303 that corresponds to the normative encoding order. Similarly, chroma channel two transformer units may be provided in a chroma channel two transformer unit order 1304 that corresponds to the normative encoding order.

[0062] Now, with a view to Fig. 13C, a processing order 1305 for the transformer units of the prediction unit 1000 is provided based on the techniques discussed with respect to the processing orders 802, 902. For example, the processing order 1305 may be formed by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out), and then packing all available luma transformer units. In the discussed context, this sorting may provide the processing order 1205 as follows: Y0, U0, V0, Y1, U1, V1, Y2, Y4, Y3, U3, V3, Y5, Y6, Y8, Y7, Y9, Y10, Y12, Y11, Y13, Y14, Y15.As discussed elsewhere herein, the processing order 1305 can be translated to or from a normative encoding order 1006 (Y0-Y15, U0-U3, V0-V3) so that intraprocessing can occur with less idle time. This processing order 1205 can be used at one or both of the encoder and decoder elements based on the implementation of an encoding buffer.

[0063] In another embodiment, an encoding order may be generated based on the techniques discussed with respect to processing orders 803, 903. For example, a processing order may be formed from orders 1302, 1303, 1304 by packing as many groups of a luma transformer unit, a chroma channel one transformer unit, a luma transformer unit, and a chroma channel two transformer unit as available (e.g., until one of these transformer units runs out) and then packing all available luma transformer units or all available chroma transformer units. In the context discussed, this sorting can provide a coding order as follows: Y0, U0, Y1, V0, Y2, U1, Y4, V1, Y3, U2, Y5, V2, Y6, U3, Y8, V3, Y5, U2, Y3, Y5, Y6, Y8, Y7, Y9, Y10, Y12, Y11, Y13, Y14, Y15.

[0064] The systems discussed and the interleaving techniques discussed herein can provide enhanced processing at an encoder and / or decoder while generating or executing on standards-compliant bitstreams.

[0065] Fig. 14 is a flowchart providing an exemplary process 1400 for video coding, including interleaving transformer blocks by color in a processing order arranged according to at least some implementations of the present disclosure. The process 1400 may include one or more operations 1401 through 1408 as shown in Fig. 14. The process 1400 may form at least a portion of the video encoding process. In one non-limiting example, the process 1400 may form at least a portion of a video encoding process performed by a device or system discussed herein, such as encoder 400 and / or encoder 600. Furthermore, the process 1400 is described herein with reference to system 1500 of Fig. 15. In some embodiments, operations 1401 through 1404 may be performed by an encoder, and operations 1405 through 1408 may be performed by a decoder separate from the encoder.

[0066] Fig. 15 is an illustrative diagram providing an example system 1500 for video coding, including interleaving transformer blocks by color in a processing order arranged according to at least some implementations of the present disclosure. As shown in Fig. 15, system 1500 may include a central processor 1501, a video processor 1502, a memory 1503 (e.g., electronic memory, computer memory, computer storage space, or the like), and a conversion buffer 1504. As also illustrated, video processor 1502 may include or implement an encoder 1511 and / or a decoder 1512. In the example of system 1500, memory 1503 may store video data or corresponding content, such as input video, video data, video sequences, images, image data, pixel samples, transform coefficients, bitstream data, and / or any other data as discussed herein.

[0067] As illustrated, in some examples, encoder 1511 and / or a decoder 1512 may be implemented via video processor 1502. In other examples, one or more or portions of encoder 1511 and / or a decoder 1512 may be implemented via central processor 1501 or another processing unit, such as an image processor, a graphics processor, or the like. Furthermore, in some embodiments, system 1500 may include only encoder 1511 and may be characterized as an encoder system. In other embodiments, system 1500 may include only encoder 1512 and may be characterized as an encoder system. Encoder 1511 may include any suitable features, such as those from encoder 400 and / or any other encoder components, such as motion estimation and compensation modules, in-loop filter modules, and the like.Similarly, encoder 1512 may include any suitable features, such as those from decoder 600 and / or any other encoder components, such as motion estimation and compensation modules, in-loop filter modules, and the like.

[0068] Conversion buffer 1504 may include any suitable memory or storage space, such as volatile or non-volatile memory resources. For example, conversion buffer 1504 may provide an encoder conversion buffer 405 associated with encoder 1511 and / or a decoder conversion buffer 605 associated with decoder 1512. As with encoder 1511 and decoder 1512, conversion buffer 1504 may implement a decoder conversion buffer and / or an encoder conversion buffer. As illustrated, the conversion buffer may be provided separately from video processor 1502 (e.g., on a separate chip). In other embodiments, conversion buffer 1504 may be provided on the same chip as video processor 1502 (e.g., as a system-on-a-chip package or as onboard memory of the video processor).

[0069] Video processor 1502 may include any number and type of video, image, or graphics processing units capable of providing the operations discussed herein. Such operations may be implemented via software or hardware, or a combination thereof. For example, video processor 1502 may include circuitry designed to manipulate video, images, image data, or the like obtained from memory 1503. Central processor 1501 may include any number and type of processing units or modules capable of providing control and other high-level functions for system 1500 and / or any of the operations discussed herein. Memory 1503 may be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.), and so on.In one non-limiting example, memory 1503 may be implemented by a cache memory. Conversion buffer 1504 may be implemented separately from memory 1503 (as shown) or as a portion of memory 1503.

[0070] In one embodiment, one or more portions of encoder 1511 and / or decoder 1512 may be implemented via an execution unit (EU). The EU may, for example, include programmable logic or circuitry, such as a logic core or cores, that can provide a wide range of programmable logic functions.

[0071] In one embodiment, one or more portions of encoder 1511 and / or decoder 1512 may be implemented using dedicated hardware such as fixed-function circuits and the like. Fixed-function circuits may include dedicated logic or circuits and may provide a set of dedicated functional input points that may be associated with the dedicated logic for a dedicated purpose or function.

[0072] Back to the discussion of Fig. 14, process 1400 may begin with operation 1401, where a plurality of blocks corresponding to a coding unit of a video frame may be encoded in a processing order to generate corresponding multiple blocks of quantized residual transform coefficients. The processing order implemented in operation 1401 may include any processing order as discussed herein. In one embodiment, encoding tasks such as mode selection or the like may occur and the blocks (e.g., transformer blocks or units) may be interleaved as discussed herein before intra-processing occurs. In one embodiment, such encoding tasks may be performed in the processing order. The encoding of the blocks in the processing order may include any suitable technique or techniques.For example, encoding may include one or more of residue generation, forward transform, forward quantization, inverse quantization, inverse transform, and intra-prediction operations. In one embodiment, operation 1401 may be performed by encoder 1511, as implemented by video processor 1502.

[0073] As discussed, the processing order implemented in operation 1401 may include any processing order as discussed herein. In one embodiment, the processing order includes a first luma block, immediately followed by a first chroma channel one block. For example, the first luma block may be a spatially upper-left luma transformer block of the encoding unit. The first chroma channel one block may be the only chroma channel one block of the encoding, or a spatially upper-left luma transformer block of the encoding unit, or the like.

[0074] In one embodiment, the processing order may include the first luma block, immediately followed by the first chroma channel one block, immediately followed by a first chroma channel two block of the one or more chroma channel two blocks, immediately followed by a second luma block of the one or more luma blocks, as discussed with respect to processing order 802 and elsewhere herein. For example, the first luma block may correspond to a spatially upper-left region of the encoding unit, and the second luma block may correspond to a second region of the encoding unit located directly to the right of the upper-left region.

[0075] In one embodiment, the processing order may include the first luma block, immediately followed by the first chroma channel one block, immediately followed by a second luma block of the one or more luma blocks, immediately followed by a first chroma channel two block of the one or more chroma channel two blocks, immediately followed by a third luma block of the one or more luma blocks, as discussed with respect to processing order 803 and elsewhere herein. For example, the first luma block may correspond to a spatially upper-left region of the encoding unit, the second luma block may correspond to a second region of the encoding unit located directly to the right of the upper-left region, and the third luma block may correspond to a third region of the encoding unit located directly below the upper-left region.

[0076] In one embodiment, the processing order may comprise multiple contiguous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, and a subsequent contiguous group of remaining luma blocks as discussed with respect to processing order 803 and elsewhere herein. In one embodiment, the processing order may comprise multiple contiguous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, and a subsequent contiguous group of remaining luma blocks as discussed with respect to processing order 802 and elsewhere herein.

[0077] In one embodiment, the processing order may include luma blocks, chroma channel one blocks, and chroma channel two blocks, each arranged based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left scans begins at an upper-left block of the encoding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan, as discussed with respect to processing order 1005 and elsewhere herein.In one embodiment, the processing order may include luma blocks sorted based on a spatial scan of the luma blocks such that the spatial scan includes a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block, as discussed with respect to processing orders 1005, 1105 and elsewhere herein.

[0078] In one embodiment, the processing order may include luma blocks sorted based on a spatial scan of the luma blocks, where the spatial scan includes a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block, as discussed with respect to processing order 1205 and elsewhere herein.

[0079] Processing may continue in operation 1402, where the blocks may be interleaved from the processing order discussed with respect to operation 1401 to a normative coding order. For example, the normative coding order may be any standards-based coding order or the like. In one embodiment, transformer blocks (e.g., quantized residual quantized coefficients) may be stored by video processor 1502 in the processing order to transform buffer 1504 and retrieved from transform buffer 1504 to video processor 1502 in the normative coding order for further processing.

[0080] Processing may continue in operation 1403, where the blocks may be entropy-encoded in the normative coding order. In one embodiment, the transformer blocks (e.g., quantized residual quantized coefficients) may be entropy-encoded by encoder 1511 in the normative coding order to generate a bitstream compliant with standards (e.g., AVC, HEVC, AV1, VP9, ​​or the like). Entropy encoding may be performed using one or more suitable techniques, such as samples-to-bin / bit processing or the like.

[0081] Processing may continue in operation 1404, where the bitstream generated in operation 1403 may be stored, transmitted, or the like. In one embodiment, the bitstream may be stored in memory 1503. In one embodiment, the bitstream may be transmitted to external memory, an external decoder device or system, multiple external decoder devices or systems, or the like.

[0082] As discussed, in some embodiments, operations 1401-1404 may be performed by an encoder device or system that is separate from a decoder device or system that performs operations 1405-1408.

[0083] Processing may continue at operation 1405 on the same or a separate device, where a bitstream may be received for processing. The bitstream may be the same bitstream as discussed with respect to operation 1404, or may be a different bitstream generated using the techniques discussed, or not. In any case, the bitstream received at operation 1405 may be a standards-compliant (e.g., AVC, HEVC, AV1, VP9, ​​or the like) bitstream comprising blocks in a normative coding order. For example, the blocks may be quantized residual transform coefficients corresponding to a coding unit of a video frame in a normative coding order.In one embodiment, the normative encoding order includes two or more directly adjacent luma blocks, followed by one or more chroma channel one blocks, followed by one or more chroma channel two blocks. For example, the blocks may be sorted based on a raster scan of the luma blocks, followed by a raster scan of the chroma channel one blocks, followed by a raster scan of the chroma channel two blocks.

[0084] Processing may continue in operation 1406, where the blocks may be interleaved or translated from the normative encoding order into a processing order. As discussed, the blocks may include quantized residual transform coefficients corresponding to a coding unit of a video frame. The processing order may include any processing order discussed herein. In one embodiment, the processing order includes at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks. In one embodiment, transformer blocks (e.g.,quantized residual quantized coefficients) are stored by the video processor 1502 in the normative encoding order on the conversion buffer 1504 and retrieved from the conversion buffer 1504 to the video processor 1502 in the processing order for further processing.

[0085] As discussed, the processing order implemented in operation 1406 may include any processing order as discussed herein. In one embodiment, the processing order may include the first luma block, immediately followed by the first chroma channel one block, immediately followed by a first chroma channel two block of the one or more chroma channel two blocks, immediately followed by a second luma block of the two or more luma blocks as discussed with respect to processing order 802 and elsewhere herein. For example, the first luma block may correspond to a spatially upper-left region of the encoding unit, and the second luma block may correspond to a second region of the encoding unit located directly to the right of the upper-left region.

[0086] In one embodiment, the processing order may include the first luma block, immediately followed by the first chroma channel one block, immediately followed by a second luma block of the two or more luma blocks, immediately followed by a first chroma channel two block of the one or more chroma channel two blocks, immediately followed by a third luma block of the two or more luma blocks, as discussed with respect to processing order 803 and elsewhere herein. For example, the first luma block corresponds to a spatially upper-left region of the encoding unit, the second luma block corresponds to a second region of the encoding unit located directly to the right of the upper-left region, and the third luma block corresponds to a third region of the encoding unit located directly below the upper-left region.

[0087] In one embodiment, interleaving the blocks may comprise providing continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and thereafter providing a continuous group of remaining luma blocks as discussed with respect to processing order 802 and elsewhere herein.In one embodiment, interleaving the blocks may comprise providing one or more continuous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and thereafter providing a continuous group of remaining luma blocks as discussed with respect to processing order 803 and elsewhere herein.

[0088] In one embodiment, the processing order comprises the luma blocks spatially scanned in a spatial wavefront order with respect to the encoding unit and sorted based on neighboring dependencies among the luma blocks, as discussed with respect to processing order 1205 and elsewhere herein. In one embodiment, the processing order may include the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each ordered based on a plurality of spatially lower-left oriented scans, where a first of the plurality of lower-left arranged scans begins at an upper-left block of the encoding unit, and each subsequent lower-left oriented scan begins at a block to the right of each previous lower-left oriented scan, as discussed with respect to processing order 1005 and elsewhere herein.

[0089] In one embodiment, the processing order may include the luma blocks arranged based on a spatial scan of the luma blocks, the spatial scan including a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block, as discussed with respect to processing order 1005, 1105 and elsewhere herein.

[0090] In one embodiment, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, the spatial scan including a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block, as discussed with respect to processing order 1205 and elsewhere herein.

[0091] Processing may continue in operation 1407, where intra-decoding may be performed on the blocks of the processing order to replace a reconstructed coding unit containing the reconstructed blocks. In one embodiment, intra-decoding includes performing inverse quantization, inverse transform, and intra-prediction operations on the blocks (e.g., blocks of quantized coefficients) in the processing order to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients.

[0092] Processing may continue at operation 1408, where the reconstructed coding unit, as discussed with respect to operation 1407, may be used to generate a reconstructed frame that may be displayed to a user, stored in memory, or the like. Frame reconstruction may be performed using one or more suitable techniques. For example, operations 1405-1407 may be performed for multiple coding units, and such coding units, as well as inter-predicted coding units and the like, may be combined to reconstruct one or more frames of a video sequence. The video sequence may be stored and / or transmitted to a display for presentation to a user.

[0093] Process 1400, or portions thereof, may be repeated any number of times, either in series or in parallel, and for any number of video sequences, video frames, coding units, or the like. As discussed, process 1400 may provide video coding, including interleaving transformer blocks by color into a processing order and processing in the processing order (on the encoder and / or decoder side). For example, the discussed techniques for video coding may provide improved efficiency and throughput for intra-coding operations.

[0094] Various components of the systems described herein may be implemented in software, firmware, and / or hardware, and / or combinations thereof. For example, various components of the systems or devices discussed herein may be provided at least in part by hardware of a computing system-on-a-chip (SoC) found in a computing system, such as a smartphone. Those skilled in the art will appreciate that the systems described herein may include additional components not illustrated in the corresponding figures. For example, the systems discussed herein may include additional components such as bitstream multiplexer or demultiplexer modules and the like, which are not illustrated for clarity.

[0095] While implementation of the example processes discussed herein may include performing all of the operations in the order illustrated, the present disclosure is not so limited, and in various examples, implementation of the example processes herein may include only a subset of the illustrated operations, operations performed in a different order than illustrated, or additional operations.

[0096] Furthermore, any one or more of the operations discussed herein may be performed in response to instructions provided by one or more computer program products. Such program products may include signal-bearing media providing instructions that, when executed by, for example, a processor, may provide the functionality described herein. The computer program products may be provided in any form of one or more machine-readable media. For example, a processor including one or more graphics processing units or one or more processor cores may execute one or more of the blocks of the example processes herein in response to program code and / or instructions or sets of instructions provided to the processor through one or more of the machine-readable media.In general, the machine-readable medium may convey software in the form of program code and / or instructions or sets of instructions that may cause any of the devices and / or systems described herein to implement at least portions of the operations discussed herein and / or portions of the devices, systems, or modules or components as discussed herein.

[0097] As used in an implementation described herein, the term "module" refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. The software may be packaged as a software package, code, and / or instruction set or instructions, and "hardware" as used in an implementation described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry. The modules may be implemented collectively or individually as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), and so on.

[0098] Fig. 16 is an illustrative diagram of an example system 1600 arranged according to at least some implementations of the present disclosure. In various implementations, system 1600 may be a mobile system, but system 1600 is not limited in this regard. For example, system 1600 may be incorporated into a personal computer (PC), laptop computer, ultra-laptop computer, tablet, touchpad, portable computer, handheld computer, palmtop computer, personal digital assistant (PDA), cellular phone, cellular / PDA combination, television, smart device (e.g., smartphone, smart tablet, or smart television), mobile internet device (MID), messaging device, data communication device, cameras (e.g., point-and-shoot cameras, super-zoom cameras, digital single-lens reflex (DSLR) cameras), and so on.

[0099] In various implementations, system 1600 includes a platform 1602 coupled to a display 1620. Platform 1602 may receive content from a content device, such as one or more content service devices 1630 or content delivery devices 1640, or other similar content sources. A navigation controller 1650, including one or more navigation features, may be used to interact with, for example, platform 1602 and / or display 1620. Each of these components is described in more detail below.

[0100] In various implementations, platform 1602 may include any combination of a chipset 1605, processor 1610, memory 1612, an antenna 1613, storage space 1614, a graphics subsystem 1615, applications 1616, and / or radio 1618. Chipset 1605 may include communication between processor 1610, memory 1612, storage space 1614, graphics subsystem 1615, applications 1616, and / or radio 1618. For example, chipset 1605 may include a storage adapter (not shown) capable of providing communication with storage space 1614.

[0101] Processor 1610 may be implemented as a Complex Instruction Set Computer (CISC) or Reduced Instruction Set Computer (RISC) processor, an x86 instruction set compatible processor, a multi-core, or any other microprocessor or central processing unit (CPU). In various implementations, processor 1610 may be one or more dual-core processors, a mobile dual-core processor, and so on.

[0102] The memory 1612 may be implemented as a volatile memory device, such as, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), or static RAM (SRAM).

[0103] Storage space 1614 may be implemented as a non-volatile storage device, such as, but not limited to, a magnetic disk drive, an optical disk drive, a magnetic tape drive, an internal storage device, a fixed storage device, flash memory, battery-stored SDRAM (synchronous DRAM), and / or a network-accessible storage device. In various implementations, storage space 1614 may include technology to enhance storage performance-enhanced protection for valuable digital media, for example, when multiple hard drives are included.

[0104] The graphics subsystem 1615 may perform processing of images such as still images or videos for display. The graphics subsystem 1615 may be, for example, a graphics processing unit (GPU) or a visual processing unit (VPU). Any analog or digital interface may be used to communicatively couple the graphics subsystem 1615 and the display 1620. For example, the interface may be a high-resolution multimedia interface, a DisplayPort, a wireless HDMI, and / or wireless HD-compliant technologies. The graphics subsystem 1615 may be integrated with the processor 1610 or the chipset 1605. In some implementations, the graphics subsystem 1615 may be a standalone device communicatively coupled to the chipset 1605.

[0105] The graphics and / or video processing techniques described herein may be implemented in various hardware architectures. For example, the graphics and / or video functionality may be integrated into a chipset. Alternatively, a discrete graphics and / or video processor may be used. As yet another implementation, the graphics and / or video functionality may be provided by a general-purpose processor, including a multi-core processor. In further embodiments, the functionality may be implemented in a consumer electronic device.

[0106] Radio 1618 may include one or more radio devices capable of transmitting and receiving signals using various suitable wireless communication technologies. Such technologies may include communications over one or more wireless networks. Example wireless networks include (but are not limited to) wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), cellular networks, and satellite networks. When communicating over such networks, radio 1618, in each version, may operate in accordance with one or more applicable standards.

[0107] In various implementations, display 1620 may include any screen or television-type display. For example, display 1620 may include a computer display screen, a touchscreen display, a video monitor, a television-like device, and / or a television. Display 1620 may be digital and / or analog. In various implementations, display 1620 may be a holographic display. Additionally, display 1620 may be a transparent surface onto which an optical projection may occur. Such projections may convey various forms of information, images, and / or objects. For example, such projections may be a visual overlay for a mobile augmented reality (MAR) application. Under the control of one or more software applications 1616, platform 1602 may display user interface 1622 on display 1620.

[0108] In various implementations, one or more content service devices 1630 may be hosted by a national, international, and / or independent service and thus accessible to platform 1602, such as via the Internet. Content service device(s) 1630 may be coupled to platform 1602 and / or display 1620. Platform 1602 and / or content service device(s) 1630 may be coupled to a network 1660 to communicate (e.g., send and / or receive) media information to and from network 1660. Content delivery device(s) 1640 may be coupled to platform 1602 and / or display 1620.

[0109] In various implementations, content service device(s) 1630 may include a cable television box, a personal computer, a network, a telephone, internet-enabled devices or devices capable of conveying digital information and / or content, and any other similar devices capable of communicating content in one or both directions between content providers and the platform 1602 and / or display 1620, via a network 1660, or directly. It will be appreciated that content may be communicated in one and / or both directions to and from any of the components in the system 1600 and a content provider via the network 1660. Examples of content may include any media information, including, for example, video, music, medical and gaming information, and so on.

[0110] Content service device(s) 1630 may receive content such as cable television programming, including media information, digital information, and / or other content. Examples of content providers may include any cable or satellite television, radio, or internet content provider. The examples provided are not intended to limit implementations according to the present disclosure in any way.

[0111] In various implementations, platform 1602 may receive control signals from navigation controller 1650, which includes one or more navigation features. The navigation features may be used, for example, to interact with user interface 1622. In various embodiments, the navigation may be a pointing device, which may be a computer hardware component (particularly a human-machine interface) that allows a user to input spatial (e.g., continuous and multi-dimensional) data into a computer. Many systems, such as a graphical user interface (GUI) and televisions and displays, allow the user to control and deliver data to the computer or television using physical gestures.

[0112] Movements of the navigation features may be replicated on a display (e.g., display 1620) by movements of a pointer, cursor, focus ring, or other visual indicator displayed on the display. For example, under the control of software applications 1616, the navigation features on the navigation may be associated with virtual navigation features presented, for example, on user interface 1622. In various embodiments, it need not be a separate component but may be integrated into platform 1602 and / or display 1620. However, the present disclosure is not limited to the elements or context illustrated or described herein.

[0113] In various implementations, drivers (not shown) may include technology to, for example, enable users to instantly turn platform 1602 on or off like a television upon initial power-up by pressing a button. Program logic may allow platform 1602 to stream content to media adapters or other content service device(s) 1630 or content delivery device(s) 1640 even when the platform is "off." Further, chipset 1605 may, for example, include hardware and / or software support for 5.1 surround sound audio and / or high-definition 7.1 surround sound audio. Drivers may include a graphics driver for integrated graphics platforms. In various embodiments, the graphics driver may include a Peripheral Component Interconnect (PCI) Express graphics card.

[0114] In various implementations, each of one or more components depicted in system 1600 may be integrated. For example, platform 1602 and content service device(s) 1630 may be integrated, or platform 1602 and content delivery device(s) 1640 may be integrated, or platform 1602, content service device(s) 1630, and content delivery device(s) 1640 may be integrated. In various embodiments, platform 1602 and display 1620 may be an integrated unit. For example, display 1620 and content service device(s) 1630 may be integrated, or display 1620 and content delivery device(s) 1640 may be integrated. These examples are not intended to limit the present disclosure.

[0115] In various embodiments, system 1600 may be implemented as a wireless system, a wired system, or a combination thereof. When implemented as a wireless system, system 1600 may include components and interfaces suitable for communication over shared wireless media, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, and so on. An example of shared wireless media may include portions of a wireless spectrum, such as an RF spectrum, and so on.When implemented as a wired system, the System 1600 may include components and interfaces suitable for communication over wired communication media, such as input / output (I / O) adapters, physical connectors for connecting the I / O adapter to a correspondingly wired communication medium, a network interface card (NIC), a hard disk controller, a video controller, an audio controller, and the like. Examples of wired communication media may include a wire, a cable, metal lines, a printed circuit board (PCB), a backplane, a switching material, a semiconductor material, twisted pair cables, a coaxial cable, fiber optics, etc.

[0116] Platform 1602 may establish one or more logical or physical channels to communicate information. The information may include media information and control information. The media information may refer to any data representing content intended for a user. Examples of content may include, for example, data from a voice conversation, video conference, streaming video, an electronic mail ("email") message, voice messages, alphanumeric symbols, graphics, images, video, text, and so on. Data from voice conversations may include, for example, speech information, silence periods, background noise, calming sounds, tones, and so on. Control information may refer to any data representing commands, instructions, or control words intended for an automated system.For example, control information may be used to route media information through a system or to instruct a node to process the media information in a predetermined manner. However, embodiments are not limited to the elements or context described in . Fig. 16 is / are shown or described.

[0117] As described above, System 1600 can be embodied in various physical styles or form factors. Fig. 17 illustrates an exemplary small form factor device 1700 arranged according to at least some implementations of the present disclosure. In some examples, system 1600 may be implemented over device 1700. In other examples, system 1500, or portions thereof, may be implemented over device 1700. In various embodiments, for example, device 1700 may be implemented as a mobile computing device with wireless capabilities. A mobile computing device may refer to any device that includes a processing system and a mobile power source or supply, such as one or more batteries.

[0118] Examples of a mobile computing device may include a personal computer (PC), laptop computer, ultra-laptop computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a cellular phone, a combination cellular phone / PDA, a smart device (e.g., smartphone, smart tablet, or mobile smart television), a mobile internet device (MID), a messaging device, a data communications device, cameras, and so on.

[0119] Examples of a mobile computing device may also include computers arranged to be worn by a person, such as wrist computers, finger computers, ring computers, eyeglass computers, belt clip computers, wristband computers, shoe computers, clothing computers, and other wearable computers. In various embodiments, a mobile computing device may be implemented, for example, as a smartphone capable of executing computer applications as well as voice communications and / or data communications. For example, while some embodiments are described with a mobile computing device implemented as a smartphone, it should be understood that other embodiments may also be implemented using other wireless computing devices. The embodiments are not limited in this context.

[0120] As in Fig.17, the device 1700 may include a housing having a front 1701 and a back 1702. The device 1700 includes a display 1704, an input / output (I / O) device 1706, and an integrated antenna 1708. The device 1700 may also include navigation features 1712. The I / O device 1706 may include any suitable I / O device for inputting information into a mobile computing device. Examples of the I / O device 1706 may include an alphanumeric keyboard, a numeric keypad, a touchpad, input keys, buttons, switches, microphones, speakers, a voice recognition device, and software, and so forth. Information may also be input into the device 1700 via a microphone (not shown) or may be digitized by a voice recognition device. As shown, the device 1700 may include a camera 1705 (e.g.,including a lens, an aperture, and an imaging sensor), and a flash 1710 integrated into the back 1702 (or elsewhere) of the device 1700. In other examples, the camera 1705 and the flash 1710 may be integrated into the front 1701 of the device 1700, or front and back cameras may be provided. The camera 1705 and the flash 1710 may be components of a camera module to generate image data processed into streaming video output to display 1704 and / or communicated externally from the device 1700, for example, via antenna 1708.

[0121] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on.Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computer code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as desired computing speed, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0122] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor, which, when read by a machine, causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as IP cores, may be stored on a tangible machine-readable medium and delivered to various customers or manufacturing facilities for loading into the manufacturing machines that actually build the logic or processor.

[0123] While certain features set forth herein have been described with reference to various implementations, this description is not intended to be limiting. Therefore, various modifications to the implementations described herein, as well as other implementations that would be apparent to one of ordinary skill in the art to which this disclosure pertains, are considered to be within the spirit and scope of this disclosure.

[0124] The following embodiments relate to further embodiments.

[0125] In one or more first embodiments, a computer-implemented method for video coding comprises receiving a plurality of blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame in a normative coding order for coding, wherein the normative coding order comprises two or more directly adjacent luma blocks followed by one or more chroma channel one blocks, followed by one or more chroma channel two blocks, interleaving the plurality of blocks of quantized residual transform coefficients from the normative coding order into a processing order, the processing order comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, and performing the inverse quantization,Inverse transform and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order to generate a reconstructed coding unit corresponding to a plurality of blocks of quantized residual transform coefficients.

[0126] Further, in the first embodiments, the processing order includes the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the two or more luma blocks.

[0127] Further, in the first embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the two or more luma blocks, and the first luma block corresponds to a spatially upper left region of the coding unit and the second luma block corresponds to a second region of the coding unit directly right of the upper left region.

[0128] In addition to the first embodiments, the processing order includes the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks.

[0129] Further, in the first embodiments, the processing order includes the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks, and the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region.

[0130] Further, in the first embodiments, interleaving the plurality of blocks comprises providing continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently providing a continuous group of remaining luma blocks.

[0131] Further, in the first embodiments, interleaving the plurality of blocks comprises providing one or more continuous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently providing a continuous group of remaining luma blocks.

[0132] Further, in the first embodiments, the processing order includes the luma blocks spatially scanned in a spatial wavefront order with respect to the coding unit and sorted based on neighboring dependencies among the luma blocks.

[0133] Further, in the first embodiments, the processing order includes the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each arranged based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left arranged scans begins at an upper left block of the coding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan.

[0134] Further, in the first embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block.

[0135] Further, in the first embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block.

[0136] In one or more second embodiments, a system for video coding comprises a decoupling buffer for storing blocks of quantized residual transform coefficients assigned to an encoding unit of a video frame and a processor coupled to the decoupling buffer, wherein the processor is to store the blocks of quantized residual transform coefficients in a normative encoding order in the decoupling buffer, wherein the normative encoding order comprises two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks to retrieve the blocks from the decoupling buffer in an interleaved processing order, the processing order comprising at least a first luma block of the two or more luma blocks,directly followed by a first chroma channel one block of the one or more chroma channel one blocks and performing the inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order to generate a reconstructed coding unit corresponding to a plurality of blocks of quantized residual transform coefficients.

[0137] Further, in the second embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the two or more luma blocks.

[0138] Further, in the second embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the two or more luma blocks, and the first luma block corresponds to a spatially upper left region of the coding unit and the second luma block corresponds to a second region of the coding unit directly right of the upper left region.

[0139] In addition to the second embodiments, the processing order includes the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks.

[0140] Further, in the second embodiments, the processing order includes the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks, and the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region.

[0141] Further, in the second embodiments, the processor for retrieving the blocks from the decoupling buffer in the interleaved processing order comprises retrieving, by the processor, continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently retrieving a continuous group of remaining luma blocks.

[0142] Further, in the second embodiments, the processor for retrieving the blocks from the decoupling buffer in the interleaved processing order comprises retrieving by the processor one or more continuous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently retrieving a continuous group of remaining luma blocks.

[0143] Further, in the second embodiments, the processing order includes the luma blocks spatially scanned in a spatial wavefront order with respect to the coding unit and sorted based on neighboring dependencies among the luma blocks.

[0144] Further, in the second embodiments, the processing order includes the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each arranged based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left arranged scans begins at an upper left block of the coding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan.

[0145] Further, in the second embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block.

[0146] Further, in the second embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block.

[0147] In one or more third embodiments, a computer-implemented method for video coding comprises coding a plurality of blocks corresponding to a coding unit of a video frame in a processing order to generate corresponding plurality of blocks of quantized residual transform coefficients, wherein the coding comprises at least inverse quantization, inverse transform, and intra-prediction operations, and wherein the processing order comprises at least a first luma block directly followed by a first chroma channel one block, interleaving the plurality of blocks of quantized residual transform coefficients from the processing order into a normative coding order, wherein the normative coding order comprises the first luma block directly followed by one or more directly adjacent luma blocks, followed by the first chroma channel one block, followed by one or more chroma channel two blocks,and entropy coding the plurality of blocks of quantized residual transform coefficients in the normative coding order to generate a bitstream.

[0148] Further, in the third embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the one or more luma blocks, and wherein the first luma block corresponds to a spatially upper left region of the coding unit and the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region.

[0149] Further, in the third embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the one or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the one or more luma blocks, and wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region.

[0150] Further, in the third embodiments, the processing order comprises a plurality of continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, and a subsequent continuous group of remaining luma blocks.

[0151] Further, in the third embodiments, the processing order comprises a plurality of continuous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, and a subsequent continuous group of remaining luma blocks.

[0152] Further, in the third embodiments, the processing order includes the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each arranged based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left arranged scans starts at an upper left block of the coding unit, and each subsequent downward-left oriented scan starts at a block to the right of each previous downward-left oriented scan.

[0153] Further, in the third embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block.

[0154] Further, in the third embodiments, the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block.

[0155] In one or more fourth embodiments, a system for video coding comprises a decoupling buffer for storing a plurality of blocks corresponding to a coding unit of a video frame in a processing order and a processor coupled to the decoupling buffer, wherein the processor encodes the plurality of blocks in the processing order to generate corresponding plurality of blocks of quantized residual transform coefficients, wherein the encoding comprises at least inverse quantization, inverse transform, and intra-prediction operations, and wherein the processing order comprises at least a first luma block, directly followed by a first chroma channel one block, interleaving the plurality of blocks of quantized residual transform coefficients from the processing order into a normative coding order, wherein the normative coding order comprises the first luma block,directly followed by one or more directly adjacent luma blocks, followed by the first chroma channel one block, followed by one or more chroma channel two blocks, and entropy coding the multiple blocks of quantized residual transform coefficients in a normative coding order to generate a bitstream.

[0156] Further, in the fourth embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a second luma block of the one or more luma blocks, and wherein the first luma block corresponds to a spatially upper left region of the coding unit and the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region.

[0157] Further, in the fourth embodiments, the processing order comprises the first luma block, directly followed by the first chroma channel one block, directly followed by a second luma block of the one or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the one or more luma blocks, and wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region.

[0158] Further, in the fourth embodiments, the processing order comprises a plurality of continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, and a subsequent continuous group of remaining luma blocks.

[0159] Further, in the fourth embodiments, the processing order comprises a plurality of continuous groups consisting of a single luma block, immediately followed by a single chroma channel one block, immediately followed by a chroma channel two block, and a subsequent continuous group of remaining luma blocks.

[0160] Further, in the fourth embodiments, the processing order includes the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each arranged based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left arranged scans starts at an upper left block of the coding unit, and each subsequent downward-left oriented scan starts at a block to the right of each previous downward-left oriented scan.

[0161] Further, in the fourth embodiments, the processing order includes luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block to the right of the second block, and a fifth block directly to the right of the third block.

[0162] Further, in the fourth embodiments, the processing order includes luma blocks sorted based on a spatial scan of the luma blocks, wherein the spatial scan includes at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block.

[0163] In one or more fifth embodiments, the at least one machine-readable medium may include a plurality of instructions that, in response to execution on a computing device, cause the computing device to perform a method according to any of the above embodiments.

[0164] In one or more sixth embodiments, an apparatus or system may include means for performing a method according to any of the above embodiments.

[0165] It should be understood that the embodiments are not limited to the embodiments so described, but may be practiced with modifications and changes without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limited in this regard, and in various implementations, the above embodiments may include the implementation of only a subset of these features, the implementation of these features in a different order, the implementation of various combinations of such features, and / or the implementation of more features than those expressly listed. The scope of the embodiments should, therefore, be determined by reference to the appended claims, along with the full scope of equivalents to those claims.

Claims

[1] A computer-implemented method (1400) for video coding, comprising: Receiving (1405) a plurality of blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame for coding in a normative coding order, the normative coding order comprising two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks; Interleaving (1406) the plurality of blocks of quantized residual transform coefficients from the normative encoding order into a processing order (422), the processing order (422) comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks; and Performing (1407) inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order (422) to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients. [2] The method (1400) of claim 1, wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit located directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit located directly below the upper left region. [3] The method (1400) of claim 1, wherein interleaving the plurality of blocks comprises: Providing continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently providing a continuous group of remaining lumablocks. [4] The method (1400) of claim 1, wherein the processing order comprises luma blocks spatially scanned in a spatial wavefront order with respect to the encoding unit and sorted based on neighboring dependencies among the luma blocks. [5] The method (1400) of claim 1, wherein the processing order comprises the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each sorted based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left oriented scans begins at an upper-left block of the encoding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan. [6] The method (1400) of claim 1, wherein the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, the spatial scan comprising at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block. [7] The method (1400) of claim 1, wherein the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, the spatial scan comprising at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block. [8] System (1600) for video coding, comprising: a decoupling buffer for storing blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame; and a processor (1610) coupled to the decoupling buffer, the processor storing the blocks of quantized residual transform coefficients in a normative encoding order in the decoupling buffer, the normative encoding order comprising two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks that retrieve blocks from the decoupling buffer in an interleaved processing order, the processing order comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks,directly followed by a third luma block of the two or more luma blocks and to perform inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients. [9] The system (1600) of claim 8, wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region. [10] The system (1600) of claim 8, wherein retrieving the blocks from the decoupling buffer in the interleaved processing order by the processor (1610) comprises retrieving continuous groups by the processor (1610) consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently retrieving a continuous group of remaining luma blocks. [11] The system (1600) of claim 8, wherein the processing order comprises the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each sorted based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left oriented scans begins at an upper left block of the encoding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan. [12] The system (1600) of claim 8, wherein the processing order comprises luma blocks sorted based on a spatial scan of the luma blocks, the spatial scan comprising at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly below the first block, a fourth block directly to the right of the second block, and a fifth block directly to the right of the third block. [13] The system (1600) of claim 8, wherein the processing order comprises the luma blocks sorted based on a spatial scan of the luma blocks, the spatial scan comprising at least a first block at an upper left luma block of the encoding unit, a second block directly to the right of the first block, a third block directly to the right of the second block, a fourth block directly below the first block, and a fifth block directly to the right of the fourth block. [14] System comprising: Means for receiving a plurality of blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame for coding, in a normative coding order, the normative coding order comprising two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks; Means for interleaving the plurality of blocks of quantized residual transform coefficients from the normative coding order into a processing order, the processing order comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks; and Means for performing inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients. [15] The system of claim 14, wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region. [16] The system of claim 14, wherein the means for interleaving the plurality of blocks comprises: Means for providing consecutive groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and Means for providing a continuous group of remaining lumablocks after the continuous groups. [17] The system of claim 14, wherein the processing order comprises the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each sorted based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left oriented scans begins at an upper left block of the encoding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan. [18] Machine-readable medium(s), comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to perform video encoding by: Receiving a plurality of blocks of quantized residual transform coefficients corresponding to a coding unit of a video frame for coding in a normative coding order, the normative coding order comprising two or more directly adjacent luma blocks followed by one or more chroma channel one blocks followed by one or more chroma channel two blocks; Interleaving the plurality of blocks of quantized residual transform coefficients from the normative coding order into a processing order, the processing order comprising at least a first luma block of the two or more luma blocks, directly followed by a first chroma channel one block of the one or more chroma channel one blocks, directly followed by a second luma block of the two or more luma blocks, directly followed by a first chroma channel two block of the one or more chroma channel two blocks, directly followed by a third luma block of the two or more luma blocks; and Performing inverse quantization, inverse transform, and intra-prediction operations on the plurality of blocks of quantized coefficients in the processing order to generate a reconstructed coding unit corresponding to the plurality of blocks of quantized residual transform coefficients. [19] The machine-readable medium of claim 18, wherein the first luma block corresponds to a spatially upper left region of the coding unit, the second luma block corresponds to a second region of the coding unit directly to the right of the upper left region, and the third luma block corresponds to a third region of the coding unit directly below the upper left region. [20] The machine-readable medium of claim 18, wherein the interleaving of the plurality of blocks comprises: Providing continuous groups consisting of a first single luma block, immediately followed by a single chroma channel one block, immediately followed by a second single luma block, immediately followed by a single chroma channel two block, until the chroma channel one blocks and the chroma channel two blocks are exhausted, and subsequently providing a continuous group of remaining lumablocks. [21] The machine-readable medium of claim 18, wherein the processing order comprises the luma blocks, the chroma channel one blocks, and the chroma channel two blocks, each sorted based on a plurality of spatially downward-left oriented scans, wherein a first of the plurality of downward-left oriented scans begins at an upper-left block of the encoding unit, and each subsequent downward-left oriented scan begins at a block to the right of each previous downward-left oriented scan.

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