REAR STORAGE ELEMENT WITH LOCAL STORAGE SELECTION PORT

Abstract

Method for manufacturing a storage unit, wherein the method comprises: Forming, on a first side of a semiconductor wafer (101), a semiconductor unit (100) having at least one gate structure (113) and a first source / drain region (116) at a first end of the at least one gate structure (113) arranged on the first side of the semiconductor wafer (101); Form on the first side of the semiconductor wafer (101): a first electrically conductive element that contacts the first source / drain region (116) to form a source line (152); and a second electrically conductive element that is electrically isolated from the source line (152), wherein the second electrically conductive element defines a word line (154); Form on a second side of the semiconductor wafer (101), which is opposite the first side: of a storage element (214) on a first surface of a second source / drain region (106), and a third electrically conductive element which contacts the storage element (214), wherein the third electrically conductive element defines a bit line (220), wherein the storage element (214) is in electrical connection with the second source / drain region (106) of the semiconductor unit (100), wherein the second source / drain region (106) is different from the first source / drain region (116), wherein the second source / drain region (106) is formed on the second side of the semiconductor wafer (101), which is opposite the first side, wherein the second source / drain region (106) has a second surface extending to the first side of the semiconductor wafer (101) and a second end opposite the first end, which contacts at least one gate structure (113); where the formation of the storage element (214) exhibits: Hollowing out the second side of the semiconductor wafer (101) to expose the first surface of the second source / drain region (106) opposite the second surface; Forming an electrically conductive storage contact (212) on the first surface of the second source / drain region (106) such that the electrically conductive storage contact (212) and the second source / drain region (106) are aligned in the same direction; and Formation of the storage element (214) on the electrically conductive storage contact (212).

Description

TECHNICAL FIELD

[0001] The present invention relates generally to manufacturing methods and structures obtained thereby for semiconductor memories and memory units, in particular non-volatile memory units. BACKGROUND

[0002] Unlike conventional random access memory (RAM) chip technologies, data in magnetic RAM (MRAM) is not stored as electrical charge or current flows, but rather by magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each capable of holding a magnetization. The two ferromagnetic plates are separated by a thin insulating layer to define a magnetic tunnel junction (MTJ). One of the two ferromagnetic plates is a permanent magnet configured with a specific magnetization direction, while the other ferromagnetic plate has a magnetization direction that can be changed to match that of an external field or changed using an applied current to store data.

[0003] Because MRAM devices employ an MTJ to achieve magnetic data storage, unlike dynamic random access memory (DRAM) technology, MRAM devices do not require constant charge refresh. Accordingly, MRAM devices retain memory contents when power is off without requiring continuous power consumption, offering significant improvements in overall energy efficiency. However, exotic materials may be required to fabricate the MTJ, such as non-CMOS compatible materials, magnetic ferrite materials, and so on. Furthermore, MRAM devices fabricated using conventional back-end-of-line (BEOL) processes suffer from dimensional limitations that hamper attempts to reduce the overall MRAM footprint.

[0004] This is partly based on previously published documents. Document US 2017 / 0 141 298 A1 describes a memory cell structure, a memory device, and a corresponding manufacturing method. The memory cell structure described therein includes an MRAM, which reduces the resistance of connections to an existing MTJ. Furthermore, the size of the memory cells can be reduced, which can reduce the performance disadvantages of the MTJs due to heat generation. Furthermore, document US 2016 / 0 293 664 A1 describes semiconductor device structures that can be usefully used for bulk transistors and corresponding manufacturing methods.

[0005] Despite the progress already made, there is still a need in the field to solve this problem. SUMMARY

[0006] This problem is solved by the subject matter of the independent claims. Further embodiments arise from the respective dependent claims.

[0007] From a first aspect, the present invention provides a method of manufacturing a memory device, the method comprising: forming a semiconductor device having at least a gate structure and a first source / drain region on a first side of a semiconductor wafer; and forming a memory element on a second side of the semiconductor wafer opposite the first side; wherein the memory element is in electrical connection with a second source / drain region of the semiconductor device that is different from the first source / drain region.

[0008] In another aspect, the present invention provides a memory device comprising: a wafer extending along a horizontal axis to define a first side and a second side opposite the first side, and extending along a vertical axis to define a height of the wafer; a semiconductor device on the wafer, the semiconductor device comprising: at least one gate structure on the first side of the wafer; a first source / drain region on the first side of the wafer contacting a first end of the at least one gate structure; a second source / drain region on the second side of the wafer extending into the first side to contact a second end of the at least one gate structure disposed opposite the first end;and a storage element on the second side of the wafer, the storage element being in contact with the second source / drain region;

[0009] In another aspect, the present invention provides a method of manufacturing a memory device, the method comprising: forming a semiconductor device having at least a gate structure, a first source / drain region, and a second source / drain region on a first side of a semiconductor wafer, the first source / drain region having a greater length than the second source / drain region to define an extended portion extending beyond the second source / drain region; forming a buried insulator layer on a top surface of the first source / drain region on the first side of the semiconductor wafer; forming an electrically conductive piercing via extending through the buried insulator layer and in contact with the extended portion such that the piercing via is offset with respect to the gate structure;and forming an offset storage element on a second side of the semiconductor wafer opposite the first side, the offset storage element contacting a surface of the piercing via and being offset with respect to the gate structure;

[0010] In another aspect, the present invention provides a method of manufacturing a memory device, the method comprising: forming a semiconductor device having at least a gate structure and a first source / drain region on a first side of a semiconductor wafer; forming a buried insulator layer on a top surface of the first source / drain region on the first side of the semiconductor wafer; forming an electrically conductive via / contact passing through the buried insulator layer and in contact with the first source / drain region on a second side of the semiconductor wafer opposite the first side;and forming a memory element on the second side of the semiconductor wafer, wherein the memory element and the via / contact are each in electrical connection with a second source / drain region of the semiconductor device that is different from the first source / drain region;

[0011] Embodiments of the present invention relate to a method for fabricating a memory device. One non-limiting example includes forming a semiconductor device having at least a gate structure and a first source / drain region on a first side of a semiconductor wafer. The method further includes forming a memory element on a second side of the semiconductor wafer opposite the first side, wherein the memory element is in electrical communication with a second source / drain region of the semiconductor device that is different from the first source / drain region.

[0012] Embodiments of the present invention relate to a memory device comprising a semiconductor device on a wafer. The semiconductor device has a gate structure, a first source / drain region, and a second source / drain region. The gate structure is arranged on the first side of the wafer. The first source / drain region is also arranged on the first side of the wafer and is in contact with a first end of the gate structure. The second source / drain region is arranged on the second side of the wafer and extends into the first side to be in contact with a second end of the gate structure. Furthermore, the memory device has a memory element on the second side of the wafer. The memory element is in contact with the second source / drain region.

[0013] Embodiments of the present invention relate to a method for fabricating a memory device. A non-limiting example of the method comprises forming a semiconductor device having at least a gate structure, a first source / drain region, and a second source / drain region on a first side of a semiconductor wafer, wherein the first source / drain region has a greater length than the second source / drain region to define an extended portion extending beyond the second source / drain region. The method further comprises forming a buried insulator layer on a top surface of the first source / drain region on the first side of the semiconductor wafer.The method further comprises forming an electrically conductive piercing via extending through the buried insulator layer and in contact with the extended portion, such that the piercing via is offset relative to the gate structure. The method further comprises forming an offset memory element on a second side of the semiconductor wafer opposite the first side, wherein the offset memory element is in contact with a surface of the piercing via and is offset relative to the gate structure.

[0014] Embodiments of the present invention relate to a method for fabricating a memory device. One non-limiting example includes forming a semiconductor device having at least a gate structure and a first source / drain region on a first side of a semiconductor wafer. The method further includes forming a buried insulator layer on a top surface of the first source / drain region on the first side of the semiconductor wafer. The method further includes forming an electrically conductive via / contact extending through the buried insulator layer and in contact with the first source / drain region on a second side of the semiconductor wafer opposite the first side.The method further comprises forming a memory element on the second side of the semiconductor wafer, wherein the memory element and the via / contact are each in electrical connection with a second source / drain region of the semiconductor device that is different from the first source / drain region.

[0015] Further advantages are achieved by the methods according to the present invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, reference may be made to the detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The details of the exclusive rights described herein are particularly pointed out and expressly claimed in the claims at the conclusion of the specification. The above and other advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-sectional view of a vertical type field effect transistor (VTFET) formed on a wafer according to embodiments of the invention; Fig. 2 illustrates the VTFET after forming a word line and a source line on the front side of the wafer according to embodiments of the invention; Fig. 3 illustrates a reversed orientation of the VTFET according to embodiments of the invention; Fig. 4 illustrates the VTFET after recessing the backside of the wafer according to embodiments of the invention; Fig. 5 illustrates the VTFET after exposing a buried source / drain region according to embodiments of the invention; Fig. 6 illustrates the VTFET after forming a backside source / drain contact according to embodiments of the invention; Fig. 7 illustrates the VTFET after forming a storage contact on the backside source / drain contact according to embodiments of the invention; Fig. 8 illustrates the VTFET after stacking a plurality of MTJ layers on the memory contact to form an MRAM device according to embodiments of the invention; Fig. 9 illustrates the MRAM device after patterning the MTJ layer to form a magnetic memory element according to embodiments of the invention; and Fig. 10 illustrates the MRAM device after forming a bit line on the magnetic storage element according to embodiments of the invention; Fig. 11 is a cross-sectional view of a finished MRAM device having a backside storage element and a frontside memory access VTFET, according to embodiments of the invention; Fig. 12 is a schematic diagram illustrating an MRAM array according to embodiments of the invention; Fig. 13 is a front view of a wafer including a planar memory access FET according to embodiments of the invention; Fig. 14 is a cross-sectional view taken along the line AA of the Fig. 13 according to embodiments of the invention; Fig. 15 illustrates a memory array after forming a word line and a source line on the front side of the wafer according to embodiments of the invention; Fig. 16 illustrates a flipped orientation of the wafer after stacking a bonding film and a solid handle wafer onto the wordline according to embodiments of the invention; Fig. 17 illustrates the wafer after backside recessing according to embodiments of the invention; Fig. 18 illustrates the memory array after forming a memory element and a bit line according to embodiments of the invention; Fig. 19 is a cross-sectional view of a wafer having an offset piercing via contacting a source / drain region of a VTFET according to embodiments of the invention; Fig. 20 illustrates a plurality of MTJ layers stacked on the staggered piercing via to form a staggered memory element according to embodiments of the invention; Fig. 21 is a cross-sectional view of a VTFET formed on a wafer according to embodiments of the invention; and Fig. 22 illustrates the wafer after forming an MRAM device having a backside via / contact formed on a source / drain region of the VTFET.

[0017] The diagrams shown herein are illustrative. Numerous variations of the diagrams or methods described herein may exist without departing from the scope of the invention. For example, the operating steps may be performed in a different order, or operating steps may be added, omitted, or modified. Furthermore, the term "coupled" and variations thereof describe a connection path between two elements and do not imply a direct connection between the elements without intervening elements / connections. All such variations are considered part of the description.

[0018] In the accompanying figures and the following detailed description of the described embodiments, the various elements illustrated in the figures are designated by two- or three-digit reference numerals. With few exceptions, the leftmost digit(s) of each reference number corresponds to the figure in which the element is first illustrated. DETAILED DESCRIPTION

[0019] For the sake of brevity, conventional processes associated with the fabrication of semiconductor devices and ICs may or may not be described in detail herein. Further, the various tasks and process steps described herein may be incorporated into a more comprehensive process or into a process with additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, so in the interest of brevity, numerous conventional steps are only briefly mentioned or omitted entirely without describing the well-known details of the processes.

[0020] The term "RAM" and variations thereof are used in this detailed description to describe a data storage device capable of storing one or more bits of data (e.g., a "0" or "1"). The term "intermediate semiconductor device" and variations thereof refer to a semiconductor device at a stage of fabrication prior to its final state.

[0021] As an overview of technologies specifically relevant to aspects of the invention, non-volatile memory (NVM) technologies are cited, which aim to provide an NVM device with improved processing speeds and high density, while offering low leakage current and a reduced device footprint. These emerging NVM technologies include phase-change random access memory (PCRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM). For example, MRAM devices offer advantages over conventional electrically charged semiconductor memory devices and current-based memory devices, such as dynamic random access memory (DRAM) and flash memory. For example, the storage element of a DRAM device is a capacitor, which loses its charge over time.As a result, memory modules that use DRAM must refresh the cells in their chips approximately 20 times per second, reading and rewriting their contents each time. As DRAM cells shrink in size, the cells must be refreshed more frequently, resulting in higher power consumption.

[0022] Because MRAM devices utilize an MTJ to achieve magnetic data storage, they do not require constant charge refresh. Thus, MRAM devices retain memory contents when power is off without the need for continuous power consumption, offering a significant improvement in overall energy efficiency. However, exotic materials may be required for MTJ fabrication, such as non-CMOS compatible materials, magnetic ferrite materials, and so on. Furthermore, MRAM devices fabricated using conventional back-end-of-line (BEOL) processes suffer from dimensional limitations that hamper attempts to reduce the overall MRAM footprint.

[0023] As an overview of aspects of one or more embodiments of the invention, a backside memory architecture providing a memory device (e.g., PCRAM device, ReRAM device, FeRAM device, MRAM device, etc.) is described. The backside memory architecture includes an access transistor on a first surface (e.g., front side) of a semiconductor wafer and a memory element on the opposite second surface (e.g., back side) of the wafer. The access transistor may be configured as a vertical field-effect transistor (VTFET) having an embedded memory contact in contact with a magnetic memory element formed on the backside of the wafer.The access transistor can also be designed as a planar-type FET, or finFET, which uses a piercing via to electrically connect to a magnetic storage element formed on the backside of the wafer. In either case, an MRAM device with a reduced footprint can be manufactured.

[0024] Aspects of one or more embodiments of the invention address the above-described disadvantages of the prior art because the backside memory architecture described herein overcomes MTJ height limitations that hamper conventional BEOL fabrication techniques. Furthermore, the backside memory architecture allows for routing a backside bitline along the edge of the memory array to the frontside, thus further reducing the overall footprint of the MRAM device.

[0025] For a more detailed description of aspects of the invention, Fig. 1 illustrates a semiconductor device intermediate stage 100 according to one or more non-limiting embodiments. The semiconductor device intermediate stage 100 includes a wafer 101 extending along a first axis (e.g., X-axis) defining a length, a second axis (e.g., Y-axis) defining a width, and a third axis (e.g., Z-axis) defining a height. The wafer 101 has a first side and a second side disposed opposite the first side. The first side is referred to, for example, as a front side (front side), while the second side is referred to, for example, as a back side (back side).

[0026] In one or more embodiments, the semiconductor device intermediate stage 100 further comprises a transistor device, such as a VTFET. The VTFET has one or more channel regions 110 arranged perpendicularly between a first source / drain (S / D) region 116 and a second S / D region 106. The first S / D region 116 is referred to as the upper S / D region 116 and the second S / D region 106 is referred to as the lower S / D region 106. The upper S / D region 116 and the lower S / D region 106 are made of a semiconductor material, such as silicon (Si) or silicon germanium (SiGe), and may be formed by one or more epitaxial growth techniques.The epitaxial growth process can be performed using various well-known techniques, including, but not limited to, vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE) using a gaseous or liquid precursor, for example, silicon tetrachloride.

[0027] The VTFET further includes one or more gate structures 113. Each gate structure 113 includes a gate dielectric layer 114 encapsulating the channel region 110 and an electrically conductive contact 112 surrounding all portions of the gate dielectric layer 114. Accordingly, the perpendicular orientation of the channel region 110 allows the gate structure 113 to encapsulate or surround all walls of the channel region 110, thereby improving electrostatic gate control and providing the potential to reduce gate voltages. S / D spacers 108 are formed between the gate dielectric layer 114 and the S / D regions 106 and 116, respectively, to improve the electrical isolation of the S / D regions from the gate structure 113. During operation, current flows through the channel region 110 in a perpendicular direction between the upper S / D region 116 and the lower S / D region 106, thus flowing predominantly perpendicular to the upper surface of the device.

[0028] A first interlayer dielectric (ILD) 120 is formed on the front side of wafer 101 and encapsulates gate structure 113 and upper S / D region 116. A first via 118 is formed in first ILD 120 to provide electrical access to upper S / D region 116. For example, one or more masking and patterning processes may be performed to form a cavity in first ILD layer 120 exposing a top surface of upper S / D region 116. Subsequently, the cavity may be filled with an electrically conductive material, such as a metal material, to form the first ILD 118. A chemical mechanical planarization (CMP) process may be performed to remove excess metal material from the top surface of ILD 120. Thus, the top surfaces of the ILD 120 and the first via 118 are aligned (ie, they are coplanar).

[0029] Furthermore, Fig. 1, the lower S / D region 106 is configured as a buried S / D region and is in contact with a semiconductor layer 102. The semiconductor layer 102 may be composed of various semiconductor materials, including, but not limited to, Si, and may be used as a seed layer for the epitaxial growth of the lower S / D region 106.

[0030] The backside of the wafer 101 may further include shallow trench isolation (STI) regions 104, which serve to electrically isolate the lower S / D region 106 from neighboring semiconductor devices (not shown). The STI regions 104 may be formed with a desired height, which serves to determine the height of a memory device contact (in Fig. 1 not shown) to be formed on the backside of wafer 101 during subsequent manufacturing steps described in more detail below. In one or more non-limiting embodiments, STI regions 104 have a total height of, for example, about 100 nanometers (nm). The difference (e.g., 70 nm) between the total height of STI regions 104 (e.g., 100 nm) and the total height of lower S / D region 106 (e.g., 30 nm) will define the height of the memory device contact described in more detail below.

[0031] Fig. 2 shows the semiconductor unit intermediate of Fig. 1 after forming a memory line array 150 on the front side of the wafer 101. The memory line array includes a source line 152 and a word line 154. One or more back-end-of-line (BEOL) manufacturing processes may be performed to form the source line 152 and the word line 154. For example, first, the source line 152, which is made of an electrically conductive material, is formed on the top surface of the first ILD 120. The source line 152 runs along the first axis (e.g., the X-axis) such that a portion of the source line 152 is in contact with a top surface of the first via 118. A second ILD 121 is deposited on a top surface of the source line 152 and then patterned to form a cavity that defines the dimensions of the word line 154.Subsequently, the cavity is filled with an electrically conductive material to form the word line 154, which is separated from the source line 152 by a second ILD 120 and runs in a direction opposite to that of the source line 152 (e.g., along the Y-axis).

[0032] Fig. 3 to 10 show the semiconductor device 100 after the wafer 101 has been turned over. Thus, various manufacturing processes can be performed on the back side of the wafer 101 to form a back-side memory element (in Fig. 3 (not shown). Note that wafer 101 may be flipped over after applying a bonding film 202 and a solid handle wafer 204 to the top of wordline 154. Furthermore, depending on the device application, additional metal lines and / or vias may be formed on the front side in addition to the wordline. For example, a first portion of wordline 154 may be formed on the front side of wafer 101, while a second portion of wordline 154 is routed to the back side of wafer 101.

[0033] The handling wafer 204 is formed on the bonding film 202. The bonding film 202 is made of an adhesive material or polyimide with a Si adhesive. Alternatively, the bonding film 202 may be made of an oxide-based or nitride-based material to enable bonding to dielectric materials. The bonding film 202 may be configured as a single layer or it may comprise multiple layers. The solid handling wafer 204 may be made of various materials, such as Si, and may provide additional support during one or more subsequent manufacturing processes.

[0034] Fig. 4 shows the semiconductor device 100 after recessing the semiconductor layer 102. The semiconductor layer 102 may be recessed using various methods, including, but not limited to, wafer grinding, a reactive ion etching (RIE) process, and a CMP process. When using, for example, a CMP process, the semiconductor layer 102 may be recessed until the STI regions 104 are reached (i.e., stopping at the STI regions 104). Accordingly, exposed surfaces of the STI regions 104 and the remaining semiconductor layer 102 are aligned (i.e., they are coplanar).

[0035] Fig. 5 shows the semiconductor device 100 after removing the remaining semiconductor layer 102 to expose the underlying lower S / D region 106. A selective etching process may be performed that selectively etches away the remaining semiconductor layer 102 while preserving the STI regions 104 and the lower S / D region 106. Thus, a cavity 208 is formed that exposes the underlying lower S / D region 106.

[0036] The selective etching process includes, for example, a wet etching process employing ammonium hydroxide (NH4OH) chemistry. If the semiconductor layer 102 is formed from Si and the lower S / D region 106 is formed from SiGe, a wet etching process employing NH4OH chemistry may be used, which attacks the Si material of the semiconductor layer 102 more aggressively than the SiGe material of the lower S / D region 106. For example, the NH4OH chemistry can achieve an etch ratio of 4:1, meaning it can etch the Si material four times more aggressively than the SiGe material. SiGe is generally used in the S / D region of pFETs. Alternatively, the access transistor (e.g., VTFET) can be formed as an nFET, which can include SiC S / D regions 106. In this case, the removal of Si may be performed using a chemistry that aggressively attacks the Si material of the semiconductor layer 102 while preserving the SiC material of the S / D region 106.Furthermore, carbon doping can be used to vary the etching ratio between the materials.

[0037] Fig. 6 shows the semiconductor device 100 after depositing an electrically conductive material in the cavity 208 to form an S / D contact 210 on the lower S / D region 106. The electrically conductive material may be a metal material, including, but not limited to, titanium (Ti), titanium nitride (TiN), and tungsten (W). Excess conductive material may be removed from the backside of the wafer 101 by performing a CMP process, stopping at the STI regions 104. Thus, the exposed surface of the S / D contact 210 is aligned with the exposed surface of the STI regions 104. Although the height of the S / D contact 210 is illustrated as 70 nm, the dimensions of the S / D contact 210 are not limited thereto.

[0038] As in Fig. 7, the S / D contact 210 may be partially recessed below the surfaces of the STI regions 104. For example, to recess a tungsten (W) S / D contact 210, an RIE process employing fluorine-based chemistry may be used. Although not illustrated, the S / D contact 210 may include one or more contact liners. For example, a first liner (not shown) of titanium (Ti) may be deposited on the S / D contact 210. Subsequently, a second liner (not shown) of titanium nitride (TiN) may be deposited on the first liner (e.g., Ti liner).

[0039] The resulting cavity can be filled with a second conductive material, such as TaN, to form a memory contact 212. The memory contact 212 is optional and can be omitted in one or more embodiments of the invention. The second conductive material 212 can be deposited using various techniques, such as physical vapor deposition (PVD) or other sputtering techniques. Thus, the S / D contact 210 can be completed by performing various manufacturing processes on the backside of the wafer 101. Furthermore, the backside formation of the S / D contact 210 and the memory contact 212 results in self-alignment of the lower S / D region 106, the backside formation of the S / D contact 210, and the memory contact 212.In other words, the buried lower S / D region 116 can be used to form a self-aligned contact for a memory element, which is described in more detail below. The contact (also referred to as a terminal element) can be etch-resistant and serve to protect underlying elements and structures during patterning of the backside memory element.

[0040] As in Fig. As shown in Figure 8, the memory element 214 is formed on exposed surfaces of the memory contact 212 and the STI regions 104. The memory element 214 will be described below as an MRAM memory element. However, it should be noted that the invention is not limited thereto, and that various other types of memory elements may be employed without departing from the scope of the invention.

[0041] In one or more non-limiting embodiments, the MRAM memory element 214 is configured as a memory stack 214 comprising a plurality of individual magnetic tunnel junction (MTJ) layers 215a-215c arranged perpendicular to one another. The MTJ layers include, for example, a fixedly magnetized magnetic layer 215a, a tunnel barrier dielectric layer 215b, and a freely magnetizable magnetic layer 215c. The fixedly magnetized magnetic layer 215a is formed on the memory contact 212. The freely magnetizable magnetic layer 215c is disposed over the fixedly magnetized magnetic layer 215a. The tunnel barrier dielectric layer 215b is sandwiched between the fixedly magnetized magnetic layer 215a and the freely magnetizable magnetic layer 215c. The fixedly magnetized magnetic layer 215a and the freely magnetizable magnetic layer 215c are made of a ferromagnetic material.The dielectric tunnel barrier layer 215b is composed of an oxide or metal oxide material, such as aluminum oxide (AlO2). Accordingly, the stack of MTJ layers 215a through 215c defines an MTJ enabling magnetic storage to form an MRAM bit / cell.

[0042] The MTJ layers 215a to 215c may be deposited, for example, using a PVD process. Each MTJ layer 215a to 215c may have a perpendicular thickness (extending, for example, along the Z-axis) in the range of about 10 nm or less. Although three MTJ layers 215a to 215c are described herein, the number of MTJ layers is not limited thereto.

[0043] Furthermore, Fig. 8, a photoresist mask 216 is formed on the memory stack 214. The photoresist mask 216 may be formed by first depositing a photoresist layer on the memory stack and then performing a lithographic patterning process.

[0044] Fig. 9 shows the semiconductor device 100 after performing an ion beam etching (IBE) process that transfers the pattern defined by the photoresist mask 216 into the memory stack 214. Accordingly, a magnetic memory element 217 (e.g., MRAM element 217) is formed on the memory contact 212. In contrast to conventional MRAM devices that include an MRAM element and an access transistor formed on a single side (e.g., the front side) of a wafer, one or more non-limiting embodiments of the invention described herein provide an MRAM element 217 on a second side (e.g., the back side) of the wafer 101, while the access transistor (e.g., VTFET) is arranged on the opposite side (e.g., the front side) of the wafer 101.

[0045] Furthermore, as in Fig. 9, a memory stack insulation film 218 is deposited, encapsulating the MRAM element 217. The memory stack insulation film 218 is made of a nitride material, such as silicon nitride (SiN), and is deposited, for example, by a chemical vapor deposition (CVD) process. The insulation film 218 supports film adhesion while inhibiting the diffusion of metal atoms from surfaces of the MRAM element 217. Furthermore, the insulation film 218 can limit the thermal degradation of the MRAM element 217 during further processing.

[0046] As in Fig. 10, a third ILD layer 219 is deposited on the insulating film 218 to surround the MRAM element 217. Subsequently, the third ILD layer 219 is recessed to expose a top surface of the insulating film 218. An RIE process may be performed to recess the ILD layer 219 and may continue until the top surface of the insulating film 218 is removed and the underlying MRAM element 217 is exposed. Alternatively, a first etch process may be performed to lower the ILD layer 219 until the top surface of the insulating film 218 is exposed. Subsequently, a different etch process (e.g., an etch process using a different chemistry) may be used to remove the top surface of the insulating film 218 to expose the underlying MRAM element 217.

[0047] Furthermore, as in Fig. 10, a bit line 220 made of an electrically conductive material is formed on the third ILD 219. The bit line 220 extends along the first axis (e.g., the X-axis) such that a portion of the bit line 220 contacts the exposed surface of the MRAM element 217. Although not shown, the wafer 101 may be flipped again after the formation of the bit line 220, and processing of the front-side components may continue if necessary.

[0048] Fig. 11 shows a finished MRAM device 600 including a backside storage element 217 and a frontside VTFET 608. The backside storage element 217 may, for example, be configured as an MTJ. A circuit schematic is superimposed on the MRAM device 600 to facilitate identification of some of the components. For example, the circuit schematic illustrates that the VTFET 608 is connected between a source line 152 and the storage element 217. Accordingly, the VTFET 608 may serve as an access transistor of a memory bit / cell defined by the backside storage element 217. The finished MRAM device 600 may also include an additional via 604 at the edge of the array for accessing the bit line 220 from the frontside of the wafer 101.

[0049] Fig. Figure 12 shows a schematic diagram illustrating an MRAM array 700. The MRAM array 700 is formed on a wafer having a front side 704 and a back side 702. The front side 704 includes a plurality of access transistors 710A, 710B, and 710C. Each transistor 710A to 710C has a first source terminal, a gate terminal, and a second source / drain terminal. Each first source / drain terminal is connected to a common source line 708 formed on the front side 704. Each gate terminal is connected to a corresponding word line 714A, 714B, and 714C formed on the front side 704.

[0050] The backside 702 includes a plurality of MTJs 712A, 712B, and 712C. Each MTJ 712a to 712c may include a dielectric tunnel barrier layer 713b sandwiched between a fixedly magnetized magnetic layer 713a and a freely magnetizable magnetic layer 713c. The second S / D terminal of each access transistor 710A, 710B, and 710C extends into the backside 702 and is connected to a first terminal of a corresponding MTJ 712A, 712B, and 712C. The opposite terminal of the MTJs 712A, 712B, and 712C is connected to a bit line 706 formed on the backside 702.

[0051] Furthermore, the MRAM array 700 includes a sense amplifier 716 formed on the front side 704. The sense amplifier 716 includes a bit line input terminal 717, a reference input terminal 718, and an output terminal 720. The bit line input terminal 717 is connected to the bit line 706. The reference input terminal 718 is connected to a reference voltage source. The reading of a bit is performed by current sense amplifiers that compare the desired bit to a reference cell. The bit can be determined to be in a high or low state by evaluating the resistance of the cell relative to a reference cell using the sense amplifier.

[0052] Fig. Figure 13 shows a view of a first side (e.g., a front view) of a wafer 302, which, as Fig. 13, a transistor array 300, according to one or more embodiments. The front side 401 of the resulting transistor array 300 has one or more transistors 308 connected to the word line 310 and the source line 304. The transistors 308 may be configured as planar-type FETs or fin-type FETs (finFETs). The gate of each transistor 308 is in contact with the word line 310, and a first source / drain terminal of the transistor 308 is in contact with the source line 304 via a via 416. The second source / drain terminal of the transistor 308 is connected to one side of an MRAM element (in Fig. 13 not shown) formed on the opposite side (i.e., the backside) of wafer 302. Furthermore, a bit line 306 is formed on the backside of wafer 302 and is in contact with the second side of the memory element. Transistor array 300 may be fabricated through a series of manufacturing steps, as described in more detail below. Fig. 14 to 18 are illustrated.

[0053] Fig. 14 shows a transistor array intermediate stage 300 along line AA after completion of a middle-of-line (MOL) manufacturing process. The transistor array intermediate stage 300 includes a wafer 302 having a front side 401 and a back side 403. The front side 401 includes a buried oxide layer (BOX) 404 and an intermediate layer 406. The BOX layer 404 is made of various dielectric materials, such as SiO2, and has a thickness in the range of, for example, about 5 nm to about 50 nm. The intermediate layer 406 is formed on a first surface of the BOX layer 404 and is made of a semiconductor material, including, but not limited to, Si. The thickness of the intermediate layer 406 is, for example, in the range of about 2 nm to about 10 nm.

[0054] One or more transistors 308 are formed on a top surface of the intermediate layer 406. Each transistor 308 includes a gate structure 412, a first source / drain region 411, and a second source / drain region 413. The gate structure 412 includes a gate 408 disposed between a pair of opposing spacers 410. The gate 408 may be formed from an electrically conductive material, including, for example, tungsten (W), and the spacers may be formed from a nitride material, such as SiN.

[0055] The first S / D region 411 and the second S / D region 413 are formed on opposite sides of the gate structure 412. The first and second S / D regions 411 and 413 may be made of, for example, Si, germanium (Ge), SiGe, silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), the like, or a combination thereof. Various epitaxial growth methods may be performed to form the S / D region, including, but not limited to, metal organic CVD (MOCVD) epitaxy, molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. Furthermore, the epitaxial source / drain regions can be doped by in-situ doping during growth and / or subsequent implantation to a concentration higher than or equal to 5×10 19 cm -3The dopants may include, for example, boron, indium, or the like for a p-type transistor, and may include, for example, phosphorus, arsenic, and the like for an n-type transistor. The first S / D region 411 and the second S / D region 413 may be formed by various epitaxial growth techniques, including, but not limited to, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), and liquid-phase epitaxy (LPE) using a gaseous or liquid precursor, such as silicon tetrachloride.

[0056] The front side 401 further comprises a first ILD layer 414 and an electrically conductive via 416. The ILD layer 414 is formed on the upper surface of the intermediate layer 406 and encapsulates the transistors 308. The ILD layer 414 consists of a dielectric material, such as SiO2, and serves to electrically isolate the transistors 308 from each other. The via 416 extends through the ILD layer 414 and is in contact with the upper surface of the first S / D region 411. Accordingly, the source line (in Fig. 14 not shown) form an electrical connection with the first S / D region 411.

[0057] The backside 403 includes a second ILD 402 formed on an opposite side of the BOX layer 404. A piercing via 418 passes through the interlayer 406 and the BOX layer 404 to provide access to the backside 403. The piercing via 418 has a first end in contact with the second S / D region 413 of a given transistor 308 and a second end extending into the second ILD 402.

[0058] Fig. 15 shows the transistor array 300 after various BEOL processing techniques for creating the word line 310 and the source line 304 on the front side of the wafer 302. The source line 304 is formed by depositing a third ILD layer 420, consisting of, for example, SiO2, on a top surface of the first ILD 414. The third ILD layer 420 is patterned to form a cavity that exposes the underlying via 416. The cavity is filled with an electrically conductive material to form the source line 304, which is in contact with the via 416.

[0059] How Fig. As further shown in Figure 15, a fourth ILD layer 422, consisting of SiO2, for example, is deposited on a top surface of the third ILD layer 420 and covers the source line 304. The word line 310 is formed on the top surface of the fourth ILD layer 422 and is made of an electrically conductive material. The fourth ILD layer 422 serves to electrically isolate the word line 310 from the source line 304. Although a single word line 310 is shown, additional metal lines and vias may be formed depending on the application.

[0060] In Fig. 16, the transistor array 300 is flipped over after applying a bonding film 452 and a bulk handle wafer 454 to the top of the word line 310. Before flipping the transistor array 300 (i.e., from the front side 401 to the back side 403), the bonding film 452, which is made of an adhesive material or polyimide with a Si adhesive, is formed on the top surface of the word line 310. Alternatively, the bonding material may be an oxide-based or nitride-based film for dielectric bonding. The bulk handle wafer 454 is formed on the top surface of the bonding film 452. The bonding film 452 is formed on the top surface of the handle wafer 454 and then attached to the wafer 101. The bulk handle wafer 454 may be made of various materials, such as Si, and may provide additional support when performing one or more subsequent manufacturing processes.

[0061] Fig. 17 shows the transistor array 300 after removing the second ILD 402. The second ILD 402 may be removed, for example, by performing a chemical mechanical planarization (CMP) process that stops at a top surface of the BOX layer 404. Accordingly, a portion of the piercing via 418 is accessible at the surface of the BOX layer 404.

[0062] Fig. 18 shows the transistor array 300 as an MRAM array after creating an MRAM element 504 and the bit line 306. Although a single MRAM element 504 and bit line 306 are shown, it should be noted that additional MRAM elements and bit lines may be formed, corresponding to additional transistors 308n formed on the wafer 302.

[0063] The MRAM element 504 defines an MTJ capable of enabling magnetic storage to form an MRAM bit / cell. The MRAM element 504 is shown formed on top of a storage contact, for example, made of TaN. The MRAM element 504 may be fabricated by depositing a stack of MTJ layers 505a, 505b, and 505c onto the top surface of the BOX layer 404 and then patterning the MRAM stack such that a portion of the MRAM stack remaining on top of the storage contact 505 defines the MRAM element 504. The MTJ layers 505a through 505c include a tightly magnetized magnetic layer 505a, a dielectric tunnel barrier layer 505b, and a freely magnetizable magnetic layer 505c. The fixedly magnetized magnetic layer 505a and the freely magnetizable magnetic layer 505c are made of a ferromagnetic material.The dielectric tunnel barrier layer 505b is made of an oxide or metal oxide material, such as aluminum oxide (AlO2). The dielectric tunnel barrier layer 505b has a thickness that allows electrons to tunnel from the freely magnetizable magnetic layer 505c to the tightly magnetized magnetic layer 505a. Although three MTJ layers are described, it should be noted that the MRAM element 504 is not limited to this and may include additional MTJ layers.

[0064] A memory stack insulation film 506 is deposited on a top surface of the BOX layer 404 and corresponds to the outer surfaces of the MRAM element 504. The memory stack insulation film 506 is made of a nitride material, such as silicon nitride (SiN), and is deposited, for example, by a chemical vapor deposition (CVD) process. An etching process is performed to lower an upper portion of the memory stack insulation film 506 and expose the underlying MRAM element 504.

[0065] How Fig. 18 further shows, a fifth ILD layer 508, consisting of, for example, SiO2, is deposited on the memory stack insulation film 506 to encapsulate the MRAM element 504. Subsequently, the fifth ILD layer 508 is recessed to expose an upper surface of the memory stack insulation film 506. An RIE process may be performed to recess the fifth ILD layer 508 and may be continued until the upper surface of the memory stack insulation film 506 is removed and the underlying MRAM element 504 is exposed. Alternatively, a first etching process may be performed to lower the fifth ILD layer 508 until the upper surface of the memory stack insulation film 506 is exposed. Subsequently, another etching process (e.g.an etching process using a different chemistry) may be used to remove the top surface of the memory stack insulation film 506 and expose the underlying MRAM element 504.

[0066] Fig. 19 and Fig. 20 show a cross-sectional view of a semiconductor device intermediate stage 100 according to one or more embodiments of the invention. Fig. Figure 19 shows the semiconductor device intermediate stage 100 after the wafer 101 has been flipped over to expose the backside. The semiconductor device 100 includes a VTFET with a gate structure 113 sandwiched between a second S / D region 106 and a first S / D region 116.

[0067] The semiconductor device intermediate 100 further includes a buried insulator layer 450 on a top surface of the second S / D region 106 and an offset piercing via 455 extending through the buried insulator 450 to form contact with the second S / D region 106. In one or more embodiments of the invention, the buried insulator 450 and the offset piercing via 455 are formed on the front side of the wafer, i.e., before flipping the wafer 101 to expose the back side. The length of the second S / D contact 106 is greater than the length of the first S / D contact 116. In this way, the first S / D contact provides an extended portion 107 that extends beyond the first S / D contact 116 and supports a portion of one end of the offset piercing via 455. The buried insulator layer 450 may comprise a layer made of an oxide material, such as SiO2.The offset piercing via 455 may be made of an electrically conductive material, such as a metal material.

[0068] As in Fig. 20, an offset storage element 217 is formed on a top surface of the offset piercing via 455. The offset storage element 217 may include a storage contact 212 formed on a top surface of the offset piercing via 455 and a plurality of MTJ layers stacked on the storage contact 212. Fabrication of the offset storage element 217 may be performed by performing similar fabrication processes as used to fabricate the Fig. 9 and Fig. 10. A bit line 220 is formed on an upper surface of the ILD layer 219, which is in contact with an upper surface of the offset memory element 217 to form a completed MRAM semiconductor device 100.

[0069] Fig. 21 and Fig. 22 show a cross-sectional view of a semiconductor device intermediate stage 100 according to one or more embodiments of the invention. As Fig. As shown in Figure 21, the semiconductor device intermediate stage 100 includes a VTFET with one or more channel regions 110 extending between a second S / D region 106 and a first S / D region 116. A gate structure 113 surrounds the outer portions of the channel regions 110.

[0070] The semiconductor device intermediate stage 100 further includes a buried insulator layer 500. The buried insulator layer 500 is formed on a top surface of the second S / D region 106. The buried insulator layer 500 may be made of an oxide material, including, but not limited to, SiO2.

[0071] Fig. 22 shows a finished MRAM semiconductor device after forming a backside via / contact 502 formed on a top surface of the second S / D region 106. The backside via / contact 502 may be formed by removing a portion of the buried insulator layer 500 to form a cavity (not shown) exposing the top surface of the second S / D region 106. The cavity is then filled with an electrically conductive material, such as a metal material, to form the backside via / contact 502.

[0072] How Fig. 22 further shows, a memory element 217 is formed on a top surface of the backside via / contact 502. The memory element 217 may include a memory contact 212 formed on a top surface of the backside via / contact 502 and a plurality of MTJs stacked on the memory contact 212. Fabrication of the memory element 217 may be achieved by performing similar fabrication processes as used to form the Fig. 9 and Fig. 10. A bit line 220 is formed on an upper surface of the ILD layer 219 and is in contact with an upper surface of the memory element 217 to form the MRAM semiconductor device 100.

[0073] As described herein, various non-limiting embodiments of the invention address deficiencies of the prior art by providing an MRAM device with a backside memory architecture that overcomes MTJ height limitations that hamper conventional BEOL fabrication techniques. Furthermore, this backside memory architecture allows for routing a backside bitline along the edge of the memory array to the frontside, thereby further reducing the overall footprint of the MRAM device.

[0074] One or more embodiments of the present invention are described herein with reference to corresponding drawings. Alternative embodiments may be developed without departing from the scope. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and in the drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, with the described functionality being retained even when the orientation is changed. These connections and / or positional relationships may be direct or indirect, unless otherwise indicated, and the present invention is not intended to be limiting in this regard.Accordingly, a coupling between units may refer to a direct or an indirect coupling, and a positional relationship between units may be a direct or an indirect positional relationship. As an example of an indirect positional relationship, the description of forming a layer "A" above a layer "B" in the present description includes situations where one or more intermediate layers (e.g., layer "C") are arranged between layer "A" and layer "B," as long as the relevant features and functionalities of layer "A" and layer "B" are not substantially altered by the intermediate layer(s).

[0075] The following definitions and abbreviations are to be used for the interpretation of the claims and the description. As used herein, the terms "comprises," "having," "includes," "including," "has," "having," "contains," and "containing," and any other variations thereof, are intended to denote non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements, but may also include other elements not expressly listed or inherent in such composition, mixture, process, method, article, or device.

[0076] Furthermore, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." An embodiment or configuration described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or configurations. The terms "at least one" and "one or more" are intended to include any integer greater than or equal to one, i.e., one, two, three, four, and so on. The term "a plurality" is intended to include any integer greater than or equal to two, i.e., two, three, four, five, and so on. The term "connection" can include an indirect "connection" and a direct "connection."

[0077] The use of "an embodiment," "an embodiment," "an embodiment," etc., throughout the specification means that the described embodiment may include a particular property, structure, or feature, but each embodiment may or may not include the particular property, structure, or feature. Furthermore, such language does not necessarily refer to the same embodiment. Further, where a particular property, structure, or feature is described in connection with one embodiment, it is understood that it is within the skill of one skilled in the art to affect the property, structure, or feature in connection with other embodiments, whether explicitly described or not.

[0078] For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "above", "below" and derivatives thereof shall refer to the described structures and methods as oriented in the drawings. The terms "overlying", "on", "thereupon", "disposed upon", and "disposed above" mean that a first element, such as a first structure, is disposed on a second element, such as a second structure, with intervening elements, such as an interface structure, between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intervening conductive, insulating, or semiconducting layers.

[0079] The term "selective for," such as "a first element that is selective for a second element," means that the first element can be etched and the second element can act as an etch stop.

[0080] The terms "about," "substantially," "approximately," and variations thereof are intended to reflect the degree of error associated with the measurement of the particular quantity, based at least in part on the equipment available at the time the application is filed. For example, "about" may include a range of ± 8%, 5%, or 2% of a given value.

[0081] As noted herein, conventional processes associated with the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein for the sake of brevity. However, by way of background, a more general discussion of semiconductor device fabrication processes that may be employed in practicing one or more embodiments of the present invention will now be provided. Although specific fabrication steps employed in practicing one or more embodiments of the present invention may be individually known, the described combination of steps and / or the resulting structures are particular to the present invention.The particular combination of steps described in connection with the manufacture of a semiconductor device according to the present invention thus employs various, individually known physical and chemical processes carried out on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.

[0082] In general, the various processes used to fabricate a microchip that will be packaged into an IC fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, layers, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD).

[0083] A recess process includes any process, such as etching, grinding, etc., that removes material from the wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of different areas of the semiconductor substrate allows the substrate's conductivity to be altered by applying a voltage.

[0084] By creating patterns of these various components, millions of transistors can be manufactured and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the creation of three-dimensional relief images or structures on the semiconductor substrate for subsequent transfer of the structure to the substrate. In semiconductor lithography, the structures are formed using a light-sensitive polymer called a photoresist. To produce the complex structures that form a transistor and the numerous wires that connect the millions of transistors in a circuit, lithography and etching pattern transfer steps are repeated multiple times.Each structure printed on the wafer is aligned with previously formed structures so that the conductors, insulators, and selectively doped regions are slowly built up to form the finished unit.

[0085] The flowchart and block diagrams of the figures illustrate possible implementations of manufacturing and / or working methods according to one or more embodiments of the present invention. In the flowchart, various functions / work steps of the method are represented by blocks. In some alternative implementations, the functions represented in the blocks may occur in a different order than shown in the figures. For example, depending on the functionality involved, two consecutively shown blocks may actually be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order.

[0086] The description of one or more embodiments of the present invention has been provided for illustrative purposes and is not intended to be exhaustive or limited to the described embodiments. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments described herein.

Claims

[1] A method of manufacturing a memory unit, the method comprising: Forming, on a first side of a semiconductor wafer (101), a semiconductor device (100) having at least one gate structure (113) and a first source / drain region (116) at a first end of the at least one gate structure (113) arranged on the first side of the semiconductor wafer (101); Forming on the first side of the semiconductor wafer (101): a first electrically conductive element contacting the first source / drain region (116) to form a source line (152); and a second electrically conductive element electrically insulated from the source line (152), the second electrically conductive element defining a word line (154); Forming on a second side of the semiconductor wafer (101) opposite the first side: a memory element (214) on a first surface of a second source / drain region (106), and a third electrically conductive element contacting the memory element (214), the third electrically conductive element defining a bit line (220), wherein the storage element (214) is in electrical connection with the second source / drain region (106) of the semiconductor unit (100), wherein the second source / drain region (106) is different from the first source / drain region (116), wherein the second source / drain region (106) is formed on the second side of the semiconductor wafer (101) which is opposite to the first side, wherein the second source / drain region (106) has a second surface extending to the first side of the semiconductor wafer (101) and a second end, opposite the first end, contacting the at least one gate structure (113); wherein forming the storage element (214) comprises: Hollowing out the second side of the semiconductor wafer (101) to expose the first surface of the second source / drain region (106) opposite the second surface; Forming an electrically conductive storage contact (212) on the first surface of the second source / drain region (106) such that the electrically conductive storage contact (212) and the second source / drain region (106) are aligned in a same direction; and Forming the storage element (214) on the electrically conductive storage contact (212). [2] The method of claim 1, wherein forming the memory element (214) further comprises: Stacking a plurality of individual magnetic tunnel junction layers, MTJ layers, (215a-215c, 712A-712C) onto the electrically conductive storage contact (212); and Patterning the MTJ layers (215a-215c, 712A-712C) to form an MTJ memory element (217). [3] The method of claim 2, wherein stacking the plurality of individual MTJ layers (215a-215c, 712A-712C) comprises: Depositing a fixedly magnetized magnetic layer (215a, 713a) on a surface of the storage contact (212); Depositing a dielectric tunnel barrier layer (215b, 713b) on the fixedly magnetized magnetic layer (215a, 713a); and Depositing a freely magnetizable magnetic layer (215c, 713c) on the dielectric tunnel barrier layer (215b, 713b). [4] The method of claim 3, wherein the fixedly magnetized magnetic layer (215a, 713a) and the freely magnetizable magnetic layer (215c, 713c) are made of a ferromagnetic material and the dielectric tunnel barrier layer (215b, 713b) comprises an oxide material. [5] The method of claim 4, wherein the first source / drain region (116), the at least one gate structure (113) and the second source / drain region (106) are aligned along a vertical axis defining a vertical axis of a vertical type field effect transistor, VTFET. [6] Storage unit (100) comprising: a semiconductor wafer (101) extending along a horizontal axis to define a first side and a second side opposite the first side, and extending along a vertical axis to define a height of the semiconductor wafer (101); on a first side of a semiconductor wafer (101): a semiconductor device (100) having at least one gate structure (113) and a first source / drain region (116) at a first end of the at least one gate structure (113) arranged on the first side of the semiconductor wafer (101); a first electrically conductive element contacting the first source / drain region (116) to form a source line (152); and a second electrically conductive element electrically isolated from the source line (152), the second electrically conductive element defining a word line (154); on a second side of the semiconductor wafer (101) opposite the first side: a memory element (214) on a first surface of a second source / drain region (106), and a third electrically conductive element contacting the memory element (214), the third electrically conductive element defining a bit line (220), wherein the storage element (214) is in electrical connection with the second source / drain region (106) of the semiconductor unit (100), wherein the second source / drain region (106) is different from the first source / drain region (116), wherein the second source / drain region (106) is formed on the second side of the semiconductor wafer (101) which is opposite to the first side, wherein the second source / drain region (106) has a second surface, which extends to the first side of the semiconductor wafer (101) and has a second end, opposite the first end, in contact with the at least one gate structure (113); an electrically conductive storage contact (212) on the first surface of the second source / drain region (106) such that the electrically conductive storage contact (212) and the second source / drain region (106) are aligned in a same direction; and the storage element (214) on the electrically conductive storage contact (212). [7] The memory device (100) of claim 6, wherein the memory device comprises a plurality of individual magnetic tunnel junction (MTJ) layers (215a-215c, 712A-712C) stacked one above the other along the vertical axis to form a magnetic memory element. [8] The memory device (100) according to claim 7, wherein the plurality of MTJ layers (215a-215c, 712A-712C) comprise: a fixedly magnetized layer (215a, 713a) on a surface of the storage contact (212); a dielectric tunnel barrier layer (215b, 713b) on the fixedly magnetized layer (215a, 713a); and a freely magnetizable layer (215c, 713c) on the dielectric tunnel barrier layer (215b, 713b). [9] The memory device (100) according to claim 8, wherein the fixedly magnetized layer (215a, 713a) and the freely magnetizable layer (215c, 713c) are made of a ferromagnetic material and the dielectric tunnel barrier layer (215b, 713b) comprises an oxide material. [10] The memory device (100) of claim 9, wherein the oxide material is. [11] The memory unit (100) according to any one of claims 6 to 10, wherein the at least one gate structure (113) comprises a plurality of gate structures arranged between the first source / drain region (116) and the second source / drain region (106).

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