IMPROVED IN-SYSTEM TEST COVERAGE BASED ON COMPONENT DEGRADATION DETECTION

Abstract

Method (700) comprising: Performing (B710) several instances of a failure test on a hardware component (102) of a computer platform (100) by applying different values ​​of a physical operating parameter to the hardware component (102) for each of the instances; Determining (B720), from the results (208) of the several instances of the failure test, a value of the physical operating parameter at which the hardware component (102) transitions from passing the failure test to failing the failure test; Determining (730) a degradation rate (212), specifying a change magnitude of a limit value of the physical operating parameter at which the hardware component (102) is able to pass the failure test, wherein the change magnitude is relative to the elapsed time, based at least partially on the value of the physical operating parameter; Determining (740) that the degradation rate (212) exceeds a reference degradation rate;and determining one or more remedial measures based at least partly on the degradation rate (212) that exceeds the reference degradation rate.;

Description

BACKGROUND OF THE INVENTION

[0001] Computer chips and other circuit assemblies are typically tested by manufacturers before deployment and / or distribution to verify proper functioning and detect manufacturing defects. For example, computer chips can be tested using automated test equipment (ATE) before deployment. However, some chips develop defects after deployment due to various factors (e.g., environmental hazards, aging, etc.), and in many applications, field fault detection capabilities are critical. For instance, safety requirements for autonomous functionalities specify that components must maintain a fault-tolerant time interval (FTTI) of 100 milliseconds, which represents the permissible time between the occurrence of a permanent fault and the execution of a corrective action.

[0002] Conventionally, an in-system test (IST) can be used to detect the occurrence of a permanent fault as it arises, in order to comply with a FTTI (Field-Time To Inventory). Even if a hardware component—for example, an integrated circuit (IC)—passes an IST, latent defects may exist in the component or its connections, evolving over time. As these latent defects develop, the component may typically produce proper outputs—but occasionally incorrect outputs—so the fault check will not detect permanent faults. Therefore, the autonomous vehicle may operate with some erroneous outputs that could compromise vehicle safety until the latent defects develop into a permanent fault detectable by an IST system. SUMMARY OF THE INVENTION

[0003] Exemplary embodiments of the present disclosure relate to improved coverage of in-system tests based on the detection of component degradation. In some aspects, systems and methods are disclosed that enable the determination of a degradation rate of a performance characteristic associated with a hardware component from the results of multiple instances of a failure test on the hardware component over time. The degradation rate can be used to predict permanent failures before they occur and / or to implement one or more corrective actions.

[0004] In some aspects, a hardware component's performance characteristics (e.g., Vmin, leakage current, etc.) can be monitored over time through fault testing and used to calculate the component's degradation rate. If the degradation rate exceeds a reference rate, one or more corrective actions can be implemented. The reference rate may represent a typical degradation rate for a given age and / or usage period of the hardware component. An unusually high degradation rate for the age and / or usage may indicate that the hardware component is approaching a permanent failure.

[0005] In other aspects, a performance characteristic can correspond to a threshold value (e.g., Vmin) of a physical operating parameter (e.g., a supply voltage, an operating clock frequency) at which a hardware component is able to pass a fault test. To detect (e.g., estimate) the threshold value, multiple instances of the fault test can be executed on the hardware component, using different values ​​of the physical operating parameter for each instance. From the fault tests, the system can determine a value of the physical operating parameter that corresponds to a transition between the hardware component that passed the fault test and the component that failed, and thus corresponds to the threshold value. The threshold value can be, for example,The acceptable range lies between a value of the physical operating parameter at which the hardware component passed the fault test and a value of the physical operating parameter at which the hardware component failed the fault test. Furthermore, one or more machine learning models can be trained to predict permanent faults based on system data such as fault test results, degradation rates, environmental data, etc. List of characters

[0006] The systems and methods presented here for improved in-system test coverage based on the detection of component degradation are described in detail below with reference to the accompanying figures: Fig. 1 is an example computing platform for predicting permanent faults in hardware components according to some embodiments of the present disclosure; Fig. Figure 2 is a flowchart showing a process for predicting permanent defects in hardware components according to some embodiments of the present disclosure; Fig. Figure 3 shows an exemplary table that covers aspects of performing multiple instances of a fault test on a hardware component according to some embodiments of the present disclosure; Fig. Figure 4 is a diagram which, according to some embodiments of the present disclosure, shows the relationships between the operating speed of hardware components and the limit values ​​of a physical operating parameter; Fig. 5A is an example of an eye diagram for a physical connection of a hardware component according to some embodiments of the present disclosure; Fig. 5B is an example of an eye diagram for the physical connection of the hardware component of Fig. 5A with degradation to a performance characteristic, according to some embodiments of the present disclosure; Fig. Figure 6 is an illustration that includes an example of a machine learning model of a permanent error predictor according to some embodiments of the present disclosure; Fig. Figure 7 is a flowchart showing a method for predicting permanent faults in hardware components based on several iterations of a fault test according to some embodiments of the present disclosure; Fig. Figure 8 is a flowchart showing a method for predicting permanent faults in hardware components using values ​​of a performance characteristic according to some embodiments of the present disclosure; Fig. Figure 9A shows an example of an autonomous vehicle, according to some embodiments of the present disclosure; Fig. 9B shows an example of camera positions and fields of view for the autonomous example vehicle from Fig. 9A according to some embodiments of the present disclosure; Fig. 9C is a block diagram of an example system architecture for the autonomous example vehicle from Fig. 9A according to some embodiments of the present disclosure; Fig. 9D is a system diagram for the communication between the cloud-based server(s) and the autonomous example vehicle from Fig. 9A according to some embodiments of the present disclosure; and Fig. Figure 10 is an example block diagram for a computing device suitable for implementing embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0007] Embodiments of the present disclosure relate to improved coverage of in-system tests based on the detection of component degradation. Systems and methods are disclosed that make it possible to determine a degradation rate of a performance characteristic associated with a hardware component from the results of multiple instances of a failure test performed on that component over time. The degradation rate can be used to predict permanent failures before they occur and / or to determine one or more other corrective actions.

[0008] The disclosure provides approaches for predicting permanent failures in hardware components and / or connections to hardware components of a computer platform (e.g., an autonomous vehicle) before they occur. This allows one or more corrective actions to be taken to improve the safety of the computer platform before a permanent failure occurs. According to the disclosure, a degradation rate of a performance characteristic associated with the hardware component can be determined, detected, and / or calculated to identify corrective actions that can be implemented.

[0009] While a performance characteristic often deteriorates over time (e.g., Vmin while still within a safe operating range), an abnormal degradation rate has been shown to be an effective indicator of an impending permanent failure. Therefore, the disclosed approaches can determine and / or detect when the degradation rate is greater than a reference degradation rate and, accordingly, implement corrective measures. For example, embodiments of the disclosure can utilize the observation that some types of latent defects deteriorate with increasing degradation rate as a permanent failure approaches, and therefore, recognizing that the performance characteristic (e.g., Vmin) is deteriorating too rapidly can be used to predict an impending permanent failure.Similarly, embodiments of the disclosure can utilize the observation that determining when the performance characteristic deteriorates at a sufficiently faster degradation rate than is typical for the age of the component can be used to predict an impending permanent failure.

[0010] In some aspects of this disclosure, the performance characteristic can be a limit value (also referred to as a physical operating parameter limit value) of a physical operating parameter at which a hardware component is able to pass a fault test. The performance characteristic can be, for example, a minimum supply voltage at which the hardware component can pass the fault test. In some embodiments, the limit value can be detected (e.g., estimated) by performing multiple instances of the fault test on the hardware component by applying different values ​​of the physical operating parameter to each instance (in other embodiments, physical operating parameters can remain fixed).From the fault tests, the system can determine a value of the physical operating parameter that corresponds to a transition between the hardware component that passed the fault test and the one that failed, and therefore to the limit value. This value can be used to determine the degradation rate of the performance characteristic, for example, by calculating how much the performance characteristic has changed over the lifetime of the component and / or the system. The degradation rate can also be calculated from a measurement that indicates the operating time of the hardware component, such as the mileage of a vehicle, the runtime of the system and / or the component, and / or the number of calculations performed by the component.

[0011] In some embodiments, the degradation rate can be calculated using at least one previous value of the physical operating parameter, determined at an earlier point in the hardware component's lifetime, along with corresponding measurement values. For example, the previous values ​​can be determined similarly to the value of the physical operating parameter, and these previous values ​​can be used to periodically determine and monitor the degradation rate relative to a reference degradation rate. As another example, a previous value could be a predetermined value assigned to a specific start point in the hardware component's lifetime, such as a value the component was designed to operate at when used on a computer platform.

[0012] If it is determined that the degradation rate exceeds a reference degradation rate, one or more corrective actions can be taken. The reference degradation rate might, for example, correspond to an expected degradation rate for the component given its age. For instance, a reference degradation rate could be based on a measurement indicating the operating time of the hardware component up to a point in time at which the degradation rate was determined. In some examples, the measurements could be divided into ranges, and each range could use the same reference degradation rate. In other examples, the reference degradation rate could be calculated using a function or model that determines the reference degradation rate based on a given measurement and / or other factors.For example, reference degradation rates can be determined based on the degradation rates of hardware components that are similar to the hardware component (e.g., share a common design with or have the same design as the hardware component) at different points in time during the component's lifetime. The reference degradation rates can be determined, for example, by calculating statistics on degradation rates at various times and / or usage levels for the components. In this way, the reference degradation rates used can correspond to what is typical or expected, considering how long and / or how much the hardware component has been operated.

[0013] In other aspects, when performing multiple instances of a failure test on a hardware component, the values ​​can be determined based on one or more properties associated with the hardware component by applying different values ​​of a physical operating parameter to each instance. For example, the system can measure the temperature(s) of the hardware component (e.g., using an internal sensor) and use the temperature(s) to determine the values. Alternatively, the system can additionally or alternatively determine the operating speed of the hardware component and use this speed to determine the values. The operating speed could be, for example, a hard-coded value read from memory, or it could be an operating speed index that evaluates the operating speed of the hardware component relative to other hardware components on a computer platform.By determining the values ​​of the physical operating parameter based on one or more characteristics, the system can account for variables that influence the limit of the physical operating parameter for the hardware component. For example, a hardware component's minimum supply voltage may decrease with increasing temperature and / or operating speed. In some examples, the one or more characteristics are used to look up one or more of the various values ​​used for fault checking in a table and / or to calculate one or more of these values.

[0014] Various types of fault tests can be used to test different types of performance characteristics as disclosed herein. In some examples, one or more fault test parameters are input into the hardware component to generate one or more outputs from the hardware component. The one or more outputs may include logical output(s), and the hardware component may pass the fault test if the logical output(s) match an expected logical output(s). For example, logical outputs can be tested if the fault test includes a scan test performed at a specific frequency, such as a Fast Test Mode Scan (FTM2CLK). As another example, logical outputs can be tested if the fault test includes a built-in self-test (BIST) of a memory device, such as Memory BIST (MBIST). The scan test may, for example,It can be used when the shutdown value of the physical operating parameter corresponds to a minimum supply voltage.

[0015] According to certain aspects of the present disclosure, the values ​​of the physical operating parameter that are varied can be representative of an operating clock frequency of the hardware component. Furthermore, the limit of the physical operating parameter for the hardware component can be a maximum operating clock frequency of the hardware component. With this approach, permanent failures can be predicted by detecting subtle gate defects in individual gates that are normally undetectable. For example, a scan test may not be sensitive enough to detect degradation in a multi-rib logic gate caused by damage to a single rib. These subtle gate defects can worsen over time and cause a permanent failure.By performing multiple instances of a scan test on the hardware component by applying different values ​​of the operating clock frequency to the hardware component, changes in the maximum operating clock frequency can be detected in order to account for such subtle errors.

[0016] In other aspects of this disclosure, in addition to or instead of a fault test that evaluates a logical output (or outputs) of the hardware component to distinguish between passing or failing the fault test, a performance characteristic determined by a fault test can correspond to an electrical characteristic of an output (e.g., a non-logical output characteristic) of the hardware component. For example, to predict a permanent electrical fault associated with electrostatic discharge and electrical overload, the fault test can be used to measure a leakage current at given values ​​of the physical operating parameters. In this example, the degradation rate can be evaluated with respect to the reference leakage current.

[0017] Aspects of this disclosure enable in-system testing of physical interfaces, such as printed circuit board (PCB) interfaces with hardware components at the system level. High-speed interfaces—such as Express interfaces of peripheral components—can become faulty over time due to events such as reference clock jitter, PCB trace corrosion, and component I / O degradation. Aspects of this disclosure enable the prediction of such permanent faults before they occur. According to this disclosure, such permanent faults can be predicted using a fault test that includes parametric testing of high-speed interfaces (HSI)—for example, and without limitation, via eye diagrams—to determine a performance characteristic corresponding to the edges of the eye openings.In such examples, the degradation rate of the performance characteristic corresponds to changes in a margin (or margins) of an eye opening. In embodiments, the parametric test may involve measuring and tracking the rate of change of the height and / or width of the eye openings in an eye diagram over time to determine whether one or more corrective actions are required.

[0018] Aspects of this disclosure may be further provided for the prediction of permanent defects using one or more machine learning models. For example, one or more machine learning models may output predictive data representing one or more confidence levels with respect to one or more predictions of one or more permanent defects. According to non-limiting embodiments, the machine learning model(s) may comprise a multi-parameter machine learning model. The multi-parameter machine learning model can continuously learn and improve the actual defect prediction based on usage, environment, etc.

[0019] Fig. Figure 1 shows an example computer platform 100for predicting permanent faults in hardware components according to some embodiments of the present disclosure. It should be understood that these and other arrangements described herein are presented only as examples. Other arrangements and elements (e.g., components, interfaces, functions, arrays, systems, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional units that may be implemented as discrete or distributed components, or in conjunction with other components, and in any suitable combination and arrangement. Various functionalities described herein, which are performed by units, may be executed by hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in memory.For example, the computing platform can . 100 and / or a degradation detection system 104 of which on one or more instances of the computing device 1000 from Fig. 10. Various functions described herein can be performed by one or more hardware components; for example, the degradation detection system. 104 and the hardware components 102A , 102B and / or 102N be implemented on one or more system-on-a-chips (SoCs).

[0020] The present disclosure may relate to the computing platform 100 described, which are in an exemplary autonomous vehicle 900 (hereafter referred to as “vehicle” 900 “or “autonomous vehicle” 900 “” is implemented, of which an example is given herein in relation to the Fig. 9A-9D is described. Although the present disclosure provides examples with autonomous vehicles, other types of objects and / or systems can also utilize the computing platform. 100 implement. For example, the systems and methods described herein can be used in high-performance computer servers, in augmented reality, virtual reality, robotics and / or other technology areas.

[0021] The computer platform 100 The hardware component(s) can be one of the elements. 102A , 102B and / or 102N (also as hardware component(s)) 102 designated) and the degradation detection system 104 include the degradation detection system. 104 can a control 122 , a fault tester 106 , a performance characteristic determiner 108 , an operating parameter determiner 110 , a test parameter determiner 112 , a degradation rate determiner114 , a degradation rate analyzer 116 , a remediation administrator 118 and a permanent error predictor 120 include.

[0022] Examples of hardware components 102 They can include an integrated circuit, a system-on-a-chip (SoC), a storage device, a logic circuit, a semiconductor chip, and / or another physical component, or a combination thereof. In at least some embodiments, the computing platform can 100 be implemented in an autonomous vehicle, such as the autonomous vehicle 900 the Fig. 9A-9D, and the hardware components 102 These components may include those used to determine vehicle controls in an advanced driver assistance system (ADAS) and / or autonomous driving system. Each of the hardware components 102It can be part of the same circuit and / or different circuits. Furthermore, each of the hardware components can... 102 communicative with the system 104 It must be coupled for the detection of degradation.

[0023] Although the hardware components 102 which can be described and represented as a multitude of hardware components, in at least one embodiment the degradation detection system 104 can be used to detect the degradation of a single hardware component and / or the computer platform 100 can have any number of instances of the degradation detection system 104 and / or components thereof. In at least one embodiment, one or more instances of the degradation detection system may be included. 104 and / or parts thereof are located on the same integrated circuit (IC) as one or more of the hardware components 102For example, a fault tester 106 correspond to a built-in self-test (BIST) of an IC and / or device that uses a corresponding hardware component 102 includes, for example, a storage device.

[0024] The degradation detection system 104 can be configured to prevent hardware component(s) degradation 102 to detect. The degradation detection system 104 As shown, it can communicate with the hardware components. 102 must be coupled (e.g., directly or indirectly) to perform one of the various functionalities described here. In at least some embodiments, the degradation detection system can 104 into an IST system of the computer platform 100 be integrated.

[0025] The test control 122 of the degradation detection system 104can be configured to perform each of the various functionalities of the degradation detection system described here. 104 coordinates and controls. For this purpose, the control system can be used. 122 any combination of the components of the degradation detection system 104 use.

[0026] Referring to Fig. 2 with Fig. 1 is Fig. 2. A flowchart illustrating a process 200 for predicting permanent defects in hardware components according to some embodiments of the present disclosure. As shown in Fig. As indicated in point 2, the error tester can 106 of the degradation detection system 104 be configured to perform fault tests on one or more of the hardware components 102 , such as the hardware component 102A , to be carried out. When applying a fault test to the hardware component 102A Can the degradation detection system104 the operating parameter determiner 110 use to determine one or more physical operating parameters that serve as inputs during the fault test 204 on the hardware component 102A to be applied, and / or the test parameter determiner 112 , to determine one or more test parameters to be used as inputs during the fault test 204 on the hardware component 102A to be applied. As a result, the hardware component 102A one or more expenses 206 generate, and the error tester 106 can result in one or more 208 of the error test, based at least partially on the measurement and / or evaluation of the outputs 206 As in Fig. As indicated in section 2, in at least some embodiments the error test can be repeated for multiple instances, and the results 208can be based on the results for the multiple instances.

[0027] The performance characteristic determiner 108 can be used to specify a value (values) 210 a performance characteristic of the hardware component 102A based on the hardware component fault test 102 to determine. The degradation rate determiner 114 can be configured to have a degradation rate 212 the performance characteristics of the hardware component 102 at least partially based on the value(s) 210 to determine the performance characteristics (e.g., based on a change in the performance characteristic values ​​over time). The degradation rate analyzer 116 can be configured to control the degradation rate 212 to analyze the performance characteristics, e.g., based on a comparison of the degradation rate with a reference degradation rate, in order to obtain analysis results. 214to generate. The remediation administrator 118 can be configured to implement one or more corrective actions that are at least partially based on the analysis results 214 of the degradation rate determiner 114 based (e.g., based on a determination that the degradation rate exceeds the reference degradation rate).

[0028] Although in Fig. 2 not shown, in at least one embodiment the permanent error predictor 120 be configured to detect a permanent fault in the hardware component 102 based at least partially on a multitude of input signals and / or data from the computer platform 100 to predict, for example, data corresponding to the degradation rate of the hardware component. In at least one embodiment, the remediation manager can 118Implement one or more corrective actions based at least partially on one or more predictions (e.g., based on one or more confidence levels) of the permanent error predictor 120 In at least one embodiment, the permanent error predictor can 120 with the remediation administrator 118 regardless of the process 200 be used.

[0029] The fault tester 106 of the degradation detection system 104 can be configured to perform fault tests on one or more of the hardware components 102 to perform. When performing a fault test, the fault tester can 106 Apply one or more operating conditions, test parameters, physical operating parameters, and / or other inputs to one or more of the hardware components. The input(s) to the hardware component(s) 102 the hardware component(s) can 102cause one or more expenses, such as the expenses 206 , to determine and / or generate. The one or more outputs of the hardware component(s) can correspond to one or more results (also referred to as "results") and / or be used to determine results of the fault test, such as the results 208 .

[0030] In at least one embodiment, the results of a fault test of a hardware component(s) include: 102 Data indicating whether the hardware component(s) 102 has passed the error test or not. For example, the error tester 106 Hardware and / or software for testing the hardware component(s) 102and include evaluating one or more outputs from the hardware component(s) to determine whether the fault test passes or fails. The one or more outputs being evaluated may include one or more logical outputs and / or one or more physical outputs (e.g., current levels, voltage levels, resistance levels, etc.). In exemplary embodiments where the fault tester 106 evaluating one or more logical outputs, the hardware component(s) 102 Determining the passing of an instance of a fault test is at least partially based on the fact that the fault tester 106 determines that the logical output(s) match an expected logical output(s). In exemplary implementations where the error tester 106 If one or more logical outputs are evaluated, the hardware component(s) 102a failure of an instance of a fault test, at least partially based on the finding of the fault tester 106 Determine that the logical output(s) do not match an expected logical output(s).

[0031] For example, the error tester 106 Test logical outputs when a fault test includes a scan test performed while a hardware component is 102 (which includes, for example, one or more logic gates that generate the logical outputs) is operated at a specific operating frequency, such as a Fast Test Mode Scan (FTM2CLK). Another example is the fault tester. 106 Test logical outputs when the hardware component(s) 102 a storage device includes / include and an error test includes a BIST, such as a storage BIST (MBIST).

[0032] In exemplary implementations where the fault tester 106If one or more physical outputs are evaluated, the hardware component(s) 102 one or more outputs of the hardware component(s) 102 to measure in order to determine whether an instance of a fault test has passed, based at least in part on the finding of the fault tester 106 that one or more of the physical outputs exceed or do not exceed a threshold. In exemplary embodiments where the fault tester 106 If one or more physical outputs are evaluated, the hardware component(s) 102 also one or more outputs of the hardware component(s) 102 to measure in order to determine a failure of an instance of a fault test that is based at least partially on the fault tester 106 determines whether one or more of the physical outputs exceed or do not exceed a threshold. For example, the fault tester can 106Determine a failure of a fault test if the leakage current from the hardware component(s) 102 exceeds a threshold value. In at least one embodiment, the fault tester can 106 one or more outputs of the hardware component(s) 102 not evaluate from a fault test. Likewise, in at least one embodiment, a fault test result, such as the result, includes 208 , a level (e.g., a measured value) of a physical output from the hardware component(s) resulting from the fault test, or equivalent to this. A fault test result could, for example, be a leakage current level from the hardware component(s). 102 include.

[0033] A test parameter can refer to an input that the error tester provides. 106 on a hardware component(s) 102applies to an instance of a fault test that relates to one or more expected outputs of the hardware component(s) 102 affects those affected by the error tester 106 They are evaluated to determine whether the error test passes or fails. For example, the criteria used by the error tester can be... 106 The evaluation of whether an output(s) leads to a pass or fail error test depends on which test parameters are applied to the hardware component. 102 can be applied. One or more test patterns of a BIST are examples of test parameters for a fault test. Other examples of test parameters for a fault test are one or more test sequences of a scan test. Another example of a test parameter is one or more physical inputs to the hardware component(s). 102 , which affect criteria used by the error tester 106They are used to evaluate whether an output(s) will result in a pass or fail error test, e.g., which threshold(s) are compared to a physical output level(s).

[0034] A physical operating parameter can refer to one or more inputs to a hardware component. 102 supplied, which controls the operating conditions under which the hardware component(s) 102 generated one or more outputs of a fault test without one or more expected outputs from the hardware component(s) 102 to influence the error tester 106 They are evaluated to determine whether the fault test passes or fails. An example of a physical operating parameter is a supply voltage applied to a hardware component during a BIST (Business Observation Test). 102is created, which has no influence on the criteria used by the fault tester to assess whether the hardware component 102 Whether or not the BIST has passed. For example, the hardware component 102 be able to generate a correct output(s) for each instance of a fault test, as the value of a physical operating parameter applied during the fault tests increases or decreases, until a certain value is reached at which the hardware component 102 It may begin to generate false output(s) from instances of the fault test. Such a value can correspond to a threshold value (e.g., Vmin) of the physical operating parameter at which the hardware component is able to pass the fault test.

[0035] In at least one embodiment, the fault tester can 106Run multiple instances of a fault test to determine a degradation rate for a performance characteristic of the hardware component(s). 102 to determine. Each instance of the fault test can include a registration of one or more physical operating parameters and / or one or more test parameters to determine one or more outputs from the hardware component(s). 102 to generate. In various examples, multiple instances of the fault test can use the same physical operating parameters and / or test parameters and / or operate with different physical operating parameters and / or test parameters. The fault tester can then 106 the operating parameter determiner 110 use to determine which physical operating parameter(s) to apply, and the test parameter determiner 112 , to determine which test parameter(s) should be applied to the hardware component(s) 102 is / are applicable.

[0036] Fig. Figure 3 shows an example table. 300 , which covers aspects of performing multiple instances of a fault test on a hardware component. The table in Fig. 3 shows the test levels 302 , 304 , 306 , 308 and 310 , which are represented as columns in Table 300. Also in Fig. The test runs are shown in section 3. 316 , 318 , 320 and 322 , which are represented as rows in Table 300. A degradation rate system 104 The test run performed can include one or more test stages, and the process 200 from Fig. 2 can be performed for each test run. In at least one embodiment, the results of a test run include one or more results from each test stage or are based on them. In such examples, the results can 208 from Fig. 2 correspond to a set of results from test stages performed in a test run. In at least one embodiment, the process can 200 from Fig. 2 correspond to a single test run and a multitude of test stages.

[0037] According to the embodiments described in the present disclosure, a test stage can include one or more instances of the fault tester. 106 These include elements that perform a fault test and determine its results. Within a test stage, each instance of the fault test can apply the same set of inputs to the hardware component(s) under test. 102 apply. Furthermore, the error tester can 106 , when he assesses whether the hardware component(s) 102 Whether the error test passes or fails, use the same set of evaluation criteria to determine the output of the hardware component(s). 102to evaluate in order to determine pass or fail. However, across the various test stages, one or more of the test parameters and / or physical operating parameters relating to the hardware component(s) may fail. 102 They can be applied differently. Fig. For example, V1, V2, V3, V4 and Vsafe represent the test levels. 302-310 The values ​​represent different values ​​of the physical operating parameters applied during a corresponding test stage, the value of which increases from left to right. In at least one embodiment, the test parameters applied during each state can remain fixed.

[0038] In Fig. Each test run includes 3 parts. 316-322 an instance of the error tester 106 , each of the test levels 302-310performs a test where an upper cell of a given instance and test stage represents a value of a physical operating parameter applied in the test stage, and a lower cell represents the results of individual instances of the fault test within the test stage. For example, the test run includes 318 an instance 328 the test stage 304 and a cell 330A represents a value of a physical operating parameter that is used during the instance 328 is applied (e.g. 470 millivolts) and a cell 330B represents results of individual instances of the error test within the test stage 304 for the instance 328 .

[0039] In at least one embodiment, the fault tester generates 106A test stage result is derived from the results of multiple instances of the fault test within that test stage. A test stage result can be more stable if it is based on multiple instances of a fault test rather than a single instance, thus improving the stability of the degradation detection system. 104 can be improved in at least one embodiment. For example, the test stages include 302-310 in Fig. 3. Five iterations of each fault test are performed, with the individual results of a fault test being represented in Table 300 by an "F" or a "P". An "F" indicates a failure of an instance of a fault test and a "P" indicates a pass of the fault test, as determined by the fault tester. 106 determined. Thus, in the instance 328 the test stage 304 the hardware component(s) 102 failed the error test twice and then passed the error test three times.

[0040] In at least one embodiment, the fault tester determines 106 a The result of a test stage is a pass, based at least partially on a majority of the embodiments of the fault test within the test stage that lead to a pass, and can determine a fault, based at least partially on a majority of the embodiments of the fault test within the test stage that lead to a fault. For example, the instance 328 as passed for the test level 304be determined. In embodiments where the results of a fault test include or correspond to one or more levels of physical outputs of the hardware component(s), the result of an instance of the value for a test stage may be based at least partially on one or more statistical values ​​calculated by the fault tester from the individual physical output levels of the multiple instances of the fault test (e.g., an average, a mode, a median, etc.).

[0041] As described here, the results of a test run (e.g., the results) can be 208 from Fig. 2), how the test run 318 , corresponding to the results of one or more test stages of the test run. The performance characteristic determiner 108 can be a performance characteristic of the hardware component(s) 102at least partially determined based on the results of a test run. As described here, the performance characteristic can correspond to a limit value of a physical operating parameter at which a hardware component 102 is able to pass an error test.

[0042] The performance characteristic determiner 108 can analyze the results of multiple instances of the fault test of a test run to detect and / or estimate the threshold value, which is based at least partially on a value of the physical operating parameter at which the hardware component 102 from passing the error test to failing the error test (e.g., at different test levels). For example, during the test run, the probability increases. 318 from Fig. 3 a value of the physical operating parameter applied during the fault test, from test stage 302 to 310. Between the test levels 302and 304 The hardware component 102 The system transitions from failing the fault test to passing the fault test and continues to pass the fault test if the value of the physical operating parameter is further increased. For example, the limit value (e.g., Vmin) of the physical operating parameter (e.g., a supply voltage) for the hardware component can be set. 102 e.g. less than or equal to 470 millivolts and 440 millivolts.

[0043] In at least one embodiment, the performance characteristic determiner 108 Determine the value corresponding to the limit as the value that is applied in the test stage in which the hardware component 102 transitions to a passing grade in the fault test (e.g., 470 millivolts), or a value between the pass and fail values, such as an average of the values ​​in the test stages. 302 and 304applied values ​​(e.g., 455 millivolts). Although an example supply voltage is provided, a power characteristic can correspond to any one or more other types or physical operating parameters.

[0044] As in Fig. As shown in section 3, the degradation detection system can be used. 104 Perform any number of test runs over time. Each test run can correspond to a different operating time during which a hardware component is used. 102 was operated until the degradation detection system 104 performs a test run. For example, test runs can be performed periodically and / or at irregular times or intervals. In at least one embodiment, the degradation rate system performs 104 a test run that is at least partially based on a measurement that covers an operating time during which the hardware component 102was operated, represents or corresponds to it, such as a distance traveled (e.g. mileage) by a vehicle or other object that the computing platform 100 houses, a runtime of the computing platform 100 and / or the hardware component 102 and / or a number of calculations and / or operations performed by the hardware component 102 were carried out.

[0045] Fig. For example, 3 represents a mileage of 0 kilometers during a test run. 316 , 100 Kilometers during test run 318 , 1,000 kilometers during test run 320 and 10,000 kilometers during the test run 322 during the test runs 316-322 As shown, any number of intermediate test runs can be performed by the degradation detection system. 104 It appears that tests have been carried out that are not shown. In at least one embodiment, the degradation rate determiner can be used.114 Determine a degradation rate for each test run, based at least partially on one or more values ​​of a performance characteristic determiner for the test run (determined by the performance characteristic determiner). 108 ) and one or more previous values ​​of the performance characteristic. The one or more previous values ​​can be derived from one or more previous test runs. Furthermore, the degradation rate can correspond to the amount of change in the performance characteristic relative to an elapsed time or operating duration.

[0046] For example, if the degradation rate determiner 114 is used to simulate component degradation for the test run 320 To determine a performance characteristic for Fig. 3. Correspond to a limit value (e.g., Vmin) of the physical operating parameter at which the hardware component is able to pass the fault test. As described here, the power characteristic determiner can 108 for the test run 318 Determine 470 millivolts as a value of the power characteristic. Using a similar approach, the power characteristic determiner can 108 for the test run 320 Determine 580 millivolts as a value for the power characteristic.

[0047] For example, during the test run 320 the transition between passing and failing the test levels 306 and 308 , which indicates that the limit has deteriorated over time due to the hardware component 102 A higher voltage is required to pass the fault test. In at least one embodiment, the degradation rate determiner can 114the degradation rate for the test run 320 as a difference between the value of the performance characteristic divided by a difference between measurements representing operating times of the hardware component 102 up to the test runs 318 and 320 The degradation rate can be calculated based on the operation of the system. In the example provided, the degradation rate can be (580mV - 470mV) / (1000km - 100km) = approximately 0.12 mV / km.

[0048] The degradation rate determiner 114 Similarly, it can determine degradation rates for different test runs, and the degradation rate analyzer 116 It can analyze each of the different degradation rates in order to monitor the degradation rates over time. In at least one embodiment, the degradation rate analyzer can 116It should be configured to analyze the degradation rate(s) of a performance characteristic, for example, based on comparing a degradation rate with a reference degradation rate to generate analysis results. The reference degradation rate can be a typical degradation rate for a given age and / or usage level of the hardware component. 102 corresponding to, and / or for a hardware component where there is no risk of developing a permanent defect. Different reference degradation rates can be used for comparison with other degradation rates, e.g., based on the measurement(s) that represent an operating lifetime of the hardware component. 102This represents (e.g., determined by applying the measurement to a lookup table or function), and / or the same degradation rate can be used for different degradation rates. For example, the same degradation rate can be used to monitor short-term degradation rates, while different degradation rates can be used to monitor longer-term degradation rates that correspond to the age and / or usage (e.g., overall age and / or usage) of the hardware component. 102 A short-term degradation rate can be useful to identify a hardware component that is close to a permanent failure, and a longer-term degradation rate can be useful to identify an abnormal hardware component.

[0049] The analysis results 214may include one or more signals and / or indicators that one or more degradation rates have been exceeded, and one or more remedial measures to be implemented by the remedial manager. 118 Actions taken can be based, at least in part, on a type of reference degradation rate that has been exceeded (e.g., short-term or long-term), a number of degradation rates that have been exceeded, and / or other factors. For example, an action for exceeding a long-term degradation rate might cause an engine warning light to illuminate and / or indicate that a part should be replaced. An action for exceeding a short-term reference degradation rate might involve triggering one or more functions of the hardware component. 102 equivalent to an autonomous vehicle, such as autonomous driving, until a part is replaced.

[0050] Various types of remedial measures are considered, which are to be implemented by the Remedial Administrator. 118 This can be initiated. Examples include disabling one or more functions of the computer platform. 100 , such as a function that is linked to the hardware component 102 is executed. In exemplary implementations where the computer platform 100 an automated driving system of the vehicle 900 the Fig. 9A-9D, one or more remedies may disable the vehicle's autonomous driving function. 900 and / or include one or more ADAS functions. Further examples of corrective measures include initiating the display of an indicator (or indicators) for the degradation rate(s) exceeding the reference degradation rate(s). The indicator may be a display on a dashboard and / or instrument panel of the autonomous vehicle. 900These include, for example, a "Check Engine" warning light, a message on a screen or head-up display (e.g., of the vehicle). 900 the Fig. 9A-9D) etc. Other examples include acoustic indicators such as an audible warning signal, automated scheduling of a repair service for the computer platform 100 , automated controls of the autonomous vehicle 900 (e.g., to pull the vehicle to the side of the road or to drive it to a specific location such as a repair shop), etc. Other examples of corrective actions include marking or creating an entry in a log on the computer platform. 100 , e.g. in a system log and / or a file.

[0051] According to further aspects of the present disclosure, the operating parameter determiner 110Determine a value (values) of a physical operating parameter (physical operating parameter) for a fault test, which is based at least partially on one or more properties associated with the hardware component(s). 102 are associated. For example, the operating parameter determiner can be used. 110 a measurement of the temperature(s) of a hardware component 102 use the temperature(s) to determine the value(s). In at least one embodiment, the measurement can be performed by an internal sensor of the hardware component. 102 originate from and / or are associated with the hardware component 102 be associated with an IC. The operator 110 can initiate a temperature measurement and / or query one or more temperature measurements (e.g., from a register) to determine one or more temperatures of the hardware component 102 to determine.

[0052] Another example of one or more characteristics determined by the operating parameter determination device. 110 can be used to determine one or more values ​​of one or more physical operating parameters, an operating speed of the hardware component(s) 102 This includes, for example, an operating speed that can be a fixed-coded value determined by the operating parameter setting device. 110 is read from memory and can be an operating speed index that indicates the operating speed of a hardware component. 102 compared to other hardware components 102 (e.g. ICs) of the computer platform 100evaluated. An example of an operating speed index is NVIDIA's Speedo. In at least one embodiment, an operating speed value is based at least partially on the performance of one or more ring oscillators within a chip, which is evaluated before being deployed on the computer platform. 100 can be tested and stored in conjunction with the chip.

[0053] By determining the value(s) of a physical operating parameter(s) used for fault checking, based on one or more characteristics, the operator can 110 Consider variables that influence the performance characteristics of a hardware component. 102 They may possess characteristics, but not necessarily represent latent detection. For example, for the same hardware component... 102or hardware component class a minimum supply voltage of the hardware component 102 decrease with increasing temperature and / or operating speed. In some examples, one or more characteristics are used to look up one or more of the various values ​​used for fault checking in a table and / or to calculate one or more of these values ​​(e.g., using a function). For example, when calculating a value of a physical operating parameter, an initial value can be provided that is adjusted, at least in part, based on one or more of the characteristics.

[0054] Fig. 4 is a diagram 400, which, according to some embodiments of the present disclosure, shows the relationships between the operating speed of hardware components and limit values ​​of a physical operating parameter. Each point in the diagram 400 , such as the points 402 and 404 , can represent a limit value of a corresponding hardware component, which is measured before use on a computer platform, e.g. in a factory, or at the beginning of use on a computer platform, e.g. the computer platform 100 , is tested. In at least some embodiments, the limit value of each hardware component can be determined using the approaches described herein (e.g., using system instantiation). 104 for the detection of degradation and one or more test runs on the computer platform 100 (may or may not take place). As shown, the point 402a hardware component 102 with an operating speed of 1800 and a limit value of 0.74 V. The point 404 can a hardware component 102 with an operating speed of 1650 and a limit value of 0.79 V. A threshold line. 406 is attached to the points of the diagram 400 adjusted, which shows that the limit value tends to decrease as the operating speed increases.

[0055] The operator 110 can the relationship of the diagram 400 This can be used when determining a value (of values) of a physical operating parameter (of physical operating parameters) for a fault test, so that the limit value can be identified in fewer iterations of the fault test and taken into account when determining the degradation rate. Fig. Table 300, for example, shows an operating speed of 1622, which the operator 110can be used to derive the values ​​of the physical operating parameter in Table 300.

[0056] Also in Table 300, the operating parameter determiner is specified. 110 The temperature value shown in the table means that the values ​​of the physical operating parameter will differ for different test runs. For example, a temperature of 45 degrees Celsius results in a value of 460 mV for the test run. 316 at the test stage 302 and a temperature of 75 degrees Celsius results in a value of 440 mV for the test run 318 at the test stage 302 As described here, the temperature, operating speed and / or other characteristics can be recorded in a table that the operating parameter determiner uses. 110 used to determine the values ​​of the physical operating parameters for the test stages 302-310 to look up and / or calculate the values.

[0057] Back to Fig. 4: The diagram 400 shows the threshold lines 406 , 408 , 410 and 412 , which correspond to the applied values ​​of the physical operating parameter at the test stages 302 , 304 , 306 or 308 and / or reference values ​​of the degradation rate. The threshold lines 408 , 410 and 412 Threshold values ​​for the limit values ​​of the hardware components can correspond to the points in the diagram. 400 different operating durations after use correspond to, and can deviate from the threshold line. 406 It must be offset to detect the degradation of the hardware components over time. In at least one embodiment, the degradation rate analyzer determines 116 that a hardware component 102a latent defect is present if the performance characteristic (in this case, the limit value) is too high for the age and / or usage of the hardware component. 102 is to implement one or more remedial measures by the Remedial Measures Administrator 118 to trigger it, as described here.

[0058] As in Fig. As shown in Figure 4, the degradation rate analyzer can 116 Determine during initial deployment that the hardware component 102 a latent defect is included if the limit value corresponds to a value on the threshold line. 408 during or before use. The degradation rate analyzer 116 can determine that the hardware component 102 exhibits a latent defect if the limit value has a corresponding value on the threshold line. 410 from deployment to up to 5000 operating hours. The degradation rate analyzer 116can determine that the hardware component 102 exhibits a latent defect if the limit value has a corresponding value on the threshold line. 412 from provision up to 5000 operating hours and beyond. Although the operating hours in Fig. As shown in Figure 4, another form of measuring the usage or age of hardware components can also be used.

[0059] In at least one embodiment, the degradation rate determiner provides 114 the degradation rate analyzer 116 with a measurement of the usage or age of a hardware component 102 as well as with the performance characteristic value(s) derived from one or more test runs. The degradation rate analyzer 116It uses the measurement to calculate and / or look up a reference value for the degradation rate and determines whether the value(s) of the performance characteristic exceeds the reference value for the degradation rate. If the degradation rate analyzer 116 If it is determined that the reference value(s) for the degradation rate is / are being exceeded, this may be indicated in the analysis results (e.g., the analysis results). 214 ) be included, which are addressed to the remediation administrator 118 be provided to initiate one or more of the measures described herein.

[0060] While Fig. 3. While a supply voltage is used as an example of a physical operating parameter that can be varied for fault testing, one or more other types of physical operating parameters can be used in addition to or instead of a supply voltage. Examples include values ​​for a supply current, an input resistance, an input impedance, or an operating clock frequency. In accordance with aspects of the disclosure, a scan-mode test, such as a fast-scan-mode test (e.g., FTM2CLK) for logic gates, can be used to detect subtle gate defects, even if they affect individual gates. The subtle gate defects can deteriorate over time to cause a permanent fault that can be predicted using the approaches described here.This can be achieved, for example, without limitation, by closing the FTM2CLK-specific timing independently of the functional timing during an IC design process, so that FTM2CLK is sensitive to subtle time-zero errors. In exemplary implementations, values ​​of an operating clock frequency can be varied across test stages of a test run to determine a limit corresponding to the operating clock frequency (e.g., using approaches that are related to ). Fig. 3 are described and include the evaluation of passing or failing error tests).

[0061] Embodiments of the present disclosure can be used to test physical interfaces, such as printed circuit board (PCB) interfaces, peripheral component interconnect express (PEX) interfaces, or high-speed serial interface (HSI) interfaces of hardware components of a computer platform. High-speed interfaces can become faulty over time due to events such as reference clock jitter, PCB trace corrosion, and component I / O degradation. Aspects of the present disclosure enable the prediction of permanent faults in physical interfaces before they occur. According to the present disclosure, such permanent faults can be predicted if the fault tester 106A fault test is used that includes parametric testing of high-speed interfaces (HSIs)—for example, and without limitation, via eye diagrams—to determine pass or fail based on spans in eye openings. In such examples, the performance characteristic of a margin (or multiple margins) of an eye opening may correspond to the degradation rate. The degradation rate may correspond to the rate of change of the margin(s) of the eye opening. In embodiments, the parametric test may include measuring and tracking the rate of change of the height and / or width of the eye openings in an eye diagram over time to determine whether one or more corrective actions are required.

[0062] Referring to Fig. 5A and Fig. 5B is Fig. 5A an example of an eye diagram 500 for a physical connection of a hardware component 102according to some embodiments of the present disclosure. Fig. 5B is an example of an eye diagram. 518 for the physical connection of the hardware component 102 from Fig. 5A with degradation to a performance characteristic according to some embodiments of the present disclosure.

[0063] The eye diagram 500 can be an output(s) 514 the hardware component 102 for one from the error tester 106 The test run performed corresponds to the eye diagram. 518 can one or more expenses 516 the hardware component 102 for a test run, which is performed by the fault tester 106 will be carried out at a later date. The eye chart 500 includes an eye opening 510 , which are due to the expenses 514 is formed. Similarly, the eye diagram includes 518 an eye opening 520, which are due to the expenses 516 is formed. In Fig. 5A and Fig. 5B are the dimensions of the eye opening. 520 unlike the dimensions of the eye opening 510 , which is due to a deterioration of the physical connection. In at least one embodiment, the performance characteristic determiner corresponds to / correspond to 108 specific value(s) of a performance characteristic(s) of one or more measurements of one or more dimensions of the eye openings 510 and 520 For example, the error tester can 106 a height 506 and / or a width 512 the eye openings 510 and 520 to measure in order to calculate or determine one or more values ​​of one or more performance characteristics, and the results 208can correspond to one or more of these measurements. The degradation rate determiner 114 can use the value(s) of the performance characteristic(s) to determine a degradation rate of the physical connection of the hardware component 102 to determine as described herein.

[0064] In at least one embodiment, the fault tester can 106 Use the same set of physical operating parameter values ​​to test one or more physical interfaces, which can be applied using a single test stage per test run. In other examples, multiple test stages and different values ​​of the physical operating parameters can be used to determine a boundary performance characteristic, as described here. Furthermore, the results can be 208 of the fault tester 106may or may not include passing or failing the fault test and may involve measurements of a physical output(s) of the hardware component. 102 to include or not. In exemplary embodiments where the fault tester 106 Evaluating a measurement(s) for pass / fail might, for example, involve determining whether one or more measurements, or a combination thereof, exceed a threshold value. Another example is that the one or more measurements, or a combination thereof, could be used as values ​​for a performance characteristic.

[0065] In other aspects of the present disclosure, a fault tester may 106The fault test performed to predict a permanent electrical fault related to electrostatic discharge and electrical overload includes a leakage current test in which a value of the power characteristic is compared to the leakage current from a hardware component. 102 with a given value (given values) of a physical operating parameter. In this example, one (or more) value(s) of a physical operating parameter that applies to the hardware component can be (or can be) 102 The value(s) of the power characteristic that is applied are essentially determined each time the fault test is performed. In at least one embodiment, the value(s) of the power characteristic can correspond to a measurement of the leakage current. In embodiments where the fault tester 106Evaluating a measurement(s) for pass or fail may involve determining whether one or more measurements, or a combination thereof, exceed a threshold value. As another example, the one or more measured values, or a combination thereof, may be used as values ​​for a performance characteristic or characteristics. In at least one embodiment, the degradation rate analyzer can 116 a notification in the analysis results 214 provide when the degradation rate analyzer 116 An increase in leakage flow has been identified, so the remediation manager 118 may take one or more of the various measures described herein.

[0066] Aspects of the present disclosure may further provide that the degradation detection system 104It predicts permanent defects using one or more machine learning models. For example, the degradation detection system can 104 a permanent error predictor 120 include, which can output prediction data that represent one or more confidence values ​​with respect to one or more predictions of one or more permanent errors.

[0067] Fig. Figure 6 shows an example of one or more machine learning models. 612 of the permanent error predictor 120 according to some embodiments of the present disclosure. The machine learning model(s) 612 from Fig. 6 can be an example of a machine learning model (machine learning models) 612 be that which is in the permanent error predictor 120 can be used. The machine learning model(s) 612may include one or more types of machine learning models, such as machine learning models using linear regression, logistic regression, decision trees, support vector machines (SVM), Naive Bayes, k-nearest neighbor (Knn), K-mean clustering, random forest, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., autocoders, convolutional neurons, recurrent neurons, perceptrons, long / short term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversarial, liquid state machine, etc.) and / or other types of machine learning models.

[0068] The neural convolutional network can, for example, use inputs that include data from any components and functions of the computer platform. 100 include, for example, as in Fig. 6 shown, the operating parameter determiner 110 , the performance characteristic determiner108 and the error tester 106 and / or other inputs to the machine learning model(s) 612 The data can be transmitted in a convolutional stream of a convolutional network into the machine learning model(s). 612 The convolution stream can comprise any number of layers, and one or more layers can include an input layer.

[0069] The machine learning model(s) 612 can use any one or more combinations of the different data provided by the computer platform 100 collected and / or from one or more components of the degradation detection system 104 be generated and used with one or more hardware components 102These include, for example, any of the various degradation rates, error test results, performance characteristic values, indicators of degradation rates in analysis data, etc. Further examples include error code correction (ECC) data, usage data (e.g., corresponding to a measurement of the usage and / or age of the hardware component and / or the computer platform). 100 ) and / or environmental data (e.g., corresponding to one or more environmental measurements such as pressure, temperature, humidity, etc.). According to non-limiting embodiments, the machine learning model(s) comprises 612 a multiparameter machine learning model.

[0070] The machine learning multiparameter model can continuously learn and improve its actual failure prediction based on usage, environment, etc. As shown, the machine learning model(s) can... 612 Forecast data 614generate which represent one or more confidence values ​​with respect to one or more predictions of one or more permanent errors.

[0071] In at least one embodiment, the remediation administrator can 118 initiate one or more of the various measures described herein, which are at least partially based on the forecast data 614 are based, for example, at least partially on the determination of one or more confidence values ​​that exceed one or more thresholds.

[0072] Fig. 7 is a flowchart that shows a process 700 for predicting permanent faults in hardware components according to some embodiments of the present disclosure, based on several iterations of a fault test. The method 700 includes in block B710The execution of multiple instances of a fault test on a hardware component. For example, the test control 122 the error tester 106 use to perform multiple instances of a fault test on the hardware components 102A the computer platform 100 to perform this by applying different values ​​of a physical operating parameter to the hardware component for each of the instances. 102A can be applied. This can be done, for example, during a test run. 320 happen.

[0073] The procedure 700 includes in block B720 Determining the value of a physical operating parameter at which the hardware component transitions from passing the fault test to failing. For example, the power characteristic determiner 108 from the results 208 Determine a value of the physical operating parameter for the multiple instances of the fault test, at which the hardware component102A from passing the error test to failing the error test. An example might include a value that corresponds to the test level. 306 and the test stage 308 of the test run 320 corresponds.

[0074] The procedure 700 includes in block B730 Determining a degradation rate based on the value. For example, the degradation rate determiner can 114 the degradation rate 212 determine which corresponds to a limit value of the physical operating parameter at which the hardware component 102A is able to pass the fault test, at least partially, based on the value of the physical operating parameter. For example, the degradation rate can be based on the value assigned to the test stage. 306 and the test stage 308 of the test run 320corresponds to a value that corresponds to a limit value of the performance characteristic from a previous test run.

[0075] The procedure 700 includes in block B740 Determining that the degradation rate exceeds a reference degradation rate. For example, the degradation rate analyzer can 116 determine that the degradation rate 212 exceeds a reference degradation rate.

[0076] The procedure 700 in block B750 This includes determining one or more corrective actions. For example, the corrective action manager can 118 one or more remedial measures based at least partially on the degradation rate 212 , which exceeds the reference degradation rate (e.g. using the analysis results) 214 and / or the prediction data 614 ).

[0077] Fig. 8 is a flowchart that shows a process 800 for predicting permanent faults in hardware components using values ​​of a performance characteristic according to some embodiments of the present disclosure.

[0078] The procedure 800 includes in block B810 The application of one or more test parameters of a fault test to a hardware component. For example, the fault tester can 106 one or more test parameters of a fault test on the hardware component 102A the computer platform 100 apply to one or more outputs of the hardware component 102A to produce.

[0079] The procedure 800 includes in block B820 Determining a value for a performance characteristic determiner based on the error test. For example, the performance characteristic determiner can 108a value representing a performance characteristic of the hardware component 102A at least partially based on the analysis of one or more outputs of the hardware component 102A determine.

[0080] The procedure 800 includes in block B830 Determining the degradation rate of a performance characteristic that exceeds a reference degradation rate based on the value. For example, the degradation rate analyzer 116 determine that a degradation rate of the performance characteristic of the hardware component 102A exceeds a reference degradation rate, based at least partially on a measurement representing an operating period during which the hardware component 102A was operated.

[0081] The procedure 800 includes in block B840 Determining one or more corrective actions. For example, the corrective action administrator can 849Determine one or more corrective measures that are based at least partially on the degradation rate of the performance characteristic that exceeds the reference degradation rate.

[0082] Referring to Fig. 9A - Fig. 9D, is Fig. 9A a representation of an example of an autonomous vehicle 900 according to some embodiments of the present disclosure. The autonomous vehicle 900 (here alternatively as "vehicle") 900The term “autonomous vehicle” can include a passenger vehicle, such as a car, truck, bus, and / or any other type of vehicle that carries one or more passengers. Autonomous vehicles are generally described in terms of levels of automation defined by the National Highway Traffic Safety Administration (NHTSA), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (SAE) in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and earlier and future versions of this standard). 900 It can have functionality corresponding to one or more of the Level 3 to Level 5 autonomous driving levels. For example, the vehicle can 900Depending on the embodiment, they may exhibit conditional automation (Level 3), high automation (Level 4) and / or full automation (Level 5).

[0083] The vehicle 900 It can include components such as a chassis, vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. Various vehicle components 900 are described herein, which may include some exemplary hardware components (e.g., those in Fig. 1 described hardware component(s) 102 In some embodiments, the error tester and other components of the computing platform can be 100 be continuously implemented while the vehicle 900 is in operation and / or when the vehicle is not in active operation.

[0084] The vehicle 900 can a drive system 950These include, for example, an internal combustion engine, a hybrid electric drive unit, a fully electric motor, and / or another type of drive system. The drive system 950 can be connected to the vehicle's drivetrain 900 be connected, which may include a transmission to propel the vehicle. 900 to enable the drive system 950 can in response to receiving signals from the throttle / accelerator device 952 can be controlled.

[0085] A steering system 954 , which can include a steering wheel, can be used to control the vehicle 900 to steer (e.g. along a desired path or route) when the drive system 950 is in operation (e.g., when the vehicle is in motion). The steering system 954 can send signals from a steering actuator 956 received. The steering wheel may be optional for the functionality of full automation (Level 5).

[0086] In at least one embodiment, a hardware component 102 out of Fig. 1 in the steering actuator 956 It must be included, and the remedial action administrator. 118 can perform one or more actions related to the steering actuator 956 trigger (e.g. engine warning light, warning on the dashboard, fault code recording, etc.).

[0087] The brake sensor system 946 can be used to control the vehicle brakes in response to receiving signals from the brake actuators. 948 and / or to activate brake sensors.

[0088] In at least one embodiment, a hardware component 102 out of Fig. 1 in the brake actuators 948 and / or include the brake sensors, and the remediation administrator 118 can perform one or more actions related to the steering actuator 956(e.g., engine warning light, dashboard warning, fault code recording, etc.) trigger.

[0089] The control(s) 936 , which contain one or more system-on-a-chip (SoCs) 904 ( Fig. 9C) and / or GPU(s), signals (e.g., representing commands) can be sent to one or more components and / or systems of the vehicle. 900 send signals. For example, the control unit(s) can send signals to actuate the vehicle brakes via one or more brake actuators. 948 , for operating the steering system 954 via one or more steering actuators 956 , for actuating the drive system 950 via one or more throttle / acceleration controllers 952 send. In at least one embodiment, the signals can be used to initiate one or more corrective actions by the corrective action manager. 118 to effect and / or cause. The control(s) 936may include one or more integrated computing devices (e.g., supercomputers) that process sensor signals and issue operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle. 900 to support. The control(s) 936 can / can a first control 936 for autonomous driving functions, a second control system 936 for functional safety functions, a third control 936 for the functionality of artificial intelligence (e.g., computer-aided vision), a fourth control 936 for infotainment functionality, a fifth control 936 for redundancy in emergencies and / or other controls. In some examples, a single control may be sufficient. 936 two or more of the above-mentioned functionalities, two or more controls 936can take on a single functionality and / or any combination thereof.

[0090] The control(s) 936 The signals can be used to control one or more components and / or systems of the vehicle. 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). The sensor data can, for example, and without limitation, come from one or more sensors of the global navigation satellite system. 958 (e.g. Global Positioning System sensor(s)), RADAR sensor(s) 960 , Ultrasonic sensor(s) 962 , LiDAR sensor(s) 964 , Inertial Measurement Unit (IMU) sensor(s) 966 (e.g., accelerometer(s), gyroscope(s), magnetic compass(s), magnetometer, etc.), microphone(s) 996 , stereo camera(s) 968 , wide-angle camera(s) 970 (e.g., fisheye cameras), infrared camera(s) 972 , Surround view camera(s) 974(e.g. 360-degree cameras), long-range and / or medium-range camera(s) 998 , speed sensor(s) 944 (e.g., to measure the vehicle's speed) 900 ), vibration sensor(s) 942 , steering sensor(s) 940 , brake sensor(s) (e.g. as part of the brake sensor system) 946 ), and / or other sensor types.

[0091] One or more of the controllers 936 Inputs (e.g., in the form of input data) can be received from an instrument cluster. 932 of the vehicle 900 receive and output (e.g., in the form of output data, display data, etc.) via a human-machine interface (HMI) display 934 , an acoustic signal generator, a loudspeaker and / or via other components of the vehicle 900 Provide information such as vehicle speed, RPM, time, map data (e.g., the HD map). 922 from Fig. 9C), position data (e.g. the position of the vehicle) 900 , as on a map), direction, position of other vehicles (e.g., an occupancy grid), information about objects and the status of objects, as from the control(s) 936 perceived, etc. For example, the HMI display can 934 Display information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about driving maneuvers that the vehicle has performed, is currently performing, or will perform (e.g., changing lanes now, exiting in two miles). 34B take, etc.).

[0092] The vehicle 900 It also includes a network interface. 924 , which includes one or more wireless antenna(s) 926 and / or modem(s) for communication over one or more networks. For example, the network interface 924be able to communicate via LTE, WCDMA, UMTS, GSM, CDMA2000, etc. The 926 wireless antenna(s) can also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) via local area networks such as Bluetooth, Bluetooth LE, Z-Wave, ZigBee, etc., and / or low-power wide-area networks (LPWANs) such as LoRaWAN, SigFox, etc.

[0093] In at least one embodiment, one or more remedial measures can be implemented by the remedial measures administrator. 118 the transmission of any of the various indicators or messages described herein via the network interface 924 include.

[0094] Fig. 9B is an example of camera positions and fields of view for the exemplary autonomous vehicle. 900 from Fig. 9A, according to some embodiments of the present disclosure. The cameras and their respective fields of view represent one embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included and / or the cameras may be located at different camera positions on the vehicle. 900 condition.

[0095] The camera types for the cameras can include, among others, digital cameras designed for use with the vehicle's components and / or systems. 900The camera(s) can be trained. The camera(s) can operate at Automotive Safety Integrity Level (ASIL) B and / or another ASIL. Depending on the embodiment, the camera types can achieve any frame rate, e.g., 60 frames per second (fps), 820 fps, 240 fps, etc. The cameras can use rolling shutter, global shutter, another shutter type, or a combination thereof. In some examples, the color filter array can include a red-clear color filter array (RCCC), a red-clear-blue color filter array (RCCB), a red-blue-green clear color filter array (RBGC), a Foveon X3 color filter array, a Bayer sensor color filter array (RGGB), a monochrome sensor color filter array, and / or another type of color filter array. In some embodiments, clear pixel cameras, such as... B. Cameras with an RCCC, RCCB and / or RBGC color filter array can be used to increase light sensitivity.

[0096] In some examples, one or more of the camera(s) can be used to perform advanced driver assistance system (ADAS) functions (e.g., as part of a redundant or fail-safe design). For example, a multi-function monocular camera can be installed to enable features such as lane keeping assist, traffic sign recognition, and intelligent headlight control. One or more of the camera(s) (e.g., all cameras) can simultaneously capture and provide image data (e.g., video).

[0097] One or more cameras can be mounted in an assembly, such as a custom-designed (3D-printed) assembly, to eliminate stray light and reflections from inside the vehicle (e.g., reflections from the dashboard mirrored in the windshield's side mirrors) that could interfere with the camera's image acquisition. Regarding side mirror mounting assemblies, these can be custom 3D-printed so that the camera mounting plate conforms to the shape of the side mirror. In some cases, the camera can be integrated into the side mirror itself. For side cameras, the camera(s) can also be integrated into the four pillars at each corner of the cabin.

[0098] Cameras with a field of view that includes parts of the environment in front of the vehicle 900It includes (e.g., forward-facing cameras), can be used for all-around vision to help identify forward-facing paths and obstacles, and with the help of one or more controllers. 936 and / or control SoCs to provide information critical for generating an occupancy grid and / or determining preferred vehicle paths. Forward-facing cameras can be used to perform many of the same ADAS functions as LiDAR, including emergency braking, pedestrian detection, and collision avoidance. Forward-facing cameras can also be used for ADAS functions and systems such as lane departure warning (LDW), adaptive cruise control (ACC), and / or other functions like traffic sign recognition.

[0099] A variety of cameras can be used in a forward-facing configuration, such as a monocular camera platform incorporating a CMOS (Complementary Metal Oxide Semiconductor) color imager. Another example is a wide-angle camera. 970 be, which can be used to detect objects entering the field of view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 9B shows only one wide-angle camera; any number of wide-angle cameras can be used. 970 on the vehicle 900 are located. Additionally, the wide-angle camera(s) can be used. 998 (e.g., a pair of wide-angle stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. The wide-angle camera(s) 998 It can also be used for object detection and classification, as well as basic object tracking.

[0100] One or more stereo cameras 968 They can also be included in a forward-facing configuration. The stereo camera(s) 968 It can include an integrated control unit that incorporates a scalable processing unit, which can provide programmable logic (FPGA) and a multi-core microprocessor with an integrated CAN or Ethernet interface on a single chip. Such a unit can be used to create a 3D map of the vehicle's surroundings, including distance estimation for all points in the image. An alternative stereo camera(s) 968It may include a compact stereo vision sensor(s) comprising two camera lenses (one on the left and one on the right) and an image processing chip that measures the distance between the vehicle and the target object and uses the generated information (e.g., metadata) to activate the autonomous emergency braking and lane departure warning functions. Other types of stereo camera(s) 968 can be used in addition to or as an alternative to those described here.

[0101] Cameras with a field of view that includes parts of the surroundings to the sides of the vehicle 900 The system includes (e.g., side cameras), which can be used for the surround view and provide information used to create and update the occupancy grid and to generate side-impact collision warnings. For example, the surround camera(s) 974 (e.g. four surround-view cameras) 974 as in Fig. 9B shown) on the vehicle 900be positioned. The surrounding camera(s) 974 Can / can wide-angle camera(s) 970 , fisheye camera(s), 360-degree camera(s) and / or similar. For example, four fisheye cameras could be positioned at the front, rear and sides of the vehicle. In an alternative configuration, the vehicle could have three surround camera(s). 974 (e.g. left, right and rear) and use one or more other camera(s) (e.g. a front-facing camera) as a fourth surround-view camera.

[0102] Cameras with a field of view that includes parts of the environment behind the vehicle 900The system includes (e.g., reversing cameras) and can be used for parking assistance, surround view, rear collision warnings, and creating and updating the occupancy grid. A variety of cameras can be used, including but not limited to cameras that are also suitable as forward-facing cameras (e.g., long-range and / or mid-range cameras). 998 , stereo camera(s) 968 ), Infrared camera(s) 972 etc.), as described here.

[0103] Fig. 9C is a block diagram of an exemplary system architecture for the exemplary autonomous vehicle. 900 from Fig. 9A, according to some embodiments of the present disclosure. It should be understood that these and other arrangements described herein are presented only as examples. Other arrangements and elements (e.g., machines, interfaces, functions, arrays, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional units that may be implemented as discrete or distributed components, or in conjunction with other components, in any suitable combination and location. Various functionalities described herein, which are performed by units, may be executed by hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in memory.

[0104] All components, features and systems of the vehicle 900 in Fig. 9C are shown in such a way that they go over the bus 902 are connected. The bus 902 It can include a CAN data interface (Controller Area Network) (here alternatively referred to as "CAN bus"). A CAN can be a network within the vehicle. 900 to support the control of various features and functionalities of the vehicle 900 It is used for various functions, such as operating the brakes, accelerator, brakes, steering, windshield wipers, etc. A CAN bus can be configured to contain dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). The CAN bus can be read to determine the steering wheel angle, vehicle speed, engine speed (RPM), button positions, and / or other vehicle status indicators. The CAN bus can be ASIL B compliant.

[0105] Although the bus 902 Although described here as a CAN bus, this should not be understood as a limitation. For example, FlexRay and / or Ethernet can also be used in addition to or as an alternative to the CAN bus. Although a single line is used to represent the bus 902 The fact that it is used should not be understood as a limitation. For example, it can be any number of buses. 902 These can include one or more CAN buses, one or more FlexRay buses, one or more Ethernet buses, and / or one or more other types of buses using a different protocol. In some examples, two or more buses may be used. 902 They can be used to perform different functionalities, and / or they can be used for redundancy. For example, a first bus 902 for the collision avoidance functionality and a second bus 902for control purposes. In each example, any bus can be used. 902 with each of the vehicle's components 900 communicate, and two or more buses 902 can communicate with the same components. In some examples, each SoC can 904 , every control 936 and / or every computer within the vehicle has access to the same input data (e.g., input from the vehicle's sensors). 900 ) and be connected to a common bus, such as the CAN bus.

[0106] The vehicle 900 can be one or more controllers 936 include, as they are described here in Fig. 9A are described. The control(s) 936 can be used for a variety of functions. The control(s) 936 can interact with various other components and systems of the vehicle 900 be coupled and can be used to control the vehicle900 , the vehicle's artificial intelligence 900 , the infotainment system for the vehicle 900 and / or similar.

[0107] The vehicle 900 can be one or more system-on-a-chip (SoC) 904 include the SoC 904 CPU(s) can 906 , GPU(s) 908 , processor(s) 910 , Cache(s) 912 , accelerator 914 , data storage 916 and / or include other components and features not shown. The SoC(s) 904 can / are able to control the vehicle 900 can be used in a wide variety of platforms and systems. For example, the SoC(s) 904 in a system (e.g. the vehicle's system) 900 ) with an HD card 922 The map refreshes and / or updates can be combined via a network interface. 924 from one or more servers (e.g. server(s) 978out of Fig. 9D) can be obtained.

[0108] In at least one embodiment, one or more of the SoC(s) 904 one or more hardware components 102 (e.g. the CPU(s)) 906 , the GPU(s) 906 , the processor(s) 910 , the cache(s) 912 , the accelerator(s) 914 and / or the data storage device(s) 916 ) and / or one or more degradation detection systems 104 include.

[0109] The CPU(s) 906 may comprise a CPU cluster or CPU complex (here alternatively referred to as "CCPLEX"). The CPU(s) 906 may include multiple cores and / or L2 caches. In some implementations, the CPU(s) 906 for example, eight cores in a coherent multiprocessor configuration. In some embodiments, the CPU(s) 906comprise four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 MB L2 cache). The CPU(s) 906 (e.g., the CCPLEX) can be configured to support simultaneous cluster operation, so that at any given time any combination of CPU clusters can be used. 906 can be active.

[0110] The CPU(s) 906The CPU(s) can implement power management functions that include one or more of the following features: individual hardware blocks can be automatically clocked when idle to save dynamic power; each core can be clocked when the core is not actively executing instructions due to the execution of WFI / WFE instructions; each core can be independently power-controlled; each core cluster can be independently clocked when all cores are clocked or power-controlled; and / or each core cluster can be independently power-controlled when all cores are power-controlled. 906The system can / can further implement an improved power state management algorithm where permissible power states and expected wake-up times are specified, and the hardware / microcode determines the best power state to enter for the core, cluster, and CCPLEX. The processor cores can support simplified sequences for inputting the power state into software, offloading the work to the microcode.

[0111] The GPU(s) 908 may include an integrated GPU (referred to here alternatively as "iGPU"). The GPU(s) 908 They can be programmable and efficient for parallel workloads. The GPU(s) 908 In some examples, an improved Tensor instruction set can be used. The GPU(s) 908The system may include one or more streaming microprocessors, each of which may include an L1 cache (e.g., an L1 cache with a memory capacity of at least 96 KB), and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In some embodiments, the GPU(s) 908 comprise at least eight streaming microprocessors. The GPU(s) 908 The GPU(s) can use programming interface(s) (API(s)) for calculations. Additionally, the GPU(s) can... 908 use one or more parallel computing platforms and / or programming models (e.g., CUDA from NVIDIA).

[0112] The GPU(s) 908 They can be energy-optimized for best performance in automotive and embedded applications. The GPU(s) 908They can be manufactured, for example, on a finite field-effect transistor (FinFET). The GPU(s) 908However, they can also be manufactured using other semiconductor fabrication methods. Each streaming microprocessor can contain a number of mixed-precision compute cores divided into multiple blocks. For example, 64 PF32 cores and 32 PF64 cores can be divided into four processing blocks. In such an example, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learning matrix arithmetic, an L0 instruction cache, a warp scheduler, a distribution unit, and / or a 64 KB register file. Furthermore, the streaming microprocessors can include independent parallel integer and floating-point data paths to enable efficient execution of workloads with a mix of computations and addressing operations.Streaming microprocessors can include an independent thread scheduling function to enable fine-grained synchronization and cooperation between parallel threads. They can also incorporate a combined L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0113] The GPU(s) 908 It may include high-bandwidth memory (HBM) and / or a 16 GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / second in some examples. In some examples, synchronous graphics random-access memory (SGRAM), such as type 5 synchronous graphics dual-data-rate random-access memory (GDDR5), may be used in addition to or as an alternative to HBM memory.

[0114] The GPU(s) 908It may include a unified memory technology that incorporates access counters to enable more accurate migration of memory pages to the processor that accesses them most frequently, thereby improving efficiency for memory areas shared by processors. In some examples, support for address translation services (ATS) may be used so that the GPU(s) 908 directly to the page tables of the CPU(s) 906 can access it. In such examples, a failed attempt by the memory management unit (MMU) of the GPU(s) can result in... 908 an address translation request to the CPU(s) 906 be transmitted. The CPU(s) can respond. 906 search their page tables for the virtual-physical mapping for the address and send the translation back to the GPU(s) 908This is how unified memory technology can transfer a single, unified virtual address space for the memory of both the CPU(s) and the memory of the CPU(s). 906 as well as the GPU(s) 908 enable the programming of the GPU(s) 808 and the porting of applications to the GPU(s) 908 simplified.

[0115] Furthermore, the GPU(s) 908 include an access counter that tracks the frequency of accesses to the GPU(s) 908 It can track the memory of other processors. The access counter can help ensure that memory pages are moved to the physical memory of the processor that accesses them most frequently.

[0116] The SoC(s) 904 can / can have any number of cache(s) 912 include, among those described here. The cache(s) 912 can include, for example, an L3 cache that serves both the CPU(s) 906 as well as the GPU(s)908 is available (e.g., the one that is compatible with both the CPU(s)) 906 as well as with the GPU(s) 908 is connected). The cache(s) 912 It may include a write-back cache that can track the states of lines, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). The L3 cache can vary depending on the implementation. 4 This includes MB or more, although smaller cache sizes can also be used.

[0117] The SoC(s) 904 can / may include one or more accelerators 914 include (e.g., hardware accelerators, software accelerators, or a combination thereof). The SoC(s) 904It can include, for example, a hardware acceleration cluster, which may contain optimized hardware accelerators and / or a large amount of on-chip memory. The large on-chip memory (e.g., 4 MB SRAM) can enable the hardware acceleration cluster to accelerate neural networks and other computations. The hardware acceleration cluster can complement the GPU(s). 908 and to relieve some tasks of the GPU(s) 908 can be used (e.g. to increase GPU cycles) 908 to release for the execution of other tasks). The accelerator(s) 914This can be used, for example, for targeted workloads (e.g., perception, convolutional neural networks (CNNs), etc.) that are stable enough to be suitable for acceleration. The term "CNN" as used here can encompass all types of CNNs, including area-based or regional convolutional neural networks (RCNs) and fast RCNs (e.g., for object detection).

[0118] The accelerator(s) 914(e.g., the hardware acceleration cluster) may include a deep learning accelerator (DLA). The DLA(s) may include one or more tensor processing units (TPUs), which can be configured to provide an additional ten trillion operations per second for deep learning applications and inference. The TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). The DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as inference. The design of the DLA(s) can provide more performance per millimeter than a general-purpose GPU and far surpasses the performance of a CPU. The TPU(s) may perform multiple functions, including a convolution function for a single instance, which, for example,Supports INT8, INT16 and FP16 data types for features and weights, as well as post-processor functions.

[0119] The DLA(s) can quickly and efficiently run neural networks, especially CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety-related events.

[0120] The DLA(s) can perform any functionality of the GPU(s) 908execute, and by using an inference accelerator, a designer can, for example, use either the DLA(s) or the GPU(s). 908 target any desired function. For example, the designer can concentrate the processing of CNNs and floating-point operations on the DLA(s) and other functionalities on the GPU(s). 908 and / or other accelerators 914 left to chance.

[0121] The accelerator(s) 914(e.g., the hardware acceleration cluster) may include a programmable vision accelerator (PVA), which may alternatively be referred to here as a computer vision accelerator. The PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (ADAS), autonomous driving, and / or augmented reality (AR) and / or virtual reality (VR) applications. The PVA(s) may offer a balance between performance and flexibility. For example, each PVA may, without limitation, include any number of RISC (Reduced Instruction Set Computer) cores, direct memory access (DMA), and / or any number of vector processors.

[0122] The RISC cores can interact with image sensors (e.g., the image sensors of one of the cameras described herein), image signal processor(s), and / or the like. Each RISC core can include any amount of memory. Depending on the implementation, the RISC cores can use a variety of protocols. In some examples, the RISC cores can run a real-time operating system (RTOS). The RISC cores can be implemented with one or more integrated circuits, application-specific integrated circuits (ASICs), and / or memory devices. The RISC cores can include, for example, an instruction cache and / or tightly coupled RAM.

[0123] DMA can enable components of the PVA(s) to operate independently of the CPU(s). 906Accessing system memory. The DMA can support any number of features used to optimize the PVA, including, but not limited to, support for multidimensional addressing and / or circular addressing. In some examples, the DMA can support up to six or more dimensions of addressing, which may include block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0124] Vector processors can be programmable processors designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In some examples, the PVA may comprise a PVA core and two vector processing subsystem partitions. The PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem may act as the primary processing engine of the PVA and may include a vector processing unit (VPU), an instruction cache, and / or vector memory (e.g., VMEM). A VPU core may include a digital signal processor, such as a SIMD (Single Instruction, Multiple Data) or VLIW (Very Long Instruction Word) digital signal processor. The combination of SIMD and VLIW can improve throughput and speed.

[0125] Each vector processor can include an instruction cache and can be coupled to dedicated memory. As a result, in some examples, each vector processor can be configured to operate independently of the others. In other examples, the vector processors included in a particular PVA can be configured to use data parallelism. In some embodiments, the multitude of vector processors contained in a single PVA can execute the same computer vision algorithm, but for different regions of an image. In other examples, the vector processors contained in a particular PVA can simultaneously execute different computer vision algorithms on the same image, or even different algorithms on sequential images or portions of an image.Among other things, the hardware acceleration cluster can comprise any number of PVAs, and each PVA can contain any number of vector processors. Furthermore, the PVA(a) can include additional ECC (Error Correcting Code) memory to improve the overall system security.

[0126] The accelerator(s) 914 (e.g., the hardware acceleration cluster) may include an on-chip computer vision network and SRAM to provide high-bandwidth, low-latency SRAM for the accelerator(s). 914to provide. In some examples, the on-chip memory can comprise at least 4 MB of SRAM, consisting, for example, and without limitation, of eight freely configurable memory blocks accessible to both the PVA and the DLA. Each pair of memory blocks can include an extended peripheral bus (APB) interface, a circuit array, a controller, and a multiplexer. Any memory type can be used. The PVA and the DLA can access the memory via a backbone that provides high-speed access to the memory for both the PVA and the DLA. The backbone can include an on-chip computer vision network that connects the PVA and the DLA to the memory (e.g., using the APB).

[0127] The on-chip computer vision network can include an interface that, prior to the transmission of control signals / addresses / data, ensures that both the PVA and the DLA provide ready-to-use and valid signals. Such an interface can provide separate phases and channels for the transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. This type of interface can conform to ISO 26262 or IEC 61508 standards, although other standards and protocols can also be used.

[0128] In some examples, the SoC(s) 904The application includes a real-time ray tracing hardware accelerator as described in US patent application no. 16 / 101,232, filed on August 10, 2018. The real-time ray tracing hardware accelerator can be used to quickly and efficiently determine the positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for radar signal interpretation, for sound propagation synthesis and / or analysis, for simulating SONAR systems, for general wave propagation simulation, for comparison with lidar data for localization and / or other functions, and / or for other uses.

[0129] The accelerator(s) 914(e.g., the hardware accelerator cluster) have a wide array of uses for autonomous driving. The PVA can be a programmable vision accelerator that can be used for critical processing steps in ADAS and autonomous vehicles. The capabilities of the PVA are well-suited to algorithmic domains that require predictable processing with low power consumption and low latency. In other words, the PVA is well-suited for semi-dense or dense regular computations, even with small datasets, that require predictable runtimes with low latency and low power consumption. In the context of autonomous vehicle platforms, PVAs are therefore designed to execute classical computer vision algorithms because they are efficient at object detection and operate with integer mathematics.

[0130] According to one embodiment of the technology, the PVA is used, for example, to perform computer-aided vision. In some examples, a semi-global matching-based algorithm can be used, although this is not intended as a limitation. Many applications for Level 3-5 autonomous driving require motion estimation / stereo matching during driving (e.g., structure of motion, pedestrian detection, lane detection, etc.). The PVA can perform a computer-aided vision function based on input from two monocular cameras.

[0131] In some examples, PVA can be used to perform a dense optical flow. This involves processing unprocessed radar data (e.g., using a 4D Fast Fourier Transform) to deliver processed radar data. In other examples, PVA is used for time-of-flight depth processing by processing unprocessed time-of-flight data to provide, for example, processed time-of-flight data.

[0132] Dynamic Lane Assist (DLA) can be used to power any type of network to improve control and driving safety, including, for example, a neural network that outputs a confidence score for each object detection. Such a confidence score can be interpreted as a probability or as the relative "weighting" of each detection compared to other detections. This confidence score allows the system to make further decisions about which detections should be considered true positives and which as false positives. For example, the system can set a confidence threshold and consider only those detections that exceed the threshold as true positives. In an automatic emergency braking (AEB) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable.Therefore, only the most reliable detections should be considered as triggers for AEB. The DLA can use a neural network for confidence regression. The neural network can take as input at least a subset of parameters, such as the dimensions of the bounding box, the ground plane estimate (obtained, for example, from another subsystem), or the output of the inertial measurement unit (IMU) sensor. 966 , which are related to the orientation of the vehicle 900 correlates the distance, the 3D position estimates of the object, which are generated by the neural network and / or other sensors (e.g., LiDAR sensor(s)) 964 or radar sensor(s) 960 ) will be obtained, and others.

[0133] The SoC(s) 904 can / can data storage 916 (e.g., a storage device). Regarding the data storage device(s) 916 Could it be on-chip memory of the SoC(s)? 904This involves storing neural networks that are to be executed on the GPU and / or the DLA. In some examples, the capacity of the data storage (or storage) may be limited. 916 be large enough to store multiple instances of neural networks for redundancy and security. The data storage(s) 912 L2 or L3 cache(s) can be used 912 include the reference to the data storage location(s). 916 may include a reference to the memory associated with the PVA, DLA and / or other accelerators. 914 is associated as described here.

[0134] The SoC(s) 904 can / can use one or more processor(s) 910 (e.g., embedded processors). The processor(s) 910The system may include a boot and power management processor, which can be a dedicated processor and subsystem to handle boot power and management functions and the associated security enforcement. The boot and power management processor may be part of the SoC's boot sequence. 904 It can be and provide runtime power management services. The boot power supply and management processor can provide clock and voltage programming, support for low-power system transitions, management of SoC(s) 904 temperatures and temperature sensors, and / or management of the SoC(s) 904 power supply states. Each temperature sensor can be implemented as a ring oscillator whose output frequency is proportional to the temperature, and the SoC(s) 904 The ring oscillators can be used to measure the temperature of the CPU(s). 906 , GPU(s) 908 and / or the accelerator(s)914 to detect. If it is determined that the temperatures exceed a threshold, the boot and power management processor can enter a temperature fault routine and shut down the SoC(s). 904 put the vehicle into a state of reduced performance and / or 900 put the vehicle into a chauffeur-to-safe-stop mode (e.g., the vehicle). 900 to bring to a secure stop).

[0135] The processor(s) 910 It may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine can be an audio subsystem that provides full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In some examples, the audio processing engine is a dedicated processor core with a digital signal processor and dedicated RAM.

[0136] The processor(s) 910 It may further include an "always on" processor engine that can provide the necessary hardware functions to support low-power sensor management and to wake up use cases. The "always on" processor engine may include a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and forwarding logic.

[0137] The processor(s) 910It may further include a security cluster engine, which incorporates a dedicated processor subsystem for the security management of automotive applications. The security cluster engine may include two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt control, etc.), and / or routing logic. In a security mode, the two or more cores can operate in lockstep mode and function as a single core with comparison logic to detect differences between their operations.

[0138] The processor(s) 910It may include a video image compositor, which can be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate the final image for the playback window. The video image compositor may include lens distortion correction on the wide-angle camera(s). 970 , on the surround camera(s) 974 and / or on the cabin monitoring camera sensors. The cabin monitoring camera sensor is preferably monitored by a neural network running on a separate instance of the Advanced SoC and configured to detect cabin events and respond accordingly.

[0139] The video image compositor can also be configured to perform stereo image equalization on the input frames from the stereo lens. The video image compositor can further be used for assembling the user interface when the operating system desktop is in use and the GPU(s) are active. 908 It doesn't have to constantly render new surfaces. Even if the GPU(s) 908 When the video image compositor is switched on and actively performing 3D rendering, it can be used to utilize the GPU(s). 908 to relieve stress and thus improve performance and responsiveness.

[0140] The SoC(s) 904 The SoC(s) may also include a serial MIPI camera interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that can be used for camera and related pixel input functions. 904may further include an input / output control that can be controlled by software and can be used to receive I / O signals that are not assigned to any specific role.

[0141] The SoC(s) 904 The SoC(s) may also include a variety of peripheral interfaces to enable communication with peripheral devices, audio codecs, power management, and / or other devices. 904 can be used to receive data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LiDAR sensor(s)) 964 , RADAR sensor(s) 960 etc., which can be connected via Ethernet), data from the bus 902 (e.g., vehicle speed) 900 , steering wheel position etc.), data from GNSS sensor(s) 958 (e.g., connected via Ethernet or CAN bus) to process. The SoC(s) 904may include further dedicated high-performance mass storage controllers, which may contain their own DMA engines and which can be used to manage the CPU(s) 906 to free them from routine data management tasks.

[0142] The SoC(s) 904 The SoC(s) can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack along with deep learning tools. 904 They can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, the accelerator(s) can 914 in combination with the CPU(s) 906 , the GPU(s) 908and the data storage device(s) 916 form a fast, efficient platform for autonomous vehicles of levels 3-5.

[0143] The vehicle 900 can still use the network interface 924 include one or more wireless antennas 926 This can include (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). The network interface 924 can be used to establish a wireless connection via the internet to the cloud (e.g., to the server(s)) 978and / or other network devices), with other vehicles and / or with computing devices (e.g., passenger client devices). To communicate with other vehicles, a direct connection can be established between the two vehicles and / or an indirect connection (e.g., via networks and the internet). Direct connections can be established via a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link can be assigned to the vehicle 900 Information about vehicles near the vehicle 900 deliver (e.g. vehicles in front of, beside and / or behind the vehicle) 900 This functionality can be part of a cooperative adaptive cruise control function of the vehicle. 900 be.

[0144] The network interface 924 may include a SoC that provides modulation and demodulation functionality and handles communication with the controller(s).936 enabled via wireless networks. The network interface 924 The system can include a radio frequency front end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. Frequency conversions can be performed using known methods and / or superheterodyne methods. In some examples, the functionality of the radio frequency front end can be provided by a separate chip. The network interface can include wireless functionality for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0145] The vehicle 900 can further include one or more data storage devices 928 include memory located outside the chip (e.g., outside the SoC(s)) 904 ) may include. The data storage device(s) 928may include one or more memory elements, including RAM, SRAM, DRAM, VRAM, Flash, hard disks and / or other components and / or devices capable of storing at least one bit of data.

[0146] The vehicle 900 can still use one or more GNSS sensors 958 include the GNSS sensor(s) 958 (e.g., GPS and / or supported GPS sensors) to support mapping, perception, occupancy grid generation, and / or path planning functions. Any number of GNSS sensors can be used. 958 can be used, for example, and without limitation, a GPS that uses a USB port with an Ethernet-to-serial (RS-232) bridge.

[0147] The vehicle 900 can still use RADAR sensor(s) 960 include the radar sensor(s) 960 can / are possible from the vehicle 900It can be used for long-range vehicle detection, even in darkness and / or adverse weather conditions. The functional radar safety levels can be ASIL B. The radar sensor(s) 960 can / can use the CAN and / or the bus 902 (e.g. for transmitting the data from the RADAR sensor(s)) 960 The generated data is used for control and access to object tracking data, with some examples using Ethernet for access to the raw data. A variety of radar sensor types can be used. For example, and without limitation, the radar sensor(s) can be... 960 It should be suitable for use with front, rear, and side radar. Some examples use pulse-Doppler radar sensor(s).

[0148] The radar sensor(s) 960The configurations can include various options, such as long-range with a narrow field of view, short-range with a wide field of view, short-range with side coverage, etc. In some examples, long-range radar can be used for adaptive cruise control functionality. Long-range radar systems can provide a wide field of view, achieved through two or more independent scans, for example, within a range of 250 m. The 960 radar sensor(s) can assist in distinguishing between stationary and moving objects and can be used by ADAS systems for emergency braking assistance and forward collision warnings. Long-range radar sensors can include monostatic multimodal radars with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface.In an example with six antennas, the middle four antennas can generate a focused beam pattern designed to capture the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. The other two antennas can extend the field of view, allowing vehicles entering the... 900 Those entering or leaving the lane can be quickly identified.

[0149] Medium-range radar systems can, for example, have a range of up to 860 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 850 degrees (rear). Short-range radar systems can, without limitation, include radar sensors designed for installation at both ends of the rear bumper. When such a radar sensor system is installed at both ends of the rear bumper, it can generate two beams that continuously monitor the blind spot at the rear and to the sides of the vehicle.

[0150] Short-range radar systems can be used in an ADAS system for blind spot detection and / or as a lane change assistant.

[0151] The vehicle 900 can still use ultrasonic sensor(s) 962 include the ultrasonic sensor(s) 962 , the one / those at the front, rear and / or sides of the vehicle 900It can be positioned and used for parking assistance and / or for creating and updating an occupancy grid. A variety of ultrasonic sensors can be used. 962 different ultrasonic sensors can be used. 962 They can be used for different detection ranges (e.g., 2.5 m, 4 m). The ultrasonic sensor(s) 962 can operate at functional safety levels of ASIL B.

[0152] The vehicle 900 can the LIDAR sensor(s) 964 include the LiDAR sensor(s) 964 The LIDAR sensor(s) can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functionalities. 964 can / may correspond to the functional safety level ASIL B. In some examples, the vehicle can 900 multiple LiDAR sensors 964include (e.g., two, four, six, etc.) that can use Ethernet (e.g., to deliver data to a Gigabit Ethernet switch).

[0153] In some examples, the LIDAR sensor(s) can... 964 be able to provide a list of objects and their distances for a 360-degree field of view. Commercially available LiDAR sensor(s) 964 They can have an advertised range of approximately 800m, with an accuracy of 2cm-3cm and support for an 800Mbps Ethernet connection, for example. In some examples, one or more non-protruding LiDAR sensors may be used. 964 can be used. In such examples, the LIDAR sensor(s) 964 It can be implemented as a small device that is installed in the front, rear, sides and / or corners of the vehicle. 900 can be embedded. The LiDAR sensor(s) 964In such examples, a horizontal field of view of up to 820 degrees and a vertical field of view of 35 degrees can be provided, with a range of 200 m even for objects with low reflectivity. The front-facing LiDAR sensor(s) 964 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0154] In some cases, LiDAR technologies, such as 3D flash LiDAR, can also be used. 3D flash LiDAR uses a laser flash as a transmission source to illuminate the vehicle's surroundings up to a distance of approximately 200 m. A flash LiDAR unit includes a sensor that records the travel time of the laser pulse and the reflected light at each pixel, which in turn corresponds to the vehicle's range to the objects.

[0155] The vehicle can still use IMU sensor(s). 966 include the IMU sensor(s) 966can be located in the middle of the rear axle of the vehicle in some examples. 900 be arranged. The IMU sensor(s) 966 The IMU sensor(s) may include, for example, without limitation, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In some examples, such as six-axis applications, the IMU sensor(s) may include, for example, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. 966 Accelerometers and gyroscopes are included, while in nine-axis applications the IMU sensor(s) 966 These may include accelerometers, gyroscopes, and magnetometers.

[0156] In some embodiments, the IMU sensor(s) can be 966It can be implemented as a miniaturized, high-performance GPS-based inertial navigation system (GPS / INS) that combines MEMS inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and orientation. In some examples, the IMU sensors can be used 966 the vehicle 900 enabling the course to be estimated without the need for input from a magnetic sensor by directly observing speed changes from GPS and combining them with the IMU sensors. 966 can be correlated. In some examples, the IMU sensor(s) 966 and the GNSS sensor(s) 958 combined in a single integrated unit.

[0157] The vehicle can use the microphone(s) 996 include those in and / or around the vehicle 900 are attached around it. The microphone(s) 996can be used, among other things, to detect and identify emergency vehicles.

[0158] The vehicle can still include any number of camera types, e.g. stereo camera(s). 968 , wide-angle camera(s) 970 Infrared camera(s) 972 , Surround camera(s) 974 , long-range and / or medium-range camera(s) 998 and / or other camera types. The cameras can be used to capture image data around the entire perimeter of the vehicle. 900 The camera types used depend on the specific design and requirements of the vehicle. 900 and any combination of camera types can be used to provide the necessary coverage around the vehicle 900to ensure this. Furthermore, the number of cameras can vary depending on the specific implementation. The vehicle may, for example, include six cameras, seven cameras, ten cameras, twelve cameras, and / or any other number of cameras. The cameras may, by way of example and without limitation, support Gigabit Multimedia Serial Link (GMSL) and / or Gigabit Ethernet. Each of the camera(s) is referred to herein with reference to Fig. 9A and Fig. 9B is described in more detail.

[0159] The vehicle 900 can still use the vibration sensor(s) 942 include the vibration sensor(s) 942 It can measure vibrations from vehicle components, such as the axle(s). For example, changes in vibrations could indicate a change in the road surface. In another example, if two or more vibration sensors are used... 942The differences between the vibrations can be used to determine the friction or slippage of the road surface (e.g., when the difference in vibration is between a driven axle and a freely rotating axle).

[0160] The vehicle 900 Can an ADAS system 938 include the ADAS system. 938 In some examples, it may include a SoC. The ADAS system 938 It may include autonomous / adaptive / automatic cruise control (ACC), cooperative adaptive cruise control (CACC), forward collision warning (FCW), automatic emergency braking (AEB), lane departure warning (LDW), lane keeping assist (LKA), blind spot warning (BSW), rear cross traffic alert (RCTW), collision warning system (CWS), lane centering (LC) and / or other features and functions.

[0161] In at least one embodiment, each of the various actions of the remediation administrator can be performed. 118 regarding the ADAS system 938 and / or one or more of the above-mentioned functionalities (e.g. displaying, disabling, logging, etc.) will occur.

[0162] The ACC systems can use radar sensor(s). 960 , LiDAR sensor(s) 964 and / or use camera(s). ACC systems can include longitudinal ACC and / or lateral ACC. Longitudinal ACC monitors and regulates the distance to the vehicle immediately in front. 900 and automatically adjusts the vehicle speed to maintain a safe distance from vehicles ahead. The lateral ACC manages the distance control and advises the vehicle. 900 , to change lanes when necessary. Lateral ACC is related to other ADAS applications such as LCA and CWS.

[0163] CACC uses information from other vehicles transmitted via the network interface 924 and / or the radio antenna(s) 926 Data can be received from other vehicles via a wireless connection or indirectly via a network connection (e.g., via the internet). Direct connections can be provided through a vehicle-to-vehicle (V2V) communication link, while indirect connections can be an infrastructure-to-vehicle (12V) communication link. Generally, the V2V communication concept provides information about the immediately preceding vehicles (e.g., vehicles directly in front of the vehicle). 900 and are in the same lane as this one), while the 12V communication concept provides information about traffic further ahead. CACC systems can incorporate either one or both 12V and V2V information sources. Based on the information about the vehicles in front of the vehicle... 900CACC can be more reliable and has the potential to improve traffic flow and reduce road congestion.

[0164] FCW systems are designed to warn the driver of a hazard so they can take corrective action. FCW systems use a forward-facing camera and / or radar sensor(s). 960 These systems are coupled with a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically linked to feedback for the driver, such as a display, speaker, and / or vibrating component. FCW systems can issue a warning, for example, in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0165] AEB systems detect an impending forward collision with another vehicle or object and can automatically apply the brakes if the driver does not intervene within a specified time or distance parameter. AEB systems may use forward-facing camera(s) and / or radar sensor(s). 960 They use chips coupled with a dedicated processor, DSP, FPGA, and / or ASIC. When the AEB system detects a hazard, it typically first warns the driver so they can take corrective action to avoid the collision. If the driver fails to take corrective action, the AEB system can automatically apply the brakes to prevent or at least mitigate the effects of the predicted collision. AEB systems may include techniques such as dynamic brake assist and / or anticipatory braking.

[0166] The vehicle 900The infotainment SoC can continue to be used. 930 include (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as a SoC, the infotainment system may not be a SoC and may comprise two or more discrete components. The Infotainment SoC 830 may include a combination of hardware and software to provide audio (e.g., music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation systems, rear parking sensors, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fluid level, oil level, door open / close status, air filter information, etc.) to the vehicle. 900 The infotainment SoC 930It can include, for example, radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, audio controls on the steering wheel, hands-free systems, a heads-up display (HUD), and an HMI display. 934 , a telematics device, a control panel (e.g. for controlling and / or interacting with various components, functions and / or systems) and / or other components.

[0167] The infotainment SoC 930 It can include GPU functionality. The infotainment SoC 930 can be taken by bus 902 (e.g. CAN bus, Ethernet, etc.) with other devices, systems and / or components of the vehicle 900 communicate. In some examples, the infotainment SoC can 930 be coupled with a monitoring MCU so that the infotainment system's GPU can perform some autonomous driving functions when the primary control(s) 936(e.g. the vehicle's primary and / or backup computers) 900 ) fail. In such an example, the infotainment SoC may fail. 930 the vehicle 900 put it into a chauffeur-to-safe-stop mode, as described here.

[0168] The vehicle 900 can still be an instrument cluster 932 include (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 932 It can include a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). The instrument cluster 932It can include a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, shift position indicator, seatbelt warning light(s), parking brake warning light(s), engine function light(s), airbag (SRS) system information, lighting controls, safety system controls, navigation information, etc. In some examples, the information can be retrieved from the infotainment system-on-a-chip (SoC). 930 and the instrument cluster 932 displayed and / or shared. In other words, the instrument cluster 932 can be part of the infotainment SoC 930 It includes or vice versa.

[0169] In at least one embodiment, one or more indicators can be specified by the remediation administrator. 118 be provided using one or more of the infotainment SoCs 930 , of the instrument cluster 932 or the HMI display 934be displayed and / or shown.

[0170] Fig. 9D is a system diagram for the communication between the cloud-based server(s) and the example autonomous vehicle. 900 from Fig. 9A, according to some embodiments of the present disclosure. The system 976 can the server(s) 978 , the network(s) 990 and the vehicles, including the vehicle 900 , include. The server(s) 978 can / can use a variety of GPUs 984(A)-984(H) (hereinafter collectively referred to as GPUs) 984 (referred to herein as PCIe switches 982(A)-982(H)), PCIe switches 982(A)-982(H) (hereinafter collectively referred to as PCIe switches 982), and / or CPUs 980(A)-980(B) (hereinafter collectively referred to as CPUs) 980 (designated) include. The GPUs 984 , the CPUs 980and the PCIe switches can be interconnected via high-speed interconnects, such as, without limitation, NVIDIA's NVLink 988 interfaces and / or PCIe 986 connections. In some examples, the GPUs 984 via NVLink and / or NVSwitch SoC and the GPUs 984 and the PCIe switches 982 connected via PCIe interconnects. Although eight GPUs 984 , two CPUs 980 The fact that two PCIe switches are shown should not be interpreted as a limitation. Depending on the specific implementation, each of the servers can be used. 978 any number of GPUs 984 , CPUs 980 and / or PCIe switches. The server(s) 978 For example, eight, sixteen, thirty-two and / or more GPUs can be used. 984 include.

[0171] The server 978 can (can) via the network(s) 990and receive image data from the vehicles that are representative of images showing unexpected or changed road conditions, e.g., recently started roadworks. The server(s) 978 can (can) via the network(s) 990 and neural networks for the vehicles 992 , updated neural networks 992 and / or map information 994 The information transmitted includes details on traffic and road conditions. The map information updates 994 Updates for the HD card are possible 922 This includes, for example, information about construction sites, potholes, detours, floods, and / or other obstacles. In some examples, the neural networks can 992 , the updated neural networks 992 and / or the map information 994resulting from new training and / or experience represented in data received from any number of vehicles in the environment, and / or based on training conducted in a data center (e.g., using the server(s)) 978 and / or other server).

[0172] The server(s) 978can be used to train machine learning models (e.g., neural networks) based on training data. The training data can be generated by the vehicles and / or created in a simulation (e.g., using a game engine). In some examples, the training data is tagged (e.g., if the neural network benefits from supervised learning) and / or subjected to other preprocessing, while in other examples, the training data is not tagged and / or preprocessed (e.g., if the neural network does not require supervised learning). Once the machine learning models are trained, they can be used by the vehicles (e.g., via the network(s)). 990 (transferred to the vehicles), and / or the machine learning models can be accessed from the server(s) 978They can be used to monitor the vehicles remotely.

[0173] In some examples, the server(s) 978 Receive data from the vehicles and apply that data to current real-time neural networks for intelligent, real-time inference. The server(s) 978 This may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 984, such as the DGX and DGX Station machines developed by NVIDIA. In some examples, the server(s) may 978 However, it includes a deep learning infrastructure that uses only CPU-powered data centers.

[0174] The deep learning infrastructure of the server(s) 978 It can be capable of rapid, real-time inference and can use this capability to determine the state of the processors, software, and / or associated hardware in the vehicle. 900to evaluate and verify. For example, the deep learning infrastructure can provide periodic updates from the vehicle. 900 received, such as a sequence of images and / or objects that the vehicle 900 in this sequence of images (e.g., via computer vision and / or other machine object classification techniques). The deep learning infrastructure can execute its own neural network to identify the objects and match them with the data from the vehicle. 900 to compare identified objects. If the results do not match and the infrastructure concludes that the AI ​​in the vehicle 900 if the server(s) malfunction, 978 a signal to the vehicle 900 send a fail-safe computer to the vehicle. 900 instructs the driver to take over control, notify the passengers, and perform a safe parking maneuver.

[0175] The server can perform inferences. 978 the GPU(s) 984 and include one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). The combination of GPU-powered servers and inference acceleration can enable real-time responsiveness. In other examples, such as when performance is less critical, servers with CPUs, FPGAs, and other processors can be used for inference.

[0176] Fig. Figure 10 is a block diagram of an example computing device. 1000 , which is suitable for use in the implementation of some embodiments of the present disclosure. The computing device 1000 can a bus 1002 include, which directly or indirectly connects the following devices: storage 1004 , one or more central processing units (CPUs) 1006 , one or more graphics processing units (GPUs) 1008, a communication interface 1010 , Input / Output (I / O) Ports 1012 , Input / Output Components 1014 , a power supply 1016 and one or more presentation components 1018 (e.g. advertisement(s)).

[0177] Although the various blocks in Fig. 10 as via the bus 1002 The fact that components are shown connected by cables is not intended to be restrictive and is only for clarity. In some examples, for instance, a presentation component may be shown. 1018 , such as a display device, as an I / O component 1014 This can be considered (e.g., if the display is a touchscreen). CPUs can serve as another example. 1006 and / or GPUs 1008 a storage area (e.g., the storage area can be a storage area). 1004 a storage device in addition to the GPUs' memory 1008 , the CPUs 1006and / or other components). In other words, the computing device of Fig. Figure 10 is for illustrative purposes only. No distinction is made between categories such as "workstation", "server", "laptop", "desktop", "tablet", "client device", "mobile device", "handheld device", "game console", "electronic control unit (ECU)", "virtual reality system" and / or other device or system types, as all fall within the scope of the computing device of Fig. 10 should be considered.

[0178] The bus 1002 It can represent one or more buses, such as an address bus, a data bus, a control bus, or a combination thereof. The bus 1002may include one or more bus types, e.g. an ISA bus (Industry Standard Architecture), an EISA bus (Extended Industry Standard Architecture), a VESA bus (Video Electronics Standards Association), a PCI bus (Peripheral Component Interconnect), a PCIe bus (Peripheral Component Interconnect Express) and / or another type of bus.

[0179] The storage 1004 Computer-readable media can encompass a wide variety of media. These media can be any available media to which the computing device has access. 1000 can be accessed. Computer-readable media can include both volatile and non-volatile media, as well as removable and non-removable media. By way of example, and without limitation, computer-readable media can include computer storage and communication media.

[0180] Computer storage media can include both volatile and non-volatile media, and / or removable and non-removable media, implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, and / or other data types. For example, storage can be 1004 Computer storage media store computer-readable instructions (e.g., representing one or more programs and / or one or more program elements, such as an operating system). Computer storage media can include RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, Digital Versatile Discs (DVD) or other optical disk storage, magnetic cartridges, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and to which the computing device can access it. 1000It can access, but is not limited to. As used here, the term "computer memory" does not inherently include signals.

[0181] Communication media can embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal, such as a carrier wave or other transport mechanism, and include any information transmission media. The term "modulated data signal" can refer to a signal in which one or more of its properties have been set or modified to encode information within the signal. Communication media can include, but are not limited to, wired media such as a wired network or a direct-wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media. Combinations of the aforementioned media should also be included in the scope of computer-readable media.

[0182] The CPU(s) 1006It can be configured to execute computer-readable instructions to control one or more components of the computing device. 1000 to control in order to execute one or more of the procedures and / or processes described here. The CPU(s) 1006 Each CPU can comprise one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) capable of processing a large number of software threads simultaneously. 1006 can include any type of processor and depends on the type of computing device implemented. 1000 Different types of processors are included (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). Depending on the type of computing device. 1000 The processor can be, for example, an ARM processor implemented with a reduced instruction set (RISC), or an x86 processor implemented with a complex instruction set (CISC). The computing device1000 can one or more CPUs 1006 include, in addition to one or more microprocessors or additional co-processors, such as mathematical co-processors.

[0183] The GPU(s) 1008 can / are able to from the computing device 1000 They are used for rendering graphics (e.g., 3D graphics). The GPU(s) 1008 It can comprise hundreds or thousands of cores capable of processing hundreds or thousands of software threads simultaneously. The GPU(s) 1008 can occur in response to rendering commands (e.g., rendering commands from the CPU(s)) 1006 (received via a host interface) generate pixel data for output images. The GPU(s) 1008 It can include graphics memory, such as display memory, for storing pixel data. The display memory can be part of the memory. 1004 It includes the GPU(s). 1008It can include two or more GPUs working in parallel (e.g., via a single connection). In combination, each GPU can 1008 Generate pixel data for different parts of an output image or for different output images (e.g., one GPU for a first image and a second GPU for a second image). Each GPU can have its own dedicated memory or share memory with other GPUs.

[0184] In examples where the computing device 1000 the GPU(s) 1008 not included, the CPU(s) 1006 used for rendering graphics.

[0185] The communication interface 1010 may include one or more receivers, transmitters and / or transceivers that enable the computing device 1000 To enable communication with other computing devices via an electronic communications network, including wired and / or wireless communication. The communication interface1010 It can include components and functionalities that enable communication over a range of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communication over Ethernet), low-power wide area networks (e.g., LoRaWAN, SigFox, etc.), and / or the Internet.

[0186] The I / O ports 1012 can enable the computing device 1000 logically coupled with other devices, including the I / O components 1014 , the presentation component(s) 1018 and / or other components, some of which are integrated into the computing device 1000 They can be built-in (e.g., integrated). Example I / O components 1014These include a microphone, mouse, keyboard, joystick, gamepad, game controller, satellite dish, scanner, printer, wireless device, etc. The I / O components 1014 They can provide a natural user interface (NUI) that processes air gestures, speech, or other physiological inputs generated by a user. In some cases, the inputs can be transmitted to an appropriate network element for further processing. An NUI can use any combination of speech recognition, pen recognition, facial recognition, biometric recognition, gesture recognition (both on-screen and off-screen), air gestures, head and eye tracking, and touch recognition (as detailed below) in conjunction with a display of the computing device. 1000 implement. The computing device 1000It can include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations thereof, for gesture recognition and control. Additionally, the computing device can 1000 This includes accelerometers or gyroscopes (e.g., as part of an inertial measurement unit (IMU)) that enable motion detection. In some examples, the output of the accelerometers or gyroscopes can be taken from the computing device. 1000 They can be used to render immersive augmented reality or virtual reality.

[0187] The power supply 1016 The power supply can include a hardwired power supply, a battery power supply, or a combination of both. 1016 can the computing device 1000 to supply power in order to operate the components of the computer device 1000 to enable.

[0188] The presentation component(s) 1018The presentation component(s) may include a display (e.g., a monitor, touchscreen, television screen, heads-up display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. 1018 can / can access data from other components (e.g., the GPU(s)) 1008 , the CPU(s) 1006 etc.) receive and output the data (e.g. as image, video, sound, etc.).

[0189] The disclosure can be described in the general context of computer code or machine-usable instructions, including computer-executable instructions such as program modules that are executed by a computer or other machine, such as a personal data assistant or other portable device. In general, program modules, including routines, programs, objects, components, data structures, etc., comprise code that performs specific tasks or implements certain abstract data types. The disclosure can be practiced in a variety of system configurations, including handheld devices, consumer electronics, general-purpose computers, more specialized computing devices, etc. The disclosure can also be applied in distributed computing environments where tasks are performed by remotely operating devices connected via a communication network.

[0190] When "and / or" is used here in reference to two or more elements, it refers to only one element or a combination of elements. For example, "element A, element B and / or element C" can include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. Furthermore, "at least one of element A or element B" can include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Similarly, "at least one of element A and element B" can include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

[0191] The subject matter of this disclosure is specifically described herein to satisfy legal requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have considered that the claimed subject matter may also be embodied in other ways to encompass various steps or combinations of steps similar to those described in this document in conjunction with other present or future technologies. Although the terms "step" and / or "block" may be used here to denote various elements of the processes employed, these terms should not be interpreted as implying a particular sequence among or between the various steps disclosed herein, unless the sequence of each step is expressly described. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US J3016201806

[0082] US J3016201609

[0082] US 16 / 101232

[0128]

Claims

[1] Procedure encompassing: Performing multiple instances of a fault test on a hardware component of a computer platform by applying different values ​​of a physical operating parameter to the hardware component for each instance; Determine, from the results of the multiple instances of the fault test, a value of the physical operating parameter at which the hardware component transitions from passing the fault test to failing the fault test; Determining a degradation rate that corresponds to a limit value of the physical operating parameter at which the hardware component is able to pass the fault test, based at least partially on the value of the physical operating parameter; Determine that the degradation rate exceeds a reference degradation rate; and Determine one or more remedial measures based at least partially on the degradation rate exceeding the reference degradation rate. [2] Method according to claim 1, wherein determining the degradation rate of the limit value of the physical operating parameter comprises: Performing multiple additional instances of the fault test on the hardware component by applying different values ​​of the physical operating parameter to the hardware component for each of the additional instances; Determining an additional value of the physical operating parameter from the results of the multiple additional instances of the fault test, in which the hardware component transitions from passing the fault test to failing the fault test; and Calculating the degradation rate based on a difference between the value and the additional value and an operating time between running the multiple instances and running the multiple additional instances. [3] Method according to claim 1, wherein the physical operating parameter is a power supply voltage for the hardware component, and the degradation rate goes down to a minimum value of the power supply voltage at which the hardware component is able to pass the fault test. [4] The method of claim 1, further comprising determining the results of each of the multiple instances of the fault test, wherein determining for each instance comprises comparing one or more outputs of the hardware component with one or more expected outputs of the hardware component. [5] Method according to claim 1, wherein the hardware component comprises a storage device, the fault test comprises a built-in self-test of the storage device, and performing the fault test comprises applying a test pattern of the built-in self-test to the storage device. [6] Method according to claim 1, further comprising determining each of the different values ​​of the physical operating parameter, based at least partially on a temperature measurement of the hardware component. [7] Method according to claim 1, further comprising determining each of the different values ​​of the physical operating parameter at least partially based on an operating speed of the hardware component. [8] Method according to claim 1, further comprising determining the reference degradation rate based on a measurement representing an operating time of the hardware component until the execution of the multiple instances of the fault test. [9] Method according to claim 1, wherein the hardware component belongs to an automated driving system of a vehicle and the one or more remedies comprise disabling the autonomous driving of the vehicle. [10] Procedure encompassing: Applying one or more test parameters of a fault test to a hardware component of a computer platform to generate one or more outputs from the hardware component; Determining a value of a performance characteristic of the hardware component, at least partially, based on analyzing one or more outputs of the hardware component; Determine that a degradation rate of the hardware component's performance characteristic exceeds a reference degradation rate, at least partially based on a measurement representing an operating time of the hardware component; and Determine one or more corrective actions, at least partially, based on the degradation rate of the performance characteristic that exceeds the reference degradation rate. [11] Method according to claim 10, wherein the determination of the value of the performance characteristic is based at least partially on the comparison of the one or more outputs of the hardware component and one or more expected outputs of the hardware component. [12] Method according to claim 10, wherein the one or more outputs of the hardware component include a logical output and the determination of the value of the performance characteristic is based at least partially on a comparison between the logical output of the hardware component and an expected logical output of the hardware component. [13] Method according to claim 10, wherein determining the value of the power characteristic is based at least partially on determining a level of an electrical characteristic of one or more outputs of the hardware component. [14] Method according to claim 10, wherein the performance characteristic corresponds to one or more of a minimum operating voltage, a minimum operating current or a maximum operating clock frequency below which the hardware component is able to pass the fault test. [15] Method according to claim 10, wherein the performance characteristic corresponds to a leakage current of the hardware component. [16] Method according to claim 10, wherein the one or more outputs of the hardware component comprise output signals and determining the value of the performance characteristic comprises: determining one or more dimensions of an eye pattern formed by the output signals; and determining that the one or more dimensions of the eye pattern exceed a threshold value. [17] Method according to claim 10, wherein one or more remedial measures comprise causing the display of an indicator of the degradation rate which exceeds the reference degradation rate. [18] System comprising a hardware component of an autonomous driving circuit of a vehicle, wherein the hardware component is used by the autonomous driving circuit to generate control signals that control the autonomous driving of a vehicle while an operating value of a supply voltage is applied to the hardware component; one or more processing devices and one or more storage devices that are communicatively coupled to the one or more processing devices and store programmed commands which, when executed by the one or more processing devices, cause the following instantiations: a fault tester that performs multiple instances of a fault test on the hardware component by applying supply voltage values ​​to the hardware component that are smaller than the operating value and determining a value that corresponds to a minimum supply voltage at which the hardware component is able to pass the fault test; a degradation rate determiner that determines a degradation rate of the minimum supply voltage based on the value corresponding to the minimum supply voltage; and a remediation determiner that determines one or more remedial measures at least partially based on the degradation rate of the minimum supply voltage. [19] System according to claim 18, wherein the autonomous driving control and the one or more processing devices are implemented on a system-on-a-chip (SoC). [20] System according to claim 18, wherein the fault tester determines the value corresponding to the minimum supply voltage based on the identification of a transition between a first of the values ​​of the supply voltage at which the hardware component passes the fault test and a second of the values ​​of the supply voltage at which the hardware component fails the fault test.