Chip component and process for manufacturing chip components

Abstract

A chip component comprising: a component main body on which a functional element is formed; a pair of internal electrodes designed to cover both end sections of the component main body and connected to the functional element; a barrier layer formed on the surface of each of the pair of internal electrodes, consisting mainly of nickel; and an external connection layer formed on a surface of the barrier layer and consisting mainly of tin, where the barrier layer consists of an alloy coating containing nickel and phosphorus, formed by electrolytic coating, the phosphorus content in the alloy coating of an inner region adjacent to each pair of internal electrodes differs from that of an outer region adjacent to the external terminal layer, and at least the inner region of the barrier layer exhibits magnetic properties.

Description

[0001] The present invention relates to a surface-mount chip component in which external electrodes for soldering are provided at both end sections of a component main body, and to a method for manufacturing such a chip component.

[0002] A chip resistor, which is one example of a chip component, mainly comprises a rectangular, parallelepiped, insulating substrate (component body), a pair of front electrodes arranged on the front surface of the insulating substrate so that they face each other with a predetermined distance between them, a resistor (functional element) that forms a bridge between the pair of front electrodes, a protective film covering the resistor, a pair of back electrodes arranged on the back of the insulating substrate so that they face each other with a predetermined distance between them, a pair of end-face electrodes, each of which bridges the corresponding front and back electrodes, and a pair of external electrodes formed at each of the end sections of the insulating substrate, each of which bridges the corresponding front electrode.Covers back electrode and end surface electrode.

[0003] The corresponding front electrode, back electrode, and end-face electrode serve as internal electrodes, and each electrode is formed from a material containing silver (Ag) or copper (Cu) as its main component. Each of the external electrodes contains a barrier layer, primarily composed of nickel (Ni), deposited on the surface of the internal electrode, and an external terminal layer, primarily composed of tin (Sn), deposited on the surface of the barrier layer. The barrier layer and the external terminal layer are formed by an electrolytic coating.

[0004] When mounting a chip resistor with this structure on a printed circuit board (PCB), the resistor is placed onto a designated area of ​​the PCB's wiring pattern after the solder paste has been applied. Each of the external connection layers then overlaps the solder paste. Melting and solidifying the solder paste in this state solders each external connection layer to the contact surface. A eutectic solder, for example, is used, in which tin (Sn) and lead (Pb) are mixed in a ratio of approximately 6:4 (Sn 63% - Pb 37%). Although the melting point of a eutectic solder with this composition is 183°C, heat at or above this melting point is required to melt the solder.Accordingly, the phenomenon can occur that Ag and Cu, which form an internal electrode, melt due to the heat at the time of soldering, which is called "solder leaching".

[0005] To prevent solder leaching, a barrier layer formed by nickel plating is provided. It is known that a nickel coating with a thickness of 2 µm or more can effectively prevent solder leaching. However, a thick nickel coating (especially 15 µm or more) can be easily detached from the insulating substrate by external stress, which can lead to problems such as a break in the connection due to detachment and sulfidation of the detached portion due to corrosion gas. As described in JP H07-230904 A, a terminal electrode structure has been proposed in which, after the deposition of gold (Au) on the internal electrode of the chip resistor, a nickel coating (barrier layer) and a tin coating (external terminal layer) are successively formed to increase the adhesion of the nickel coating forming the barrier layer.

[0006] In recent years, the use of lead-free solder, which contains almost no lead, has been recommended with regard to global environmental protection. Since the melting point of this lead-free solder is 220°C and the heating temperature during soldering is higher than when using eutectic solder, the nickel forming the barrier layer readily melts into the solder material. Consequently, it is necessary to prevent solder leaching by thickening the nickel plating; however, a thick nickel plating is prone to flaking. Thus, preventing both solder leaching and flaking is difficult, and thickening the nickel plating also increases plating time and material costs.In this context, as in the case of the terminal electrode structure according to JP H07-230904 A, carrying out the process of depositing gold as an underlayer of the nickel coating can increase the adhesion of the nickel coating, but this increases the cost.

[0007] JP H11-67 588 A discloses a chip component comprising a main body and a pair of internal electrodes electrically connected to the functional element. Each internal electrode is covered by a barrier layer, which is simultaneously covered by an external terminal layer. The terminal layer consists primarily of tin, while the barrier layer is an alloy coating containing nickel and phosphorus, produced by electrolytic deposition.

[0008] DE 11 2013 001 682 T5 also discloses a chip component with a functional element and three layers of electrodes covering the end faces of the component, the middle layer being made of a nickel-phosphorus alloy.

[0009] The present invention was made in view of the circumstances of the prior art described above, and the first object of the present invention is to provide a chip component having a terminal electrode structure capable of preventing both solder leaching and solder detachment, and the second object is to provide a method for manufacturing the chip component with the structure described above.

[0010] To solve the problem described above, the present invention provides a chip component comprising a component main body on which a functional element is formed; a pair of internal electrodes configured to cover both end sections of the component main body and connected to the functional element; a barrier layer formed on a surface of each of the two internal electrodes and consisting mainly of nickel;and an external terminal layer formed on a surface of the barrier layer and consisting mainly of tin, wherein the barrier layer consists of an alloy coating containing nickel and phosphorus and is formed by electrolytic coating, wherein a concentration rate of phosphorus in the alloy coating of an inner region adjacent to each of the two internal electrodes differs from that of an outer region adjacent to the external terminal layer, and wherein at least the inner region of the barrier layer has magnetic properties.

[0011] The chip component has the structure described above, wherein the barrier layer, which serves as the sublayer of the external connection layer, is formed from an alloy coating (Ni-P) comprising nickel (Ni) as the main component and containing phosphorus (P), and since the use of the alloy coating slows down the diffusion into the tin compared to the use of nickel, it is possible to prevent solder leaching at high temperature without making the barrier layer too thick.Furthermore, since the concentration rate of phosphorus in the alloy coating forming the barrier layer differs between the inner and outer regions, meaning that at least the inner region of the barrier layer has magnetic properties, it is possible to use these magnetic properties to, for example, perform magnetic sorting in a product testing process and to stabilize the product's orientation through its magnetic properties in an adhesive tape process when the product is stored in tape-like packaging or when the product is removed from the packaging and mounted on a printed circuit board.

[0012] In the chip component with the structure described above, in order to provide the inner region of the barrier layer with magnetic properties, the proportion of phosphorus in the inner region of the barrier layer is preferably 5% or less.

[0013] To solve the second problem described above, the present invention provides a method for manufacturing a chip component comprising the following steps: forming a functional element on a component main body; generating a pair of internal electrodes to cover both end sections of the component main body; generating a barrier layer containing nickel as a major component and phosphorus on a surface of each of the pair of internal electrodes by electrolytic coating;and forming an external terminal layer, consisting mainly of tin, on a surface of the barrier layer by electrolytic coating, wherein the step of forming the barrier layer by electrolytic coating includes a step of changing a current density over time to make a concentration rate of phosphorus in an inner region adjacent to each of the pair of internal electrodes different from that in an outer region adjacent to the external terminal layer.

[0014] According to the chip component, which is manufactured as described above, the barrier layer, which serves as the sublayer of the external connection layer, is formed from an alloy coating (Ni-P) comprising nickel (Ni) as the main component and containing phosphorus (P), and since the use of the alloy coating slows down the diffusion into the tin compared to the use of nickel, it is possible to prevent solder leaching at high temperature, even without making the barrier layer too thick.Furthermore, the concentration rate of phosphorus in the alloy coating is made different between the inner and outer regions by changing the current density over time during the step of generating the barrier layer by electrolytic coating, in order to provide the barrier layer with an area where the concentration rate of phosphorus is low and an area where the concentration rate of phosphorus is high, whereby the area where the concentration rate of phosphorus is low can have magnetic properties.This makes it possible to use the magnetic properties of the barrier layer to, for example, perform magnetic sorting in a product testing process and to stabilize the position of the product through the magnetic properties in a taping process, the storage of the product in a tape-like packaging, or at the time of removing the product from the packaging and mounting it on a printed circuit board.

[0015] In this case, if the step to form the barrier layer includes a step in which an electrolytic coating is first carried out at a predetermined current density to form a low-phosphorus plating layer in which the phosphorus concentration rate is 0.5% or less, and a step in which the current density is subsequently reduced to form a high-phosphorus plating layer in which the phosphorus concentration rate is high, it is possible to easily generate the barrier layer, which has both magnetic and heat resistance properties, simply by controlling the current density of the electrolytic coating.

[0016] According to the chip component of the present invention and its manufacturing process, it is possible to prevent both solder leaching and solder detachment of a barrier layer designed as a sublayer of an external connection layer, and also to reliably carry out a product testing process and a taping process by utilizing the magnetic properties provided in the barrier layer. Fig. Figure 1 is a top view of a chip resistor according to the embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II of Fig. 1 was recorded. Fig. Figure 3 is a flowchart of a manufacturing process for the chip resistor.

[0017] An embodiment of the present invention is described below with reference to the drawings. Fig. Figure 1 is a top view of a chip resistor 10 according to the embodiment of the present invention. Fig. 2 is a cross-sectional view along line II-II of Fig. 1.

[0018] As in Fig. 1 and Fig. As shown in Figure 2, the chip resistor 10, which is one example of a chip component, mainly comprises a rectangular, parallelepiped insulating substrate 1, a pair of front electrodes 2 formed longitudinally at both ends on the front surface of the insulating substrate 1, and a resistor 3 configured to form a bridge between the pair of front electrodes 2, a protective layer 4 covering the entire resistor 3 and part of the front electrodes 2, a pair of back electrodes 5 formed longitudinally at both ends on the rear surface of the insulating substrate 1, a pair of end surface electrodes 6 formed longitudinally at both end surfaces of the insulating substrate 1 to conductively connect one of the front electrodes 2 and one of the corresponding back electrodes 5, and a pair of external electrodes 7.which covers one of the front electrodes 2, one of the back electrodes 5, and one of the end surface electrodes 6, which correspond to each other.

[0019] The insulating substrate 1 is a main component body, made, for example, of ceramic. The insulating substrate 1 is obtained by dividing a disc-shaped and large-format substrate into several pieces along a first dividing groove and a second dividing groove, which extend vertically and horizontally, respectively.

[0020] Each of the front electrodes 2 is rectangular in shape. The front electrodes 2 are positioned on opposite short sides of the insulating substrate 1 at a predetermined distance between them. The pair of front electrodes 2 is produced by screen printing the Ag pastes and drying and firing the printed pastes.

[0021] The resistor 3 is a functional element and is manufactured by screen printing resistance pastes such as ruthenium oxide, drying, and firing the printed pastes. The resistor 3 is rectangular in plan view, and both ends of the resistor 3 overlap the front electrodes 2 longitudinally. It should be noted that an adjustment groove 3a is formed in the resistor 3, which is provided for adjusting the resistance of the resistor 3.

[0022] The protective layer 4 consists of a double-layer structure with a base layer and a top layer. The base layer is produced by screen printing and firing of the glass pastes and is formed in such a way that it covers the resistor 3 before the adjustment groove 3a is formed. The top layer is produced by screen printing the epoxy resin pastes and heating and curing the printed pastes. After the adjustment groove 3a has been formed on the resistor 3, it is applied from above the base layer in such a way that it completely covers the resistor 3, including the adjustment groove 3a and the base layer.

[0023] Each of the back electrodes 5 is configured to form a rectangular shape. The back electrodes 5 are formed on the back side of the insulating substrate 1 at positions corresponding to the positions of the front electrodes 2, with a predetermined distance between them. The back electrode pair 5 is produced by screen printing the Ag pastes and drying and firing the printed pastes.

[0024] The pair of end-surface electrodes 6 is produced by sputtering Ni-Cr onto the end faces of the insulating substrate 1 or by applying Ag pastes to the end faces of the insulating substrate 1 and heating and curing the applied pastes. Each electrode 6 is configured to conductively connect one of the corresponding front electrodes 2 and one of the corresponding back electrodes 5. The corresponding front electrode 2, end-surface electrode 6, and back electrode 5 serve as an internal electrode with a U-shaped cross-section.

[0025] Each of the external electrodes 7 comprises a barrier layer 8, which is applied to the surface of the internal electrode (front electrode 2, end-face electrode 6, and back electrode 5), and an external connection layer 9, which is applied to the surface of the barrier layer 8. The barrier layer 8 and the external connection layer 9 are formed by electrolytic plating. The barrier layer 8 is an alloy coating (Ni-P plating layer) comprising nickel (Ni) as its main component and containing phosphorus (P), and its thickness is in the range of 2 µm to 15 µm. The external connection layer 9 is a tin plating layer comprising tin (Sn) as its main component, and its thickness is in the range of 2 µm to 15 µm.

[0026] In the alloy coating forming the barrier layer 8, the diffusion into the tin forming the external terminal layer 9 can be suppressed more effectively the higher the phosphorus content of nickel is. However, since an increase in phosphorus content leads to a loss of the magnetic properties of the barrier layer 8, the phosphorus-to-nickel ratio in the barrier layer 8 is adjusted to be in the range of 0.5 to 5%. At this point, the phosphorus concentration in the barrier layer 8 is adjusted differently between an inner and an outer region by controlling the current density of an electrolytic coating, so that at least the inner region of the barrier layer 8 exhibits magnetic properties.

[0027] In particular, by carrying out an electrolytic coating at high current density in an initial stage, a layer with a low phosphorus content, in which the concentration rate of phosphorus is 0.5% or less, is formed in the inner region of the barrier layer 8, and afterwards, by reducing the current density and carrying out an electrolytic coating at low current density, a layer with a high phosphorus content, in which the concentration rate of phosphorus is about 2% to 5%, is formed in the outer region of the barrier layer 8.

[0028] Next, a method for manufacturing the chip resistor 10 with the structure described above will be presented with reference to a [document / reference] in [source]. Fig. 3. Flowchart shown is described.

[0029] The first step is to prepare a large-format substrate from which multi-part insulating substrates 1 are fabricated. The large-format substrate includes the first and second division slots to form a grid pattern, and each of the grids divided by the first and second division slots serves as a single chip area. As shown in Fig. As shown in Figure 3, the following steps, which will be described later, are carried out together on the large-format substrate described above.

[0030] The first step is to screen print the Ag pastes onto the back of the large-format substrate and to dry the printed pastes to form the pair of backside electrodes 5 that are opposite each other with a predetermined distance between them at both ends in the longitudinal direction of each area to form chips (step S1).

[0031] The next step is to screen print the Ag-Pd pastes onto the front surface of the large-format substrate and to dry the printed pastes to form the pair of front electrodes 2, which are opposite each other with a predetermined distance between them at both ends in the longitudinal direction of each area to form chips (step S2).

[0032] The next step involves the simultaneous firing of the front electrodes 2 and the back electrodes 5 at a high temperature of approximately 850°C. It should be noted that the front electrodes 2 and the back electrodes 5 can be fired individually, and furthermore, the front electrodes 2 can be formed before the back electrodes 5 by reversing their formation order.

[0033] The next step is to screen-print the resistance pastes, which contain ruthenium oxide or similar, onto the front of the large-format substrate and to dry the printed pastes to form the resistor 3, both ends of which overlap the front electrodes 2, and then to fire the resistor 3 at a high temperature of about 850°C (step S3).

[0034] The next step is to screen print the glass pastes onto an area covering resistor 3, and to dry the printed pastes to form the substrate layer covering resistor 3, and then to fire the substrate layer at a temperature of about 600°C (step S4).

[0035] The next step is to send a laser beam from above the substrate layer while measuring a resistance value of the resistor 3 by placing a probe against the front electrode pair 2 to form the adjustment groove 3a on the resistor 3, thereby setting the resistance value (step S5).

[0036] The next step involves screen-printing the epoxy resin pastes from above the substrate layer and then heating and curing the printed pastes at a temperature of approximately 200°C to form the coating layer (step S6). This creates the protective layer 4, which consists of a double-layer structure comprising the substrate layer and the top layer.

[0037] The next step, following the primary subdivision of the large-format substrate into strip-shaped substrates along the primary parting groove (step S7), is to sputter Ni / Cr onto the subdivided surfaces of each strip-shaped substrate to form the end-surface electrodes 6 for connecting the front electrodes 2 and the back electrodes 5, which are located on the front and back surfaces of each strip-shaped substrate, respectively (step S8). The end-surface electrodes 6 can also be formed by applying Ag-based pastes to the subdivided surfaces of each strip-shaped substrate instead of sputtering Ni / Cr, and then heating and curing the applied pastes.

[0038] The next step, following the secondary division of the strip-shaped substrates into a plurality of chip-shaped substrates along the second division groove (step S9), is to apply an electrolytic coating to these chip-shaped substrates to form the barrier layers 8 that cover the internal electrodes (front and back electrodes 2, end-surface electrodes 6, and back electrodes 5) at both end sections of each chip-shaped substrate (step S10). Each of the barrier layers 8 is designed to form an alloy coating (Ni-P plating layer) comprising nickel (Ni) as the main component and containing phosphorus (P), with a thickness specified in the range of 2 µm to 15 µm.

[0039] In the alloy coating forming the barrier layer 8, the diffusion into the tin, which forms the external terminal layer 9 to be formed in the next step, can be suppressed more effectively the higher the phosphorus content contained in the nickel. However, since an increase in the phosphorus content leads to a loss of the magnetic properties of the barrier layer 8, the phosphorus-to-nickel ratio in the barrier layer 8 is adjusted to be in the range of 0.5 to 5%. At this point, by controlling the current density (current per unit area) of the electrolytic device used for electrolytic coating, a layer with a low phosphorus content, in which the phosphorus concentration is 0.5% or less, is formed in the inner region of the barrier layer 8 under conditions of high current density in an initial stage.Subsequently, by reducing the current density and electrolytic coating under low current density conditions, a layer with a high phosphorus content, in which the phosphorus concentration rate is high (approximately 2% to 5%), is formed in the outer region of the barrier layer 8. As a result, the inner region of the barrier layer 8, where the phosphorus concentration rate is low, can impart magnetic properties to the barrier layer 8, while the outer region of the barrier layer 8, where the phosphorus concentration rate is high, can suppress diffusion.

[0040] The next step is to perform an electrolytic coating on each chip-shaped substrate to form the external connection layers 9 for covering the surfaces of the barrier layers 8 (step S11). Each of the external connection layers 9 is a plating layer made of Sn, consisting mainly of tin (Sn), with a thickness in the range of 2 µm to 15 µm. In this way, the external electrodes 7 are formed, each consisting of a bilayer structure with the barrier layer 8 and the external connection layer 9.

[0041] As described above, in the chip resistor 10 according to the present embodiment, the barrier layer 8, which serves as a sublayer of the external terminal layer 9 formed from a tin coating, is formed from an alloy coating comprising nickel as the main component and containing phosphorus, and since the use of the alloy coating (Ni-P) slows down the diffusion into the tin compared to the use of nickel, it is possible to prevent solder leaching at high temperature, even without making the barrier layer 8 too thick.To prevent the loss of the magnetic properties of the barrier layer 8, the ratio of the phosphorus content in the alloy coating is also made different between the inner and outer regions, so that at least the inner region of the barrier layer 8 has magnetic properties, and accordingly it is possible to use the magnetic properties of the barrier layer 8 to, for example, carry out magnetic sorting in a product testing process and to stabilize the position of the product by using the magnetic properties in a taping process, for storing the product in a tape-like packaging, or at the time of removing the product from the packaging and mounting it on a printed circuit board.

[0042] In the method for producing the chip resistor 10 according to the present embodiment, the current density of the electrolytic device is controlled during the electrolytic coating process. First, an electrolytic coating is applied at a high current density to form a layer with a low phosphorus content, where the phosphorus concentration is 0.5% or less, in the inner region of the barrier layer 8. Then, by decreasing the current density, a layer with a high phosphorus content, where the phosphorus concentration is high (approximately 2% to 5%), is formed in the outer region of the barrier layer 8. Consequently, it is possible to form the barrier layer 8, which exhibits both magnetic and heat resistance properties, simply by controlling the current density of the electrolytic coating.Since the barrier layer 8 can be formed by changing the current density in a single plating step, it is possible to form the barrier layer 8 with excellent adhesion without interfaces, even though the concentration rate of phosphorus is varied, compared to generating the barrier layer 8 in separate plating steps.

[0043] In the embodiment described above, the low-phosphorus layer, in which the phosphorus concentration is 0.5% or less, is formed in the inner region of the barrier layer 8, and the high-phosphorus layer, in which the phosphorus concentration is approximately 2% to 5%, is formed in the outer region of the barrier layer 8. Meanwhile, the electrolytic coating process for forming the barrier layer 8 can be designed such that the current density is gradually changed from a high-current-density to a low-current-density state, so that the phosphorus concentration in the barrier layer 8 increases continuously from the inner region to the outer region without any boundaries.

[0044] In the embodiment described above, the present invention is applied to a chip resistor with resistor 3 as the functional element. However, the present invention is also applicable to a chip component that has a different functional element than a resistor, for example, an inductor or a capacitor. Reference symbol list 1 Insulating substrate (component main body) 2 front electrode (internal electrode) 3. Resistor (functional element) 4 protective layers 5 Backside electrode (internal electrode) 6 End surface electrode (internal electrode) 7 external electrode 8 barrier layer 9 external connection layer 10 Chip resistor (chip component)

Claims

[1] A chip component comprising: a component main body on which a functional element is formed; a pair of internal electrodes formed to cover both end portions of the component main body and connected to the functional element; a barrier layer formed on a surface of each of the pair of internal electrodes and consisting mainly of nickel; and an external terminal layer formed on a surface of the barrier layer and consisting mainly of tin, where the barrier layer consists of an alloy coating containing nickel and phosphorus and is formed by electrolytic plating, the phosphorus content in the alloy coating of an inner region adjacent to each pair of internal electrodes differs from that of an outer region adjacent to the external terminal layer, and at least the inner region of the barrier layer has magnetic properties. [2] The chip component according to claim 1, wherein the content ratio of phosphorus in the inner region of the barrier layer is 5% or less. [3] A method of manufacturing a chip component comprising the following steps: Creating a functional element on a component main body; Creating a pair of internal electrodes to cover both end portions of the component main body; Forming a barrier layer containing nickel as a main component and phosphorus on a surface of each of the pair of internal electrodes by electrolytic plating; and Creating an external connection layer consisting mainly of tin on a surface of the barrier layer by electrolytic plating, where the step of forming the barrier layer by electrolytic plating includes a step of changing a current density over time to make a concentration rate of phosphorus in an inner region adjacent to each pair of the internal electrodes different from that in an outer region adjacent to the external terminal layer. [4] The method for forming the barrier layer according to claim 3, wherein the step of forming the barrier layer comprises a step of first performing electrolytic plating at a predetermined current density to form a plating layer having a low concentration rate of phosphorus of 0.5% or less, and a step of thereafter reducing the current density to form a plating layer having a high concentration rate of phosphorus in which the concentration rate of phosphorus is large.

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