METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE

Abstract

Metal-insulator-metal capacitor module, which features: a lower electrode base (202; 203) embedded in a lower metal layer (M x ) is trained; a lower electrode (204) which is formed in a dielectric region (230; 232) and which is conductively coupled to the lower electrode base (202; 203) and has: a cup-shaped lower electrode component (220) formed in a lower electrode opening (221) in the dielectric region (230; 232); a lower electrode filling component (222) formed in an inner opening defined by the cup-shaped lower electrode component (220); a planar insulator (206) formed above the lower electrode (204); a lower electrode contact (216) formed in a lower electrode contact opening (312) in the dielectric region (230; 232), wherein the electrode contact opening (312) is laterally offset from the electrode opening (221); an upper electrode (208) embedded in an upper metal layer (M x+1 ) is formed above the planar insulator (206); and a connecting element (214) for the lower electrode, which is located in the upper metal layer (M x+1 ) is formed, wherein the connecting element (214) for the lower electrode (204) is conductively connected to the lower electrode base (202; 203) via the lower electrode contact (216); wherein the lower electrode contact (216) and the cup-shaped lower electrode component (220) are formed by a conformal metal layer (320); wherein the lower electrode filling component (222) is formed by a metal filling layer (330); wherein the lower electrode opening (221) is partially filled by the conformal metal layer (320) and partially by the metal filler layer (330); and wherein the lower electrode contact opening (312) is filled with the conformal metal layer (320) and is free of the metal filler layer (330).

Description

[0001] The present disclosure relates to metal-insulator-metal (MIM) capacitors formed in integrated circuit structures.

[0002] A metal-insulator-metal capacitor (MIM capacitor) is a capacitor consisting of a top metal electrode, a bottom metal electrode, and an insulator (dielectric) between the two electrodes.

[0003] MIM capacitors are important components in many electrical circuits, such as many analog, mixed-signal, and high-frequency circuits using complementary metal-oxide-semiconductor (RF CMOS) circuits. MIM capacitors typically offer better performance than alternatives like POP (poly-oxide-poly) and MOM (metal-oxide-metal lateral flux) capacitors due to lower resistance, better matching for analog circuits (e.g., matching device characteristics such as resistance and capacitance), and / or a better signal-to-noise ratio.

[0004] MIM capacitors are typically built between two compound metal layers (e.g., aluminum layers), which are called metal layers M x and M x+1 These can be described as MIM capacitors. For example, a MIM capacitor can be manufactured using an existing metal layer M. xare designed as a bottom electrode (bottom plate), wherein an insulator and a top electrode are placed over the bottom electrode and a metal layer M is applied over it. x+1 It is connected to the upper and lower electrodes via corresponding vias. The area between the two metal layers M x and M x+1 The formed upper electrode can be made of a different metal than the metal layers M. x and M x+1 be formed. The metal layers M x and M x+1 For example, the electrodes can be made of aluminum, while the upper electrode can be made of titanium / titanium nitride (Ti / TiN), tantalum / tantalum nitride (Ta / TaN) or tungsten (W).

[0005] The upper electrode typically exhibits a higher resistance than the lower electrode because the upper electrode may be limited by thickness constraints and the chosen material, thus limiting the performance of conventional MIM capacitors. MIM capacitors generally have very tight process margins, particularly for the metal etching used to form the upper electrode.

[0006] Furthermore, in MIM capacitors formed in aluminum interconnect (i.e., where the metal layers M x and M x+1 (The aluminum interconnect layers) mean that the lower aluminum electrode is prone to the formation of bumps on its upper surface, for example, as a result of high-temperature processing of aluminum, a metal with a low melting point. These bumps on the lower electrode can negatively or unpredictably affect the breakdown voltage of the MIM capacitor.

[0007] Fig. Figures 1A-1F show side cross-sectional views of an exemplary prior art method for forming a MIM capacitor module 10. As shown in Fig. As shown in 1A, a metallic compound layer M is used. x formed over a dielectric region, e.g. an intermetallic dielectric (IMD) layer known as IMD x is referred to as the metal layer M x It can be made of aluminium or another suitable metal.

[0008] Next, as in Fig. Figure 1B shows an insulating layer 100 deposited, followed by an upper electrode layer 102, from which an upper electrode (top plate) of the MIM capacitor module 10 is formed, as shown in Fig. 1C is shown, which is described further below. The insulating layer 100 can be silicon nitride (Si3N4, also simply referred to as SiN) with a thickness T. insof approximately 50 nm (500 Å), which can be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process. The upper electrode layer 102 can be titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable metal with a thickness T te exhibiting thicknesses of approximately 200 nm (2000 Å). te the upper electrode layer 102, which defines the thickness of the upper capacitor electrode 108 (see Fig. 1C), is typically determined by the thickness of a subsequently formed IMD layer. x+1 (see Fig. 1F, which is described below) limited. For example, the thickness T te the upper electrode layer 102 by the thickness of the subsequently formed IMD x+1 -layer (see Fig. 1F, discussed below), an etch margin of the etching of the upper electrode (see Fig. 1C, discussed below) and a process margin of subsequent chemical-mechanical planarization (CMP) may be limited. In a typical IMD X+1 A layer thickness of 800 nm (8000 Å) can determine the thickness T te The thickness of the upper electrode 102 may be limited to approximately 300 nm (3000 Å) or less. This limited thickness T te The upper electrode layer 102 (and thus the upper capacitor electrode 108) can lead to a high series resistance and a low quality factor (Q-factor) in certain applications, e.g., high-frequency (RF) applications.

[0009] After the insulating layer 100 and the upper electrode layer 102 have been applied, the information printed in the wafer scoring area can be very difficult to read (due to the insulating layer 100, the upper electrode layer 102 and the underlying metal layer M). x), which can lead to manufacturing problems. For example, the wafer lot number and / or the wafer number printed in the wafer scoring area may be difficult to read, which can lead to various problems, such as the inability to conduct controlled experiments with specific wafers distributed across different process conditions, or to record wafer activities (e.g., rejects or incidents) associated with the wafer number.

[0010] Next, as in Fig. Figure 1C shows the application and structuring of a photoresist layer to form a first photomask 106 over the upper electrode layer 102, and etching to delineate the upper electrode 108 of the MIM capacitor from the upper electrode layer 102, wherein the portion of the silicon nitride insulator layer 100 below the upper electrode 108 defines the MIM capacitor insulator, designated 100a. The etching of the upper electrode typically has a very small process margin. In particular, the etching is designed to occur at approximately half the height of the thickness T. ins the insulating layer ends at 100.

[0011] The exact depth of the etching of the upper electrode, which is the thickness T ins etchedThe remaining insulating layer 100 outside the base area of ​​the upper electrode 108, which is referred to as the etched area of ​​the insulating layer 100b, generally depends on certain process parameters, such as the thickness and unevenness of the silicon nitride deposition, as well as the uniformity and selectivity of the etching. If the etching is not deep enough (so that the etched T ins If the etched insulating layer 100b is too thick, the upper electrode layer 102 may not be completely removed in some areas of the wafer (e.g., due to uneven etching), leaving metal residues or stringers on the wafer. These metal residues or stringers can lead to incomplete etching in a subsequent metal etching step, cause metal short circuits, and result in a loss of yield or reliability of the device.

[0012] If, on the other hand, the etching of the upper electrode is too deep (so that T ins_etched (if the etched area of ​​the insulating layer 100b is too thin), the resulting MIM capacitor module 10 may exhibit an inappropriately low breakdown voltage, particularly due to the corner “C” formed in the insulating layer 100 by the etching of the upper electrode described above, as further described below in relation to Fig. 1F explained.

[0013] Therefore, the effective range for thickness T can be ins_etched The etched area of ​​the insulating layer 100b can be very small, thus defining small process margins for etching the upper electrode. For a deposited silicon nitride insulating layer with a thickness T ins of 50 nm (500 Å) the effective target thickness T ins_etched The area 100b of the etched insulating layer has a very small tolerance, for example between 23-27 nm (230-270 Ω).

[0014] Next, as in Fig. 1D shown, the remaining parts of the first photoresist mask 106 were removed and a new photoresist layer was applied and structured to form a second photoresist mask 112 over the upper electrode 108, extending beyond the upper electrode 108 in a first lateral direction.

[0015] Next, as in Fig. Figure 1E shows a metal etching performed to define the lower electrode 116 of the MIM capacitor.

[0016] Finally, as in Fig. Figure 1F shows the construction of the MIM capacitor module 10 by removing the second photomask 112, forming an IMD layer (IMD x+1 ), forming vias 120, each contacting the upper electrode 108 and the lower electrode 116, and forming an upper electrode contact 122 and a lower electrode contact 124 in a metal layer M x+1 above IMDx+1 -Shift completed.

[0017] The MIM capacitor module 10, according to the state of the art, can have various defects. For example, as mentioned above, the thickness T can be te the upper electrode 108 due to a vertical distance limitation between the metal layers M x and M x+1 be limited, represented by the thickness T IMDx+1 of the IMD area x+1 The limited thickness T te The upper electrode 108 can lead to a high series resistance, which is unsuitable for certain applications (e.g. RF applications).

[0018] Furthermore, the MIM capacitor may exhibit a low and / or unpredictable breakdown voltage. For example, the breakdown voltage of the capacitor may be very sensitive to the thickness T. ins_etchedthe etched insulating layer in region 100b, particularly at corner C below the lateral edge of the upper electrode 108, as described above. Furthermore, the breakdown voltage of the capacitor can also be sensitive to the bumps “H” formed on the lower electrode 116 of the capacitor. The formation of bumps can be very difficult to control in the manufacturing process described above. For example, bumps H can form on the lower electrode 116 as a result of various heated process steps during and after the manufacturing of the capacitor, including heat treatment steps and / or heated aluminum deposition steps (e.g., at 400°C). These bumps H can lead to an uncontrolled low breakdown voltage of the capacitor module 10.

[0019] Furthermore, as already mentioned, the deposition of the different material layers (lower metal layer, insulating layer and upper electrode layer) over the wafer ridge area can hinder the readability of the information printed in the wafer ridge area (e.g. wafer number and batch number), which can complicate the manufacturing process.

[0020] A metal-insulator-metal capacitor and a manufacturing process are disclosed in US Patent Application US 2005 / 0067701A1. A capacitor and a method for its manufacture are disclosed in US Patent Application US 2012 / 0091559A1. A semiconductor device with a MIM-type capacitor and a method for its manufacture are disclosed in US Patent Application US 2002 / 0179955A1. A metal-insulator-metal (MIM) capacitor is disclosed in US Patent Application US 2021 / 0265263A1.

[0021] There is a need for improved MIM capacitor modules and training processes that provide larger process margins and / or better capacitor performance. These and other problems are solved by independent claim 1. Further developments are characterized by dependent claims.

[0022] The present disclosure provides an integrated MIM capacitor module having a base of the lower electrode embedded in a lower metal layer M x is formed, a lower electrode which is conductively connected to the base of the lower electrode, a planar insulator which is formed above the lower electrode, an upper electrode which is embedded in an upper metal layer M x+1 formed above the planar insulator is a lower electrode connection element that is embedded in the upper metal layer M x+1The lower electrode is formed and has a lower electrode contact that conductively connects the lower electrode connection element to the base of the lower electrode. The lower electrode has a cup-shaped lower electrode component and a lower electrode filling component, which is formed in an inner opening defined by the cup-shaped lower electrode component.

[0023] One aspect provides a metal-insulator-metal capacitor module comprising a lower electrode base formed in a lower metal layer, a lower electrode conductively connected to the base of the lower electrode, a planar insulator formed above the lower electrode, and an upper electrode formed in an upper metal layer above the planar insulator. The lower electrode has a cup-shaped lower electrode component and a lower electrode filling component formed in an internal opening defined by the cup-shaped lower electrode component.

[0024] In one embodiment, the planar insulator has a uniform vertical thickness across the entire lateral width of the planar insulator.

[0025] In one embodiment, the lower electrode is formed in a dielectric region, and the planar insulator is formed on a planar insulator support surface comprising (a) a planarized top surface of the cup-shaped lower electrode component, (b) a planarized top surface of the lower electrode filling component, and (c) planarized top surface regions of the dielectric region on opposite sides of the lower electrode. The planar insulator extends laterally across the entire lateral width of the lower electrode and beyond, such that the planar insulator extends over the planarized top surface regions of the dielectric region on opposite sides of the lower electrode.

[0026] The planar insulator can have a uniform vertical thickness across its entire lateral width. In some examples, the planar insulator has a uniform vertical thickness across its full lateral width in a first lateral direction. In other examples, the planar insulator has a uniform vertical thickness across its entire lateral width in a first lateral direction and in a second lateral direction perpendicular to the first lateral direction.

[0027] In one embodiment, the lower electrode is formed in a dielectric region, the planar insulator extends laterally over a full lateral width of the lower electrode and beyond, so that the planar insulator extends over parts of the dielectric region laterally next to the lower electrode, and the planar insulator has a uniform vertical thickness over a full lateral width of the planar insulator.

[0028] In one embodiment, the lower electrode is formed in a dielectric region, the planar insulator extends laterally over a full lateral width of the lower electrode in a first lateral direction and in a second lateral direction perpendicular to the first lateral direction, such that the planar insulator extends over sections of the dielectric region laterally next to the lower electrode in both the first and second lateral directions, and the planar insulator has a uniform vertical thickness over a full lateral width of the planar insulator in both the first and second lateral directions.

[0029] In one embodiment, the cup-shaped component of the lower electrode is formed on the base of the lower electrode.

[0030] In one embodiment, the planar insulator is formed on a planarized insulator support surface, which has a planarized top surface of the cup-shaped lower electrode component and a planarized top surface of the lower electrode filling component.

[0031] In one embodiment, the lower electrode is formed in a dielectric region between the lower metal layer and the upper metal layer, and the metal-insulator-metal capacitor module has a lower electrode connection element formed in the upper metal layer and a lower electrode contact formed in the dielectric region between the lower metal layer and the upper metal layer, wherein the lower electrode connection element is conductively connected to the base of the lower electrode via the lower electrode contact.

[0032] In one embodiment, the contact of the lower electrode and the cup-shaped component of the lower electrode are formed from a conformal metal, and the filling component of the lower electrode is formed from a different filling metal than the conformal metal.

[0033] In one embodiment, the conformal metal contains tungsten, and the filler metal contains titanium nitride.

[0034] In one embodiment, the lower metal layer has a lower bonding layer; and the upper metal layer has an upper bonding layer.

[0035] In one embodiment, both the lower bonding layer and the upper bonding layer are made of aluminum.

[0036] In one embodiment, the lower metal layer has a siliciated polysilicon layer, wherein the base of the lower electrode formed in the lower metal layer has a metal silicide region formed on a polysilicon region and the upper metal layer has a first metal compound layer.

[0037] In one embodiment, the lateral surfaces of the upper electrode are self-aligned with the lateral surfaces of the planar insulator.

[0038] Another aspect is an integrated circuit structure comprising an interconnect and a metal-insulator-metal (MIM) capacitor module. The interconnect has a lower interconnect formed in a lower metal layer, an upper interconnect formed in an upper metal layer, and a plated through-hole connecting the lower and upper interconnects. The MIM capacitor module has a lower electrode base formed in the lower metal layer, a lower electrode conductively coupled to the base of the lower electrode, a planar insulator formed over the lower electrode, and an upper electrode formed in the upper metal layer.The lower electrode has a cup-shaped lower electrode component and a lower electrode filling component, which is formed in an internal opening defined by the cup-shaped lower electrode component. The cup-shaped lower electrode and the connecting vias are formed from a common conformal metal.

[0039] In one embodiment, the planar insulator has a uniform vertical thickness across the entire lateral width of the planar insulator.

[0040] In one embodiment, the lower electrode is formed in a dielectric region, and the planar insulator is formed on a planarized insulator support surface comprising (a) a planarized top surface of the cup-shaped lower electrode component, (b) a planarized top surface of the lower electrode filling component, and (c) planarized top surface regions of the dielectric region on opposite sides of the lower electrode. The planar insulator extends laterally over a full lateral width of the lower electrode and beyond, such that the planar insulator extends over the planarized top surface regions of the dielectric region on opposite sides of the lower electrode.

[0041] In one embodiment, the lower electrode is formed in a dielectric region, the planar insulator extends laterally over a full lateral width of the lower electrode and beyond, so that the planar insulator extends over parts of the dielectric region laterally next to the lower electrode, and the planar insulator has a uniform vertical thickness over a full lateral width of the planar insulator.

[0042] In one embodiment, an upper surface of the cup-shaped lower electrode and a filling component of the lower electrode define a planar upper surface of the lower electrode, and the planar insulator is formed on the planar upper surface of the lower electrode.

[0043] In one embodiment, the metal-insulator-metal capacitor module further comprises a lower electrode contact that provides a conductive connection between the base of the lower electrode and a lower electrode connecting element formed in the upper metal layer, wherein the connecting via, the lower electrode contact and the lower electrode are formed in a dielectric region between the lower metal layer and the upper metal layer.

[0044] In one embodiment, the interconnect vias, the contact of the lower electrode and the cup-shaped component of the lower electrode are formed from a common conformal metal.

[0045] In one embodiment, the lower metal layer has a lower bonding layer, and the upper metal layer has an upper bonding layer.

[0046] In one embodiment, the lower metal layer has a siliciated polysilicon layer, wherein the lower connecting element has a first metal silicide region formed on a first polysilicon region, and the base of the lower electrode has a second metal silicide region formed on a second polysilicon region, and the upper metal layer has a first metal compound layer.

[0047] Another aspect provides a method for forming a metal-insulator-metal capacitor module in an integrated circuit structure. A lower metal layer is formed, which includes a base for the lower electrode. A dielectric region is deposited over the lower metal layer. The dielectric region is patterned and etched to form a well opening and a contact opening for the lower electrode. A conformal metal is deposited to simultaneously form (a) a cup-shaped lower electrode component in the well opening and (b) a lower electrode contact in the lower electrode contact opening, with both the cup-shaped lower electrode component and the lower electrode contact being conductively coupled to the base of the lower electrode.A filler metal is deposited to form a fill component for the lower electrode in an internal opening defined by the cup-shaped lower electrode component. A planarization process defines a planarized insulator support surface, featuring a planarized upper surface of the cup-shaped lower electrode component and a planarized upper surface of the lower electrode fill component. A planar insulator is formed on the planarized insulator support surface. An upper metal layer is formed, comprising (a) an upper electrode above the planarized insulator and (b) a connecting element for the lower electrode that is conductively connected to the lower electrode contact.

[0048] In one embodiment, the planar insulator has a uniform vertical thickness across the entire lateral width of the planar insulator.

[0049] In one embodiment, the planarized insulator support surface formed by the planarization process comprises the planarized top surface of the cup-shaped lower electrode component, the planarized top surface of the lower electrode filling component, and planarized top surface regions of the dielectric region on opposite sides of the lower electrode. The planar insulator extends laterally across the entire lateral width of the lower electrode and beyond, such that the planar insulator extends over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode.

[0050] In one embodiment, the planar insulator extends laterally over a full lateral width of the lower electrode and beyond, such that the planar insulator extends over portions of the dielectric region laterally adjacent to the lower electrode, and the planar insulator has a uniform vertical thickness over a full lateral width of the planar insulator.

[0051] In one embodiment, the method comprises depositing an insulating layer on the planarized insulator support surface, depositing an upper metal layer on an insulator layer region of the insulator layer, and structuring and etching the upper metal layer and the underlying insulator layer region to define the upper electrode and the underlying planar insulator, wherein lateral surfaces of the upper electrode are self-aligned with lateral surfaces of the planar insulator.

[0052] Another aspect provides a method for forming an integrated circuit structure comprising a metal-insulator-metal capacitor and an interconnect. A lower metal layer is formed, providing a base for the lower electrode and a lower interconnect. A dielectric region is deposited over the lower metal layer. The dielectric region is patterned and etched to form (a) a well opening and a contact opening for the lower electrode over the base of the lower electrode, and (b) a via opening for the lower interconnect. Conformal metal is deposited to simultaneously form (a) a cup-shaped lower electrode component in the well opening, (b) a lower electrode contact in the lower electrode contact opening, and (c) a via in the via opening.A filler metal is deposited to form a filler component for the lower electrode within an internal opening defined by the cup-shaped lower electrode component. A planarization process defines a planarized insulator support surface, featuring a planarized upper surface for both the cup-shaped lower electrode component and the lower electrode filler component. The cup-shaped lower electrode component and the lower electrode filler component together form a lower electrode. A planar insulator is formed on the planarized surface of the insulator support.An upper connecting metal layer is formed, comprising (a) an upper electrode above the planarized insulator, (b) a connecting element for the lower electrode that is conductively connected to the contact of the lower electrode, and (c) an upper connecting element that is conductively connected to the via.

[0053] Exemplary aspects of the present revelation are described below in connection with the figures in which: Fig. Figures 1A-1F are side cross-sectional views showing an example of a prior art method for forming a MIM capacitor module; Fig. 2A is a side cross-sectional view of a MIM capacitor module formed between two metal compound layers in an integrated circuit structure according to an example; Fig. 2B is a side cross-sectional view of a MIM capacitor module formed between a silicided polysilicon layer and a first metal compound layer in an integrated circuit structure according to an example; Fig. Figures 3-12 are cross-sectional side views that show an example method for forming an integrated circuit structure that implements the in Fig. 2A shows the example MIM capacitor module together with an example interconnect structure; Fig. 13 is a flowchart showing an example procedure for forming an example MIM capacitor module and interconnection structure in an integrated circuit structure according to an example; and Fig. 14 is a flowchart showing an example procedure for forming an example integrated circuit structure including an example MIM capacitor module and a nearby interconnection structure according to an example.

[0054] It is understood that the reference sign for an illustrated element appearing in several different figures has the same meaning in all figures, and that the mention or discussion of an illustrated element in connection with a particular figure also applies to any other figure in which the same illustrated element is shown.

[0055] The present disclosure provides a MIM capacitor module formed between (and comprising) two metal layers in an integrated circuit structure. The MIM capacitor module has a base of the lower electrode that is embedded in a lower metal layer M. xis formed, a lower electrode which is conductively coupled to the base of the lower electrode, a planarized insulator formed above the lower electrode, an upper electrode which is embedded in an upper metal layer M x+1 formed above the insulator is a lower electrode connection element that is embedded in the upper metal layer M x+1The lower electrode comprises a cup-shaped lower electrode component and a lower electrode fill component formed within an internal opening defined by the cup-shaped lower electrode component. The lower electrode can be formed by a Damascene process involving the formation of a cup opening, the deposition of a conformal metal layer (e.g., tungsten) that forms the cup-shaped lower electrode component within the cup opening, the deposition of a fill metal (e.g., titanium nitride) to form the lower electrode fill component within the internal opening of the cup-shaped lower electrode component, and the execution of a planarization process (e.g.,a CMP process) to (a) remove the upper parts of the conformal metal layer and filler metal and (b) define a planarized insulator support surface on the top of the lower electrode.

[0056] The planar insulator can then be formed on the planarized insulator support surface and have a uniform thickness across the entire lateral width of the insulator, which can provide an improved breakdown voltage of the capacitor compared to certain conventional capacitors. By forming the lower electrode from refractory metals, e.g., tungsten and titanium nitride, the upper surface of the lower electrode, which comes into contact with the planarized insulator, can be free of the bumps common in certain conventional capacitors (e.g., capacitors using an aluminum lower electrode), which can provide a higher and more uniform breakdown voltage compared to such conventional capacitors. Furthermore, the upper and lower electrodes can each have a considerable thickness, e.g.,a thickness of at least 400 nm (4000 Ω), which, compared to certain conventional capacitors with a thinner top electrode and / or bottom electrode, can provide improved performance in certain applications (e.g., RF applications).

[0057] As already mentioned, the MIM capacitor module is formed between (and also has) two metal layers, in particular a lower metal layer M. x (in which the base of the lower electrode is formed) and an upper metal layer M x+1 (in which the upper electrode and the connecting element of the lower electrode are formed). As used herein, a “metal layer”, e.g. in connection with the lower metal layer M, can be x and the upper metal layer M x+1 , any metal or metallized layer or layers, including: (a) a compound metal layer, e.g. of aluminium, copper or another metal, formed by a damascene process or by a subtractive structuring process (e.g. deposition, structuring and etching of a metal layer), or (b) a siliciated polysilicon layer having a number of siliciated polysilicon structures (i.e. polysilicon structures on which a metal silicide layer is formed), e.g. a siliciated polysilicon gate of a metal-oxide semiconductor field-effect transistor (MOSFET).

[0058] As in Fig. As shown in Figure 2A, a MIM capacitor module can, for example, be placed between two adjacent metal compound layers M x and M x+1 can be built at any depth within an integrated circuit structure. Another example: As in Fig. As shown in Figure 2B, a MIM capacitor module can be constructed between a silicon-containing polysilicon layer and a first metal compound layer (generally referred to as the metal-1 layer), wherein the silicon-containing polysilicon layer forms the lower metal layer M x with x=0 (i.e., M0) and the first metallic compound layer (metal-1 layer) is the upper metal layer M x+1 (i.e., M1) is defined.

[0059] Fig. Figure 2A is a side cross-sectional view of an exemplary MIM capacitor module 200a, which, according to an example, is sandwiched between two metal compound layers M x and M x+1 is formed in an integrated circuit structure (and includes parts thereof). The exemplary MIM capacitor module 200a has (a) a base of the lower electrode 202 embedded in a lower metal compound layer M xis formed, (b) a lower electrode 204 which is conductively connected to the base of the lower electrode 202, (c) a planar insulator 206 which is formed above the lower electrode 204, and (d) an upper electrode 208 which is formed in an upper metal compound layer M x+1 is formed above the planar insulator 206. The MIM capacitor module 200a also has a [missing information] in the upper metal compound layer M x+1 formed connecting element 214 for the lower electrode and a contact 216 for the lower electrode, which conductively connects the connecting element 214 for the lower electrode to the base of the lower electrode 202.

[0060] The metal compound layers M x and M x+1 They can be made of aluminum, copper, or another suitable alloying metal. For example, the lower electrode 202, which is located in the metal compound layer M, can be made of aluminum, copper, or another suitable alloying metal. xis formed, and the upper electrode 208 and the connecting element 214 of the lower electrode, which is in the upper metal compound layer M x+1 are made of aluminum, copper or another suitable alloy metal.

[0061] The lower electrode 204 has (a) a cup-shaped lower electrode component 220 formed in a cup opening 221 in a dielectric region 230, e.g., an oxide intermetal dielectric (IMD), and (b) a lower electrode filling component 222 formed in an inner opening 224 defined by the cup-shaped lower electrode component 220. The lower electrode 204 can be formed using a Damascene process, as described below with reference to the Fig. 4A-4B to 7A-7B are described in more detail. The cup-shaped lower electrode 220 can be formed from a conformal metal, e.g., tungsten. The filler component 222 of the lower electrode can be formed from a "filler metal" that differs from the conformal metal formed by the cup-shaped lower electrode 220. For example, the filler metal forming the lower electrode 222 can be TiN or another high-melting-point metal that differs from the conformal metal formed by the cup-shaped lower electrode 220.

[0062] In some examples, the lower electrode contact 216 and the cup-shaped lower electrode component 220 can be formed simultaneously by deposition of tungsten or another conformal metal, as described below with reference to Fig. 5 explained. In some examples, an adhesive layer 226 (e.g. a TiN layer with a thickness in the range of 5-30 nm (50-300 Ω)) is deposited in front of the conformal metal (which forms the lower electrode contact 216 and the cup-shaped lower electrode component 220) to improve the adhesion between the conformal metal and the dielectric area 230, especially in the cup opening 221.

[0063] In some examples, the lower electrode contact 216 is designed as a through-hole and can also be referred to as the through-hole for the lower electrode. As further described below with reference to the Fig. As explained in 4A-5, the contact 216 of the lower electrode can, for example, be designed as a via, at the same time as connecting vias that are arranged in the dielectric area 230 (IMD area) at positions other than the MIM capacitor module 200a.

[0064] As in Fig. As shown in Figure 2A, the planar insulator 206 can be formed on a planarized insulator support surface 240. The planarized insulator support surface 240, which can be formed by chemical-mechanical planarization (CMP) or another planarization process, has a planarized top surface 234 of the cup-shaped lower electrode component 220, a planarized top surface 236 of the lower electrode filling component 222, and planarized top surface areas 238a and 238b of the dielectric region 230 on opposite lateral sides of the lower electrode 204 (in the x-direction or in both the x- and y-directions).

[0065] The planarized insulator support surface 240 can be free of metal bumps because the bottom electrode 204 is formed from high-melting-point metals (e.g., tungsten and titanium nitride) that resist the formation of bumps, unlike the aluminum bottom electrode of the prior art MIM capacitor module 10, shown in Figure IF and discussed above. Forming the planar insulator 206 on a surface free of bumps can provide a higher and more uniform breakdown voltage of the capacitor, e.g., compared to a conventional capacitor having a bottom electrode with bumps.

[0066] The surface roughness of the planarized insulator support surface 240 can depend on the specific process parameters (e.g., CMP process parameters). In some examples, the planarized insulator surface 240 exhibits a surface roughness of less than 5 nm (50 Å) (root mean square, RMS). In other examples, the planarized insulator surface 240 exhibits an RMS surface roughness of less than 2 nm (20 Å).

[0067] The planar insulator 206 can be formed directly on the planarized insulator support surface 240. The width W ins of the planarized insulator 206 in the x-direction can be measured with the width W te the upper electrode 208 above it. This is the result of anisotropic metal etching extending through both the upper electrode 208 and the planarized insulator 206, e.g. as in Fig. 11 shown and described below.

[0068] In some examples, e.g., as in Fig. As shown in Figure 2A, the upper electrode 208 and the planar insulator 206 have a larger width (W te , W ins) formed as the underlying lower electrode 204 in the x-direction, such that the planar insulator 206 extends over the entire lateral width of the lower electrode 204 and over the planarized upper surface regions 238a and 238b of the dielectric region 230 on opposite sides of the lower electrode 204 in the x-direction. In other words, the planar insulator 206 extends over the planarized upper surface 234 of the cup-shaped lower electrode component 220, the planarized upper surface 236 of the lower electrode filling component 222, and the planarized upper surface regions 238a and 238b of the dielectric region 230.In some examples, the planarized insulator 206 extends laterally over the entire lateral width of the lower electrode 204 in both the x and y directions and additionally extends over parts of the dielectric region 230 on all lateral sides of the lower electrode 204, so that a perimeter of the planarized insulator region 206, viewed from above, surrounds a perimeter of the lower electrode 204.

[0069] The planar insulator 206 has a uniform thickness T ins across the entire lateral width W ins of the planar insulator 206. In some examples, the thickness T varies. ins the insulating layer 206, for example, by less than 10% across the entire lateral width W ins of the planar insulator 206. In some embodiments, the thickness T varies. ins the insulating layer 206 by less than 5% or even less than 1% across the entire lateral width W ins of the planar insulator 206.

[0070] This uniform thickness T ins across the entire lateral width W ins The planar insulator 206 can exhibit an increased and predictable breakdown voltage for the resulting MIM capacitor module 200, e.g., compared to a capacitor with a partially etched or otherwise varying thickness, e.g., the MIM capacitor 10 manufactured according to the prior art, which is in Fig. 1F was shown and discussed above.

[0071] Furthermore, the lower electrode 204 can be formed by the formation of a layer between two metal layers M x and M x+1 have a thickness that extends over the entire thickness of the dielectric region 230 between the metal layers M x and M x+1 extends. By forming the upper electrode 208 from the metal compound layer M x+1 The upper electrode 208 can have a thickness T te exhibiting the thickness of the metal compound layer Mx+1 is defined. Thus, the thickness of the lower electrode T can be determined. be and the thickness of the upper electrode T te This may be sufficient to provide the desired performance characteristics for various applications (e.g., including RF applications) compared to certain conventional capacitors that have a thinner top electrode and / or bottom electrode. In some examples, the thickness T may be be the lower electrode at least 400 nm (4000Å) and the thickness of the upper electrode T te at least 400 nm (4000 Ω).

[0072] Fig. Figure 2B is a side cross-sectional view of an exemplary MIM capacitor module 200b, formed (and containing parts thereof) between a siliciated polysilicon layer and a first metal compound layer (commonly referred to as the Metal-1 layer), as shown in the example. In this example, the siliciated polysilicon layer defines a lower metal layer M0 (i.e., the lower metal layer M). x , where x=0) and the first metal compound layer (metal-1) is an upper metal layer M1.

[0073] The MIM capacitor module 200b is similar to the one in Fig. 2A shown and discussed above, the MIM capacitor module 200a, except that the MIM capacitor module 200b is located between the siliciated polysilicon layer M0 and the first metal compound layer M1, and not between two metal compound layers M x and M x+1 is trained.

[0074] The MIM capacitor module 200b comprises: (a) a base of the lower electrode 203 formed in the siliciated polysilicon layer M0, (b) a lower electrode 204 comprising a cup-shaped lower electrode component 220 and a lower electrode filling component 222, (c) a planar insulator 206 formed over the lower electrode 204, (d) an upper electrode 208 and a lower electrode connection element 214 formed in the first metal compound layer M1, and (e) a lower electrode contact 216 conductively connecting the lower electrode connection element 214 to the base of the lower electrode 203. The lower electrode 204 and the lower electrode contact 216 are formed in a dielectric region 232, e.g., a pre-metallic dielectric (PMD) region.

[0075] As in Fig. As shown in Figure 2B, the base of the lower electrode 203 is formed by a siliciated polysilicon structure having a metal silicide layer 252 formed on the upper surface of a polysilicon structure 250. The metal silicide layer 252 can have any suitable metal silicide, for example, titanium silicide (TiSi₂), cobalt silicide (CoSi₂), or nickel silicide (NiSi), with a thickness in the range of 10–30 nm (100–300 Å) or another suitable thickness. The cup-shaped lower electrode 220 and the lower electrode contact 216 can be formed on the metal silicide layer 252. The metal silicide layer 252 provides a conductive connection between the lower electrode 204 and the lower electrode contact 216.

[0076] Fig. Figures 3-12 are side cross-sectional views showing, according to an example, a method for forming an exemplary integrated circuit structure 300, which includes the exemplary MIM capacitor module 200a. Fig. 2A together with an adjacent connecting structure 302.

[0077] First, as in Fig. Figure 3 shows a lower metallic compound layer M x formed over a dielectric region 304, e.g., a pre-metallic dielectric (PMD) region or an inter-metallic dielectric (IMD) region. The metal layer M x can be formed from aluminum, copper, or another suitable metal. The metal layer M xcan be deposited, structured, and etched to form (a) the base of the lower electrode 202 for the MIM capacitor module 200a and (b) a lower connecting element 306. Alternatively, the lower electrode 202 and the lower connecting element 306 can also be formed by a damascene process. Both the lower electrode 202 and the lower connecting element 306 can have a wire or other lateral, elongated structure (e.g., in the direction of the y-axis) or a discrete pad (e.g., with a square, circular, or substantially square or circular shape in the xy-plane) or any other suitable shape and structure.

[0078] Resist stripping can be performed to remove residual parts of the photomask that are used for structuring the metal layer M. x was used. An IMD range of 230 can be applied over the metal layer M xcan be formed, for example by oxide deposition (e.g. using HDP and PECVD processes), followed by a CMP process to planarize the oxide.

[0079] Next, as in Fig. 4A (side view in cross-section) and the corresponding Fig. Figure 4B (top view) shows the IMD area 230 structured and etched (e.g., using a plasma etching process) to simultaneously form (a) at least one interconnection via opening 310 for various interconnection structures, (b) a contact opening 312 for the lower electrode, and (c) the well opening 221 for forming the lower electrode 204 of the MIM capacitor module 200. The interconnection via opening 310 and the contact opening 312 for the lower electrode can each be a narrow via opening with a lateral diameter or width W. viabe designed. In contrast, the well opening 221 can have a significantly larger width (x-direction) and / or length (y-direction) than the narrow via openings 310 and 312. The shape and dimensions of the well opening 221 can be selected based on various parameters, e.g., for the effective fabrication of the MIM capacitor module 200 (e.g., effective deposition of the materials of the lower electrode (e.g., tungsten and TiN) in the well opening 221) and / or for the desired performance characteristics of the resulting MIM capacitor module 200. In some examples, the well opening 221 can have a square or rectangular shape in plan view, e.g., as in Fig. 4B shown. In other examples, the tub opening 221 may have a round or oval shape in the top view.

[0080] As already mentioned, the width W tub in the x-direction and / or the length L tubin the y-direction of the tub opening 221 be significantly larger than the width W via each via opening. In some embodiments, for example, the width W tub and / or the length L tub the bathtub opening 221 at least twice as large as the width W via each via opening. In special embodiments, the width W tub and / or the length L tub the bathtub opening 221 at least five times as large as the width W via each via opening. In some examples, the width W is via Each via opening is in the range of 0.1-0.5 µm, while the width W tnb and the length L tub The dimensions of the tub opening 221 are in the range of 1-100 µm.

[0081] After etching to create openings 310, 312, and 221, any remaining photoresist material can be removed by resist stripping. Next, as shown in Fig. Figure 5 shows the adhesive layer 226 (e.g., comprising titanium nitride (TiN)) being deposited over the integrated circuit structure 300 and in the openings 310, 312, and 221, e.g., with a thickness in the range of 5–30 nm (50–300 Å). A conformal metal layer 320, e.g., tungsten (W), is then deposited over the adhesive layer 226, e.g., by chemical vapor deposition (CVD), with a thickness in the range of 100–500 nm (1000–5000 Å). As shown, the conformal metal layer 320 (a) fills the via opening 310 to form a via 332, (b) fills the contact opening 312 of the lower electrode to form the contact 216 of the lower electrode, and (c) partially fills the well opening 221 to form the cup-shaped component 220 of the lower electrode within the well opening 221. The cup-shaped lower electrode component structure 220 defines an inner opening 324.The interconnection via 332, the contact 216 of the lower electrode and the cup-shaped lower electrode component 220 are further processed as described below, including a CMP process which is carried out in . Fig. 7A is shown and defines the final form of the respective elements 332, 216 and 220.

[0082] The deposited conformal metal layer 320 can exhibit high tensile stresses due to the inherent material properties of the conformal metal, e.g., tungsten. Therefore, a deposition thickness greater than 500 nm (5000 Å) (e.g., a thickness of 700 nm (7000 Å)) can cause the conformal metal layer 320 to crack or detach, or cause the underlying silicon wafer (not shown) to warp or break, e.g., during a subsequent CMP process.

[0083] Next, as in Fig. Figure 6 shows a filler metal layer 330 deposited over the integrated circuit structure 300, extending into the inner opening 324 of the cup-shaped structure of the lower electrode 220. The metal layer 330 can be thick enough to fill the inner opening 324 at least to the upper edge of the adjacent dielectric region 230. The filler metal layer 330 can be deposited by a reactive PVD or CVD process without creating bumps, which can provide a higher breakdown voltage for the resulting MIM capacitor module 200a compared to prior art designs that allow or promote bump formation on the lower electrode of the capacitor (and / or other capacitor components), e.g., as above with respect to the one in Fig. The example capacitor shown in 1F is discussed according to the state of the art.

[0084] In some examples, the filler metal layer 330 comprises titanium nitride (TIN) or another high-melting-point metal (different from the conformal metal of the conformal metal layer 320) that exhibits inherent compressive stresses (e.g., at a layer thickness of less than 1 µm). The inherent compressive stresses of the filler metal layer 330 can counteract the inherent tensile stresses of the underlying conformal metal layer 320 (e.g., the tungsten layer), thereby reducing the risk of delamination between the layers, silicon wafer fracture, or other mechanical defects. In another example, the filler metal layer 330 is formed from aluminum, which provides lower resistance to the resulting lower electrode 204, as described in the following example: Fig. 2A is described, but it also brings with it the possibility of hill formation.

[0085] Next, as in Fig. 7A (side view in cross-section) and the corresponding Fig. Figure 7B (top view) shows a planarization process (e.g., a CMP process) performed to remove the upper parts of the interconnect metal layer 330, the conformal metal layer 320, and the adhesive layer 226, thereby defining the final shape of the interconnect via 332, the contact of the lower electrode 216, the cup-shaped component of the lower electrode 220, and the lower electrode filling component 222. The planarization process can be designed to terminate in the dielectric region 230. As mentioned earlier, the cup-shaped lower electrode component 220 and the lower electrode filling component 222 together form the lower electrode 204 of the MIM capacitor module 200a.

[0086] The planarization process (e.g., CMP process) defines a polished, planarized insulator support surface 240 to support the planar insulator 206, which is shaped as described below. As in Fig. As shown in Figure 7A, the planarized insulator support surface 240 has a planarized upper surface 234 of the cup-shaped lower electrode component 220, a planarized upper surface 236 of the lower electrode filling component 222, and planarized upper surface areas 238a, 238b of the dielectric region 230 on opposite sides of the lower electrode 204. The planarized support surface 240 of the insulator provides a smooth, planarized surface without protrusions suitable for forming the planar insulator 206, as described below. The planarized upper surface 234 of the cup-shaped lower electrode 220 and the planarized upper surface 236 of the lower electrode filling component 222, for example, provide smooth, planarized surfaces of high-melting-point metals (e.g., tungsten and titanium nitride, as described above) that are free of bumps and are suitable for forming the planar insulator 206.

[0087] Next, as in Fig. Figure 8 shows an insulating layer 350 applied to the structure 300. The insulating layer 350 can comprise silicon nitride (Si3N4, κ~7) with a thickness T ins in the range of 40-60 nm (400-600 Å), for example by a PECVD deposition process. In other examples, the insulating layer can be silicon dioxide (SiO2) or a dielectric material with a high k-value, e.g. Al2O3 (κ~10), Ta2O5 (κ~25), HfO2 (κ~22) or ZrO2 (κ~35), which is deposited, for example, by a PECVD deposition process or an ALD (Atomic Layer Deposition) process.

[0088] Next, as in Fig. As shown in Figure 9, the insulating layer 350 is structured and etched such that a region 354 of the insulating layer remains above the lower electrode 204. The insulating layer region 354 extends laterally across the entire lateral width of the lower electrode 204 in the x-direction and additionally extends over a portion of the dielectric region 230 on each lateral side of the lower electrode 204. In some examples, the region of the insulating layer 354 extends laterally across the entire lateral width of the lower electrode 204, in both the x- and y-directions, and additionally extends over portions of the dielectric region 230 on all lateral sides of the lower electrode 204, so that, viewed from above, a perimeter of the region of the insulating layer 354 surrounds a perimeter of the lower electrode 204.

[0089] The insulating layer 350 can be etched using a relatively simple dielectric etching process, unlike prior art methods which require difficult etching of the upper metal electrode. As shown, the thickness T remains unchanged. ins the insulator layer 350 is the same over the entire lateral width (x-direction) of the area of ​​the insulator layer 354.

[0090] An upper metallic compound layer M x+1 is formed on the integrated circuit structure 300. First, as in Fig. Figure 10 shows an upper metal layer 360, e.g. aluminium, comprising aluminium, copper or another suitable metal, deposited over the dielectric region 230 and the remaining part of the insulating layer region 354.

[0091] Next, as in Fig. Figure 11 shows a photoresist layer applied and structured to define a photomask 364, which has a first photoresist element 364a (for forming an upper connecting element 370, as described below), a second photoresist element 364b (for forming the lower electrode connecting element 214, as described below), and a third photoresist element 364c (for forming the upper electrode 208 of the MIM capacitor module 200, as described below). As shown, the width W can be te_resist The third photomask element 364c must be larger than the width W te the lower electrode 204, but smaller than the width W ins_layer of the area of ​​the insulating layer 354, so that the subsequent metal etching to form the upper electrode 208 (see Fig. 12, which is discussed further below) the lateral edges (in x-direction) of the upper electrode 208 align themselves with the underlying planar insulator 206, which results from the area of ​​the insulator layer 354, and at the same time prevents any etching of the lower electrode 204.

[0092] Fig. Figure 12 shows the results of the metal etching by the in Fig. Figure 11 shows the photomask 364 and the area after the photomask 364 has been removed, e.g., by a resist stripping process. The etching can be selective to etch through parts of the upper metal layer 360 and the underlying insulator layer region 354 that are not covered by the photomask 364 (see Figure 11). Fig. 11), but terminate in the dielectric region 230, e.g., at a depth of 50–100 nm (500–1000 Ω) in the dielectric region 230. As shown, the etch forms (a) the upper connecting element 370 in contact with the connecting via 332, (b) the lower electrode connecting element 214 in contact with the lower electrode contact 216, and (c) the upper electrode 208 over a remaining portion of the insulator layer 354 that defines the planar insulator 206. As shown, the lateral edges of the upper electrode 208 are aligned with the underlying planar insulator 206 by the metal etching.

[0093] In the illustrated example, the planar insulator 206 extends laterally over the entire lateral width W. be the lower electrode 204 in the x-direction and additionally over a part of the dielectric region 230 on each lateral side of the lower electrode 204 (in the x-direction). Thus, the width W extendsins of the planar insulator 206 via the planarized upper surface 234 of the cup-shaped lower electrode component 220, the planarized upper surface 236 of the lower electrode filling component 222, and the planarized upper surface areas 238a and 238b of the dielectric region 230 on opposite sides of the lower electrode 204. Thus, the width W ins of the planarized insulator 206 larger than the width W be of the lower electrode 204. In some examples, the planar insulator 206 extends laterally over the entire lateral width of the lower electrode 204 in both the x and y directions and additionally extends over parts of the dielectric region 230 on all lateral sides of the lower electrode 204, so that, viewed from above, a perimeter of the planar insulator region 206 surrounds a perimeter of the lower electrode 204.

[0094] By extending across the entire lateral width of the lower electrode 204, the planar insulator protects the underlying lower electrode 204 from metal etching by the upper metal layer 360. As described above, the insulator layer 206 has a lateral width W of W. ins of the planar insulator 206 (in the x-direction or in both the x- and y-directions) a uniform thickness T ins on. In some examples, the thickness T varies. ins the insulating layer 206, for example, by less than 10%, less than 5% or less than 1% over the entire lateral width W ins of the planar insulator 206 (in the x-direction or both in the x-direction and in the y-direction).

[0095] Some examples show Fig. 12. The completion of the MIM capacitor module 200a. After forming the MIM capacitor module 200a, the process can be continued with the construction of further interconnect structures, e.g. by forming further metallic interconnect layers and / or dielectric layers. Fig. Figure 13 is a flowchart showing an exemplary procedure 1300 for forming a MIM capacitor module in an integrated circuit structure according to an example. At Figure 1302, a lower metal layer M is x formed, which has a base of the lower electrode. In one example, the lower metal layer M has x a lower compound metal layer (which, for example, contains aluminum). In another example, the lower metal layer M x a siliciated polysilicon layer. At 1304, a dielectric region (e.g., an oxide region) is formed above the lower metal layer M. xisolated and planarized, e.g. through a CMP process.

[0096] Next, as in Fig. As indicated by the dashed box in Figure 13, a Damascene process is performed at 1306-1312 to form a lower electrode of the MIM capacitor module. First, at 1306, the dielectric region is structured and etched to form a well opening and a contact opening for the lower electrode. Next, at 1308, a conformal metal (e.g., tungsten) is deposited to simultaneously form (a) a cup-shaped lower electrode component in the well opening and (b) a lower electrode contact in the lower electrode contact opening, with both the cup-shaped lower electrode component and the lower electrode contact being conductively coupled to the base of the lower electrode.

[0097] In process 1310, a filler metal (e.g., titanium nitride) is deposited to form a filler component for the lower electrode in an internal opening defined by the cup-shaped lower electrode component. In process 1312, a planarization process is performed to define the final shape of the cup-shaped lower electrode component and the lower electrode filler component, and to define a planarized insulator support surface. This surface has a planarized upper surface of the cup-shaped lower electrode component, a planarized upper surface of the lower electrode filler component, and planarized upper surface areas of the dielectric region on opposite sides of the lower electrode. The cup-shaped lower electrode component and the lower electrode filler component together form the lower electrode of the capacitor.

[0098] In 1314, a planar insulator is formed on the planarized insulator support surface. The planarized insulator extends over the entire lateral width of the lower electrode (in the x-direction or in both the x- and y-directions) and can have a uniform vertical thickness over the entire lateral width of the planarized insulator (in the x-direction or in both the x- and y-directions). In 1316, an upper metal layer M x+1 formed, comprising (a) an upper electrode above the insulator and (b) a connecting element for the lower electrode, which is conductively connected to the contact of the lower electrode. The upper metal layer M x+1 may have a compound metal layer, e.g. a first compound metal layer (metal-1 layer) or a higher compound metal layer (which e.g. contains aluminium).

[0099] Fig. Figure 14 is a flowchart illustrating, according to an example, a method 1400 for forming an exemplary integrated circuit structure, which includes an exemplary MIM capacitor module and an adjacent interconnect structure. Figure 1402 describes a lower metal layer M x formed, which has a base of the lower electrode and a lower connecting element. In one example, the lower metal layer M x a lower compound metal layer (which, for example, contains aluminum). In another example, the lower metal layer M x a siliciated polysilicon layer. In 1404, a dielectric region (e.g., an oxide region) is formed above the lower metal layer M. x isolated and planarized, e.g. through a CMP process.

[0100] Next, as in Fig.As indicated by the dashed box in Figure 14, a damascene process is performed at 1406-1412 to form a lower electrode and lower electrode contact of the MIM capacitor module. First, at 1406, the dielectric area is structured and etched to form (a) a cup opening and a contact opening above the lower electrode and (b) a via opening above the lower connecting element.

[0101] In process 1408, a conformal metal (e.g., tungsten) is deposited to simultaneously form (a) a cup-shaped lower electrode component in the cup opening, (b) a lower electrode contact in the contact opening of the lower electrode, and (c) a via in the via opening. In process 1410, a filler metal (e.g., titanium nitride) is deposited to form a filler component for the lower electrode in an internal opening defined by the cup-shaped lower electrode component.In 1412, a planarization process is performed to define the final shape of the cup-shaped lower electrode component and the lower electrode filling component, and to define a planarized insulator support surface that has a planarized upper surface of the cup-shaped lower electrode component, a planarized upper surface of the lower electrode filling component, and planarized upper surface areas of the dielectric region on opposite sides of the lower electrode. The cup-shaped lower electrode component and the lower electrode filling component together form the lower electrode of the capacitor.

[0102] In 1414, a planar insulator is formed on the planarized insulator support surface. The planarized insulator extends over the entire lateral width of the lower electrode (in the x-direction or in both the x- and y-directions) and can have a uniform vertical thickness over the entire lateral width of the planarized insulator (in the x-direction or in both the x- and y-directions). In 1416, an upper metal layer M x+1 formed, comprising (a) an upper electrode above the insulator, (b) a connecting element of the lower electrode that is conductively connected to the contact of the lower electrode, and (c) an upper connecting element that is conductively connected to the via. The upper metal layer M x+1 may have a compound metal layer, e.g. a first compound metal layer (metal-1 layer) or a higher compound metal layer (which e.g. contains aluminium).

Claims

[1] Metal-insulator-metal capacitor module comprising: a lower electrode base (202; 203) embedded in a lower metal layer (M x ) is trained; a lower electrode (204) which is formed in a dielectric region (230; 232) and which is conductively coupled to the lower electrode base (202; 203) and has: a cup-shaped lower electrode component (220) formed in a lower electrode opening (221) in the dielectric region (230; 232); a lower electrode filling component (222) formed in an inner opening defined by the cup-shaped lower electrode component (220); a planar insulator (206) formed above the lower electrode (204); a lower electrode contact (216) formed in a lower electrode contact opening (312) in the dielectric region (230; 232), wherein the electrode contact opening (312) is laterally offset from the electrode opening (221); an upper electrode (208) embedded in an upper metal layer (M x+1 ) is formed above the planar insulator (206); and a connecting element (214) for the lower electrode, which is located in the upper metal layer (M x+1 ) is formed, wherein the connecting element (214) for the lower electrode (204) is conductively connected to the lower electrode base (202; 203) via the lower electrode contact (216); wherein the lower electrode contact (216) and the cup-shaped lower electrode component (220) are formed by a conformal metal layer (320); wherein the lower electrode filling component (222) is formed by a metal filling layer (330); wherein the lower electrode opening (221) is partially filled by the conformal metal layer (320) and partially by the metal filler layer (330); and wherein the lower electrode contact opening (312) is filled with the conformal metal layer (320) and is free of the metal filler layer (330). [2] Metal insulator-metal capacitor module according to claim 1, wherein the planar insulator (206) has a uniform vertical thickness over a full lateral width of the planar insulator (206). [3] Metal insulator-metal capacitor module according to claim 1, wherein the planar insulator (206) has a uniform vertical thickness over a full lateral width of the planar insulator in a first lateral direction and in a second lateral direction perpendicular to the first lateral direction. [4] Metal-insulator-metal capacitor module according to any one of claims 1 to 3, wherein: the planar insulator (206) is formed on a planarized insulator support surface (240) which has (a) a planarized upper surface of the cup-shaped lower electrode component (234), (b) a planarized upper surface of the lower electrode filling component (236) and (c) planarized upper surface areas of the dielectric region (238) on opposite sides of the lower electrode (204); and the planar insulator (206) extends laterally over a full lateral width of the lower electrode (204) and beyond, so that the planar insulator (206) extends over the planarized upper surface areas of the dielectric region (238) on opposite sides of the lower electrode (204). [5] Metal-insulator-metal capacitor module according to any one of claims 1 to 3, wherein: the planar insulator (206) extends laterally over a full lateral width of the lower electrode (204) and beyond, such that the planar insulator (206) extends laterally alongside the lower electrode (204) over parts of the dielectric region (230; 232); and the planar insulator (206) has a uniform vertical thickness (T ins ) over a full lateral width of the planar insulator (206). [6] Metal-insulator-metal capacitor module according to any one of claims 1 to 3, wherein: the planar insulator (206) extends laterally over a full lateral width of the lower electrode (204) and beyond in a first lateral direction and in a second lateral direction perpendicular to the first lateral direction, such that the planar insulator (206) extends laterally alongside the lower electrode (204) over parts of the dielectric region (230; 232) in both the first and second lateral directions; and the planar insulator (206) has a uniform vertical thickness (T ins ) over a full lateral width of the planar insulator (206) in both the first and second lateral directions. [7] Metal-insulator-metal capacitor module according to any one of claims 1 to 6, wherein the cup-shaped component (220) of the lower electrode (204) is formed on the lower electrode base (202; 203). [8] Metal-insulator-metal capacitor module according to any one of claims 1 to 7, wherein the planar insulator (206) is formed on a planarized insulator support surface (240) which has a planarized upper surface of the cup-shaped lower electrode component (234) and a planarized upper surface of the lower electrode filling component (236). [9] Metal-insulator-metal capacitor module according to claim 1, wherein the conformal metal layer (320) comprises tungsten and the filler metal (330) comprises titanium nitride. [10] Metal-insulator-metal capacitor module according to any one of claims 1 to 9, wherein the lower metal layer (M x ) has a lower compound layer; and the upper metal layer (M x+1 ) has an upper bonding layer. [11] Metal-insulator-metal capacitor module according to any one of claims 1 to 12, wherein: the lower metal layer (M x) has a silicidal polysilicon layer, wherein the lower metal layer (M x ) formed lower electrode base (203) has a metal silicide area (252) formed on a polysilicon area (250); and the upper metal layer (M x+1 ) has a first metal compound layer. [12] Metal-insulator-metal capacitor module according to any one of claims 1 to 11, wherein: define an upper surface of the cup-shaped lower electrode component (234) and a lower electrode filling component (222) and a planar upper surface of the lower electrode (240); and the planar insulator (206) is formed on the planar upper surface of the lower electrode (240). [13] Integrated circuit structure which features: a connection structure that exhibits: a lower connecting element (306) which is embedded in a lower metal layer (M x ) is trained; an upper connecting element (370) embedded in an upper metal layer (M x+1 ) is trained; and a through-hole connection (332) which is conductively connected between the lower connecting element (306) and the upper connecting element (370); and one of the metal-insulator-metal capacitor modules according to claims 1 to 12, wherein the cup-shaped lower electrode component (220) of the metal-insulator-metal capacitor module and the interconnection via (332) are formed from a common conformal metal. [14] Integrated circuit structure according to claim 13, wherein: the metal-insulator-metal capacitor module has a contact of the lower electrode which provides a conductive connection between the lower electrode base (202; 203) and a connecting element of the lower electrode (214) formed in the upper metal layer; and wherein the interconnection via, the contact of the lower electrode and the lower electrode (204) in a dielectric region (230; 232) between the lower metal layer (M x ) and the upper metal layer (M x+1 are trained.

Images