INTEGRATED CIRCUIT STRUCTURE INCLUDING A METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE AND A THIN-FILM RESISTOR MODULE (TFR)

Abstract

Integrated circuit structure that features: (a) a metal-insulator-metal capacitor module (302) comprising: a lower electrode base (310) embedded in a lower metal layer (M x ) is trained; a lower electrode (312) located in a dielectric region (324) between the lower metal layer (M x ) and an upper metal layer (M x+1 ) is formed, wherein the lower electrode (312) has: a cup-shaped lower electrode component (330); and a lower electrode filling component (332) formed in an inner opening (331) defined by the cup-shaped lower electrode component (330); an insulator (314) formed above the lower electrode (312); and an upper electrode (316) located in the upper metal layer (M x+1 ) is formed above the insulator (314); and (b) a thin-film resistance modulus (304) comprising: a pair of metal heads (352) located in the dielectric region (324) between the lower metal layer (M x ) and the upper metal layer (M x+1 ) are formed, each having a metal head (352): a cup-shaped head component (364) ; and a head-filling component (368) formed in an inner opening (365) defined by the cup-shaped head component (368); and a resistive element (354) connected via the pair of metal heads (352), wherein the cup-shaped head component (364) of each metal head (352) and the cup-shaped lower electrode component (330) are formed from a conformal metal; and the head-fill component (368) of each metal head (352) and the lower electrode-fill component (332) are formed from a filler metal other than the conformal metal, wherein the conformal metal comprises tungsten, and the filler metal comprises titanium nitride.

Description

[0001] The present disclosure relates to analog components formed in integrated circuit devices, and in particular to an integrated circuit structure comprising a metal-insulator-metal (MIM) capacitor module and a thin-film resistor module (TFR).

[0002] Capacitors and resistors that are monolithically integrated into integrated circuit devices are called integrated capacitors and resistors, respectively. Integrated capacitors and resistors are common components in many integrated circuit devices. For example, various analog, mixed-signal, and RF CMOS (radio frequency complementary metal oxide semiconductor) integrated circuit devices use integrated capacitors and resistors, either separately or in combination. Integrated capacitors and resistors can offer several advantages over their discrete counterparts (i.e., capacitors and resistors located off-chip). For example, integrated capacitors and resistors can often be manufactured more cost-effectively compared to typical discrete (off-chip) capacitors and resistors.Furthermore, system-on-chip devices that incorporate integrated capacitors and resistors can have a smaller number of pins (providing improved usability and a better form factor) and lower parasitic capacitance.

[0003] MIM capacitor modules are typically built between two interconnected metal layers (e.g., aluminum layers), which are referred to as metal layers M x and M x+1 These can be described as MIM capacitor modules. For example, a MIM capacitor module can be manufactured using an existing metal layer M. x are designed as a bottom electrode (bottom plate), wherein an insulator and a top electrode are placed over the bottom electrode and a metal layer M is applied over it. x+1 It is connected to the upper and lower electrodes via corresponding vias. The area between the two metal layers M xand M x+1 The formed upper electrode can be made of a different metal than the metal layers M. x and M x+1 be formed. The metal layers M x and M x+1 For example, the electrodes can be made of aluminum, while the upper electrode can be made of titanium / titanium nitride (Ti / TiN), tantalum / tantalum nitride (Ta / TaN) or tungsten (W).

[0004] The upper electrode typically exhibits a higher resistance than the lower electrode because the upper electrode is limited, for example, by its thickness and the material chosen, which restricts the performance of conventional MIM capacitor modules. MIM capacitor modules generally have very tight process margins, especially for the metal etching used to form the upper electrode.

[0005] Furthermore, in MIM capacitor modules that are in aluminum interconnect (i.e., where the metal layers M x and Mx+1 Aluminum interconnect layers are present, and the lower electrode, also made of aluminum, may be prone to the formation of bumps on its upper surface, for example, as a result of high-temperature processing of aluminum, a metal with a low melting point. These bumps on the lower electrode can negatively or unpredictably affect the breakdown voltage of the MIM capacitor module.

[0006] The Fig. Figures 1A-1F show side cross-sectional views of an exemplary prior art method for forming a MIM capacitor module 10. As shown in Fig. As shown in 1A, a metallic compound layer M is used. x formed over a dielectric region, e.g. an intermetallic dielectric (IMD) layer known as IMD x is referred to as the metal layer M x It can be made of aluminium or another suitable metal.

[0007] Next, as in Fig. Figure 1B shows an insulating layer 100 deposited, followed by an upper electrode layer 102, from which an upper electrode (top plate) of the MIM capacitor module 10 is formed, as shown in Fig. 1C is shown, which is described further below. The insulating layer 100 can be silicon nitride (Si3N4, also simply referred to as SiN) with a thickness T. ins of approximately 50 nm (500 Å), which can be deposited by a plasma-enhanced chemical vapor deposition (PECVD) process. The upper electrode layer 102 can be titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or another suitable metal with a thickness T te exhibiting a thickness of approximately 200 nm (2000 Å). te the upper electrode layer 102, which defines the thickness of the upper capacitor electrode 108 (see Fig. 1C), is typically determined by the thickness of a subsequently formed IMD layer. x+1 (see Fig. 1F, which is described below) is limited. In addition, an etch margin from the etching of the upper electrode (see Fig. 1C, see below) and a process margin of subsequent chemical-mechanical planarization (CMP), for example to limit the thickness T te to contribute to the upper electrode layer 102. In a typical IMD x+1 -Layer thickness of 800 nm (8000 Ω) can determine the thickness T te The thickness of the upper electrode 102 may be limited to approximately 300 nm (3000 Å) or less. This limited thickness T te The upper electrode layer 102 (and thus the upper capacitor electrode 108) can lead to a high series resistance and a low quality factor (Q-factor) in certain applications, e.g., high-frequency (HF) applications.

[0008] After the insulating layer 100 and the upper electrode layer 102 have been applied, the information printed in the area of ​​the wafer scoring of the underlying silicon substrate can be very difficult to read (due to the upper electrode layer 102, the insulating layer 100 and the underlying metal layer M). x ), which can lead to manufacturing problems. For example, the wafer lot number and / or the wafer number printed in the scoring area of ​​the wafer may be difficult to read, which can cause various problems, such as the inability to conduct controlled experiments with specific wafers distributed across different process conditions, or to record wafer activities (e.g., rejects or incidents) associated with the wafer number.

[0009] Next, as in Fig. Figure 1C shows that a photoresist layer is applied and structured to form a first photomask 106 over the upper electrode layer 102, and etching is performed to delineate the upper electrode 108 of the MIM capacitor from the upper electrode layer 102, wherein the portion of the insulating layer 100 below the upper electrode 108 of the MIM capacitor defines the insulator of the MIM capacitor, which is designated 100a. The etching of the upper electrode typically has a very small process margin. In particular, the etching is designed to occur at approximately half the height of the thickness T. ins the insulating layer ends at 100.

[0010] The exact depth of the etching of the upper electrode, which is the thickness T ins_etchedThe remaining insulating layer 100 outside the base area of ​​the upper electrode 108, which is defined as the etched area 100b of the insulating layer 20, typically depends on certain process parameters, such as the thickness and uniformity of the silicon nitride deposition, as well as the uniformity and selectivity of the etching. If the etching is not deep enough (so that T ins_etched If the etched area of ​​the insulating layer 100b is too thick, the upper electrode layer 102 may not be completely removed in some areas on the wafer (e.g., due to uneven etching on the wafer), leaving metal residues or stringers on the wafer. These metal residues or stringers can lead to incomplete etching in a subsequent metal etching step, cause metal short circuits, and result in a loss of yield or reliability of the device.

[0011] If, on the other hand, the etching of the upper electrode is too deep (so that T ins_etched (if the etched area of ​​the insulating layer 100b is too thin), the resulting MIM capacitor module 10 may exhibit an inappropriately low breakdown voltage, particularly due to the corner “C” formed in the insulating layer 100 by the etching of the upper electrode described above, as further described below in relation to Fig. 1F explains. Therefore, the effective margin for thickness T can be ins_etched The etched area of ​​the insulating layer 100b can be very small, thus defining small process margins for etching the upper electrode. For a deposited silicon nitride insulating layer with a thickness T ins of 50 nm (500 Å) the effective target thickness T ins_etched The area 100b of the etched insulating layer has a very small tolerance, for example between 23 - 27 nm (230-270 Ω).

[0012] Next, as in Fig. 1D shown, the remaining parts of the first photoresist mask 106 were removed and a new photoresist layer was applied and structured to form a second photoresist mask 112 over the upper electrode 108, extending beyond the upper electrode 108 in a first lateral direction.

[0013] Next, as in Fig. Figure 1E shows a metal etching performed to define the lower electrode 116 of the MIM capacitor.

[0014] Finally, as in Fig. Figure 1F shows the construction of the MIM capacitor module 10 by removing the second photomask 112, forming an IMD layer (IMD x+1 ), forming vias 120, each contacting the upper electrode 108 and the lower electrode 116, and forming an upper electrode contact 122 and a lower electrode contact 124 in a metal layer M x+1 above IMD X+1 -Shift completed.

[0015] The MIM capacitor module 10, according to the state of the art, can have various defects. For example, as mentioned above, the thickness T can be te the upper electrode 108 due to a vertical distance limitation between the metal layers M x and M x+1 be limited, represented by the thickness T IMDx+1 of the IMD area x+1 The limited thickness T te The upper electrode 108 can lead to a high series resistance, which is unsuitable for certain applications (e.g. RF applications).

[0016] Furthermore, the MIM capacitor module 10 may exhibit a low and / or unpredictable breakdown voltage. For example, the breakdown voltage of the capacitor may be very sensitive to the thickness T. ins_etchedthe etched insulating layer in region 100b, particularly at corner C below the lateral edge of the upper electrode 108, as described above. Furthermore, the breakdown voltage of the capacitor can also be sensitive to the bumps “H” formed on the lower electrode 116 of the capacitor. The formation of bumps can be very difficult to control in the manufacturing process described above. For example, bumps H can form on the lower electrode 116 as a result of various heated process steps during and after the manufacture of the capacitor module, including heat treatment steps and / or heated aluminum deposition steps (e.g., at 400°C). These bumps H can lead to an uncontrolled low breakdown voltage of the capacitor module 10.

[0017] Furthermore, as already mentioned, the deposition of the different material layers (lower metal layer, insulating layer and upper electrode layer) over the wafer ridge area can hinder the readability of the information printed in the wafer ridge area (e.g. wafer number and batch number), which can complicate the manufacturing process.

[0018] Turning now to integrated transistors, a common type is the thin-film resistor (TFR), which has a pair of metal heads connected by a resistive element or TFR film.

[0019] Fig. Figure 2 shows a cross-section through two exemplary TFR modules, 200A and 200B, fabricated using conventional techniques. The fabrication of a conventional TFR module, 200A or 200B, typically requires three additional mask layers, related to the fabrication process of the respective IC device. Specifically, a first added mask layer can be used to create the metal heads 202A and 202B, a second added mask layer can be used to create a resistor element 204, and a third added mask layer can be used to create the TFR vias 206A and 206B.As shown, the resistive element 204 of the TFR module 200A is formed over the top of the metal heads 202A and 202B, while the resistive element 204 of the TFR module 200B is formed over the bottom of the metal heads 202A and 202B. However, each formation typically uses three additional mask layers. TFR modules and MIM capacitor modules are often expensive to manufacture. As mentioned earlier, the process for forming a MIM capacitor module or a TFR module often involves several additional mask layers that supplement the IC manufacturing process. Furthermore, MIM capacitor modules and TFR modules are typically manufactured independently, which further increases the number of additional mask layers required to form both types of devices in an integrated circuit device.

[0020] A MIM capacitor and its manufacturing process are disclosed in US Patent 2005 / 0 067 701 A1. A manufacturing process for a resistor and a capacitor is disclosed in US Patent 6 365 480 B1. A semiconductor device with a MIM-type capacitor and a method for its manufacture are disclosed in US Patent 2002 / 0 179 955 A1. Thin-film resistor integration in copper damascus metallization is disclosed in US Patent 2016 / 0 218 062 A1. Zero-mask high-density metal / insulator / metal capacitor is disclosed in US Patent 2002 / 0 163 029 A1.

[0021] There is a need to construct integrated capacitors and resistors, in particular to design MIM capacitor modules and TFR modules together, efficiently and at a lower cost compared to conventional methods. This and other tasks are solved by the independent claims. Further developments are characterized by the dependent claims.

[0022] The present disclosure provides an integrated circuit (IC) structure comprising both a metal in-mold capacitor module (MIM) and a translucent refractive index (TFR) module formed simultaneously in a dielectric region between two metal layers in the IC structure, e.g., an intermetallic dielectric (IMD) region or a premetallic dielectric (PMD) region. In some examples, the IC structure includes at least one interconnection structure formed in the dielectric region between the two metal layers in the IC structure, simultaneously with the MIM capacitor module and the TFR module.

[0023] As used herein, a structure formed “between” two metal layers (e.g., a MIM capacitor module, a TFR module, and / or an interconnect structure formed between two layers, as disclosed herein) refers to a structure which (a) has at least one component formed in a dielectric region between two metal layers, and (b) has at least one component formed in one or both of the two metal layers.

[0024] One aspect provides an integrated circuit structure comprising a MIM capacitor module and a TFR module. The MIM capacitor module has a lower electrode base formed in a lower metal layer, a lower electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed above the lower electrode, and an upper electrode formed in the upper metal layer above the insulator. The lower electrode has a cup-shaped lower electrode component and a lower electrode filling component formed in an internal opening defined by the cup-shaped lower electrode component.The TFR module features a pair of metal heads formed in the dielectric region between the lower and upper metal layers, and a resistive element connected across the pair of metal heads. Each metal head of the pair has a cup-shaped head component and a head-filling component formed within an internal opening defined by the cup-shaped head component.

[0025] In one example, the TFR module has a pair of head bases formed in the lower metal layer, with each metal head being conductively connected to a corresponding head base.

[0026] In one example, the cup-shaped head component of each metal head and the cup-shaped lower electrode component are formed from a conformal metal, while the head-fill component of each metal head and the lower electrode fill component are formed from a filler metal other than the conformal metal. In one example, the conformal metal is tungsten, and the filler metal is titanium nitride.

[0027] In one example, the insulator has a uniform vertical thickness across its entire lateral width.

[0028] In one example, the insulator is formed on a flat support surface, which has a flat top surface of the cup-shaped lower electrode and a flat top surface of the filling of the lower electrode.

[0029] In one example, the insulator is formed on a planarized support surface having (a) a planarized upper surface of the cup-shaped lower electrode component, (b) a planarized upper surface of the lower electrode filling component, and (c) planarized upper surface regions of the dielectric region on opposite sides of the lower electrode, and the insulator extends laterally over a full width of the lower electrode and beyond, such that the insulator extends over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode.

[0030] In one example, the thin-film resistive module has a resistive element-insulator cap element formed on the resistive element, and the resistive element-insulator cap element, like the insulator, is formed from a common insulator material.

[0031] In one example, the lower metal layer has a lower compound layer, and the upper metal layer has an upper compound layer. In another example, the lower metal layer has a silicidal polysilicon layer, wherein the lower electrode formed in the lower metal layer has a metal silicidal region formed on a polysilicon region, and the upper metal layer has a first metallic compound layer.

[0032] In one example, the metal-insulator-metal capacitor module has a connecting element for the lower electrode formed in the upper metal layer and a lower electrode contact formed in the dielectric region between the lower and upper metal layers. The lower electrode contact provides a conductive connection between the terminal element of the lower electrode formed in the upper metal layer and the base of the lower electrode formed in the lower metal layer.

[0033] In some examples, the integrated circuit structure features an interconnection structure comprising a lower interconnect formed in the lower metal layer and an upper interconnect formed in the upper metal layer, which is connected to the lower interconnect via at least one via. In one example, the at least one via and the cup-shaped lower electrode element are formed from a common conformal metal.

[0034] Another aspect provides a method for forming an integrated circuit structure. The method includes forming a lower metal layer with a lower electrode base, depositing a dielectric region over the lower metal layer, structuring and etching the dielectric region to form a lower electrode well opening and a pair of head well openings, and forming a lower electrode in the lower electrode well opening, wherein the lower electrode has a cup-shaped lower electrode component and a lower electrode filling component in an internal opening defined by the cup-shaped lower electrode component. The method also includes forming a metal head in each of the two head well openings, wherein each metal head has a cup-shaped head component and a head filling component in an internal opening defined by the cup-shaped head component.The process also includes forming an insulator over the lower electrode, forming a resistive element connected via the pair of metal heads, and forming an upper metal layer with an upper electrode over the insulator.

[0035] In one example, the procedure involves performing a planarization process to define a planarized support surface, which has a planarized top surface of the cup-shaped lower electrode component and a planarized top surface of the lower electrode filling component, and forming the insulator over the planarized support surface.

[0036] In one example, the method involves forming the insulator with a uniform vertical thickness over the entire lateral width of the insulator.

[0037] In one example, the method involves performing a planarization process to define a planarized support surface that includes (a) a planarized upper surface of the cup-shaped lower electrode component, (b) a planarized upper surface of the lower electrode filling component, and (c) planarized upper surface regions of the dielectric region on opposite sides of the lower electrode. The insulator extends laterally across the entire width of the lower electrode and beyond, such that the insulator extends over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode.

[0038] Another aspect provides a method for forming an integrated circuit structure. The method includes forming a bottom metal layer with a bottom electrode base and a pair of top bases, forming a dielectric region over the bottom metal layer, forming openings in the dielectric region, including (a) a bottom electrode opening and (b) a pair of top openings, depositing a conformal metal extending into the bottom electrode opening and each top opening, and depositing a filler metal over the conformal metal layer extending into the electrode opening and each top opening.The method also includes the performance of a planarization process to remove portions of both the conformal metal and the filler metal, wherein (a) the remaining portions of the conformal metal and the filler metal in the lower electrode opening define a lower electrode having (i) a cup-shaped lower electrode component and (ii) a lower electrode filler component in an inner opening defined by the cup-shaped lower electrode component, and (b) remaining portions of the conformal metal and the filler metal in each of the two head openings define a pair of metal heads, wherein each metal head has (i) a cup-shaped head component and (ii) a head filler component in an inner opening defined by the cup-shaped head component.The process also features the formation of an insulator over the lower electrode, the formation of a resistive element extending over the pair of metal heads, and the formation of an upper metal layer with an upper electrode over the insulator.

[0039] In one example, the method involves forming the insulator with a uniform vertical thickness over the entire lateral width of the insulator. In one example, the planarization process defines a planarized support surface, which has a planarized top surface of the cup-shaped lower electrode component and a planarized top surface of the lower electrode filling component, and the insulator is formed on the planarized support surface.

[0040] In one example, the planarization process defines a planarized support surface that includes (a) a planarized upper surface of the cup-shaped lower electrode component, (b) a planarized upper surface of the lower electrode filling component, and (c) planarized upper surface regions of the dielectric region on opposite sides of the lower electrode. The insulator extends laterally across the entire width of the lower electrode and beyond, thus extending over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode.

[0041] In one example, the process involves forming an insulating layer over the lower electrode and over the pair of metal heads, and etching the insulating layer to form (a) the insulator over the lower electrode and (b) an insulating cap element over the resistive element.

[0042] In one example, the formation of the upper metal layer involves the formation of (a) the upper electrode over the insulator and (b) a metal cap element over the insulator cap element.

[0043] In one example, the process involves depositing a resistive film over the lower electrode and the pair of metal heads, depositing an insulating layer over the resistive film, and, after depositing the insulating layer over the resistive film, structuring and etching the resistive film and the insulating layer. Remaining portions of the resistive film define (a) an area of ​​the resistive film over the lower electrode and (b) the resistive element spanning the pair of metal heads, and remaining portions of the insulating layer define (a) the insulator over the lower electrode and (b) an insulating cap element over the resistive element.

[0044] In one example, the lower metal layer has a lower compound layer, and the upper metal layer has an upper compound layer.

[0045] In one example, the lower metal layer has a siliciated polysilicon layer, wherein (a) the lower electrode base and (b) each head base each have a metal silicide region formed on a corresponding polysilicon region, and the upper metal layer has a first metallic compound layer.

[0046] In one example, the method includes forming a via opening in the dielectric region and depositing the conformal metal in the via opening, wherein a portion of the conformal metal in the via opening defines a connecting via after the planarization process, and wherein the connecting via conductively connects a lower connecting element formed in the lower metal layer to an upper connecting element formed in the upper metal layer.

[0047] Exemplary aspects of the present revelation are described below in connection with the figures in which: Fig. 1A-1F Cross-sectional side views are showing an example of a prior art method for forming an example MIM capacitor module; Fig. 2 a cross-sectional view of two example thin-film resistors (TFRs) according to the state of the art; Fig. 3A is a cross-sectional side view of an exemplary integrated structure which, according to an example, includes an example MIM capacitor module, a TFR module and an interconnect structure formed between two metallic interconnect layers in an integrated circuit structure; Fig. 3B is a side cross-sectional view of an exemplary integrated structure comprising an exemplary MIM capacitor module, a TFR module and an interconnection structure formed between a silicidal polysilicon layer and a first metallic interconnection layer in an integrated circuit structure according to an example; Fig. Figures 4-13 are side cross-sectional views that illustrate an example method for constructing an integrated circuit structure, including the components shown in Figure 4. Fig. Figure 3A shows the example MIM capacitor module, TFR module and interconnect structure together with an example interconnect structure; Fig. 14 is a flowchart showing an example procedure for forming an example integrated circuit structure, which includes an example MIM capacitor module and an example TFR module, according to an example; and Fig. 15 is a flowchart showing a further example procedure for forming an exemplary integrated circuit structure, which includes an example MIM capacitor module and an example TFR module, according to another example.

[0048] It is understood that the reference signs for each illustrated element appearing in several different figures have the same meaning in all figures, and that the mention or discussion of an illustrated element in connection with a particular figure also applies to any other figure in which the same illustrated element is shown.

[0049] The present disclosure provides an integrated circuit (IC) comprising both a MIM capacitor module and a TFR module formed in a dielectric region between two metal layers in the IC structure, e.g. an intermetallic dielectric (IMD) region or a premetallic dielectric (PMD) region.

[0050] The MIM capacitor module has (a) a lower electrode base embedded in a lower metal layer M x(a) a lower electrode which is conductively connected to the lower electrode base, (c) an insulator which is formed over the lower electrode, and (d) an upper electrode which is embedded in an upper metal layer M x+1 is formed above the insulator. The MIM capacitor module can also (e) be formed in the upper metal layer M x+1 (f) a formed connecting element for the lower electrode and (f) a contact for the lower electrode which conductively connects the connecting element for the lower electrode to the base of the lower electrode.

[0051] The TFR module has (a) a pair of head bases embedded in the lower metal layer M xThe TFR module comprises (b) a pair of metal heads, each conductively connected to one of the head bases, and (c) a resistive element extending over the pair of metal heads and conductively connected to them. The TFR module may also include a resistive element insulator cap element above the resistive element and a metal cap element above the resistive element insulator cap element, wherein the resistive element insulator cap element is formed from a common resistive film like the insulator of the MIM capacitor module, and the metal cap element is formed in the same upper metal layer M. x+1 how the upper electrode and the lower electrode contact of the MIM capacitor module are designed.

[0052] Thus, the lower electrode of the MIM capacitor module and each metal head of the TFR module are located between the lower metal layer M x and the upper metal layer M x+1formed. Furthermore, the lower electrode and each metal head can be formed as a multi-component structure using the Damascene process. The lower electrode of the MIM capacitor module can have a cup-shaped lower electrode component and a lower electrode fill component formed in an internal opening defined by the cup-shaped lower electrode component. Similarly, each metal head of the TFR module can have a cup-shaped head component and a head fill component formed in an internal opening defined by the cup-shaped head component. The cup-shaped lower electrode and the cup-shaped head component of each metal head of the TFR module can be formed from a common conformal metal, e.g., tungsten. The lower electrode fill component and the head fill component of each metal head of the TFR module can be formed from a filler metal, e.g.,Titanium nitride, be formed.

[0053] The insulator of the MIM capacitor module can be formed on a planarized substrate (e.g., including a planarized top surface of the lower electrode). The insulator can have a uniform thickness across its entire lateral width, which can provide an improved breakdown voltage compared to certain conventional capacitor modules. By forming the lower electrode from refractory metals, such as tungsten and titanium nitride, the upper surface of the lower electrode adjacent to the insulator can be free of the bumps common in certain conventional capacitors (e.g., capacitor modules with an aluminum lower electrode), which can provide a higher and more uniform breakdown voltage compared to such conventional capacitor modules. Furthermore, the upper and lower electrodes can each have a considerable thickness, e.g.,a thickness of at least 400 nm (4000 Ω), which can provide better performance in certain applications (e.g. RF applications) compared to certain conventional capacitor modules with a thinner top electrode and / or bottom electrode.

[0054] As already mentioned, the MIM capacitor module and the TFR module are formed between two metal layers, in particular the lower metal layer M. x (in which the lower electrode base of the MIM capacitor and the pair of head bases of the TFR module are formed) and an upper metal layer M x+1 (in which the connecting element of the upper electrode and the lower electrode of the MIM capacitor module and the metal cap element over the resistive element of the TFR module are formed). As used herein, a “metal layer”, e.g. in connection with the lower metal layer M x and the upper metal layer M x+1, any metallic or metallized layer or layers, including: (a) a metallic compound layer, e.g. of aluminium, copper or another metal, formed by a damascene process or deposited by a subtractive structuring process (e.g. deposition, structuring and etching of a metal layer), or (b) a siliciated polysilicon layer comprising a number of siliciated polysilicon structures (i.e. polysilicon structures having a metal silicide layer formed on them), e.g. a siliciated polysilicon gate of a metal-oxide semiconductor field-effect transistor (MOSFET).

[0055] As in Fig. As shown in Figure 3A, for example, a MIM capacitor module and a TFR module can be placed between two adjacent metallic interconnect layers M x and M x+1can be built at any depth within an integrated circuit structure. Another example: As in Fig. As shown in Figure 3B, a MIM capacitor module and a TFR module can be built between a siliciated polysilicon layer and a first metal compound layer (generally referred to as the metal-1 layer), with the siliciated polysilicon layer forming the lower metal layer M x with x=0 (i.e., M0) and the first metal compound layer (metal-1 layer) is the upper metal layer M x+1 (i.e., M1) is defined.

[0056] Fig. Figure 3A is a side cross-sectional view of an exemplary integrated circuit structure 300a, which, according to some examples, includes an exemplary MIM capacitor module 302a, an exemplary TFR module 304a and (optionally) an exemplary interconnect structure 306a, all located between two metallic interconnect layers M x and M x+1are formed. In some examples, the integrated circuit structure 300a includes the MIM capacitor module 302a, the TFR module 304a, and the interconnection structure 306a. In other examples, the integrated circuit structure 300a includes the MIM capacitor module 302a and the TFR module 304a, but not the interconnection structure 306a. Therefore, the optional interconnection structure 306a is in Fig. 3A is shown with a dashed line.

[0057] The exemplary MIM capacitor module 300a has (a) a lower electrode base 310 embedded in a lower metal compound layer M x (b) a lower electrode 312, which is conductively coupled to the lower electrode base 310, (c) an insulator 314, which is formed over the lower electrode 312, and (d) an upper electrode 316, which is formed in an upper metal compound layer M x+1above the insulator 314. A region with a resistive film 322 can be arranged between the insulator 314 and the underlying lower electrode 312. The MIM capacitor module 302a also has a [missing information] in the upper metallic interconnect layer M x+1 formed connecting element 318 for the lower electrode and a contact 320 for the lower electrode, which conductively connects the connecting element 318 for the lower electrode to the lower electrode base 310.

[0058] The lower electrode 312 is formed in a dielectric region 324, which is in a via layer V x between the metallic compound layer M x and the upper metallic compound layer M x+1The lower electrode 312 can be formed using a Damascene process, as described below. In the illustrated example, the lower electrode 312 (a) has a cup-shaped lower electrode component 330 formed in a cup opening 331 formed in the dielectric region 324, and (b) a lower electrode filling component 332 formed in an inner opening 333 defined by the cup-shaped lower electrode component 330.

[0059] In some examples, the lower electrode contact 320 is designed as a through-hole and can also be referred to as the through-hole of the lower electrode.

[0060] In some examples, the insulator 314 can be formed above a planarized support surface 340. For example, the insulator 314 can be, as in Fig. Figure 3A shows the resistive layer 322 forming on the planarized support surface 340. The planarized support surface 340, which can be formed by chemical-mechanical planarization (CMP) or another planarization process, has (a) a planarized upper surface 341 of the cup-shaped lower electrode component 330, (b) a planarized upper surface 342 of the lower electrode filling component 332, and (c) a planarized upper surface 347 of the dielectric region 324, which has upper surface areas of the dielectric region 324 on opposite lateral sides (in the x-direction or in both the x-direction and the y-direction) of each of the lower electrodes 312. The planarized support surface 340 can be free of metal bumps because the lower electrode 312 is made of refractory metals (e.g.,tungsten and titanium nitride) are formed which resist the formation of hillocks, in contrast to the lower aluminum electrode of the MIM capacitor module 10 described above according to the prior art in . Fig. 1F. Forming the insulator 314 on a surface 10 free of bumps can provide a higher and more uniform breakdown voltage of the capacitor, e.g. compared to a conventional capacitor module which has a bottom electrode with bumps.

[0061] The surface roughness of the planarized substrate surface 340 can depend on the specific process parameters (e.g., CMP process parameters). In some examples, the planarized surface 340 exhibits a surface roughness of less than 5 nm (50 Å) (root mean square, RMS). In other examples, the planarized substrate surface 340 exhibits an RMS surface roughness of less than 2 nm (20 Å).

[0062] As already mentioned, the insulator 314 can be formed on the area of ​​the resistive layer 322, which is formed on the planarized support surface 340. The lateral width W ins The x-direction of insulator 314 can be described by the lateral width W. te the upper electrode 316 above it. This is the result of anisotropic metal etching that extends through both the upper electrode 316 and the insulator 314, e.g. as in Fig. 13 shown, which is described further below.

[0063] In some examples, e.g., as in Fig. As shown in 3A, the lateral width W te the upper electrode 316 and the corresponding lateral width W ins of the insulator 314 greater than the lateral width W be the underlying lower electrode 312 in the x-direction, so that the insulator 314 extends over the entire lateral width W bethe lower electrode 312 and extends across the planarized upper surface areas 347 of the dielectric region 324 on opposite sides of the lower electrode 312 in the x-direction. In other words, the insulator 314 extends across the planarized upper surface 341 of the cup-shaped lower electrode component 330, the planarized upper surface 342 of the lower electrode filling component 332, and the planarized upper surface areas 347 of the dielectric region 324. In some examples, the insulator 314 extends laterally across the entire lateral width W. be the lower electrode 312 in both the x-direction and the y-direction and additionally extends over parts of the dielectric region 324 on all lateral sides of the lower electrode 312, so that a circumference of the insulator 314, viewed from above, surrounds a circumference of the lower electrode 312.

[0064] The insulator 314 has a uniform thickness Tins across the entire lateral width W ins of insulator 314. In some examples, the thickness T varies. ins of insulator 314, for example, by less than 10% across the entire lateral width W ins of the insulator 314. In some embodiments, the thickness T varies. ins of the insulator 314 by less than 5% or even less than 1% over the entire lateral width W ins of insulator 314.

[0065] This uniform thickness T ins across the entire lateral width W ins The insulator 314 can provide an increased and predictable breakdown voltage for the resulting MIM capacitor module 302a, e.g., compared to a capacitor module with a partially etched or otherwise varying thickness, e.g., the one in Fig. The MIM capacitor module 10 shown and discussed above, 1F, is based on the state of the art.

[0066] Furthermore, the lower electrode 312 can be formed by the formation of a bond between two metal layers M x and M x+1 have a thickness that extends over the entire thickness of the dielectric region 324 between the metal layers M x and M x+1 extends. By forming the upper electrode 316 from the metal compound layer M x+1 The upper electrode 316 can have a thickness T te exhibiting the thickness of the metal compound layer M x+1 is defined. The thickness of the lower electrode T be and the thickness of the upper electrode T te They may therefore be sufficient to provide the desired performance characteristics for various applications (e.g., including RF applications) compared to certain conventional capacitor modules that have a thinner top electrode and / or bottom electrode. In some examples, the thickness of the bottom electrode T beat least 400 nm (4000 Ω) and the thickness of the upper electrode T te at least 400 nm (4000Å).

[0067] As in Fig. As shown in Figure 3A, the example TFR module 304a (a) has a pair of head bases 350a and 350b embedded in the lower metal compound layer M x The TFR module 304a comprises (a) a pair of metal heads 352a and 352b, each conductively coupled to a corresponding head base 350a, 350b, and (c) a resistive element 354 connected via the pair of metal heads 352a and 352b. The example TFR module 304a also includes (a) an insulator cap element 360 (formed from an insulator layer used to form the insulator 314 of the MIM capacitor module 302a), and (b) a metal resistive cap element 362, which is formed in the upper metal compound layer M. x+1 is formed above the insulator cap element 360.

[0068] The metal heads 352a and 352b are located in the through-hole plating layer V x between the lower metallic compound layer M x and the upper metallic compound layer M x+1 formed, e.g. by Damascene process. Each metal head 352a and 352b can, for example, (a) have a cup-shaped head component 364 formed in a head opening 365 formed in the dielectric region 324, and (b) a head filling component 368 formed in an inner opening 369 defined by the cup-shaped head component 364.

[0069] The resistance element 354 is formed on the polished, planarized support surface 340. As in Fig. As shown in Figure 3A, the resistive element 354 can, for example, be formed on a part of the planarized support surface 340 which has (a) a planarized top surface 345 of each cup-shaped head component 364, (b) a planarized top surface 346 of each head-filling component 368 and (c) a planarized top surface 347 of the dielectric region 324 laterally between and beside the pair of metal heads 352a and 352b.

[0070] The resistive element 354 of the TFR module 304a can be formed from a common resistive film, like the area 322 formed between the insulator 314 and the underlying lower electrode 312 of the MIM capacitor module 302a, as described below. Furthermore, the insulator cap element 360 of the TFR module 304a can be formed from a common insulating layer, like the insulator 314 of the MIM capacitor module 302a, as described below.

[0071] The (optional) connection structure 306a has a lower connecting element 380 which is located in the lower metallic connection layer M x is formed to have an upper connecting contact 382, ​​which is located in the upper metallic connecting layer M x+1 is formed, and a connection via 384, which is located in the via layer V x is formed and conductively connects the lower connecting element 380 and the upper connecting contact 382.

[0072] The cup-shaped lower electrode component 330 of the lower electrode 312, the cup-shaped head component 364 of each metal head 352a, 352b, the lower electrode contact 320, and the interconnection vias 384 can be formed from a conformal metal, e.g., tungsten. In some examples, the cup-shaped lower electrode component 330, the cup-shaped head components 364 of the metal heads 352a and 352b, the lower electrode contact 320, and the interconnection vias 384 can be formed simultaneously by deposition of tungsten or another conformal metal, as shown below with reference to Fig. 6 explained. In some examples, an adhesive layer 326 (e.g. a TiN layer with a thickness in the range of 5-30 nm (50-300 Ω)) is deposited prior to the deposition of the conformal metal in order to improve the adhesion between the conformal metal and the surrounding areas of the dielectric region 324, particularly in the well opening 331 and the head openings 365.

[0073] The lower electrode fill component 332 of the lower electrode 312 and the head fill component 368 of each metal head 352a, 352b can be formed from a “fill metal” that is different from the conformal metal forming the cup-shaped component of the lower electrode 330, each cup-shaped head component 364, the lower electrode contact 320, and the interconnect vias 384. For example, the fill metal forming the lower electrode fill component 332 and each head fill component 368 can be TiN or another high-melting-point metal different from the conformal metal. In some examples, the lower electrode fill component 332 and the head fill components 368 can be formed simultaneously by deposition of the fill metal, as shown below with reference to Fig. 7 explained.

[0074] The in Fig. The example of a TFR module 304a shown in 3A may have various advantages or improvements over certain conventional designs, e.g., compared to those in Fig. Two examples of prior art TFR designs are shown. First, the design of the TFR module 304a can be simplified compared to conventional methods. For example, the TFR module 304a can be designed with only a single additional mask added to the corresponding IC fabrication process in the background. Furthermore, the metal heads 352a, 352b of the TFR module 304a can be designed simultaneously with the lower electrode 312 of the MIM capacitor module 302a and / or the interconnect via 384. The metal heads 352a, 352b can be designed with relatively large contact areas and low resistance.

[0075] Fig. Figure 3B is a side cross-sectional view of an exemplary integrated circuit structure 300b, which includes an exemplary MIM capacitor module 302b, an exemplary TFR module 304b, and (optionally) an exemplary interconnect structure 306b, all formed between a siliciated polysilicon layer and a first metallic interconnect layer (generally referred to as the Metal-1 layer). In this example, the siliciated polysilicon layer defines a lower metal layer M0 (i.e., lower metal layer M). x with x=0) and the first metallic compound layer (Metal-1) defines an upper metal layer M1.

[0076] The illustration of the integrated circuit structure 300b is similar to that in Fig. 3A shown and discussed above, the integrated circuit structure 300a, with the exception that the illustrated structures of the integrated circuit structure 300b (MIM capacitor module 302b, TFR module 304b and optional interconnect structure 306b) are between the siliciated polysilicon layer M0 and the first metal interconnect layer M1 and not between two metal interconnect layers M x and M x+1 are trained.

[0077] In some examples, the integrated circuit structure 300b includes the MIM capacitor module 302b, the TFR module 304b, and the interconnection structure 306b. In other examples, the integrated circuit structure 300b includes the MIM capacitor module 302b and the TFR module 304b, but not the interconnection structure 306b. Therefore, the optional interconnection structure 306b is included in Fig. 3B is marked by a dashed line.

[0078] As in Fig. As shown in Figure 3B, a lower electrode base 310' of the MIM capacitor module 300b, a pair of head bases 350a' and 350b' of the TFR module 304b and a lower connecting element 380' of the connecting structure 306b are each formed as a siliciated polysilicon structure having a metal silicide layer formed on a corresponding polysilicon structure in the siliciated polysilicon layer M0.In particular, the lower electrode base 310' has a metal silicide layer 392a formed on an upper surface of a polysilicon structure 390a; the head base 350a' has a metal silicide layer 392b formed on an upper surface of a polysilicon structure 390b; the head base 350b' has a metal silicide layer 392c formed on an upper surface of a polysilicon structure 390c; and the lower connecting element 380' has a metal silicide layer 392d formed on an upper surface of a polysilicon structure 390d. The metal silicide layers 392a-392d can have any suitable metal silicide layer, for example titanium silicide (TiSi2), cobalt silicide (CoSi2) or nickel silicide (NiSi), with a thickness in the range of 10-30 nm (100-300 e) or any other suitable thickness.

[0079] The Fig. Figures 4-13 are lateral cross-sectional views, illustrating, according to an example, a method for forming the in Fig. 3A shows the exemplary integrated circuit structure 300a, including the exemplary MIM capacitor module 302a, the exemplary TFR module 304a and the exemplary interconnect structure 306a.

[0080] First, as in Fig. Figure 4 shows a lower metallic compound layer M x formed over a dielectric region 402, e.g., a pre-metallic dielectric (PMD) region or an inter-metallic dielectric (IMD) region. The metal layer M x can be formed from aluminum, copper, or another suitable metal. The metal layer M xcan be deposited, structured, and etched to form (a) the lower electrode base 310 of the MIM capacitor module 302a, (b) the pair of head bases 350a and 350b of the TFR module 304a, and (c) the lower connecting element 380 of the interconnect structure 306a. Alternatively, the lower electrode base 310, the head bases 350a and 350b, and the lower connecting element 380 can also be formed by a Damascene process. Each of the lower electrode base 310, the head bases 350a and 350b, and the lower connecting element 380 can have a wire or other laterally extended structure (e.g., in the y-axis direction), a discrete pad (e.g., with a square, circular, or substantially square or circular shape in the xy-plane), or any other suitable shape and structure. A resist strip can be applied to remove residual parts of the photomask that were used for structuring the metal layer M.x was used. A dielectric region 324 can be found above the metal layer M x This can be formed, for example, by oxide deposition (e.g., using HDP and PECVD processes), followed by a CMP process for planarization of the oxide. The dielectric region 324 can be an intermetallic dielectric (IMD) region.

[0081] Next, the dielectric region 324 will be discussed, as in Fig. 5A (side view in cross-section) and the corresponding Fig. 5B (top view) shown, structured and etched (e.g. using plasma etching) to form at least one via opening 410 for various interconnect structures, (b) a contact opening 412 for the lower electrode, (c) the well opening 331 to form the lower electrode 312 of the MIM capacitor module 302a and (d) the pair of head openings 365 to form the pair of metal heads 352a and 352b of the TFR module 304a.

[0082] The connecting via opening 410 and the contact opening 412 for the lower electrode can each be a narrow via opening with a lateral diameter or a lateral width W viain contrast, the well opening 331 and each head opening 365 can have a significantly larger width (x-direction) and / or length (y-direction) than the narrow via openings 310 and 312. The shape and dimensions of the well opening 331 and the head openings 365 can be selected based on various parameters, e.g., for the effective fabrication of the MIM capacitor module 302a and the TFR module 304a (e.g., effective deposition of the conformal metal and the filler metal (e.g., tungsten or TiN) in the openings 331 and 365) and / or for the desired performance characteristics of the resulting MIM capacitor module 302a and TFR module 304a. In some examples, the well opening 331 and the head openings 365 can each have a square or rectangular shape in plan view, as e.g., in Fig. 5B shown. In other examples, the tub opening 331 may have a round or oval shape in the top view.

[0083] As already mentioned, the width W tub in the x-direction and / or the length L tub in the y-direction of the tub opening 331 be significantly larger than the width W via each via opening. In some embodiments, for example, the width W tub and / or the length L tub the tub opening 331 at least twice as large as the width W via each via opening. In special embodiments, the width W tub and / or the length L tub the tub opening 331 at least five times as large, ten times as large or twenty times as large as the width W via each via opening. In some examples, the width W is via Each via opening is in the range of 0.1-0.5 µm, while the width W tub and the length Ltub The dimensions of the tub opening 331 are each in the range of 1-100 µm.

[0084] Furthermore, the width W can head in the x-direction and / or the length L head in the y-direction of each head opening 365 must be significantly larger than the width W via each via opening. For example, in some embodiments the width W head and / or the length L head The bathtub opening 365 is at least twice as large as the width W. via each via opening. In special embodiments, the width W head and / or the length L head Each head opening 365 at least five times, ten times, or twenty times as large as the width W via each via opening. In some examples, the width W is via Each via opening is in the range of 0.1-0.5 µm, while the width W head and the length L headEach head opening 365 lies within the range of 0.5-10 µm.

[0085] After etching to create openings 410, 412, 331 and 365, any remaining photoresist material can be removed by a resist strip.

[0086] Next, as in Fig. Figure 6 shows an adhesive layer 326 (e.g., comprising titanium nitride (TiN)) deposited over the integrated circuit structure 300a and in the openings 410, 412, 331, and 365, e.g., with a thickness in the range of 5–30 nm (50–300 Å). A conformal metal layer 420, e.g., tungsten (W), is then deposited over the adhesive layer 326, e.g., by chemical vapor deposition (CVD), with a thickness in the range of 100–500 nm (1000–5000 Å).As shown, the conformal metal layer 420 (a) fills the via opening 410 to form a connecting via 384, (b) fills the contact opening 412 of the lower electrode to form the lower electrode contact 320, (c) partially fills the well opening 331 to form the cup-shaped component 330 of the lower electrode in the well opening 331, and (d) partially fills each head opening 365 to form the cup-shaped head component 364 in each head opening 365. The cup-shaped lower electrode 330 defines an inner opening 333, and each cup-shaped head component 364 defines an inner opening 369.

[0087] The interconnect via 384, the lower electrode contact 320, the cup-shaped lower electrode component 330, and the cup-shaped head component 364 are further processed as described below, including a CMP process which is carried out in Fig. 8A is shown and defines the final form of the respective elements 384, 320, 330 and 364.

[0088] The deposited conformal metal layer 420 can exhibit high tensile stresses due to the inherent material properties of the conformal metal, e.g., tungsten. Consequently, a deposition thickness significantly greater than 500 nm (5000 Å) (e.g., a thickness of 700 nm (7000 Å)) can lead to cracking or delamination of the conformal metal layer 420, or to deformation or fracture of the underlying silicon wafer (not shown), e.g., during a subsequent CMP process. However, these dimensions should not be considered a limitation in any way.

[0089] Next, as in Fig. Figure 7 shows a filler metal layer 430 deposited over the integrated circuit structure 300 to fill the inner opening 333 of the cup-shaped lower electrode component 330 and the inner opening 369 of each cup-shaped head component 364. The filler metal layer 330 can be deposited with sufficient thickness to fill the inner openings 333 and 369 at least to the upper edge of the dielectric region 324. The portion of the filler metal layer 430 that fills the inner opening 333 of the cup-shaped lower electrode component 330 defines the lower electrode filler component 332, and the portion of the filler metal layer 430 that fills the inner opening 369 of each cup-shaped head component 364 defines a corresponding head filler component 368. The filler metal layer 430 can be deposited by a reactive PVD or CVD process without the formation of bumps, which can provide a higher breakdown voltage for the resulting MIM capacitor module 302a, compared to prior art designs that allow or promote the formation of bumps on the lower electrode of the capacitor (and / or other capacitor components), e.g., as above with respect to the one in Fig. The example of a capacitor module 10 shown in 1F is discussed according to the state of the art.

[0090] In some examples, the filler metal layer 430 consists of titanium nitride (TiN) or another high-melting-point metal (different from the conformal metal of the conformal metal layer 420) that exhibits inherent compressive stresses (e.g., at a layer thickness of less than 1 µm). The inherent compressive stresses of the filler metal layer 430 (e.g., the titanium nitride layer) can counteract the inherent tensile stresses of the underlying conformal metal layer 420 (e.g., the tungsten layer), thereby reducing the risk of delamination between the layers, silicon wafer fracture, or other mechanical defects. In another example, the filler metal layer 430 is made of aluminum, which provides lower resistance to the bottom electrode 312 and the metal heads 352a, 352b, but also introduces the possibility of bumping.

[0091] Next, as in Fig. 8A (side view in cross-section) and the corresponding Fig. Figure 8B (top view) shows a planarization process (e.g., CMP process) being performed to remove the upper portions of the filler metal layer 430, the conformal metal layer 420, and the adhesive layer 326, thereby forming the final shape of (a) the interconnect via 384, (b) the lower electrode contact 320, (c) the cup-shaped lower electrode component 330 and the lower electrode filler component 332 of the lower electrode 312 of the MIM capacitor module 302a, and (d) the cup-shaped head component 364 and the head filler component 368 of each metal head 352a, 352b of the TFR module 304a. The planarization process can be designed to terminate in the dielectric region 324.

[0092] The planarization process (e.g., CMP process) defines a polished, planarized support surface 340, which has (a) the planarized upper surface 341 of the cup-shaped lower electrode component 330, (b) the planarized upper surface 342 of the lower electrode filling component 332, (c) the planarized upper surface 345 of each cup-shaped head component 368, (d) the planarized upper surface 346 of each head filling component 368, and (e) the planarized upper surface 347 of the dielectric region 324, which has upper surface areas of the dielectric region 324 on opposite lateral sides (in the x-direction or both in the x-direction and in the y-direction) of each lower electrode 312 and each metal head 352a, 352b.

[0093] The planarized support surface 340 provides a smooth, planarized surface free of bumps. For example, the planarized top surfaces 341, 342, 345, and 346 (components of the planarized support surface 340) provide smooth, planarized surfaces of refractory metals used as the conformal metal layer 420 and the filler metal layer 430 (e.g., tungsten and titanium nitride, as described above). These surfaces are free of bumps and suitable for supporting the insulator 314 and the resistive element 354. As explained further below, the resistive element 354 is formed from a resistive layer 404 directly on the planarized support surface 340, while the insulator 314 is formed on a region 322 consisting of the same resistive layer 404.As explained below, the resistive foil 404 is formed as a planar layer of uniform thickness over the planarized support surface 340; therefore, the insulator 314 formed on the area of ​​the resistive foil 322 is also formed as a planar structure of uniform thickness over the lateral width of the insulator 314 (in the x-direction or both in the x- and y-directions).

[0094] Next, as in Fig. Figure 9 shows a resistive layer 404 deposited onto the structure 300, followed by the deposition of an insulator layer 406. In some examples, the resistive layer 404 can comprise SiCCr, SiCr, NiCr, TaN, or another suitable material with a thickness T resistorThe insulator layer 406, which in one example can be in the range of 10–100 nm (100–1000 Å), is deposited, for example by a physical vapor deposition (PVD) process, and which in one example has a layer resistance in the range of 200–1000 ohms per square. The insulator layer 406 can comprise silicon nitride (Si3N4, κ~7) with a thickness T ins In one example, the insulating layer is in the 40-60 nm range (400-600 Å), for example, deposited by a PECVD deposition process. In other examples, the insulating layer 406 can be silicon dioxide (SiO2) or a dielectric material with a high k-value, e.g., Al2O3 (κ~10), Ta2O5 (κ~25), HfO2 (κ~22), or ZrO2 (κ~35), deposited, for example, by a PECVD or an ALD (Atomic Layer Deposition) process.

[0095] A photoresist layer is then applied and structured to form a photomask 410 over the insulator layer 406. The structured photomask 410 has a first region 410a over the lower electrode 312 of the MIM capacitor module 302a and a second photomask 410b extending over the pair of metal heads 352a, 352b of the TFR module 304a. A lateral width W be_resist The first area of ​​photomask 410a extends laterally over a lateral width W be the lower electrode 312 extends in the x-direction or in both the x- and y-directions. Similarly, a lateral width W extends tfr_resist of the second photomask area 410b laterally over a lateral width W heads , which extends over both metal heads 352a, 352b in the x-direction or in both the x-direction and the y-direction.

[0096] Next, as in Fig. Figure 10 shows that an etching process is carried out to remove portions of the insulator layer 406 and the resistive film 404 that are uncovered by the structured photomask 410, leaving (a) a first resistive film region 404a and a first insulator layer region 406a below the first photomask region 410a, and (b) a second resistive film region 404b and a second insulator layer region 406b below the second photomask region 410b. The lateral width of the first resistive film region 404a (W region_404a ) and the first insulator layer area 406a (W region_406a ) corresponds to the lateral width W be_resist of the first photomask area 410a, such that each area extends laterally across the lateral width W be the lower electrode extends in the x-direction or in both the x-direction and the y-direction. Similarly, the lateral width of the second resistive film area corresponds to 404b (W region_404b) and the second insulator layer area 406b (W region_406b ) the lateral width W tfr_resist of the second photomask area 410b, such that each area extends laterally across the lateral width W heads extends over both metal heads 352a, 352b in the x-direction or in both the x-direction and the y-direction.

[0097] Next, an upper metal compound layer M is applied over the integrated circuit structure 300a. x+1 trained. First, as in Fig. Figure 11 shows an upper metal layer 430, comprising, for example, aluminium, copper or another suitable metal, deposited over the dielectric region 324 and the first and second insulating layer regions 406a, 406bb.

[0098] Next, as in Fig. Figure 12 shows a photoresist layer deposited and structured to form a photomask 440 comprising (a) a first photoresist element 440a for forming an upper connecting contact 382 (as described below), (b) a second photoresist element 440b (for forming the connecting element of the lower electrode 318, as described below), (c) a third photomask element 440c (for forming the upper electrode 316 and the underlying insulator 314 and the resistive film region 322, as described below), and (d) a fourth photomask element 440d (for forming the metal resistive cap element 362 and the underlying insulator cap element 360 and the resistive element 354, as described below).

[0099] As shown, the width W te_resist The third photomask element 440c must be larger than the width W bethe lower electrode 312, but smaller than the width of the first resistive film region 404a and the first insulator layer region 406a (W region_404a = W region_406a ), such that the subsequent etching of the metal to form the upper electrode 316 (see Fig. 13) the lateral edges (in the x-direction or both in the x-direction and in the y-direction) of the upper electrode 316 with the underlying insulator 314 and the resistive layer region 322 (see Fig. 13) aligns itself and simultaneously prevents any etching of the lower electrode 312.

[0100] Similarly, the width W can be tfr_cap_resist The third photomask element 440d must be larger than the width W heads , which extends over both metal heads 352a, 352b, but is smaller than the width of the second resistive film area 404b and the second insulator layer area 406b (W region_404b = W region_406b), such that the subsequent etching of the metal to form the metal resistance cap element 362 (see Fig. 13) the lateral edges (in the x-direction or both in the x-direction and in the y-direction) of the metal resistance cap element 362 with the underlying resistance element 354 and the insulator cap element 360 (see Fig. 13) aligns itself and simultaneously prevents any etching of the metal heads 352a, 352b.

[0101] Fig. Figure 13 shows the results of the metal etching by the in Fig. Figure 12 shows the photomask 440 and the area after photomask 440 has been removed, for example, by a resistab stripping process. Etching can be selective to etch through structures not covered by photomask 440 (including parts of the top metal layer 430, the first and second insulator layer areas 406a, 406b, and parts of the first and second resist film areas 404a, 404b not covered by photomask 440, as shown in Figure 12). Fig. (12 shown), but stop in the dielectric region 324, e.g. at a depth of 50-100 nm (500-1000 Ω) in the dielectric region 324. As shown, the etching forms (a) the upper connecting element 382 in contact with the connecting via 384, (b) the lower electrode connecting element 318 in contact with the lower electrode contact 320, (c) the upper electrode 316 and 25 the underlying insulator 314 and the underlying resistive film region 322, and (d) the metallic resistive cap element 362 and the underlying insulator cap element 360 and the resistive element 354.

[0102] As shown, the lateral edges of the upper electrode 316 are aligned with the corresponding lateral edges of the insulator 314 and the resistive layer 322 due to the metal etching. A lateral width of the upper electrode 316 (W te ), of the insulator 314 (W ins ) and the area of ​​the resistance layer 322 (Wresistor_film_region ) extends laterally across the lateral width W te the lower electrode in the x-direction or in both the x-direction and the y-direction.

[0103] Similarly, the lateral edges of the metallic resistance cap element 362 are aligned with the corresponding lateral edges of the underlying insulator cap element 360 and the resistance element 354. The lateral width of the metal resistance cap element 362 (W metal_cap ), the insulator cap element 360 (Wins cap) and the resistance element 354 (W tfr_element ) extends laterally across the lateral width W heads , which extends over both metal heads 352a, 352b in the x-direction or in both the x-direction and the y-direction.

[0104] The area of ​​the resistive layer 322 and the resistive element 354 each have the thickness (T resistor ) of the resistive layer 404, from which they are formed. This thickness Tresistor is the same over the entire lateral width (in the x-direction or in both the x-direction and the y-direction) of the area of ​​the resistive layer 322 or the resistive element 354. Similarly, the insulator 314 and the insulator cap element 360 each have the thickness (T ins ) of the insulating layer 406 from which they are formed, wherein the thickness T ins is uniform over the entire lateral width (in the x-direction or both in the x-direction and in the y-direction) of the insulator 314 or the insulator cap element 360.

[0105] Some examples show Fig. 13 the completion of the MIM capacitor module 302a, the TFR module 304a and the interconnection structure 306a. After forming the MIM capacitor module 302a, the TFR module 304a and the interconnection structure 306a, the process can be continued with the formation of further interconnection structures, e.g. by forming further metallic interconnection layers and / or dielectric layers. Fig. Figure 14 is a flowchart showing an exemplary procedure 1400 for forming an exemplary integrated circuit structure, which, according to an example, includes an exemplary MIM capacitor module and an exemplary TFR module. Figure 1402 describes a lower metal layer M x formed, which has a lower electrode base. In one example, the lower metal layer M x a lower compound metal layer (e.g., made of aluminum). In another example, the lower metal layer M xa siliciated polysilicon layer. In 1404, a dielectric region (e.g., an oxide region) is formed above the lower metal layer M. x isolated and planarized, e.g. through a CMP process.

[0106] Next, as in Fig. 14, indicated by the dashed box, a Damascene process is carried out at 1406-1412 to form a lower electrode and lower electrode contact of the MIM capacitor module and a pair of metal heads of the TFR module.

[0107] First, in 1406, the dielectric region is structured and etched to form a well opening and a pair of head openings. In 1408, a lower electrode is formed in the well opening, wherein the lower electrode has (a) a cup-shaped component and (b) a filling component in an inner opening defined by the cup-shaped component.

[0108] In process 1410, which can be carried out simultaneously with process 1408, a metal head is formed in each of the two head pan openings, each metal head having (a) a cup-shaped head component and (b) a head-filling component in an inner opening defined by the cup-shaped head component.

[0109] In 1412, a planarization process is performed to define a planarized support surface that has (a) a planarized upper surface of the cup-shaped lower electrode component, (b) a planarized upper surface of the lower electrode filling component, and (c) planarized upper surface areas of the dielectric region on opposite sides of the lower electrode. In 1414, a resistive element connected via the pair of metal heads is formed from a resistive film formed on the planarized support surface.

[0110] In 1416, an insulator is formed on the lower electrode of the MIM capacitor module. The insulator can be formed over the planarized substrate surface and extend laterally across the entire width of the lower electrode, such that the insulator extends over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode in the x-direction, or in both the x- and y-directions. The insulator can have a uniform vertical thickness across its entire lateral width. In some examples, as explained above, the insulator is formed over the resistive film, such that a region of the resistive film (formed on the planarized substrate surface) is located between the insulator and the planarized substrate surface.Like the insulator, the resistive layer can also have a uniform vertical thickness across the entire lateral width of the resistive layer area.

[0111] In 1418, an upper metal layer is formed over the dielectric region, wherein the upper metal layer has an upper electrode over the insulator.

[0112] Fig. Figure 15 is a flowchart showing an exemplary procedure 1500 for forming an exemplary integrated circuit structure, which, according to an example, includes an exemplary MIM capacitor module and a TFR module. Figure 1502 describes a lower metal layer M x formed, which has a lower electrode base and a pair of head bases. In one example, the lower metal layer M has x a lower compound metal layer (e.g., made of aluminum). In another example, the lower metal layer M xa siliciated polysilicon layer. At 1504, a dielectric region (e.g., an oxide region) is formed above the lower metal layer M. x isolated and planarized, e.g. through a CMP process.

[0113] Next, as in Fig. As indicated by the dashed box in Figure 15, a Damascene process is carried out at 1506-1512 to form a bottom electrode and a pair of metal heads. At 1506, the dielectric region is patterned and etched to form (a) a well opening and a pair of head openings. At 1508, a conformal metal (e.g., tungsten) is deposited and extends into the bottom electrode opening and the pair of head openings. At 1510, a filler metal (e.g., titanium nitride (TiN)) is deposited over the conformal metal and extends into the well opening and the pair of head openings.

[0114] In 1512, a planarization process is performed to remove portions of the conformal metal and filler metal, wherein (a) the remaining portions of the conformal metal and filler metal in the lower electrode orifice define a lower electrode having a cup-shaped lower electrode component and a lower electrode filler component in an inner orifice defined by the cup-shaped lower electrode component, and (b) the remaining portions of the conformal metal and filler metal in each head orifice define a metal head having a cup-shaped head component and a head filler component in an inner orifice defined by the cup-shaped head component.The planarization process can define a planarized support surface that includes (a) a planarized upper surface of the cup-shaped lower electrode component, (b) a planarized upper surface of the lower electrode filling component, (c) planarized upper surface areas of the dielectric region on opposite sides of the lower electrode, (d) a planarized upper surface of the cup-shaped head component of each metal head, (e) a planarized upper surface of the filling component of each metal head, and (f) planarized upper surface areas of the dielectric region laterally between and beside the pair of metal heads.

[0115] In 1514, a resistive element connected via the pair of metal heads is formed from a resistive film formed on the planarized substrate surface.

[0116] In 1516, an insulator is formed over the lower electrode. The insulator can be formed over the planarized support surface and extend laterally across the entire width of the lower electrode, such that the insulator extends over the planarized upper surface regions of the dielectric region on opposite sides of the lower electrode (in the x-direction or in both the x- and y-directions). In some examples, the insulator can be formed as a planar insulator having a uniform vertical thickness across its entire lateral width. In some examples, as explained above, the insulator is formed over the resistive film, such that a region of the resistive film (located on the planarized support surface) is situated between the insulator and the planarized support surface.Like the insulator, the resistive layer can also have a uniform vertical thickness across the entire lateral width of the resistive layer area.

[0117] In 1518, an upper metal layer is formed over the dielectric region, with the upper metal layer having an upper electrode over the insulator.

Claims

[1] Integrated circuit structure which features: (a) a metal-insulator-metal capacitor module (302) comprising: a lower electrode base (310) embedded in a lower metal layer (M x ) is trained; a lower electrode (312) located in a dielectric region (324) between the lower metal layer (M x ) and an upper metal layer (M x+1 ) is formed, wherein the lower electrode (312) has: a cup-shaped lower electrode component (330); and a lower electrode filling component (332) formed in an inner opening (331) defined by the cup-shaped lower electrode component (330); an insulator (314) formed above the lower electrode (312); and an upper electrode (316) located in the upper metal layer (M x+1 ) is formed above the insulator (314); and (b) a thin-film resistance modulus (304) comprising: a pair of metal heads (352) located in the dielectric region (324) between the lower metal layer (M x ) and the upper metal layer (M x+1 ) are formed, each having a metal head (352): a cup-shaped head component (364) ; and a head-filling component (368) formed in an inner opening (365) defined by the cup-shaped head component (368); and a resistive element (354) connected via the pair of metal heads (352), wherein the cup-shaped head component (364) of each metal head (352) and the cup-shaped lower electrode component (330) are formed from a conformal metal; and the head-fill component (368) of each metal head (352) and the lower electrode-fill component (332) are formed from a filler metal other than the conformal metal, wherein the conformal metal comprises tungsten, and the filler metal comprises titanium nitride. [2] Integrated circuit structure according to claim 1, wherein the thin-film resistor module (304) has a pair of head bases (350) which are embedded in the lower metal layer (M x ) are formed, wherein each metal head (352) is conductively connected to a respective head base (350). [3] Integrated circuit structure according to one of claims 1 to 2, wherein the insulator (314) has a uniform vertical thickness (T ins) over the entire lateral width (Wins) of the insulator (314). [4] Integrated circuit structure according to one of claims 1 to 3, wherein the insulator (314) is formed over a planarized support surface (340) which has a planarized upper surface of the cup-shaped lower electrode component (341) and a planarized upper surface of the lower electrode filling component (342). [5] Integrated circuit structure according to claim 4, comprising a resistive film region (322) formed on the planarized substrate surface (340), wherein the resistive film region (322) has a uniform vertical thickness over a full lateral width of the resistive film region (322); wherein the insulator (314) is formed on the resistive film region (322), wherein the insulator (322) has a uniform vertical thickness (T ins ) over a full lateral width (W ins ) of the insulator (314). [6] Integrated circuit structure according to claim 5, wherein: the planarized support surface (340) (a) has a planarized top surface of the cup-shaped lower electrode component (341), (b) a planarized top surface of the lower electrode filling component (342) and (c) planarized top surface areas of the dielectric region (324) on opposite sides of the lower electrode (312); and the insulator (314) extends laterally over a full width (W be ) of the lower electrode (312) and beyond, so that the insulator (314) extends over the planarized top surfaces of the dielectric region (324) on opposite sides of the lower electrode (312). [7] Integrated circuit structure according to any one of claims 1 to 6, wherein: the thin-film resistive module (304) comprises a resistive element insulator cap element (360) formed on the resistive element (354); and the resistive element insulator cap element (360) is formed from a common insulator material such as the insulator (314). [8] Integrated circuit structure according to any one of claims 1 to 7, wherein: the lower metal layer (M x ) has a lower bonding layer; and the upper metal layer (M x+1 ) has an upper bonding layer. [9] Integrated circuit structure according to any one of claims 1 to 8, wherein: the lower metal layer (M x ) has a silicidal polysilicon layer, wherein the lower metal layer (M x ) formed lower electrode base (310) has a metal silicide area (392) formed on a polysilicon area (390); and the upper metal layer (M x+1) has a first metal compound layer. [10] Integrated circuit structure according to any one of claims 1 to 9, wherein the metal-insulator-metal capacitor module (302) comprises: one in the upper metal layer (M x+1 ) formed lower electrode connecting element (318); and one in the dielectric region (324) between the lower metal layer (M x ) and the upper metal layer (M x+1 ) formed lower electrode contact (320); wherein the lower electrode contact (320) forms a conductive connection between the upper metal layer (M x+1 ) formed connecting element (318) of the lower electrode (312) and the one in the lower metal layer (M x ) provides a formed lower electrode base (310). [11] Integrated circuit structure according to any one of claims 1 to 10, further comprising a connection structure (306) comprising: a lower connecting element (380) located in the lower metal layer (M x ) is trained; and an upper connecting contact (382) located in the upper metal layer (M x+1 ) is formed and is connected to the lower connecting element (380) by at least one through-hole connection (384). [12] Integrated circuit structure according to claim 11, wherein the at least one interconnection via (384) and the cup-shaped lower electrode component (330) are formed from a common conformal metal. [13] Method for forming one of the integrated circuit structures according to claims 1 to 12.

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