Array substrate, its manufacturing process and display device

Abstract

The present application presents an array substrate, its manufacturing process, and a display device, and relates to the field of display technology, comprising: a substrate substrate; a first electrically conductive layer arranged on one side of the substrate substrate and comprising a plurality of electrically conductive pad sets, wherein the electrically conductive pad sets comprise at least one electrically conductive pad; a second electrically conductive layer arranged on one side of the first electrically conductive layer facing away from the substrate substrate, wherein the orthographic projection of at least one sub-region of each electrically conductive pad in the electrically conductive pad sets on the substrate substrate does not overlap with the orthographic projection of the second electrically conductive layer on the substrate substrate;wherein the thickness of the first electrically conductive layer in a direction perpendicular to the plane in which the substrate is located is greater than or equal to the thickness of the second electrically conductive layer in a direction perpendicular to the plane in which the substrate is located. The array substrate has a high rework yield and good quality.

Description

Technical area

[0001] The present application relates to the field of display technology and in particular to an array substrate and its manufacturing method and a display device. State of the art

[0002] With the rapid development of display technology, mini-LED (mini light-emitting diode) and micro-LED (micro light-emitting diode) display products have attracted considerable attention. The chip welding process is an important step in the manufacturing of the two types of display products mentioned above. In these technologies, chips are highly susceptible to poor conduction during welding or repair, resulting in poor bonding between the chip and the array substrate of the display product, which in turn results in lower yield and lower quality of the display product. Disclosure of the invention

[0003] The following technical solutions are used in the embodiments of the present application: In a first aspect, the embodiments of the present application provide an array substrate comprising: a substrate base; a first electrically conductive layer disposed on one side of the substrate base and comprising a plurality of electrically conductive pad sets, the electrically conductive pad sets comprising at least one electrically conductive pad; a second electrically conductive layer arranged on a side of the first electrically conductive layer facing away from the substrate base, wherein the orthographic projection of at least a partial region of each electrically conductive pad in the electrically conductive pad sets on the substrate base does not overlap with the orthographic projection of the second electrically conductive layer on the substrate base; wherein a thickness of the first electrically conductive layer in a direction perpendicular to the plane in which the substrate base is located is greater than or equal to a thickness of the second electrically conductive layer in a direction perpendicular to the plane in which the substrate base is located.

[0004] In some embodiments of the present application, the array substrate further comprises a first insulating layer located between the first electrically conductive layer and the second electrically conductive layer, wherein the first insulating layer has a plurality of openings and at least a portion of electrically conductive pads is exposed through these openings; wherein the orthographic projection of the portion of the electrically conductive pads on the substrate base exposed by the openings and the orthographic projection of the second electrically conductive layer on the substrate base do not overlap.

[0005] In some embodiments of the present application, the array substrate comprises a display region, and the electrically conductive wheel sets comprise first electrically conductive pad sets, wherein the first electrically conductive pad sets are located in the display region.

[0006] In some embodiments of the present application, the first electrically conductive pad sets comprise first electrically conductive pads, wherein the orthographic projection of at least the region of the first electrically conductive pads exposed by the openings on the substrate base does not overlap with the orthographic projection of the second electrically conductive layer on the substrate base.

[0007] In some embodiments of the present application, the array substrate comprises a display region and a peripheral region surrounding the display region; wherein the electrically conductive pad sets comprise second electrically conductive pad sets, the second electrically conductive pad sets being located in the peripheral region.

[0008] In some embodiments of the present application, the second electrically conductive pad sets include second electrically conductive pads and third electrically conductive pads; wherein, apart from the region of the second electrically conductive pads exposed by the openings, the orthographic projection of the other regions of the second electrically conductive pads on the substrate base partially overlaps the orthographic projection of the second electrically conductive layer on the substrate base; wherein the orthographic projection of the third electrically conductive pads on the substrate base and the orthographic projection of the second electrically conductive layer on the substrate base do not overlap.

[0009] In some embodiments of the present application, the second electrically conductive layer comprises a plurality of connecting lines arranged in the peripheral region, wherein the second electrically conductive pads are electrically connected to the connecting lines, and wherein the orthographic projection of the second electrically conductive pads on the substrate partially overlaps with the orthographic projection of the connecting lines on the substrate.

[0010] In some embodiments of the present application, the array substrate comprises a shield line, wherein the peripheral region comprises bonding regions arranged on one side of the display region; wherein a main structure of the shield line is located in regions in the peripheral region other than the bonding regions, and wherein two ends of the shield line extend into the bonding regions; wherein the two ends of the shield line are each electrically connected to the second electrically conductive pads via a connecting line.

[0011] In some embodiments of the present application, the shielding line covers at least a portion of the individual connecting lines, and the shielding line is in direct contact with the individual connecting lines.

[0012] In some embodiments of the present application, the first electrically conductive layer comprises a first electrically conductive portion comprising a ground line located in the display area; wherein the connecting lines are electrically connected to the ground line.

[0013] In some embodiments of the present application, a connection line located in a region of the peripheral region other than bonding regions is electrically connected to the ground line via a through-hole; and a connection line located in a bonding region is electrically connected to the ground line via the shield line.

[0014] In some embodiments of the present application, the peripheral region comprises a fan-out region, wherein the fan-out region is disposed between the binding region and the display region, and the fan-out region comprises a fan-out cable; wherein the third electrically conductive pads are electrically connected to the first electrically conductive portion via the fan-out cable.

[0015] In some embodiments of the present application, the binding region comprises a first binding portion and a second binding portion, wherein the first binding portion is located on a side of the second binding portion facing away from the display portion; wherein the individual second electrically conductive pads are located in the first bonding portion and the individual third electrically conductive pads are located in the second bonding portion.

[0016] In some embodiments of the present application, the individual second electrically conductive pads are arranged in the same direction, wherein the individual third electrically conductive pads are arranged in the same direction, wherein in the arrangement direction of the second electrically conductive pads there is a first gap between each two adjacent second electrically conductive pads and in the arrangement direction of the third electrically conductive pads there is a second gap between each two adjacent third conductive pads; wherein the numbers of sublayers of the first insulating layer filled in the first gap and in the second gap are equal, and wherein the number of sublayers of the first insulating layer filled in the second gap is greater than the number of sublayers of the first insulating layer located in a part of the second electrically conductive pad sets facing away from the surface of the substrate base.

[0017] In some embodiments of the present application, the first insulating layer comprises a first inorganic sublayer, a first organic sublayer, a second organic sublayer, and a second inorganic sublayer arranged sequentially, wherein the first inorganic sublayer 41 and the first electrically conductive layer are in direct contact with each other; wherein the orthographic projection of the first organic sublayer on the substrate base does not overlap with the part of the substrate base arranged in the bonding region.

[0018] In some embodiments of the present application, the orthographic projections of the first organic sublayer and the second inorganic sublayer on the substrate base and the orthographic projection of the third electrically conductive pads on the substrate base do not overlap; wherein the orthographic projections of the first organic sublayer and the second inorganic sublayer on the substrate base and the orthographic projection of the third electrically conductive pads on the substrate base do not overlap.

[0019] In some embodiments of the present application, at least the first inorganic sublayer, the second organic sublayer, and the second inorganic sublayer are arranged sequentially in the first gap, wherein at least the first inorganic sublayer, the second organic sublayer, and the second inorganic sublayer are arranged sequentially in the second gap.

[0020] In some embodiments of the present application, the array substrate further comprises a second insulating layer, wherein the second insulating layer is located on a side of the second electrically conductive layer facing away from the substrate base; wherein the second insulating layer fills the first gap and the second gap and the orthographic projection of the second insulating layer on the substrate base does not overlap with the orthographic projection of at least a portion of the second electrically conductive pads on the substrate base.

[0021] In some embodiments of the present application, the second insulating layer comprises a third inorganic sublayer and a third organic sublayer, wherein the third organic sublayer is located on a side of the third inorganic sublayer facing away from the substrate base; wherein the third inorganic sublayer and the third organic sublayer are further provided successively in the first gap and the second gap, the parts of the third inorganic sublayer lying in the gaps being in direct contact with the parts of the second inorganic sublayer lying in the gaps.

[0022] In some embodiments of the present application, the distance in the thickness direction of the substrate base between the surface of a part of the third organic sublayer facing away from the substrate base, which part is located between the gaps, and the substrate base is less than or equal to the distance in the thickness direction of the substrate base between the surface of a part of the second organic sublayer facing away from the substrate base, which part is located on the second electrically conductive pad sets, and the substrate base.

[0023] In some embodiments of the present application, the second insulating layer covers a portion of the connecting lines, and the shielding line CS covers a portion of the connecting lines.

[0024] In some embodiments of the present application, a part of the outer contour of the orthographic projection of the second insulating layer on the substrate base approximately touches a part of the outer contour of the orthographic projection of the shielding line on the substrate base.

[0025] In some embodiments of the present application, the orthographic projection of the second insulating layer on the substrate base and the orthographic projection of a partial area of ​​the second electrically conductive pads on the substrate base overlap; wherein the orthographic projection of the second insulating layer on the substrate base and the orthographic projection of a surface of the third electrically conductive pads on the substrate base facing away from the substrate base do not overlap.

[0026] In some embodiments of the present application, the array substrate further comprises a protective layer, wherein the protective layer covers a portion of the first electrically conductive pads exposed at the openings, wherein the material of the protective layer comprises an electrically conductive material.

[0027] In a second aspect, the embodiments of the present application provide a display device comprising light-emitting components and an array substrate as described above, wherein the light-emitting components are electrically connected to first electrically conductive pad sets.

[0028] In some embodiments of the present application, the display device further comprises a circuit board electrically connected to second electrically conductive pad sets of the array substrate.

[0029] In a third aspect, the embodiments of the present application provide a method for manufacturing an array substrate, which is applied to manufacture an array substrate as described above, the method comprising: Providing a substrate base; Forming a first electrically conductive layer comprising a plurality of electrically conductive pad sets comprising at least one electrically conductive pad; Forming a first inorganic sub-film, a patterned first organic sub-layer, a patterned second organic sub-layer, and a second inorganic sub-film successively on the first electrically conductive layer; forming a second electrically conductive layer; Structuring the first inorganic sub-film and the second inorganic sub-film to obtain the first inorganic sub-layer and the second inorganic sub-layer; wherein the first insulating layer comprises a first inorganic sub-layer, a first organic sub-layer, a second organic sub-layer, and a second inorganic sub-layer, and wherein the first insulating layer has a plurality of openings exposing at least a portion of the electrically conductive pads.

[0030] The above description merely provides an overview of the technical solution of the present application. To better understand the technical measures of the present application, it can be implemented according to the contents of the description. To make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present disclosure are listed below. Brief presentation of the drawings

[0031] To better illustrate the embodiments of the present application or the technical solutions in the relevant technical field, the drawings required for describing the embodiments or the prior art are briefly described below. It is obvious that the drawings in the following description represent only some embodiments of the present application, and that other drawings can be obtained based on these drawings without inventive effort on the part of a person skilled in the art. Fig. 1A to Fig. 2B and Fig. 9 show schematic structural diagrams of five types of array substrates from the related field provided by embodiments of the present application; Fig. 3 and Fig. 4 show schematic structural representations of two types of first electrically conductive pad sets provided by embodiments of the present application; Fig. Figure 5 shows a structural cross-sectional view of Fig. 4 along the A1A2 direction; Fig. 6 shows a schematic structural diagram of an array substrate for mounting components provided by embodiments of the present application; Fig. 7 shows a schematic structural top view of an array substrate provided by embodiments of the present application; Fig. 8 shows a schematic structural representation of a second electrically conductive pad set in a peripheral region of an array substrate provided by embodiments of the present application; Fig. 10 shows a partially enlarged view of a second electrically conductive pad set provided by embodiments of the present application; Fig. 11 shows a schematic structural diagram of a shield line located in the peripheral region and provided by embodiments of the present application; Fig. 12 shows another schematic structural representation of a shield line located in the peripheral region and provided by embodiments of the present application; Fig. 13 shows another structural cross-sectional view of Fig. 4 along the A1A2 direction; Fig. 14 shows a structural cross-sectional view of Fig. 10 or Fig. 11 along the B1B2 direction; Fig. 15 shows a schematic structural plan view of a display area provided by embodiments of the present application; Fig. 16 shows another schematic structural plan view of a display area provided by embodiments of the present application. Examples of implementation

[0032] The technical solutions in the embodiments of the present application are described clearly and completely below in conjunction with the drawings in the embodiments of the present application. It is obvious that the described embodiments represent only a part and not all of the embodiments of the present application. Starting from the embodiments in the present application, all other embodiments that a person skilled in the art can arrive at without inventive step also fall within the scope of the present application.

[0033] In the drawings, the thickness of regions and layers may be exaggerated for clarity. Like reference numerals throughout the drawings denote like or similar structures, so a detailed description thereof is omitted. Furthermore, the drawings are only schematic representations of the present application and are not necessarily drawn to scale.

[0034] Throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, meaning "including, but not limited to," unless the context indicates otherwise. Throughout the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example examples," "particular examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. The above terms do not necessarily refer to the same embodiment or example.Moreover, the particular features, structures, materials, or properties mentioned may be included in any one or more embodiments or examples as appropriate.

[0035] In the embodiments of the present application, the use of words such as "first", "second", etc. to distinguish between the same or similar elements having substantially the same function and effect is solely for the purpose of clearly describing the technical solutions of the embodiments of the present application and is not to be understood as an indication of relative importance or as an implicit indication of the number of technical features specified.

[0036] Embodiments of the present application provide an array substrate as described in connection with Fig. 5 and Fig. 14, which includes: a substrate base plate 1; a first electrically conductive layer 3 arranged on one side of the substrate base 1 and comprising a plurality of electrically conductive pad sets W1 and / or W2, wherein the electrically conductive pad sets W1 and / or W2 comprise at least one electrically conductive pad; a second electrically conductive layer 5 arranged on a side of the first electrically conductive layer 3 facing away from the substrate base 1, wherein the orthographic projection of at least a partial region of each electrically conductive pad in the electrically conductive pad sets W1 or W2 on the substrate base 1 does not overlap with the orthographic projection of the second electrically conductive layer 5 on the substrate base 1; wherein a thickness of the first electrically conductive layer 3 in a direction perpendicular to the plane in which the substrate base 1 is located is greater than or equal to a thickness of the second electrically conductive layer 5 in a direction perpendicular to the plane in which the substrate base 1 is located.

[0037] Fig. Figure 5 shows a structural cross-sectional view of Fig. 4 along the A1A2 direction.

[0038] In an exemplary embodiment, the aforementioned array substrate may be a submillimeter light-emitting diode (mini-LED) array substrate; or the aforementioned array substrate may be a micro-light-emitting diode (micro-LED) array substrate. The mini-LED has a size of approximately 100-300 µm, and the micro-LED has a size of 100 µm or less.

[0039] In an exemplary embodiment, the aforementioned substrate base 1 may be a glass-based substrate.

[0040] In some embodiments, the substrate base 1 may contain an organic resin material such as epoxy resin, triazine resin, silicone resin, or polyimide. For example, the substrate base 1 may be an FR4 printed circuit board (PCB) or an easily deformable flexible printed circuit board.

[0041] In some embodiments, the substrate base 1 may comprise a ceramic material such as silicon nitride, AlN, or Al2O3, or may comprise a metal or metal compound. For example, the substrate base 1 may be a metal core printed circuit board (MCPCB) or a metallic copper clad laminate (MCCL).

[0042] In an exemplary embodiment, the array substrate comprises a two-layer electrically conductive layer, e.g., a first electrically conductive layer 3 and a second electrically conductive layer 5, which together form an electrically conductive pattern.

[0043] The first electrically conductive layer 3 has, for example, a foil layer thickness in the range of 1.5 to 7 µm, and its material comprises copper (Cu). Specifically, a stacked material, e.g., of MoNb / Cu / MoNb, can be formed by sputtering, with a lower layer of MoNb (300 Å) to improve adhesion, an intermediate layer of Cu to transmit electrical signals, and a top layer of MoNb (200 Å) to prevent oxidation. Alternatively, the first electrically conductive layer 3 can be formed by electroplating, first forming a seed layer of MoNiTi to improve grain nucleation density, and then forming an anti-oxidation layer of MoNiTi after electroplating Cu.

[0044] In an exemplary embodiment, the first electrically conductive layer 3 can be used to arrange various signal lines, such as a ground line, a drive line and a power supply line.

[0045] In an exemplary embodiment, the first electrically conductive layer 3 may comprise a plurality of electrically conductive pad sets, each of the electrically conductive pad sets comprising at least one electrically conductive pad. The electrically conductive pads may be bond pads or binding clips.

[0046] For example, the electrically conductive pads in the first electrically conductive layer 3, as shown in the Fig. 13 and Fig. 14, a partial area exposed through an opening K in the first insulating layer 4 and a partial area covered by an insulating layer arranged around the opening.

[0047] The first electrically conductive layer 3 may comprise a plurality of electrically conductive pad sets, including but not limited to the following three cases: In the first case, the electrically conductive pad sets in the first electrically conductive layer comprise first electrically conductive pad sets W1 located in the display area.

[0048] In the second case, the electrically conductive pad sets in the first electrically conductive layer comprise second electrically conductive pad sets W2 located in the bonding region.

[0049] In the third case, the electrically conductive pad sets may simultaneously comprise first electrically conductive pad sets W1 located in the display region and second electrically conductive pad sets W2 located in the bonding region.

[0050] The first electrically conductive pad sets W1 are used for electrical connection to components, and the second electrically conductive pad sets W2 are used for electrical connection of the array substrate to printed circuit boards for inputting electrical signals to the array substrate. The components can include light-emitting components and driver chips.

[0051] The light-emitting components may include, for example, a mini-LED or a micro-LED type light-emitting component.

[0052] The number of conductive pads in each of the first conductive pad sets W1 is not limited here. The details can be determined depending on the product design.

[0053] In some embodiments, as in Fig. 13, the first electrically conductive pad sets W1 include first electrically conductive pads, and the first electrically conductive pads include bonding pads H.

[0054] In some embodiments, as in Fig. 7, the second electrically conductive pad sets W2 include second and third electrically conductive pads, and the second electrically conductive pads include bonding terminals BD2 and the third electrically conductive pads include bonding terminals BD1.

[0055] For example, with reference to Fig. 3, Fig. 4, Fig. 15 or Fig. 16, a first electrically conductive pad set W1 may comprise two electrically conductive pads; alternatively, a first electrically conductive pad set W1 may comprise four electrically conductive pads; alternatively, a first electrically conductive pad set W1 may comprise six electrically conductive pads.

[0056] It should be noted that the array substrate also includes an electrically conductive island mark located in the first electrically conductive layer, as shown in Fig. 3 or as in Fig. 4 to be used as an alignment mark in a subsequent process.

[0057] In an exemplary embodiment, the second electrically conductive layer 5 has a thickness of approximately 6000 Å, and the material of the second electrically conductive layer 5 comprises copper (Cu), which may have a stacked structure of, for example, MoNb / Cu / CuNi, wherein the lower MoNb layer serves to improve adhesion and the middle Cu layer serves to transmit electrical signals, and the upper CuNi layer may take into account both oxidation resistance and improved robustness.

[0058] In an exemplary embodiment, the second electrically conductive layer 5 can be used to arrange wires and cables that play a connecting role.

[0059] It should be noted that the embodiments of the present application are illustrated by the example in which the materials of both the first electrically conductive layer 3 and the second electrically conductive layer 5 comprise copper, so that in the drawings of the present application, Cu1 stands for the first electrically conductive layer 3 and Cu2 stands for the second electrically conductive layer 5.

[0060] It should also be noted that the plane in which the substrate base 1 is located means that the substrate base 1, although a three-dimensional structure, typically has a relatively small thickness relative to its length and width, and it can be assumed that the substrate base 1 is a structure tending toward a plane. Therefore, other structural features in the array substrate are described herein with reference to the plane in which the substrate base 1 is located. In practice, the substrate base 1 is not a plane.

[0061] In an exemplary embodiment, a first insulating layer 4 is provided between the first electrically conductive layer 3 and the second electrically conductive layer 5, wherein the first insulating layer 4 may comprise an inorganic sublayer and an organic sublayer.

[0062] With reference to the Fig. 1A and Fig. 1B, it is shown in the subject technology that when a bonding pad is provided in the second electrically conductive layer 5, and in the process of manufacturing an array substrate, an anomaly occurs on a component 7 mounted on the bonding pad and it needs to be removed, the removal process results in the formation of a recess in the bonding pad, the minimum thickness of the bonding pad is very small, and in the process of re-welding the component, the welding material and the remaining bonding pad material react at a high temperature and thus form an intermetallic compound that can very easily penetrate through the bonding pad, so that the risk of breakage of the bonding pad is very high.

[0063] In Fig. Figure 2B shows the film layer structure of the bonding area in the related technology, and how in combination with Fig. 2B and Fig. As shown in Figure 9, since the bonding electrodes in the bonding region must be electrically connected to the circuit board, if the overall thickness of the foil layer in the bonding region is greater, it is extremely easy for the foil layer to peel off during the bonding process. For example, a portion of the second electrically conductive layer 5 in the bonding region peels off, resulting in abnormal conduction of the array substrate to the circuit board.

[0064] In an exemplary embodiment, since the first electrically conductive layer 3 is usually provided with a signal line requiring high resistance, such as a ground line, a drive line, and the like, the thickness of the first electrically conductive layer 3 in a direction perpendicular to the plane in which the substrate base 1 is located is greater than or equal to a thickness of the second electrically conductive layer 5 in a direction perpendicular to the plane in which the substrate base 1 is located. By arranging the electrically conductive pad sets in the first electrically conductive layer 3, in a first aspect, in the case where the electrically conductive pad sets include an electrically conductive pad located in the display area, as in Fig. As shown in Figure 6, the probability that the interconnect layer M3 formed during the rework of the array substrate penetrates the first electrically conductive pads can be greatly reduced, the problem of poor conductivity of the first electrically conductive pads can be improved, and the yield of the array substrate rework can be increased. The interconnect layer M3 comprises the intermetallic compound formed at a high temperature from the welding material and the material of the first electrically conductive pads.In a second aspect, in the case where the electrically conductive pad sets comprise an electrically conductive pad located in the bonding region, due to the fact that a partial region of the first electrically conductive layer 3 is used as a second electrically conductive pad in the bonding region and a third electrically conductive pad in the bonding region, the total thickness of the film layer in the region where the second and third electrically conductive pads are located provided by the embodiments of the present application is reduced compared to the bonding terminals having two electrically conductive layers in the related technology.This improves the problem of local peeling of the film layer during the bonding process due to the larger thickness of the film layer and the larger number of film layers, reduces the difficulty of the bonding process, and improves the quality of the array substrate.

[0065] In some embodiments, as in Fig. 5, Fig. 13 and Fig. 14, the array substrate further comprises a first insulating layer 4 located between the first electrically conductive layer 3 and the second electrically conductive layer 5, wherein the first insulating layer has a plurality of openings K and through these openings K at least a portion of electrically conductive pads is exposed; wherein the orthographic projection of the partial area of ​​the electrically conductive pads on the substrate base 1 exposed by the openings K and the orthographic projection of the second electrically conductive layer 5 on the substrate base 1 do not overlap.

[0066] Show examples Fig. 5 and Fig. 13, the openings K expose a portion of each first electrically conductive pad in the first electrically conductive pad sets W1. It is understood that the openings K expose a connecting surface of the first electrically conductive pads for contacting components, wherein the orthographic projection of the connecting surface on the substrate base 1 and the orthographic projection of the second electrically conductive layer 5 on the substrate base 1 do not overlap.

[0067] An example is Fig. 14 illustrates that the openings K expose a portion of each electrically conductive pad in the second electrically conductive pad sets W2. For example, the openings K expose a portion of the second electrically conductive pads, or, alternatively, the openings K expose a portion of the third electrically conductive pads.

[0068] The sizes of the above-described openings K in the first insulating layer 4 are not limited here. Fig. 13, the openings of each electrically conductive pad in the first electrically conductive pad sets W are connected to each other to form a large-area opening. In Fig. 14, the openings of each electrically conductive pad in the second electrically conductive pad sets W2 are provided separately from each other.

[0069] In an exemplary embodiment, the openings in the second electrically conductive pad sets W2 have a depth in the range of 0.5 µm to 3 µm.

[0070] In some embodiments, the array substrate comprises a display region, and the electrically conductive pad sets comprise first electrically conductive pad sets, wherein the first electrically conductive pad sets are located in the display region.

[0071] In some embodiments, the array substrate includes a peripheral region surrounding the display region; the electrically conductive pad sets include second electrically conductive pad sets, the second electrically conductive pad sets being located in the peripheral region.

[0072] In some embodiments, the electrically conductive pad sets may simultaneously comprise the first electrically conductive pad sets W1 located in the display region and the second electrically conductive pad sets W2 located in the bonding region, wherein the electrically conductive pad sets comprise the first electrically conductive pad sets W1 and the second electrically conductive pad sets W2, wherein the first insulating layer 4 comprises a plurality of sublayers; In some embodiments, the comparison of Fig. 13 and Fig. 14 that the number of sublayers of the part of the first insulating layer 4 arranged between two adjacent first electrically conductive pad sets W1 is greater than or equal to the number of sublayers of the part of the first insulating layer 4 arranged between the individual electrically conductive pads in the second electrically conductive pad sets W2.

[0073] In some embodiments, the number of sublayers of the part of the first insulating layer 4 that is arranged between the individual first electrically conductive pads in the second electrically conductive pad sets W1 is greater than or equal to the number of sublayers of the part of the first insulating layer 4 that is arranged between the individual electrically conductive pads in the second electrically conductive pad sets W2.

[0074] In some embodiments, the number of sublayers of the part of the first insulating layer 4 that is arranged between two adjacent first electrically conductive pad sets W1 is equal to the number of sublayers of the part of the first insulating layer 4 that is arranged between the individual electrically conductive pads in the first electrically conductive pad sets W1.

[0075] By way of example, the number of sublayers of the part of the first insulating layer 4 that is arranged between two adjacent first electrically conductive pad sets W1 is four, and the number of sublayers of the part of the first insulating layer 4 that is arranged between the individual first electrically conductive pads in the first electrically conductive pad sets W1 is four, and the number of sublayers of the part of the first insulating layer 4 that is arranged between the individual electrically conductive pads in the second electrically conductive pad sets W2 is three.

[0076] By way of example, the sublayers of the part of the first insulating layer 4 that is arranged between two adjacent first electrically conductive pad sets are, in order, a first inorganic sublayer 41, a first organic sublayer 42, a second organic sublayer 43, and a second inorganic sublayer 44, but the sublayers of the part of the first insulating layer 4 that is arranged between the individual electrically conductive pads in the second electrically conductive pad sets W2 are, in order, a first inorganic sublayer 41, a second organic sublayer 43, and a second inorganic sublayer 44.

[0077] In exemplary embodiments, the material of the inorganic sublayers in the first insulating layer 4 may comprise silicon nitride, silicon oxide, or silicon nitride oxide, and the material of the organic sublayers in the first insulating layer 4 may comprise resin.

[0078] When comparing Fig. 13 and Fig. 14, it can be seen that the first organic sublayer 42 is provided near the positions where the first electrically conductive pad sets W1 are located in the display region, while the first organic sublayer 42 is not provided near the positions where the second electrically conductive pad sets W2 are located in the peripheral region, so that the first organic sublayer 42 fills an uneven region present in the display region during the manufacture of the array substrate, so that the surface of the substrate tends to become flat, and during the manufacture of the second organic sublayer 43, whose organic material has better leveling properties, is more likely to flow into the grooves present in the bonding region and thereby fills the gaps between the individual electrically conductive pads in the second electrically conductive pad sets W2 in the bonding region to facilitate a subsequent bonding process.to reduce the difficulty of the binding process and improve the yield of the binding process.

[0079] By way of example, in the case where the electrically conductive pad sets comprise first electrically conductive pad sets, a region between two adjacent first electrically conductive pads in the first electrically conductive pad sets has a gap in which an insulating layer is also provided, and specifically, a first inorganic sublayer 41, a first organic sublayer 42, a second organic sublayer 43 and a second inorganic sublayer 44 are provided successively in the gap.In this way, on the one hand, the leveling properties of the material of the second organic sublayer 43 in the array substrate can be further improved, a more sufficient flow of the material of the second organic sublayer 43 from the display region to the peripheral region can be promoted, and the difficulty of the manufacturing process can be reduced; on the other hand, a possible short circuit between any two adjacent electrically conductive pads in the same first electrically conductive pad set W1 can be avoided, and the manufacturing yield of the array substrate can be improved.

[0080] In some embodiments of the present application, in case the electrically conductive pad sets comprise first electrically conductive pad sets, the first electrically conductive pad sets W1 comprise first electrically conductive pads.

[0081] An orthographic projection of the portion of the first electrically conductive pads exposed by the openings K, such as bond pads H shown in Fig. 13, on the substrate base 1, and an orthographic projection of the second electrically conductive layer 5 on the substrate base 1 do not overlap.

[0082] For example, the first electrically conductive pads in the display area are intended for the attachment of components.

[0083] As in Fig. 13, the orthographic projection of the first insulating layer 4 on the substrate base 1 overlaps with the orthographic projection of the peripheral region of the first electrically conductive pads on the substrate base 1.

[0084] By way of example, the orthographic projection of the first organic sublayer 42 on the substrate base 1 and the orthographic projection of the first electrically conductive pad sets on the substrate base 1 do not overlap, the orthographic projection of the first inorganic sublayer 41, the second organic sublayer 43 and the second inorganic sublayer 44 on the substrate base 1 each partially overlap with the orthographic projection of the first electrically conductive pad sets on the substrate base 1, and the first inorganic sublayer 41, the second organic sublayer 43 and the second inorganic sublayer 44 cover an edge region of each first electrically conductive pad, such as bond pads H, in the first electrically conductive pad sets. The first insulating layer 4 between two adjacent first electrically conductive pads in the first electrically conductive pad sets W1 is in Fig. 13 is not shown, and its foil layer structure is similar to the foil layer structure of the edge region of the first electrically conductive pad sets.

[0085] In related technology, the second electrically conductive layer 5 comprises a bond pad, as in Fig. 2A. During the fabrication of the array substrate, a nickel-gold layer is deposited on the surface of the bond pad facing away from the substrate base 1 to improve rework yield. Since the second insulating layer 6 covering the edge of the bond pad is relatively thin in this case, metal ions can easily penetrate through the second insulating layer 6 and deposit at positions between the edge of the bond pad and the second insulating layer 6. In further processes, the peeling off of a portion of the nickel-gold layer deposited between the edge of the bond pad and the second insulating layer 6 could cause two adjacent bond pads to be connected to each other, resulting in a short-circuit problem.

[0086] In one embodiment of the present application, the first insulating layer covers the first electrically conductive layer 3 by providing the first electrically conductive pads, e.g., the bond pads H, in the first conductive layer 3. The number of sublayers of the second insulating layer is smaller compared to the formation of the bond pads in the second electrically conductive layer 5. Since the number of sublayers of the first insulating layer 4 is greater than the number of sublayers of the second insulating layer 6, the thickness of the insulating layer covering the edges of the first electrically conductive pads is greater. In this way, the edges of the first electrically conductive pads are provided with multiple protective layers.When forming a protective layer M4 (made of nickel and / or gold) of the first electrically conductive pads, metal ions are less likely to penetrate through the first inorganic sublayer 41, the second organic sublayer 43 and the second inorganic sublayer 44 to the first electrically conductive pads, thereby preventing the formation of nickel-gold in the edge region of the first electrically conductive pads and thus a short circuit between adjacent first electrically conductive pads.

[0087] In some embodiments of the present application, in case the electrically conductive pad sets comprise second electrically conductive pad sets, the second electrically conductive pad sets W2 comprise second electrically conductive pads and third electrically conductive pads; as in Fig. 7 and Fig. 11, the orthographic projection of other regions of the second electrically conductive pads on the substrate base 1, with the exception of the regions of the second electrically conductive pads exposed by the openings K, such as the bonding electrodes BD2, partially overlaps with the orthographic projection of the second insulating layer 5 on the substrate base 1; wherein the openings of the first insulating layer 4 in Fig. 7 and Fig. 11 are not shown.

[0088] For example, as in Fig. 7, the second electrically conductive layer 5 comprises a plurality of connecting lines P1 and P2 arranged in a peripheral region, wherein the second electrically conductive pads, e.g., bonding electrodes BD2, are electrically connected to the connecting lines P1 and P2, and wherein the orthographic projection of the second electrically conductive pads, e.g., the bonding electrodes BD2, on the substrate base 1 partially overlaps with the orthographic projection of the connecting lines P1 on the substrate base 1.

[0089] The orthographic projection of the third electrically conductive pads, such as the bonding electrodes BD1, as in Fig. 7, on the substrate base 1, and the orthographic projection of the second electrically conductive layer 5 on the substrate base do not overlap.

[0090] For example, the second electrically conductive pads and the third electrically conductive pads in the bonding area are provided for bonding to an external circuit board.

[0091] In one embodiment of the present application, by arranging the electrically conductive pad sets to comprise second electrically conductive pad sets and the second electrically conductive pad sets to comprise second electrically conductive pads and third electrically conductive pads, the total thickness of the film layer in the area in which the second and third electrically conductive pads are located, which are provided by the embodiments of the present application, is reduced compared to the ones as in Fig. 2B, comprising a portion of the first electrically conductive layer and a portion of the second electrically conductive layer in the related technology. This improves the problem of local peeling of the film layer during the bonding process due to the greater thickness of the film layer and the larger number of film layers, reduces the difficulty of the bonding process, and improves the quality of the array substrate.

[0092] In some embodiments of the present application, as in Fig. 7, the array substrate includes a shield line CS, and the peripheral region (including B1, B2, F and Z) includes bonding regions (including B1 and B2) arranged on one side of the display region AA; A main structure of the shielding line CS is located in the regions F and Z in the peripheral region except for the bonding regions, and two ends of the shielding line CS extend into the bonding regions B1 and B2; the two ends of the shielding line CS are each electrically connected to the second electrically conductive pads via a connecting line P1 arranged in the bonding regions.

[0093] In some embodiments of the present application, as in Fig. 7, the shielding line CS covers at least a partial area of ​​the individual connecting lines P1 and P2, and the shielding line CS is in direct contact with the individual connecting lines P1 and P2.

[0094] In an exemplary embodiment, covering at least a partial area of ​​the individual connecting lines P1 and P2 by the shielding line CS includes the following cases, but is not limited to the shielding line CS covering a partial area of ​​the individual connecting lines, or the shielding line CS covering all areas of the individual connecting lines.

[0095] It should be noted that in the case where the shielding line CS covers all areas of the individual connecting lines, the shielding line CS is in direct contact with a portion of the connecting lines and also in contact with a portion of the second insulating layer 6 facing away from the surface of the connecting lines. Details regarding the position of the shielding line CS with respect to the second insulating layer 6 are described below.

[0096] In an exemplary embodiment, the orthographic projection of the shielding line CS on the substrate base 1 is shown in the form of a non-closed ring.

[0097] In an exemplary embodiment, the material of the shielding line CS comprises an electrically conductive adhesive, such as silver adhesive.

[0098] Here, too, the thickness of the silver adhesive can be, for example, around 200 µm, and the size of the silver adhesive in the direction from the display area to the peripheral area can be around 500 µm. The term "around" refers to a size error caused by variations in the manufacturing process, which is within a tolerable range for the product.

[0099] In practice, the shielding cable CS can also be provided with a protective layer or cover plate to prevent damage to the shielding cable CS.

[0100] The material of the protective layer and the cover plate can be an inorganic material, such as glass, silicon nitride, silicon oxide, or silicon nitride; of course, the material of the protective layer and the cover plate can also be an organic material, such as resin.

[0101] In some embodiments of the present application, as in Fig. 7, the first electrically conductive layer 3 includes a first electrically conductive portion, the first electrically conductive portion including a ground line GND located in the display area AA; and the connecting lines P1 and P2 are electrically connected to the ground line GND.

[0102] For example, the first electrically conductive section may also be a driver line VLED, a power supply line PWR, as in Fig. 15; alternatively, the first electrically conductive portion may also comprise a drive line VR and VGB, a data line DATA, a longitudinal power supply line VCC-V, as shown in Fig. 16. The power supply line from Fig. 16 further comprises a transverse power supply line VCC-H located in the second electrically conductive layer 5, wherein the longitudinal power supply line VCC-V is electrically connected via a through-hole VIA to the transverse power supply line VCC-H, which are electrically connected to the first electrically conductive pads.

[0103] Specifically, Fig. 15, the first conductive portion further comprises a first wire 31 and a second wire 32, and the second conductive layer further comprises a cable 51, wherein the first electrically conductive pad sets W1 for mounting a driver chip are first electrically connected to the first electrically conductive pad sets W1 for mounting light-emitting components via a connecting cable, such as the connecting cable 51, located in the second electrically conductive layer 5, and then electrically connected to the driver line VLED via the connecting cable 51;

[0104] In Fig. 16, the first electrically conductive portion further comprises a first wire 31 and a second wire 32, and the second electrically conductive layer further comprises a cable 51, wherein the first electrically conductive pad sets W1 for mounting a driver chip are first electrically connected to the first electrically conductive pad sets W1 for mounting light-emitting components and then electrically connected to the driver line VR or VGB via the connecting cable 51, wherein the Fig. 16 comprises two types of drive lines, wherein a light-emitting component with red luminous color is connected to a drive line VR, while light-emitting components with green and blue luminous color jointly use a drive line VGB.

[0105] In an exemplary embodiment, the first electrically conductive pads, as shown in Fig. 15 and Fig. 16, a distance in the direction parallel to the substrate base 1 from the second electrically conductive layer (e.g., the cable 51) closest to these first electrically conductive pads. In products with a protective layer (nickel-gold) on the first electrically conductive pads, the distance between the first electrically conductive pads and the second electrically conductive layer closest to them in the direction parallel to the substrate base 1 is as large as possible within the limits specified by the design and manufacturing process. This is to prevent metal ions from penetrating into the vicinity of the second electrically conductive layer when a protective layer is formed on the first electrically conductive pads, which may impair the electrical properties of the second electrically conductive layer.

[0106] In an exemplary embodiment of the present application, the connecting lines include a connecting line P1 located in the bonding region and a connecting line P2 located outside the bonding region. The connecting line P2, which is located in the region Z of the peripheral region apart from the bonding region, is connected to the bonding region via a through-hole (in Fig. 7 not shown) is directly electrically connected to the ground line GND; the connecting line P1, which is located in the bonding area, is electrically connected to the ground line GND via the shielding line CS.

[0107] In Fig. 7, the ground line GND is drawn along the vertical direction as an example, and in this case, to facilitate connection, the connection line P2 is provided on the upper side of the display area AA and the connection line P2 is provided on the lower side of the display area AA. In practice, the connection line P2 may be provided on the left side of the display area AA or, alternatively, on the right side of the display area. Regardless of the direction in which the ground line is provided, the connection line P2 is provided at one end of the ground line GND and is electrically connected to the ground line GND via a through-hole, the shield line CS covers a partial portion of the connection line P2, the connection line P1 is provided near the other end of the ground line GND, and the connection line P1 is electrically connected to the ground line GND via the shield line CS.

[0108] In an exemplary embodiment of the present application, the connecting lines P1 and P2 are both electrically connected to the shield line CS, and the individual connecting lines P1 and P2 are electrically connected directly or indirectly to the ground line GND, so that the shield line CS is electrically connected to the ground line GND. In this way, on the one hand, the arrangement of the shield line CS can improve the antistatic ability of the array substrate; on the other hand, the electrical connection of the shield line CS to the ground line GND can reduce the resistance of the ground line GND, and the signal transmission capability of the lines can be improved.

[0109] In related technology, a portion of the first electrically conductive layer or the second electrically conductive layer is used as a shielding line. However, in an exemplary embodiment of the present application, the shielding line CS is not provided in the first electrically conductive layer 3 and the second electrically conductive layer 5, and the material of the shielding line CS is an electrically conductive adhesive rather than a metallic material. In this way, the influence of the arrangement of the first electrically conductive layer or the second conductive layer in a peripheral region on the cutting process is avoided.In addition, for the shielding line CS whose material is an electrically conductive adhesive, since the shielding line CS is manufactured after the cutting process, the cutting margin to be reserved is also smaller, and the shielding line CS exerts less influence on the cutting process, so that the size of the peripheral area of ​​the array substrate can be greatly reduced to reserve more design space for the display area, which is conducive to the manufacture of a narrow-bezel display product.

[0110] In some embodiments of the present application, as in Fig. As shown in Figure 7, the peripheral region includes a fan-out region F, the fan-out region F being disposed between the bonding region (including B1 and B2) and the display region AA, and the fan-out region F including a fan-out cable FL; and third electrically conductive pads, such as BD1, are electrically connected to the first electrically conductive portion via the fan-out cable FL.

[0111] In an exemplary embodiment, the first electrically conductive portion comprises a ground line GND, and third electrically conductive pads, such as BD1, are electrically connected to the ground line GND via the fan-out cable FL.

[0112] In some embodiments, the first electrically conductive portion may also include a driver line VLED and a power supply line PWR, as shown in Fig. 15. A portion of the third electrically conductive pads, such as BD1, is electrically connected to the drive line VLED via the fan-out cable FL, while another portion of the third electrically conductive pads, such as BD1, is electrically connected to the power supply line PWR via the fan-out cable FL.

[0113] Alternatively, the first electrically conductive section may also comprise a drive line VR and VGB, a data line DATA, a longitudinal power supply line VCC-V, as shown in Fig. 16. A part of the third electrically conductive pads, such as BD1, is electrically connected to the drive line VR and VGB via the fan-out cable FL, while another part of the third electrically conductive pads, such as BD1, is electrically connected to the data line DATA via the fan-out cable FL, and yet another part of the third electrically conductive pads, such as BD1, is electrically connected to the longitudinal power supply line VCC-V via the fan-out cable FL.

[0114] In some embodiments, the first electrically conductive portion may also include some dummy cables. A portion of the third electrically conductive pads, such as BD1, is electrically connected to the dummy cables via the fan-out cable FL.

[0115] It should be noted that the phrases "a portion of the third electrically conductive pads, another portion of the third electrically conductive pads, and yet another portion of the third electrically conductive pads" in the embodiments of the present application do not mean that only these three portions of the third electrically conductive pads are included. Rather, in some embodiments, a fourth portion of the third electrically conductive pads may also be included, depending on the actual situation. Furthermore, the meaning of the relevant phrases elsewhere in the present application is similar to this and will not be repeated.

[0116] In an exemplary embodiment, the fan-out cable FL may be located in the first electrically conductive layer 3; alternatively, the fan-out cable FL may be located in the second electrically conductive layer 5; alternatively, a portion of the fan-out cable FL may be located in the first electrically conductive layer 3 and another portion of the fan-out cable FL may be located in the second electrically conductive layer 5. The details may be determined depending on the actual product requirements and are not limited here.

[0117] In some embodiments of the present application, as in Fig. 7 and Fig. 8, the binding region comprises a first binding sub-region B1 and a second binding sub-region B2, wherein the first binding sub-region B1 is located on the side of the second binding sub-region B2 facing away from the display region AA; wherein the individual second electrically conductive pads, e.g. BD2, are located in the first binding sub-region B1 and the individual third electrically conductive pads, e.g. BD1, are located in the second binding sub-region B2, wherein both the second electrically conductive pads and the third electrically conductive pads comprise binding clips.

[0118] In an exemplary embodiment, the individual second electrically conductive pads are arranged one after the other in the same direction, e.g., the OA direction, and the individual third electrically conductive pads are arranged one after the other in the same direction, e.g., the OA direction.

[0119] In practice, the arrangement direction of the second electrically conductive pads may also be different from the OA direction, and the arrangement direction of the third electrically conductive pads may also be different from the OA direction, which can be determined depending on the actual situation. Furthermore, in the present application, it is not defined whether the arrangement direction of the second electrically conductive pads and the arrangement direction of the third electrically conductive pads are identical.

[0120] In an exemplary embodiment, the individual second electrically conductive pads and the individual third electrically conductive pads are arranged in two rows in the first bonding portion B1 and the second bonding portion B2, respectively, such that every third electrically conductive pad in the second bonding portion B2 is electrically connected to the fan-out cable FL and the fan-out cable FL is electrically connected to one end of the ground line GND;and that every second electrically conductive pad in the first bonding portion B1 is sequentially electrically connected to the other end of the ground line GND via the connecting line P1, the shielding line CS, whereby the number of fan-out wires FL can be reduced and the design space in the fan-out region F can be increased, while at the same time reducing the size of the fan-out region F, whereby the size of the peripheral area can be largely reduced, which is conducive to manufacturing a narrow-frame product.;

[0121] In some embodiments, a portion of the individual third electrically conductive pads may be arranged in a left region of the individual second electrically conductive pads, and another portion of the individual third electrically conductive pads may be arranged in a right region of the individual second electrically conductive pads to further reduce the size of the peripheral region.

[0122] In some embodiments of the present application, as in Fig. 10 and Fig. As shown in Figure 11, the individual second electrically conductive pads are arranged one after the other in the same direction, e.g., the OA direction, and the individual third electrically conductive pads are arranged one after the other in the same direction, e.g., the OA direction. In the arrangement direction OA of the second electrically conductive pads, there is a first gap between each two adjacent second electrically conductive pads, e.g., between BD2, and in the arrangement direction OA of the third electrically conductive pads, there is a second gap between each two adjacent third conductive pads, e.g., between BD1.The numbers of sublayers of the first insulating layer 4 filled in the first gap and in the second gap are equal, and the number of sublayers of the first insulating layer 4 filled in the second gap is greater than the number of sublayers of the first insulating layer located in a part of the second electrically conductive pad sets W2 facing away from the surface of the substrate base 1.

[0123] In an exemplary embodiment, the thickness of each sublayer in the first insulating layer 4 filled in the first gap, in a direction perpendicular to the plane in which the substrate base 1 is located, is approximately equal to the thickness of each sublayer in the first insulating layer 4 filled in the second gap, in a direction perpendicular to the plane in which the substrate base 1 is located. "Approximately equal" refers to the thicknesses varying within an allowable error range under the influence of variations in the manufacturing process. The meaning of the plane in which the substrate base is located is similar to that described above and will not be repeated.

[0124] In an exemplary embodiment, the second electrically conductive pad sets W2 comprise second electrically conductive pads and third electrically conductive pads, wherein the number of sublayers of the first insulating layer 4 that lie in a part of the second electrically conductive pads facing away from the surface of the substrate base 1 is equal to the number of sublayers of the first insulating layer 4 that lie in a part of the third electrically conductive pads facing away from the surface of the substrate base 1.

[0125] In an exemplary embodiment, the thickness of the sublayers of the first insulating layer 4, which lie in a part of the second electrically conductive pads facing away from the surface of the substrate base 1, is approximately equal to the thickness of the sublayers of the first insulating layer 4, which lie in a part of the third electrically conductive pads facing away from the surface of the substrate base 1, in a direction perpendicular to the plane in which the substrate base 1 is located.

[0126] In one embodiment of the present application, by arranging multiple or thicker sublayers of the first insulating layer 4 in the first gap and the second gap, on the one hand, it is achieved that the first insulating layer 4 is able to fill the first gap and the second gap, thereby avoiding the influence of an existing gap on the alignment process in the bonding process, improving the yield of the bonding process and reducing the difficulty of the bonding process;on the other hand, fewer or thinner sublayers of the first insulating layer 4 are arranged in a part of the second electrically conductive pad sets W2 facing away from the surface of the substrate base 1, so that the thickness of the foil layer on the second electrically conductive pad sets W2 in the bonding area is relatively thin and the problem of local detachment or poor bonding of the foil layer in the bonding area during bonding to a printed circuit board or a flexible printed circuit board is avoided.;

[0127] In some embodiments of the present application, as in Fig. 13 and Fig. 14, the first insulating layer 4 comprises a first inorganic sublayer 41, a first organic sublayer 42, a second organic sublayer 43 and a second inorganic sublayer 44 arranged one after the other, the first inorganic sublayer 41 and the first electrically conductive layer being in direct contact with each other; where Fig. 14 a sectional view in direction B1B2 in Fig. 10 or Fig. 11 shows, where in Fig. 14 the orthographic projection of the first organic sublayer 42 on the substrate base 1 does not overlap with the part of the substrate base 1 arranged in the bonding region.

[0128] In an exemplary embodiment, as in Fig. 13, the orthographic projection of the first insulating layer 42 on the substrate base 1 overlaps with the part of the substrate base 1 arranged in the bonding region.

[0129] With reference to Fig. 13, for example, a distance h1 in the thickness direction of the substrate base 1 between the surface of the first organic sublayer 42 facing away from the substrate base 1 and the substrate base 1 is less than or equal to a distance h2 in the thickness direction of the substrate base 1 between the surface of the first electrically conductive pads, e.g. bond pads H, facing away from the substrate base 1 and the substrate base 1.

[0130] It is understood that in an actual product, no first organic sublayer 42 is provided in the part of the array substrate located in the bonding region, while the first organic sublayer 42 is provided in the part of the array substrate located in the display region.

[0131] In one embodiment of the present application, in the display area, as shown in Fig. 13, the first organic sublayer 42 is provided, while in the bonding area, as shown in Fig. 14, no first organic sublayer 42 is provided. During the fabrication of the array substrate, since the organic material generally has leveling properties, the surface of the substrate tends to become flat by first filling the grooves present in the display region with the first organic sublayer 42. During the fabrication of the second organic sublayer 43, the organic material of the second organic sublayer 43 has better leveling properties and flows more easily into the bonding region to fill the first gap L1 and the second gap L2 present in the bonding region. Note that the filling described above is not necessarily complete.

[0132] In some embodiments of the present application, as in Fig. 13 and Fig. 14, the orthographic projections of the first organic sublayer 42 and the second inorganic sublayer 44 on the substrate base and the orthographic projection of the second electrically conductive pads, e.g., BD2, on the substrate base 1 do not overlap; and the orthographic projections of the first organic sublayer 42 and the second inorganic sublayer 44 on the substrate base 1 and the orthographic projection of the third electrically conductive pads, e.g., BD1, on the substrate base 1 do not overlap.

[0133] In one embodiment of the present application, a first organic sublayer 42 and a second inorganic sublayer 44 are provided neither on the surface of the second electrically conductive pads facing away from the substrate base 1 nor on the surface of the third electrically conductive pads facing away from the substrate base 1, so that the thickness of the film layer at the positions of the second electrically conductive pads and the third electrically conductive pads will be reduced, the bonding of the second electrically conductive pads and the third electrically conductive pads to the output terminals in a printed circuit board will be facilitated and the difficulty of the bonding process will be reduced, while at the same time peeling or partial peeling of the film layer at the positions of the second electrically conductive pads and the third electrically conductive pads during bonding will be avoided and thus the problem of poor bonding will be improved.

[0134] In some embodiments of the present application, as in Fig. 14, at least the first inorganic sublayer 41, the second organic sublayer 43 and the second inorganic sublayer 44 are sequentially arranged in the first gap L1, and at least the first inorganic sublayer 41, the second organic sublayer 43 and the second inorganic sublayer 44 are sequentially arranged in the second gap L2.

[0135] In an exemplary embodiment, a minimum distance h3 in the thickness direction of the substrate base 1 between the surface of the second inorganic sublayer 44 facing away from the substrate base 1 and the substrate base 1 is smaller than the distance h4 in the thickness direction of the substrate base 1 between the surface of the second electrically conductive pads (or the third electrically conductive pads) facing away from the substrate base 1 and the substrate base 1.

[0136] In some embodiments of the present application, as in Fig. 13 and Fig. 14, the array substrate further comprises a second insulating layer 6, wherein the second insulating layer 6 is located on a side of the second electrically conductive layer 5 facing away from the substrate base 1; wherein the second insulating layer 6 fills the first gap L1 and the second gap L2 and the orthographic projection of the second insulating layer 6 on the substrate base 1 does not overlap with the orthographic projection of at least a part of the second electrically conductive pads on the substrate base.

[0137] The second insulating layer 6 comprises a third inorganic sublayer 61 and a third organic sublayer 62, wherein the third organic sublayer 62 lies on a side of the third inorganic sublayer 61 facing away from the substrate base 1; In the first gap L1 and the second gap L2, a third inorganic sublayer 61 and a third organic sublayer 62 are also provided one after the other, wherein the parts of the third inorganic sublayer 61 located in the gaps L1 and L2 are in direct contact with the parts of the second inorganic sublayer 44 located in the gaps L1 and L2.

[0138] In some embodiments of the present application, the orthographic projection of the second insulating layer 4 on the substrate base 1 overlaps with the orthographic projection of a partial region of the second electrically conductive pads, e.g., a partial region of BD2, on the substrate base 1, and the orthographic projection of the second insulating layer 4 on the substrate base 1 does not overlap with the orthographic projection of another partial region of the second electrically conductive pads on the substrate base 1; the orthographic projection of the second insulating layer 4 on the substrate base 1 does not overlap with the orthographic projection of a surface of the third electrically conductive pads, e.g., BD1, on the substrate base facing away from the substrate base 1.

[0139] In an exemplary embodiment, as in Fig. 11 and Fig. 12, the second insulating layer 4 may cover a portion of the area on the second electrically conductive pads within the dashed box in Fig. 12, and expose the remaining portion of the second electrically conductive pads to cover the shield line CS. In this way, the exposed portion on the second electrically conductive pads can be prevented from being oxidized or corroded, and the second electrically conductive pads can thus be protected.

[0140] In an exemplary embodiment, in order to reduce the difficulty of the manufacturing process, in all dashed boxes in Fig. 12, a second insulating layer may be provided, ie the second insulating layer 4 may cover a partial area of ​​each second electrically conductive pad and may also extend to the area between two adjacent second electrically conductive pads.

[0141] In an exemplary embodiment, as in Fig. 10, no second insulating layer 6 is provided in the area where the third electrically conductive pads, such as BD1, are located.

[0142] In some embodiments of the present application, a distance h5 in the thickness direction of the substrate base 1 between the surface of the part of the third organic sublayer 62 facing away from the substrate base 1, which is located between the gaps L1 and L2, and the substrate base 1 is less than or equal to a distance h6 in the thickness direction of the substrate base 1 between the surface of the part of the second organic sublayer 43 facing away from the substrate base 1, which lies on the second electrically conductive pad sets (including the second electrically conductive pads and the third electrically conductive pads), and the substrate base 1.

[0143] In Fig. 14, it is drawn as an example that the distance h5 in the thickness direction of the substrate base 1 between the surface of the part of the third organic sublayer 62 facing away from the substrate base 1, which is located between the gaps L1 and L2, and the substrate base 1 is equal to the distance h6 in the thickness direction of the substrate base 1 between the surface of the part of the second organic sublayer 43 facing away from the substrate base 1, which lies on the second electrically conductive pad sets (including the second electrically conductive pads and the third electrically conductive pads), and the substrate base 1.

[0144] In one embodiment of the present application, the first gap L1 and the second gap L2 are filled as much as possible by the first insulating layer 4 and the second insulating layer 6, but not so much that the third organic sublayer 62 in the gaps protrudes beyond the part of the second organic sublayer 43 lying on the second electrically conductive pad sets, thereby improving the accuracy of the alignment process in the bonding process and also avoiding the poor bonding of the second electrically conductive pad sets to a circuit board caused by an excessively high insulating layer in the gaps.

[0145] In some embodiments of the present application, as in Fig. 12, the second insulating layer 6 covers a portion of the connecting line P2, and the shielding line CS covers a portion of the connecting line P2.

[0146] It is not defined whether the shielding line CS covering the connecting line and the second insulating layer 6 covering the connecting line overlap.

[0147] In an exemplary embodiment, there is a gap between a part of the outer contour of the orthographic projection of the second insulating layer 6 on the substrate base 1 and a part of the outer contour of the orthographic projection of the shielding line CS on the substrate base 1, so that a part of the connecting line P2 is exposed. With reference to Fig. 12 shows that at this time, the sum of the width d3 of the shielding line CS and the width d4 of the part of the second insulating layer 6 covering the connecting line P2 is smaller than the length d5 ​​of the connecting line P2.

[0148] In an exemplary embodiment, a portion of the orthographic projection of the second insulating layer 6 on the substrate base 1 overlaps with a portion of the orthographic projection of the shielding line CS on the substrate base 1. In this way, the second insulating layer 6 covers a portion of the connecting line and is in direct contact with this portion, and the shielding line CS covers another portion of the connecting line and is in direct contact with this portion. Furthermore, the shielding line CS extends to a portion of the second insulating layer 6 facing away from the surface of the connecting line and is in direct contact with this portion of the second insulating layer 6. At this point, the sum of the width d3 of the shielding line CS and the width d4 of the portion of the second insulating layer 6 covering the connecting line P2 is greater than the length d5 ​​of the connecting line P2.

[0149] If a part of the outer contour of the orthographic projection of the second insulating layer 6 on the substrate base 1 is directly tangent to a part of the outer contour of the orthographic projection of the shielding line CS on the substrate base 1, the sum of the width d3 of the shielding line CS and the width d4 of the part of the second insulating layer 6 covering the connecting line P2 is equal to the length d5 ​​of the connecting line P2.

[0150] In an exemplary embodiment, a part of the outer contour of the orthographic projection of the second insulating layer 6 on the substrate base 1 approximately touches a part of the outer contour of the orthographic projection of the shielding line CS on the substrate base 1. In this way, the exposed portion on the second electrically conductive pads can be prevented from being oxidized or corroded, and the second electrically conductive pads can thus be protected.

[0151] Approximately tangent means that a part of the outer contour of the orthographic projection of the second insulating layer 6 on the substrate base 1 and a part of the outer contour of the orthographic projection of the shielding line CS on the substrate base 1 fluctuate within a permissible error range.

[0152] In some embodiments of the present application, as in Fig. 12, the size d2 of the connection line P2 located in a region of the peripheral region other than the bonding region in the OA direction perpendicular to the reference plane is less than or equal to the size d6 of the ground line GND in the OA direction perpendicular to the reference plane, and the size d2 of the connection line P1 electrically connected to the second electrically conductive pads in the OA direction perpendicular to the reference plane is less than or equal to the size d1 of the second electrically conductive pads in the OA direction perpendicular to the reference plane, and the extension direction OB of the connection line and the thickness direction OC of the substrate base 1 are each parallel to the reference plane.

[0153] In this way, it is possible to avoid the connection line covering an area on one side of the second electrically conductive pads (or covering the area on one side of the ground line), which causes rising and makes the connection line cracked or broken in some areas, thereby improving the quality of the array substrate.

[0154] In some embodiments of the present application, as in Fig. 5 and Fig. 6, the array substrate further comprises a protective layer M4, wherein the protective layer M4 covers a portion of the first electrically conductive pads, such as bond pads H, exposed at the openings K. The material of the protective layer M4 comprises an electrically conductive material.

[0155] The number of bond pads contained in a first electrically conductive pad set W1 is not defined here and can be, for example, 2, 3, 4, 6 or 8, depending on the practical circumstances.

[0156] For example, the material of the protective layer M4 comprises nickel and / or gold.

[0157] In one embodiment of the present application, in the welding process, the welding material primarily reacts with the material of the protective layer M4 to generate a metallic interlayer connection to form a connecting layer M3 that plays a connecting role, and the protective layer M4 plays a protective role for the first electrically conductive pads, wherein the connecting layer M3 comprises the metallic interlayer connection.

[0158] The array substrate provided by embodiments of the present application also includes a dummy bonding electrode (Dummy BD1) as well as some dummy cables and, of course, other structures and components such as the black matrix layer 8, the buffer layer 2 and the like in Fig. 2A. Only structures and components related to the aspect of the invention are described here, and other structures and components included in the array substrate may be referred to the related technology.

[0159] Embodiments of the present application provide a display device comprising light-emitting components and an array substrate as described above, wherein the light-emitting components are electrically connected to first electrically conductive pad sets.

[0160] In an exemplary embodiment, the display device may also include a driver chip that provides a drive signal to the display device.

[0161] For example, the light-emitting components may comprise a mini-LED or a micro-LED-type light-emitting component. The mini-LED has a size of approximately 100-300 µm, and the micro-LED has a size of 100 µm or less.

[0162] In an exemplary embodiment, the light-emitting components have cross-sectional dimensions (parameters related to length, width, diagonal, or diameter) between about 100 µm and about 300 µm; and the thickness of the light-emitting components is, for example, 100 µm. The term "about" includes, but is not limited to, the following: The sizes of the components vary due to variations in the manufacturing process. It should be noted that the size variations are within an acceptable error range.

[0163] In some embodiments of the present application, the display device further comprises a circuit board electrically connected to second electrically conductive pad sets.

[0164] This circuit board may comprise a flexible circuit board.

[0165] The number of circuit boards included in the display device is not defined here and can be determined according to the actual situation.

[0166] The display device may be used as a backlight device, or alternatively, the display device may be used directly for display, without limitation thereto.

[0167] In one embodiment of the present application, since the display device comprises the above-mentioned array substrate and the first electrically conductive layer 3 of the array substrate is usually provided with a signal line requiring high resistance, such as a ground line, a drive line, and the like, the thickness of the first electrically conductive layer 3 in a direction perpendicular to the plane in which the substrate base 1 is located is greater than or equal to a thickness of the second electrically conductive layer 5 in a direction perpendicular to the plane in which the substrate base 1 is located. By arranging the electrically conductive pad sets in the first electrically conductive layer 3, in a first aspect, as in Fig.As shown in Figure 6, the probability that the interconnect layer M3 formed during the rework of the array substrate penetrates the first electrically conductive pads can be greatly reduced, the problem of poor conductivity of the first electrically conductive pads can be improved, and the yield of the array substrate rework can be increased. The interconnect layer M3 comprises the intermetallic compound formed at high temperature from the welding material and the material of the first electrically conductive pads.In a second aspect, due to the fact that a portion of the first electrically conductive layer 3 is used as a second electrically conductive pad in the bonding region and a third electrically conductive pad in the bonding region, the overall thickness of the film layer in the region where the second and third electrically conductive pads are located provided by the embodiments of the present application is reduced compared to the bonding terminals with two electrically conductive layers in the related technology. This improves the problem of local peeling of the film layer during the bonding process due to the greater thickness of the film layer and the larger number of film layers, reduces the difficulty of the bonding process, and improves the quality of the display device fabricated from the array substrate.

[0168] In the present application, the use of the display device is not specifically limited, which may be any product or component having a display function, such as a television, a laptop, a tablet computer, a portable display device, a mobile phone, an on-board display, a navigation device, an e-book, a digital photo frame, a light box for advertising purposes.

[0169] Embodiments of the present application provide a method for manufacturing an array substrate, which is used for manufacturing an array substrate as described above, the method comprising: S01, providing a substrate support; S02, forming a first electrically conductive layer comprising a plurality of electrically conductive pad sets comprising at least one electrically conductive pad; S03, forming a first inorganic sub-film, a structured first organic sub-layer, a structured second organic sub-layer and a second inorganic sub-film successively on the first electrically conductive layer; S04, forming a second electrically conductive layer; S05, structuring the first inorganic sub-film and the second inorganic sub-film to obtain the first inorganic sub-layer and the second inorganic sub-layer; wherein the first insulating layer comprises a first inorganic sub-layer, a first organic sub-layer, a second organic sub-layer, and a second inorganic sub-layer, and wherein the first insulating layer has a plurality of openings exposing at least a portion of the electrically conductive pads.

[0170] It should be noted that the term “film” in the embodiments of the present application refers to a full-surface film layer that is formed before structuring.

[0171] In one embodiment of the present application, during the formation of the first insulating layer, a patterned first organic sublayer and a patterned second organic sublayer are first formed such that the second inorganic film covers the first electrically conductive layer, and after the formation of the second electrically conductive layer, the second inorganic film is patterned such that the second inorganic film can protect the exposed portion in the first electrically conductive layer (e.g., the exposed portion in the electrically conductive pads) during the formation of the second electrically conductive layer, thereby preventing corrosion of the exposed portion in the first electrically conductive layer and improving the reliability of the array substrate.

[0172] The manufacturing methods of the other structures in the array substrate provided by the embodiments of the present application can be determined in conjunction with the manufacturing methods in the related technology and will not be repeated here.

[0173] Only specific embodiments of the present application are described above, but the scope of the present application is not limited thereto. Modifications or substitutions within the technical scope disclosed in the present application are obvious to any person skilled in the art and also fall within the scope of the present application. Therefore, the scope of the present application is determined by the scope of the patent claims.

Claims

[1] Array substrate comprising: a substrate base; a first electrically conductive layer disposed on one side of the substrate base and comprising a plurality of electrically conductive pad sets, the electrically conductive pad sets comprising at least one electrically conductive pad; a second electrically conductive layer arranged on a side of the first electrically conductive layer facing away from the substrate base, wherein the orthographic projection of at least a partial region of each electrically conductive pad in the electrically conductive pad sets on the substrate base does not overlap with the orthographic projection of the second electrically conductive layer on the substrate base; wherein a thickness of the first electrically conductive layer in a direction perpendicular to the plane in which the substrate base is located is greater than or equal to a thickness of the second electrically conductive layer in a direction perpendicular to the plane in which the substrate base is located. [2] The array substrate of claim 1, wherein the array substrate further comprises a first insulating layer disposed between the first electrically conductive layer and the second electrically conductive layer, wherein the first insulating layer has a plurality of openings, and at least a portion of electrically conductive pads is exposed through these openings; wherein the orthographic projection of the portion of the electrically conductive pads on the substrate base exposed by the openings and the orthographic projection of the second electrically conductive layer on the substrate base do not overlap. [3] The array substrate of claim 2, wherein the array substrate comprises a display region, wherein the first electrically conductive pad sets comprise first electrically conductive pad sets located in the display region. [4] The array substrate of claim 3, wherein the first electrically conductive pad sets comprise first electrically conductive pads, wherein the orthographic projection of at least the portion of the first electrically conductive pads exposed through the openings on the substrate base does not overlap with the orthographic projection of the second electrically conductive layer on the substrate base. [5] The array substrate according to claim 2, wherein the array substrate comprises a display region and a peripheral region surrounding the display region; wherein the electrically conductive pad sets comprise second electrically conductive pad sets, the second electrically conductive pad sets being located in the peripheral region. [6] The array substrate according to claim 5, wherein the second electrically conductive pad sets comprise second electrically conductive pad sets and third electrically conductive pad sets; wherein, apart from the region of the second electrically conductive pads exposed by the openings, the orthographic projection of the other regions of the second electrically conductive pads on the substrate base partially overlaps the orthographic projection of the second electrically conductive layer on the substrate base; wherein the orthographic projection of the third electrically conductive pads on the substrate base and the orthographic projection of the second electrically conductive layer on the substrate base do not overlap. [7] The array substrate of claim 6, wherein the second electrically conductive layer comprises a plurality of interconnection lines arranged in the peripheral region, wherein the second electrically conductive pads are electrically connected to the interconnection lines, and wherein the orthographic projection of the second electrically conductive pads on the substrate base partially overlaps the orthographic projection of the interconnection lines on the substrate base. [8] The array substrate according to claim 7, wherein the array substrate comprises a shielding line, wherein the peripheral region includes bonding regions arranged on one side of the display region; wherein a main structure of the shielding line is located in regions in the peripheral region other than the bonding regions, and wherein two ends of the shielding line extend into the bonding regions; wherein the two ends of the shielding line are each electrically connected to the second electrically conductive pads via a connecting line. [9] The array substrate according to claim 8, wherein the shielding line covers at least a portion of the individual connecting lines and is in direct contact with the individual connecting lines. [10] The array substrate according to claim 8, wherein the first electrically conductive layer comprises a first electrically conductive portion including a ground line located in the display area; wherein the connecting lines are electrically connected to the ground line. [11] The array substrate according to claim 10, wherein a connection line located in a region of the peripheral region other than bonding regions is electrically connected to the ground line via a through-hole; wherein a connection line located in a bonding region is electrically connected to the ground line via the shield line. [12] The array substrate according to claim 10, wherein the peripheral region comprises a fan-out region, the fan-out region being disposed between the bonding region and the display region, and the fan-out region comprising a fan-out cable; wherein the third electrically conductive pads are electrically connected to the first electrically conductive portion via the fan-out cable. [13] The array substrate of claim 8, wherein the bonding region comprises a first bonding portion and a second bonding portion, the first bonding portion being located on a side of the second bonding portion facing away from the display region; the individual second electrically conductive pads being located in the first bonding portion and the individual third electrically conductive pads being located in the second bonding portion. [14] The array substrate according to claim 13, wherein the individual second electrically conductive pads are arranged in the same direction, wherein the individual third electrically conductive pads are arranged in the same direction, wherein in the arrangement direction of the second electrically conductive pads there is a first gap between each two adjacent second electrically conductive pads and in the arrangement direction of the third electrically conductive pads there is a second gap between each two adjacent third conductive pads; wherein the numbers of sublayers of the first insulating layer filled in the first gap and in the second gap are the same, and wherein the number of sublayers of the first insulating layer filled in the second gap is greater than the number of sublayers of the first insulating layer located in a part of the second electrically conductive pad sets facing away from the surface of the substrate base. [15] The array substrate according to claim 14, wherein the first insulating layer comprises a first inorganic sublayer, a first organic sublayer, a second organic sublayer, and a second inorganic sublayer arranged one after the other, the first inorganic sublayer and the first electrically conductive layer being in direct contact with each other; wherein the orthographic projection of the first organic sublayer on the substrate base does not overlap with the part of the substrate base arranged in the bonding region. [16] The array substrate of claim 15, wherein the orthographic projections of the first organic sublayer and the second inorganic sublayer on the substrate base and the orthographic projection of the second electrically conductive pads on the substrate base do not overlap; wherein the orthographic projections of the first organic sublayer and the second inorganic sublayer on the substrate base and the orthographic projection of the third electrically conductive pads on the substrate base do not overlap. [17] The array substrate according to claim 16, wherein at least the first inorganic sublayer, the second organic sublayer and the second inorganic sublayer are sequentially arranged in the first gap, wherein at least the first inorganic sublayer, the second organic sublayer and the second inorganic sublayer are sequentially arranged in the second gap. [18] The array substrate of claim 17, wherein the array substrate further comprises a second insulating layer, wherein the second insulating layer is located on a side of the second electrically conductive layer facing away from the substrate base; wherein the second insulating layer fills the first gap and the second gap, and the orthographic projection of the second insulating layer on the substrate base does not overlap with the orthographic projection of at least a portion of the second electrically conductive pads on the substrate base. [19] The array substrate according to claim 18, wherein the second insulating layer comprises a third inorganic sublayer and a third organic sublayer, the third organic sublayer being located on a side of the third inorganic sublayer facing away from the substrate support; furthermore, the third inorganic sublayer and the third organic sublayer are provided one after the other in the first gap and the second gap, the parts of the third inorganic sublayer located in the gaps being in direct contact with the parts of the second inorganic sublayer located in the gaps. [20] The array substrate according to claim 19, wherein the distance in the thickness direction of the substrate base between the surface of a part of the third organic sublayer facing away from the substrate base and located between the gaps and the substrate base is less than or equal to the distance in the thickness direction of the substrate base between the surface of a part of the second organic sublayer facing away from the substrate base and located on the second electrically conductive pad sets and the substrate base. [21] The array substrate according to claim 18, wherein the second insulating layer covers a portion of the connecting lines, wherein the shield line covers a portion of the connecting lines. [22] The array substrate according to claim 21, wherein a part of the outer contour of the orthographic projection of the second insulating layer on the substrate base is approximately tangent to a part of the outer contour of the orthographic projection of the shielding line on the substrate base. [23] The array substrate according to claim 18, wherein the orthographic projection of the second insulating layer on the substrate base and the orthographic projection of a partial area of ​​the second electrically conductive pads on the substrate base overlap; wherein the orthographic projection of the second insulating layer on the substrate base and the orthographic projection of a surface of the third electrically conductive pads on the substrate base facing away from the substrate base do not overlap. [24] The array substrate according to claim 5, wherein the array substrate further comprises a protective layer, the protective layer covering a portion of the first electrically conductive pads exposed at the openings K, the material of the protective layer comprising an electrically conductive material. [25] A display device comprising light-emitting components and an array substrate according to any one of claims 1 to 24, wherein the light-emitting components are electrically connected to first electrically conductive pad sets of the array substrate. [26] The display device of claim 25, wherein the display device further comprises a circuit board electrically connected to second electrically conductive pad sets of the array substrate. [27] A method for producing an array substrate used for producing an array substrate according to any one of claims 1 to 24, comprising: Providing a substrate base; Forming a first electrically conductive layer comprising a plurality of electrically conductive pad sets comprising at least one electrically conductive pad; Forming a first inorganic sub-film, a patterned first organic sub-layer, a patterned second organic sub-layer, and a second inorganic sub-film successively on the first electrically conductive layer; forming a second electrically conductive layer; Structuring the first inorganic sub-film and the second inorganic sub-film to obtain the first inorganic sub-layer and the second inorganic sub-layer; wherein the first insulating layer comprises a first inorganic sub-layer, a first organic sub-layer, a second organic sub-layer, and a second inorganic sub-layer, and wherein the first insulating layer has a plurality of openings exposing at least a portion of the electrically conductive pads.

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