Display substrate and display device

Abstract

A display substrate and a display device, wherein the display substrate (100 / 600) comprises: a base substrate (101 / 601); a pixel circuit (110 / 610) arranged on the base substrate (101 / 601) comprising a driver transistor (T3) and a storage capacitor (C); wherein the display substrate (100 / 600) further comprises a first conductive layer (102 / 602), a second conductive layer (103 / 603) and a first semiconductor layer (104 / 604), wherein the first conductive layer (102 / 602) comprises a first interconnect structure (1021 / 6021) comprising a first end (1021a / 6021a) and a second end (1021b / 6021b) opposite each other, wherein the first end (1021a / 6021a) is connected to the first semiconductor layer (104 / 604),wherein the second end (1021b / 6021b) is electrically connected to a gate electrode of the driver transistor (T3) and a first electrode plate (Cst1) of the storage capacitor (C); wherein the first conductive layer (102 / 602) is located on a side of the first semiconductor layer (104 / 604) away from the base substrate (101 / 601), wherein the second conductive layer (103 / 603) is located on a side of the first conductive layer (102 / 602) away from the base substrate (101 / 601), and an orthographic projection of the second conductive layer (103 / 603) on the base substrate (101 / 601) overlaps with an orthographic projection of at least part of the first interconnect structure (1021 / 6021) on the base substrate (101 / 601), wherein the display substrate uses a first electrode transmission line on the second conductive layer (103 / 603) or a first power supply signal line,to at least partially obscure the first interconnect structure (1021 / 6021). Since the second conductive layer (103 / 603) is supplied with a stable signal and a capacitor is formed between the second conductive layer (103 / 603) and the first conductive layer (102 / 602), the influence of nearby data signals on the N1 node can be reduced; that is, the influence of data signals on the N1 node can be shielded, thus mitigating the problem that the display cannot show normally due to the voltage of the N1 node being affected by the data signal step.

Description

FIELD OF TECHNOLOGY

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. STATE OF THE ART

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display elements. They have the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility, and low cost, making them promising for future development. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and signal-driven by thin-film transistors (TFTs) have become mainstream products in the display field. With the continuous development of display technology, optimizing the display effect has become an inevitable trend. SUMMARY

[0003] At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate uses a first electrode transmission line on the second conductive layer (SD2) or a first power supply signal line to conceal the N1 node. Since the second conductive layer (SD2) is supplied with a stable signal and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), the influence of nearby data signals on the N1 node can be reduced, that is, the influence of data signals on the N1 node can be shielded, so that the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0004] At least one embodiment of the present disclosure provides a display substrate comprising: a base substrate; a pixel circuit disposed on the base substrate and comprising a driver transistor and a storage capacitor; wherein the display substrate further comprises a first conductive layer, a second conductive layer, and a first semiconductor layer, wherein the first conductive layer comprises a first connection structure comprising a first end and a second end opposite to each other, the first end being connected to the first semiconductor layer, the second end being electrically connected to a gate electrode of the driver transistor and a first electrode plate of the storage capacitor;wherein the first conductive layer is located on a side of the first semiconductor layer remote from the base substrate, wherein the second conductive layer is located on a side of the first conductive layer remote from the base substrate and an orthographic projection of the second conductive layer on the base substrate overlaps with an orthographic projection of at least a portion of the first interconnect structure on the base substrate;

[0005] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a plurality of subpixels, each of the plurality of subpixels comprising the pixel circuit and a light-emitting element, wherein the first conductive layer is disposed between a first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is disposed between the first conductive layer and the first electrode of the light-emitting element.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer includes a data line, a first electrode transmission line, and a first power supply signal line spaced apart from each other, wherein the first electrode transmission line is connected to the first electrode of the light-emitting element and an orthographic projection of the first electrode transmission line on the base substrate overlaps with an orthographic projection of a part of the first connection structure on the base substrate.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first interconnection structure includes an overlapping part that overlaps with the first electrode transmission line and a non-overlapping part that does not overlap with the first electrode transmission line, and wherein the non-overlapping part is farther away from the data line closest to the first interconnection structure than the overlapping part.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, an extending direction of the data line is a first direction, and a direction perpendicular or substantially perpendicular to the extending direction of the data line is a second direction; wherein the first conductive layer further comprises a power supply signal connection line including a main part and a branch part, wherein an extending direction of an entirety of the main part of the power supply signal connection line is parallel to the second direction, and an extending direction of the branch part is parallel to the first direction;the first power supply signal line comprises a block-shaped part and a strip-shaped part extending as a whole along the first direction, the strip-shaped part connecting adjacent block-shaped parts and the main part of the power supply signal connecting line being connected to the first power supply signal line to form a lattice shape;

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the stripe-shaped part includes a first stripe-shaped part and a second stripe-shaped part arranged opposite to each other, and a third stripe-shaped part connecting the first stripe-shaped part and the second stripe-shaped part, wherein an extending direction of the first stripe-shaped part and an extending direction of the second stripe-shaped part are parallel to the first direction, and the third stripe-shaped part connects central regions of the first stripe-shaped part and the second stripe-shaped part.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the stripe-shaped part comprises a hollow structure.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, a width of the block-shaped part in the second direction is larger than a width of an entirety of the strip-shaped part in the second direction.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode transmission line extends along the first direction, and the first electrode transmission line conceals a part of the first connection structure at an end position of the first electrode transmission line near the first connection structure.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further comprises a first transistor, a second transistor, a sixth transistor, and a seventh transistor;wherein a first electrode of the first transistor is connected to a gate electrode of the driver transistor, a second electrode of the first transistor is connected to a first initial signal line, a first electrode of the second transistor is connected to a gate electrode of the driver transistor, a second electrode of the second transistor is connected to a second electrode of the driver transistor, a first electrode of the sixth transistor is connected to the second electrode of the driver transistor, a first electrode of the seventh transistor is connected to a second electrode of the sixth transistor, a second electrode of the seventh transistor is connected to a second initial signal line;wherein the display substrate further comprises: a first active layer between the base substrate and the second conductive layer, wherein the first active layer comprises a third active part, a sixth active part, a seventh active part, a tenth active part, and an eleventh active part, wherein the third active part forms a channel region of the driver transistor, the sixth active part forms a channel region of the sixth transistor, the seventh active part forms a channel region of the seventh transistor, the tenth active part is connected between the seventh active part and the sixth active part, and the eleventh active part is connected between the sixth active part and the third active part;and a second active layer between the first active layer and the second conductive layer, the second active layer comprising a first active portion, a second active portion, and a twelfth active portion, the first active portion forming a channel region of the first transistor, the second active portion being connected to the first active portion to form a channel region of the second transistor, and the twelfth active portion being connected to an end of the second active portion remote from the first active portion;

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display substrate comprises a plurality of repeating units distributed along the first direction and the second direction, wherein each of the repeating units comprises two pixel circuits, and the two pixel circuits comprise a first pixel circuit and a second pixel circuit distributed along the second direction, and wherein the first pixel circuit and the second pixel circuit are arranged mirror-symmetrically;wherein each of the pixel circuits further comprises a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is connected to the data line, a second electrode of the fourth transistor is connected to a first electrode of the driver transistor, a first electrode of the fifth transistor is connected to the first power supply signal line, and a second electrode of the fifth transistor is connected to the first electrode of the driver transistor; wherein the first active layer further comprises: a fourth active part connected to one side of the third active part and forming a channel region of the fourth transistor; a fifth active part forming a channel region of the fifth transistor; an eighth active part connected to a side of the fifth active part remote from the third active part;and a ninth active part connected between two eighth active parts in the same repeating unit.;

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive layer comprises a plurality of third interconnection structures, wherein the plurality of third interconnection structures are arranged in one-to-one correspondence with the plurality of repeating units, and wherein each of the third interconnection structures is connected to the ninth active part through a first through-hole interconnection part.

[0016] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a third conductive layer, the third conductive layer comprising: a second gate line, wherein an orthographic projection of the second gate line on the base substrate extends along the second direction and overlaps with an orthographic projection of the fourth active part on the base substrate, and wherein a partial pattern of the second gate line is used to form a gate electrode of the fourth transistor;a light emission control signal line, wherein an orthographic projection of the light emission control signal line on the base substrate extends along the second direction and overlaps with an orthographic projection of the sixth active part on the base substrate, and wherein a partial structure of the light emission control signal line is used to form a gate electrode of the sixth transistor;a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends along the second direction and overlaps with an orthographic projection of the seventh active part on the base substrate, wherein a partial structure of the second reset signal line is used to form a gate electrode of the seventh transistor, and wherein the second gate line in the pixel circuit of a present row is multiplexed as the second reset signal line in the pixel circuit of an adjacent row; and a second conductive part, wherein an orthographic projection of the second conductive part on the base substrate overlaps with an orthographic projection of the third active part on the base substrate, and the second conductive part forms a gate electrode of the driver transistor and the first electrode plate of the storage capacitor;wherein, in the same pixel circuit, the orthographic projection of the second conductive part on the base substrate is arranged between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the light emission control signal line on the base substrate; wherein the orthographic projection of the second reset signal line on the base substrate is arranged on a side of the orthographic projection of the light emission control line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate.

[0017] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a fourth conductive layer, wherein the fourth conductive layer is disposed between the second active layer and the second conductive layer, and the fourth conductive layer comprises: a first reset signal line, wherein an orthographic projection of the first reset signal line on the base substrate overlaps with an orthographic projection of the first active part on the base substrate, and a partial structure of the first reset signal line forms an upper gate electrode of the first transistor; a first gate line, wherein an orthographic projection of the first gate line on the base substrate overlaps with an orthographic projection of the second active part on the base substrate, and a partial structure of the first gate line forms an upper gate electrode of the second transistor;wherein, in the same pixel circuit, the orthographic projection of the first gate line on the base substrate is arranged between the orthographic projection of the second conductive part on the base substrate and the orthographic projection of the second gate line on the base substrate, and wherein the orthographic projection of the first reset signal line on the base substrate is arranged on a side of the orthographic projection of the second gate line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate;

[0018] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a conductive film layer between the third conductive layer and the fourth conductive layer, the conductive film layer comprising: the first initial signal line, wherein an orthographic projection of the first initial signal line on the base substrate is arranged on a side of the orthographic projection of the first reset signal line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate;a third reset signal line connected to the first reset signal line through a through-hole, wherein an orthographic projection of the third reset signal line on the base substrate overlaps with the orthographic projection of the first active part on the base substrate, and wherein a partial pattern of the third reset signal line is used to form a lower gate electrode of the first transistor; a third gate line, wherein an orthographic projection of the third gate line on the base substrate overlaps with the orthographic projection of the second active part on the base substrate, and a partial pattern of the third gate line is used to form a lower gate electrode of the second transistor;and a first conductive part comprising a main part, wherein the storage capacitor comprises a second electrode plate opposite to the first electrode plate, and wherein the main part corresponds to two second electrode plates;

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive part further comprises a bridge part connecting the two second electrode plates, and wherein the first conductive part comprises a recess between the two second electrode plates.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer comprises a data line and a first power supply signal line, wherein an orthographic projection of the first power supply signal line on the base substrate covers more than 50% of an orthographic projection of the first interconnection structure on the base substrate.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel circuit further comprises a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; wherein a gate electrode of the first transistor is connected to a reset control signal line, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a first electrode of the eighth transistor and a first electrode of the second transistor; wherein a gate electrode of the second transistor is connected to a first scanning signal line, and a second electrode of the second transistor is connected to a second electrode of the driver transistor and a first electrode of the sixth transistor;wherein a gate electrode of the driver transistor is connected to a second electrode of the eighth transistor and a first electrode plate of the storage capacitor, a first electrode of the driver transistor is connected to a second electrode of the fourth transistor and a second electrode of the fifth transistor, and the second electrode of the driver transistor is connected to the second electrode of the second transistor and the first electrode of the sixth transistor; wherein a gate electrode of the fourth transistor is connected to the first scanning signal line, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driver transistor and the second electrode of the fifth transistor;wherein a gate electrode of the fifth transistor is connected to a first light-emitting control signal line, a first electrode of the fifth transistor is connected to a first power supply signal line and a second electrode plate of the storage capacitor, and a second electrode of the fifth transistor is connected to the second electrode of the fourth transistor and the first electrode of the driver transistor; wherein a gate electrode of the sixth transistor is connected to the first light-emitting control signal line, a first electrode of the sixth transistor is connected to the second electrode of the driver transistor and the second electrode of the second transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting element and a second electrode of the seventh transistor;wherein a gate electrode of the seventh transistor is connected to the first scanning signal line or the reset control signal line, a first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor and the second electrode of the sixth transistor are connected to the first electrode of the light-emitting element; wherein a gate electrode of the eighth transistor is connected to a second scanning signal line, a first electrode of the eighth transistor is connected to the second electrode of the first transistor and the first electrode of the second transistor, and a second electrode of the eighth transistor is connected to the gate electrode of the driver transistor and the first electrode plate of the storage capacitor;wherein the first electrode plate of the storage capacitor is connected to the gate electrode of the driver transistor and the second electrode of the eighth transistor, and the second electrode plate of the storage capacitor is connected to the first power supply signal line;

[0022] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises: a first active layer between the base substrate and the second conductive layer, the first active layer comprising a first active part, a second active part, a third active part, a fourth active part, a fifth active part, a sixth active part, and a seventh active part, the first active part forming a channel region of the first transistor, the second active part forming a channel region of the second transistor, the third active part forming a channel region of the driver transistor, the fourth active part forming a channel region of the fourth transistor, the fifth active part forming a channel region of the fifth transistor, the sixth active part forming a channel region of the sixth transistor, and the seventh active part forming a channel region of the seventh transistor;a second active layer between the first active layer and the second conductive layer, the second active layer comprising an eighth active portion and the eighth active portion forming a channel region of the eighth transistor;

[0023] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a third conductive layer, the third conductive layer comprising: the first scanning signal line, wherein an orthographic projection of the first scanning signal line on the base substrate extends along the second direction, and a partial pattern of the first scanning signal line is used to form gate electrodes of the second transistor and the fourth transistor; the reset control signal line, wherein an orthographic projection of the reset control signal line on the base substrate extends along the first direction, and a partial pattern of the reset control signal line is used to form gate electrodes of the seventh transistor and the first transistor;the first light emission control signal line, wherein an orthographic projection of the first light emission control signal line on the base substrate extends along the first direction, and a partial structure of the first light emission control signal line is used to form gate electrodes of the sixth transistor and the fifth transistor; and a third conductive part forming the gate electrode of the driver transistor and the first electrode plate of the storage capacitor; wherein, in the same pixel circuit, an orthographic projection of the third conductive part on the base substrate is arranged between the orthographic projection of the first scanning signal line on the base substrate and the orthographic projection of the first light emission control signal line on the base substrate;wherein the orthographic projection of the reset control signal line on the base substrate is arranged on a side of the orthographic projection of the first light emission control signal line on the base substrate that is remote from the orthographic projection of the third conductive part on the base substrate;

[0024] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a conductive film layer between the third conductive layer and the second conductive layer, the conductive film layer comprising: the second scanning signal line, wherein a partial structure of the second scanning signal line is used to form a lower gate electrode of the eighth transistor; a first conductive part comprising two second electrode plates of two storage capacitors that are adjacent in the second direction; and a fifth conductive part electrically connected to the first conductive layer.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive part further comprises a bridge part connecting the two second electrode plates, and wherein the first conductive part comprises a recess between the two second electrode plates.

[0026] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a fourth conductive layer, wherein the fourth conductive layer is disposed between the conductive film layer and the second conductive layer, and the fourth conductive layer includes the first initial signal line and a fourth scanning signal line, and a partial structure of the fourth scanning signal line forms an upper gate electrode of the eighth transistor.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, an extending direction of the data line is a first direction and a direction perpendicular or substantially perpendicular to the extending direction of the data line is a second direction, wherein the first connection structure has an inverted "L" shape, and wherein an end of a part of the inverted "L" shape extending along the second direction, which is remote from a nearest data line, is connected to the second electrode of the eighth transistor.

[0028] For example, in the display substrate provided by at least one embodiment of the present disclosure, the part of the inverted "L" shape extending along the first direction is electrically connected to the fifth conductive part of the conductive film layer; wherein the first scanning signal line includes a protruding part extending along the first direction and a part extending along the second direction, and wherein the fifth conductive part overlaps with the protruding part of the first scanning signal line extending along the first direction.

[0029] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of subpixels includes a plurality of first subpixels, a plurality of second subpixels, and a plurality of third subpixels; wherein two second subpixels form a second subpixel pair, the two second subpixels in a second subpixel pair are each a first pixel block and a second pixel block, and the first pixel block and the second pixel block are alternately arranged along the first direction or the second direction; wherein the plurality of subpixels includes a plurality of minimum repeating units, and a minimum repeating unit includes a first subpixel, a first pixel block, a second pixel block, and a third subpixel.

[0030] For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a first electrode layer, wherein the first electrode layer is located on a side of the second conductive layer remote from the base substrate, and the first electrode layer comprises a plurality of electrode parts, each of the plurality of electrode parts comprising a body part and a supplementary part connected to each other, wherein an orthographic projection of the supplementary part on the base substrate at least partially overlaps the orthographic projection of the first electrode transmission line on the base substrate, and wherein each of the plurality of electrode parts corresponds to one of the first subpixel, the first pixel block, the second pixel block, and the third subpixel.

[0031] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of electrode parts includes a first electrode part, a second electrode part, and a third electrode part having three different colors, wherein the first electrode part corresponds to the first subpixel, the second electrode part corresponds to any one of the first pixel block and the second pixel block, and the third electrode part corresponds to the third subpixel;wherein an overlap area of ​​an orthographic projection of the first electrode part on the base substrate with an orthographic projection of the first power supply signal line on the base substrate is larger than an overlap area of ​​an orthographic projection of the second electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate, and is larger than an overlap area of ​​an orthographic projection of the third electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate;wherein the overlap area of ​​the orthographic projection of the third electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate is larger than the overlap area of ​​the orthographic projection of the second electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate;

[0032] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode part corresponds to a blue subpixel that emits blue light, the second electrode part corresponds to a green subpixel that emits green light, and the third electrode part corresponds to a red subpixel that emits red light.

[0033] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive layer further comprises a plurality of first electrode transmission lines, and wherein the plurality of first electrode transmission lines are arranged in one-to-one correspondence with the plurality of electrode parts, and the electrode parts are each connected to a corresponding first electrode transmission line through a through-hole.

[0034] For example, in the display substrate provided by at least one embodiment of the present disclosure, the subpixel further comprises a light-shielding layer located on a side of an active semiconductor pattern of the driver transistor that is close to the base substrate, wherein an orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active semiconductor pattern of the driver transistor on the base substrate.

[0035] For example, at least one embodiment of the present disclosure further provides a display device comprising one of the above-mentioned display substrates. SHORT DESCRIPTION OF THE CHARACTERS

[0036] In order to more clearly explain the technical aspects of the embodiments of the present disclosure, the drawings of the embodiments are briefly presented below. Of course, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure. Fig. Figure 1 is a layout diagram for reducing the influence of data signal jumps on the N1 node by forming a 3D capacitor in an LTPS pixel circuit. Fig. Figure 2 is a layout diagram in which an anode obscures an N1 node. Fig. 3 is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present disclosure. Fig. 4 is a timing diagram of the respective nodes in a driving process of the pixel circuit in Fig. 3. Fig. 5A is a structural layout diagram of a display substrate provided by at least one embodiment of the present disclosure. Fig. 5B is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. Fig. 6 is a structural layout diagram of the second conductive layer in Fig. 5B. Fig. 7 is a structural layout diagram of the first conductive layer in Fig. 5B. Fig. 8 is a structural layout diagram in which the first conductive layer and the second conductive layer in Fig. 5B are superimposed. Fig. 9 is a schematic partial structure diagram of the first active layer in the Fig. 5B shown display substrate. Fig. 10 is a schematic partial structure diagram of the third conductive layer in the Fig. 5B shown display substrate. Fig. 11 is a schematic partial structure diagram of the conductive film layer in the Fig. 5B shown display substrate. Fig. 12 is a schematic partial structure diagram of the second active layer in the Fig. 5B shown display substrate. Fig. 13 is a schematic partial structure diagram of the fourth conductive layer in the Fig. 5B shown display substrate. Fig. 14 is a schematic diagram of a partial pixel array structure on a display substrate provided according to an embodiment of the present disclosure. Fig. 15A is a layout diagram of a stack of a pixel circuit and a first electrode of the light-emitting element in Fig. 5B. Fig. 15B is another layout diagram of a stack of a pixel circuit and a first electrode of the light-emitting element in Fig. 5B. Fig. 16 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure. Fig. 17 is a schematic partial structure diagram of a light-shielding layer in the Fig. 5B and Fig. 15 B shown display substrate. Fig. 18 is a layout diagram of a stack of a light shielding layer and a first active layer provided by an embodiment of the present disclosure. Fig. 19 is a schematic circuit structure diagram of another pixel circuit provided by an embodiment of the present disclosure. Fig. 20 is a timing diagram of the respective nodes in a driving process of the pixel circuit in Fig. 19. Fig. 21A is a structural layout diagram of another display substrate provided by an embodiment of the present disclosure. Fig. 21B is a structural layout diagram of another display substrate provided by an embodiment of the present disclosure. Fig. 22 is a structural layout diagram of the second conductive layer in Fig. 21B. Fig. 23 is a structural layout diagram of the first conductive layer in Fig. 21B. Fig. 24 is a structural layout diagram in which the first conductive layer and the second conductive layer in Fig. 21B are superimposed. Fig. 25 is a schematic partial structure diagram of the first active layer in the Fig. 19 shown display substrate. Fig. 26 is a schematic partial structure diagram of a third conductive layer in the Fig. 19 shown display substrate. Fig. 27 is a schematic partial structure diagram of a conductive film layer in the Fig. 19 shown display substrate. Fig. 28 is a schematic partial structure diagram of a second active layer in the Fig. 19 shown display substrate. Fig. 29 is a schematic partial structure diagram of a fourth conductive layer in the Fig. 19 shown display substrate. Fig. 30 is a schematic diagram of a partial pixel array structure on a display substrate provided according to an embodiment of the present disclosure. Fig. 31A is a layout diagram of a stack of the pixel circuit and a first electrode of the light-emitting element in Fig. 19. Fig. 31B is another layout diagram of a stack of the pixel circuit and a first electrode of the light-emitting element in Fig. 19. Fig. 32 is a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure. Fig. 33 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. Fig. 34 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. Fig. 35 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. Fig. 36 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF REVELATION

[0037] In order to clarify the objects, technical objects, and advantages of the embodiments of the present disclosure, the technical objects of the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings of the present disclosure. It is obvious that the described embodiments represent only a part of the embodiments, but not all embodiments of the present disclosure. Starting from the embodiments described herein, one of ordinary skill in the art can obtain other embodiments that fall within the scope of the present disclosure without inventive work.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," etc., as used in this disclosure, are not intended to indicate order, amount, or importance, but are used to distinguish different components. The terms "comprises," "including," etc., are intended to indicate that the elements or items listed before these terms include the elements or items listed after these terms, as well as their equivalents, but do not exclude other elements or items.

[0039] The features such as "perpendicular" and "identical" used in the embodiment of the present disclosure include all features such as "perpendicular" and "identical" in the narrow sense, and the cases such as "substantially perpendicular" and "substantially identical," which include certain errors that are within the acceptable range of deviation for a given value, determined by one of ordinary skill in the art, taking into account the measurement and the errors associated with measuring a given quantity (i.e., the limitations of the measurement system). The "center point" in the embodiments of the present disclosure may include a strictly geometric center point position and an approximately central position in a small area around the geometric center point. For example, "substantially" may refer to the cases within one or more standard deviations, or within 10% or 5% of the specified value.

[0040] Low-temperature polycrystalline oxide (LTPO) technology can be applied to light-emitting diode displays (LEDs), which can reduce the power consumption of the display panel. The power consumption of the display panel includes driving power and luminous power. The driving power of the display panel based on LTPO technology is lower than that of the display panel based on LTPS technology. The display panel based on LTPS technology requires a refresh rate of 60 Hz to display a still image, but the refresh rate of the display panel based on LTPO technology can be reduced to 1 Hz for displaying a still image, significantly reducing the driving power.

[0041] Based on LTPO technology, some transistors in the display panel are oxide transistors (e.g., N-type oxide transistors). The leakage current of the oxide transistor is lower, so the voltage (charge) on the capacitor can be maintained for one second to achieve a refresh rate of 1 Hz. The leakage current of the LTPS transistor is larger, so even when driving a still image pixel, the LTPS transistor requires a refresh rate of 60 Hz; otherwise, the brightness will be greatly reduced. Therefore, LTPO technology has been widely used for display substrates.

[0042] Fig. For example, Figure 1 is a layout diagram for reducing the influence of data signal jumps on the N1 node by forming a 3D capacitor in an LTPS pixel circuit. The position of the N1 node is, for example, a connection position between a lower electrode plate of the storage capacitor and the gate electrode of the driver transistor. As shown in Fig. As shown in Figure 1, in the design of an LTPS pixel circuit, in order to avoid the influence of the data signal on the N1 node, a second gate layer O2 to which a power supply signal is applied is added on the right side of the N1 node, and the power supply signal is generated through a power supply signal line O4, that is, the second gate layer O2 is electrically connected to the power supply signal line O4. A capacitor may be formed between the second gate layer O2 and the N1 node, so that the influence of the data signal jump generated by the data line O3 on the N1 node can be blocked. However, in this structural configuration, the second gate layer O2 and the N1 node are not directly arranged to overlap, so that the capacitors thereby formed do not overlap in the plane, and a spatial 3D capacitor is formed.The 3D spatial capacitor is too small to shield the N1 node, so the influence of the data signal on the N1 node cannot be effectively avoided.

[0043] Fig. For example, Figure 2 is a layout diagram in which an anode obscures an N1 node. As in Fig. 2, an anode 05 covers an N1 node. In particular, as shown in Fig. As shown in Figure 2, an anode 05R of a red subpixel covers the N1 node, and a complementary part of the anode 05R of the red subpixel spans the data line 03 on a right side of the anode 05R, and an anode 05B of a blue subpixel covers the N1 node. To avoid the difference in pixel brightness and ensure the uniformity of the display brightness, only the anode 05R of the red subpixel and the anode 05B of the blue subpixel cover the N1 node, and an anode 05G of a green subpixel does not cover the N1 node.

[0044] Due to the advantages of LTPO technology, such as high charge mobility, high pixel response speed, and low power consumption, LTPO display products have many performance specification requirements. The inventors of the present disclosure have found that these performance specifications of LTPO display products are closely related to the circuit design of the product backplane. For example, an anode transmission line located on the second conductive layer (SD2) can be used to conceal the N1 node. Since the second conductive layer (SD2) is applied with a stable signal and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1), the influence of nearby data signals on the N1 node can be reduced, i.e.The influence of data signals on the N1 node can be shielded, thus alleviating the problem that the display panel cannot display normally due to the voltage of the N1 node being affected by the data signal jump. Furthermore, this design can be used for the red subpixel, the green subpixel, and the blue subpixel to mask the N1 node, thereby solving the problem of poor light emission uniformity of the display panel due to transistor process variations.

[0045] The inventors of the present disclosure have also found that a horizontal power supply signal line (horizontal VDD) can be formed on the first conductive layer (SD1) and a vertical power supply signal line (vertical VDD) can be formed on the second conductive layer (SD2), and that the horizontal power supply signal line and the vertical power supply signal line cross to form a mesh-shaped power supply signal line, thereby making the signal in the power supply signal line more stable and saving design space.

[0046] For example, at least one embodiment of the present disclosure provides a display substrate comprising: a base substrate; a pixel circuit disposed on the base substrate and including a driver transistor and a storage capacitor; wherein the display substrate further comprises a first conductive layer, a second conductive layer, and a first semiconductor layer, wherein the first conductive layer comprises a first connection structure comprising a first end and a second end opposite each other, the first end being connected to the first semiconductor layer, the second end being electrically connected to a gate electrode of the driver transistor and a first electrode plate of the storage capacitor; wherein the first conductive layer is located on a side of the first semiconductor layer remote from the base substrate,wherein the second conductive layer is located on a side of the first conductive layer remote from the base substrate, and an orthographic projection of the second conductive layer on the base substrate overlaps with an orthographic projection of at least a portion of the first interconnection structure on the base substrate. In the display substrate, the orthographic projection of the second conductive layer on the base substrate overlaps with the orthographic projection of at least a portion of the first interconnection structure on the base substrate, such that a first electrode transmission line in the second conductive layer (SD2) can obscure at least a portion of the N1 node because the second conductive layer (SD2) is supplied with a stable signal and a capacitor is formed between the second conductive layer (SD2) and the first conductive layer (SD1).A capacitor is formed between the N1 node and a nearby data line, and the data signal has little influence on the capacitor, so that the influence of nearby data signals on the N1 node can be reduced, that is, the influence of data signals on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0047] For example, Fig. 3 is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present disclosure. As in Fig. 3, the pixel circuit 110 comprises a first transistor T1, a second transistor T2, a driver transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C.

[0048] For example, in Fig. 3, the first transistor T1 is a first reset transistor T1, the second transistor T2 is a threshold compensation transistor T2, the fourth transistor T4 is a data write transistor T4, the fifth transistor T5 is a second light emission control transistor T5, the sixth transistor T6 is a first light emission control transistor T6, and the seventh transistor T7 is a second reset control transistor T7.

[0049] For example, a first electrode of the first transistor T1 is connected to the N1 node, i.e., the first electrode of the first transistor T1 is electrically connected to a gate electrode of the driver transistor T3, a second electrode of the first transistor T1 is connected to a first initial signal terminal Vinit1, i.e., the second electrode of the first transistor T1 is electrically connected to the first reset signal line to receive a reset signal, a gate electrode of the first transistor T1 is connected to a first reset signal terminal Re1, i.e., the gate electrode of the first transistor T1 is electrically connected to a reset control signal line to receive a reset control signal. A first electrode of the second transistor T2, namely, the threshold compensation transistor, is connected to the N1 node, i.e.,The first electrode of the second transistor T2 is electrically connected to the gate electrode of the driver transistor T3, a second electrode of the second transistor T2 being connected to the second electrode of the driver transistor T3, and a gate electrode of the second transistor T2 being connected to a first gate driver signal terminal G1 for receiving a compensation control signal. The gate electrode of the driver transistor T3 is connected to node N1 for connection to the first electrode plate of the storage capacitor C, the first electrode of the first transistor T1, and the first electrode of the second transistor T2.A first electrode of the fourth transistor T4, namely the data write transistor, is connected to a data signal terminal Data to receive a data signal, a second electrode of the fourth transistor T4 is connected to the first electrode of the driver transistor T3, and a gate electrode of the fourth transistor T4 is connected to a second gate drive signal terminal G2 to receive a scan signal. A first electrode of the fifth transistor T5, i.e., a second light emission control transistor, is connected to a first power supply terminal VDD to receive a first power supply signal, a second electrode of the fifth transistor T5 is connected to the first electrode of the driver transistor T3, and a gate electrode of the fifth transistor T5 is connected to a light emission control signal terminal EM to receive a light emission control signal.A first electrode of the sixth transistor T6, namely the first light emission control transistor, is connected to the second electrode of the driver transistor T3, a second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7, and a gate electrode of the sixth transistor T6 is connected to a light emission control signal terminal EM for receiving a light emission control signal. A second electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, i.e., the second electrode of the seventh transistor T7 is electrically connected to a second reset power supply signal line for receiving a reset signal Vinit, and a gate electrode of the seventh transistor T7 is connected to a second reset signal terminal Re2, i.e.,The gate electrode of the seventh transistor T7 is electrically connected to a reset control signal line to receive a reset control signal. The first electrode plate of the storage capacitor C is connected to the N1 node and electrically connected to the gate electrode of the driver transistor T3, and the second electrode plate of the storage capacitor C is connected to the first power supply terminal VDD, i.e., the first power supply signal line. The pixel circuit can be connected to a light-emitting element 120, which may be an organic light-emitting diode (OLED), and the pixel circuit is used to drive the light-emitting element 120 to emit light. The light-emitting element 120 can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS, i.e., connected to the second power supply signal line.

[0050] The first power supply signal line refers, for example, to a signal line that outputs a voltage signal VDD and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal. The second power supply signal line refers to a signal line that outputs a voltage signal VSS and can be connected to a voltage source to output a constant voltage signal, such as a negative voltage signal.

[0051] For example, the scanning signal and the compensation control signal may be the same, i.e., the gate electrode of the data write transistor T4 and the gate electrode of the threshold compensation transistor T2 may be electrically connected to the same signal line to receive the same signal, in order to reduce the number of signal lines. For example, the gate electrode of the data write transistor T4 and the gate electrode of the threshold compensation transistor T2 may also be electrically connected to different signal lines, i.e.,the gate electrode of the data write transistor T4 is electrically connected to the second scanning signal line (second gate line), and the gate electrode of the threshold compensation transistor T2 is electrically connected to the first scanning signal line (first gate line), wherein the signals transmitted by the first scanning signal line and the second scanning signal line may be the same or different, so that the gate electrode of the data write transistor T4 and the gate electrode of the threshold compensation transistor T2 can be controlled separately and independently of each other to enable increased control flexibility of the pixel circuit.

[0052] For example, the same light emission control signal may be supplied to the first light emission control transistor T6 and the second light emission control transistor T5, that is, a gate electrode of the first light emission control transistor T6 and a gate electrode of the second light emission control transistor T5 may be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate electrodes of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 may each be electrically connected to different light emission control signal lines. In this case, the signals transmitted by different light emission control signal lines may be the same or different.

[0053] For example, the same reset control signal may be supplied to the second reset transistor T7 and the first reset transistor T1. That is, a gate electrode of the second reset transistor T7 and a gate electrode of the first reset transistor T1 may be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate electrode of the second reset transistor T7 and the gate electrode of the first reset transistor T1 may each be electrically connected to different reset control signal lines. In this case, the signals on the different reset control signal lines may be the same or different.

[0054] For example, the first transistor T1 and the second transistor T2 may be N-type transistors. For example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, where N-type metal oxide transistors have a lower leakage current, thus avoiding the problem of the N1 node leaking current through the first transistor T1 and the second transistor T2 in the light-emitting stage.Meanwhile, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors. P-type low-temperature polycrystalline silicon transistors have higher carrier mobility, which is beneficial for realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 may output the same or different voltage signals depending on the actual situation.

[0055] Fig. For example, Fig. 4 is a timing diagram of the respective nodes in a driving process of the pixel circuit in Fig. 3. G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light emission control signal terminal EM, and Data represents the timing of the data signal terminal Data. The driving method of the pixel circuit may include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. In the first reset stage t1, the first reset signal terminal Re1 outputs a high level signal, turning on the first transistor T1, and the first initial signal terminal Vinit1 inputs an initial signal to the node N1.In the compensation stage t2, the first gate drive signal terminal G1 outputs a high-level signal and the second gate drive signal terminal G2 outputs a low-level signal, turning on the fourth transistor T4 and the second transistor T2. At the same time, the data signal terminal Data outputs a drive signal to write the voltage Vdata+Vth (i.e., a sum of the voltages Vdata and Vth) to the node N1, where Vdata is the voltage of a drive signal and Vth is a threshold voltage of the drive transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, turning on the seventh transistor T7, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6.In the light-emitting stage t4, the light-emitting control signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driver transistor T3 emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0056] It should be noted that in the embodiment of the present disclosure, each pixel circuit includes both a Fig. 3 may be the 7T1C structure (ie, seven transistors and one capacitor), as well as a structure including a different number of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure, 8T1C structure, or 9T2C structure, which is not limited in the embodiment of the present disclosure.

[0057] For example, the display substrate comprises a plurality of repeating units distributed along the first direction and the second direction that intersect each other, wherein each of the repeating units comprises two pixel circuits, and the two pixel circuits comprise a first pixel circuit and a second pixel circuit distributed along the second direction, wherein the first pixel circuit and the second pixel circuit are arranged substantially mirror-symmetrically, and wherein the pixel circuit described below is described by one of the first pixel circuit and the second pixel circuit.

[0058] For example, one embodiment of the present disclosure provides a display substrate, wherein Fig. 5A is a structural layout diagram of a display substrate provided by at least one embodiment of the present disclosure, wherein Fig. 5B is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure, wherein Fig. 6 a structural layout diagram of a second conductive layer in Fig. 5B, where Fig. 7 is a structural layout diagram of a first conductive layer in Fig. 5B, and where Fig. 8 is a structural layout diagram in which a first conductive layer and a second conductive layer in Fig. 5B are superimposed. Fig. 5A to Fig. 7 only schematically show the schematic diagrams of stacked structure or single-layer structure of some film layers in the display substrate, and other film layers may also include film layers in which the gate lines are located, film layers in which the light-shielding layer is located, and so on. Compared to Fig. 5A is Fig. 5B is additionally provided with a light-shielding layer, and other structural arrangements are the same.

[0059] For example, in Fig. 3 and Fig. 5B, the display substrate 100 comprises: a base substrate 101, a pixel circuit 110 arranged on the base substrate 101, the pixel circuit 110 comprising a driver transistor T3 and a storage capacitor C, the display substrate 100 further comprising a first conductive layer 102, a second conductive layer 103 and a first semiconductor layer 104, the first conductive layer 102 comprising a first interconnection structure 1021 having a first end 1021a and a second end 1021b opposite to each other.The first end 1021a is connected to the first semiconductor layer 104, and the second end 1021b is electrically connected to the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor C; wherein the first conductive layer 102 is arranged on a side of the first semiconductor layer 104 remote from the base substrate 101, and wherein the second conductive layer 103 is arranged on a side of the first conductive layer 102 remote from the base substrate 101, and wherein an orthographic projection of the second conductive layer 103 on the base substrate 101 overlaps with an orthographic projection of at least a part of the first connection structure 1021 on the base substrate 101.In this display substrate 100, the orthographic projection of the second conductive layer 103 onto the base substrate 101 and the orthographic projection of at least a part of the first interconnection structure 1021 onto the base substrate 101 overlap, so that the second conductive layer 103 (also called SD2) can obscure at least a part of the first interconnection structure 1021 (also called N1 node). Therefore, the second conductive layer 103 and the first interconnection structure 1021 located in the first conductive layer 102 directly form a capacitor, that is, a capacitor is directly formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), so that a capacitor is formed between the N1 node and the next data line Data.Since both the light emission control signal line EM and the second initial signal line Vinit2 transmit stable DC signals, the second conductive layer 103 (SD2) is supplied with a stable signal, and the signal changes only once within the time of one frame. With this construction, the second conductive layer 103 (SD2) can directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node when the N1 node is operating normally, and the second conductive layer 103 (SD2, the upper electrode plate) is supplied with a stable signal. Due to the characteristics of the capacitor itself, the voltages at both ends of the capacitor cannot change suddenly. When the upper electrode plate is supplied with a stable signal, the signal at the lower electrode plate, i.e.The first conductive layer 102 (SD1) at the N1 node also remains stable, thereby reducing the influence of the data signal that frequently jumps within the time of one frame on the N1 node. The data signal has little influence on the capacitor, so the influence of nearby data signals on the N1 node can be reduced. That is, the influence of data signals on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0060] For example, in Fig. As shown in Figure 5B, the first semiconductor layer 104 includes active semiconductor patterns of a first transistor T1 and a second transistor T2, which will be mentioned later, and the material of the first semiconductor layer 104 is a metal oxide semiconductor, such as indium gallium zinc oxide (IGZO). The first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driver transistor T3.

[0061] In combination with Fig. 3 and Fig. 5B, the first end 1021a of the first connection structure 1021 is also electrically connected to the first electrode of the first transistor T1 (first reset transistor) and the first electrode of the second transistor T2 (threshold compensation transistor).

[0062] For example, in Fig. 5A, Fig. 5B, Fig. 6 and Fig. As shown in Figure 8, the second conductive layer 103 includes a data line 1031, a first electrode transmission line 1032, and a first power supply signal line 1033 that are spaced apart from each other. The first electrode transmission line 1032 has an elongated shape, and the entirety of the first electrode transmission line 1032 extends along an extension direction of the data line 1031 that is closest to it. The extension direction of the data line 1031 is the first direction Y, and a direction perpendicular or substantially perpendicular to the extension direction of the data line 1031 is the second direction X. Referring to Fig. 3, Fig. 5B, Fig. 6 and Fig. 8, the first electrode transmission line 1032 is connected to a first electrode of the later-described light-emitting element 120 through a through-hole. As shown in Fig. 5B, Fig. 6 and Fig. 8, for example, an orthographic projection of the entire data line 1031 on the base substrate 101 extends linearly along the first direction Y. In the same repeating unit, orthographic projections of two data lines 1031 on the base substrate 101 are located between the orthographic projections of two first power supply signal lines 1033 on the base substrate 101.

[0063] In the Fig. 7, the first conductive layer 102 further comprises a second initial signal line 1022. In combination with Fig. 3 and Fig. 7, the second initial signal line 1022 is electrically connected to the first electrode of the seventh transistor T7 (first reset transistor) to provide a reset signal. For example, the second initial signal line 1022 may be a first reset signal line electrically connected to the first electrode of the seventh transistor T7, and the display substrate 110 further comprises a second reset power supply signal line (not shown in the figure), wherein a first part of the second reset power supply signal line is located between the first conductive layer 102 and a film layer in which the gate electrode of the seventh transistor T7 is located, and is configured such that the first part is electrically connected to the first electrode of the first transistor T1 to provide a reset signal.

[0064] For example, in the Fig. 7 and Fig. 8, the first conductive layer 102 further comprises power supply signal connection lines 1023 extending along the second direction X. The second conductive layer 103 comprises data lines data and first power supply signal lines 1033 extending along the first direction Y. Each of the power supply signal connection lines 1023 is electrically connected to a plurality of first power supply signal lines 1033 arranged along the second direction X to form a grid shape. The first power supply signal line 1033 can be used to connect the first power supply terminal in Fig. 3, and the data line 1031 can be used to provide the data signal connection in Fig. 3. As for example in the Fig. 7 and Fig. As shown in Figure 8, a main part 1023a of the power supply signal connection line 1023 has a bent line shape with a convex part, and a central part of the convex part is provided with a connection block 1023b. The extending direction of the entire power supply signal connection line 1023 is parallel to the second direction X, and the extending direction of the connection block 1023b is parallel to the first direction Y. On the power supply signal connection line 1023, the number of connection blocks 1023b is a plurality, and the power supply signal connection line 1023 is connected to a plurality of first power supply signal lines 1033 on the second conductive layer 103 through the plurality of connection blocks 1023b.

[0065] For example, in Fig. 3, Fig. 5 and Fig. 7, the first conductive layer 102 further includes a first connection portion 1024 electrically connected to the first portion of the second reset power supply signal line.

[0066] For example, in Fig. 3, Fig. 5 and Fig. 7, the first conductive layer 102 further comprises a second connection part 1025 through which the first electrode of the data write transistor T4 is electrically connected to the data line 1031 to receive data signals.

[0067] For example, in Fig. 3, Fig. 5, Fig. 7 and Fig. As shown in Figure 8, the first conductive layer 102 further includes a third interconnection structure 1027, and the first electrode of the sixth transistor T6 (first light-emitting control transistor) is electrically connected to the second electrode of the second transistor T2 (threshold compensation transistor) via the third interconnection structure 1027. For example, the third interconnection structure 1027 is a branch part included in the power supply signal interconnection line 1023.

[0068] For example in Fig. 5B, Fig. 6, Fig. 7 and Fig. As shown in Figure 8, an orthographic projection of the first electrode transmission line 1032 on the base substrate 101 overlaps with an orthographic projection of a part of the first interconnection structure 1021 on the base substrate 101. The first interconnection structure 1021 has a bent line shape extending as a whole to a side far from the nearest data line 1031. The first interconnection structure 1021 includes an overlapping part that overlaps with the first electrode transmission line 1032 and a non-overlapping part that does not overlap with the first electrode transmission line 1032, and the non-overlapping part is farther from the nearest data line 1031 than the overlapping part.

[0069] For example, in Fig. 5B, Fig. 6, Fig. 7 and Fig. As shown in Figure 8, the first power supply signal line 1033 includes a block-shaped part 1033a and a strip-shaped part 1033b extending as a whole along the first direction Y, and the strip-shaped part 1033b connects the adjacent block-shaped parts 1033a along the first direction Y. The main part 1023a of the power supply signal connection line 1023 is connected to the first power supply signal line 1033 to form a grid shape. For example, the main part 1023a of the power supply signal connection line 1023 is connected to the strip-shaped part 1033b of the first power supply signal line 1033 to form a grid shape.The arrangement of the lattice shape can electrically connect the first power supply signal lines 1033 of each subpixel, which contributes to reducing the voltage drop of the first power supply signal lines 1033 and thus improving the uniformity of the display of the display panel when the display substrate is used in the display panel.

[0070] For example, in Fig. 5B, Fig. 6 and Fig. 7, the block-shaped part 1033a overlaps with the light-emitting region of at least one of the later-mentioned first subpixels and third subpixels.

[0071] As in Fig. 5B, Fig. 6 and Fig. 7, the second conductive layer 103 includes, for example, a part (e.g., a part of the data line 1031) that overlaps with a light-emitting region of the second subpixels mentioned later.

[0072] For example, in Fig. 6, a width W1 of the block-shaped part 1033a in the second direction X is larger than a width W2 of the entire strip-shaped part 1033b in the second direction X, so that the area of ​​the second conductive layer 103 can be further reduced to save space.

[0073] For example in Fig. 5B, Fig. 6, Fig. 7 and Fig. 8, the first electrode transmission line 1032 extends along the first direction Y, and wherein the first electrode transmission line 1032 obscures a part of the first connection structure 1021 at an end position of the first electrode transmission line 1032 near the first connection structure 1021, ie, an orthographic projection of the end of the first electrode transmission line 1032 near the first connection structure 1021 on the base substrate 101 overlaps with an orthographic projection of a part of the first connection structure 1021 on the base substrate 101.

[0074] For example, as in Fig. 6 and Fig. 8, the strip-shaped part 1033b includes a first strip-shaped part 1033b1 and a second strip-shaped part 1033b2 arranged opposite one another, and a third strip-shaped part 1033b3 connecting the first strip-shaped part 1033b1 and the second strip-shaped part 1033b2. The extension directions of the first strip-shaped part 1033b1 and the second strip-shaped part 1033b2 are parallel to the first direction Y, and the third strip-shaped part 1033b3 connects central regions of the first strip-shaped part 1033b1 and the second strip-shaped part 1033b2. For example, the extension direction of the third strip-shaped part 1033b3 may be parallel to the second direction X, but may also be not parallel to the second direction X but intersect with the second direction X.

[0075] For example, in one example, a planar shape of the first strip-shaped part 1033b1, the second strip-shaped part 1033b2, and the third strip-shaped part 1033b3 may be H-shaped.

[0076] For example, in one example, the stripe-shaped part 1033b has a hollow structure, and this structural configuration can reduce the area of ​​the second conductive layer 103 and thereby save space.

[0077] For example, in Fig. 3, Fig. 5B, Fig. 6, Fig. 7 and Fig. 8, the first conductive layer 102 further includes a third connection part 1026, and the second electrode of the sixth transistor T6 (first light emission control transistor) is electrically connected to the first electrode of the light-emitting element via the third connection part 1026 and the first electrode transmission line 1032.

[0078] Fig. For example, Fig. 9 is a partial schematic structure diagram of the first active layer in the Fig. 5B. As shown in the Fig. 5B to Fig. As shown in Figure 9, the pixel circuit 110 includes, for example, a first active layer 105, which includes a channel region 1051 and a source-drain region 1052 of each transistor. The source-drain region 1052 may include, for example, a source region 1052a and a drain region 1052b.

[0079] Fig. For example, FIG. 9 schematically shows that the first active layer 105 is formed by patterning a semiconductor material. The first active layer 105 can be used to form the active layers of the aforementioned driver transistor T3, the fourth transistor T4 (data write transistor), the fifth transistor T5 (second light emission control transistor), the sixth transistor T6 (first light emission control transistor), and the seventh transistor T7 (second reset control transistor) to form the channel regions of the aforementioned transistors. The first active layer 105 includes an active layer pattern (channel region) and a doped region pattern (source-drain region) of the aforementioned transistor of each subpixel, and the active layer pattern and the doped region pattern of the aforementioned transistor in the same pixel circuit are integrally formed.

[0080] In Fig. For example, in Fig. 9, each dashed rectangular frame shows parts of the above-mentioned metal layer overlapping with the first active layer 105 to serve as channel regions of the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively. The parts of the first active layer on both sides of each channel region 1051 are treated conductively by a process such as ion doping as the first electrode and second electrode of each transistor, i.e., the source-drain region 1052. The source electrode and drain electrode of each transistor may be symmetrically constructed, so there may be no difference in physical structure between the source electrode and the drain electrode.In the embodiment of the present disclosure, in order to distinguish the transistors except the gate electrode as the control electrode, one of the source electrode and the drain electrode is directly referred to as the first electrode and the other of the source electrode and the drain electrode is directly referred to as the second electrode, so that the first electrode and the second electrode of all or part of the transistors in the embodiment of the present disclosure can be interchanged as needed.

[0081] For example in Fig. 9, the first active layer 105 comprises a third active part 23, a fourth active part 24, a fifth active part 25, a sixth active part 26, a seventh active part 27, an eighth active part 28, a ninth active part 29, a tenth active part 210 and an eleventh active part 211.The third active part 23 is used to form a channel region of the driver transistor T3; the fourth active part 24 is used to form a channel region of the fourth transistor T4; the fifth active part 25 is used to form a channel region of the fifth transistor T5; the sixth active part 26 is used to form the channel region of the sixth transistor T6; the seventh active part 27 is used to form a channel region of the seventh transistor T7; the eighth active part 28 is connected to a side of the fifth active part 25 remote from the third active part 23, and the ninth active part 29 is connected between the eighth active part 28 in the first pixel circuit P1 and the eighth active part 28 in the second pixel circuit P2.The tenth active part 210 is connected between the sixth active part 26 and the seventh active part 27, and the eleventh active part 211 is connected between the sixth active part 26 and the third active part 23. The eighth active part 28 can be used to form the first electrode of the fifth transistor T5. For example, in the embodiment of the present disclosure, the eighth active parts 28 in two adjacent pixel circuits are connected by the ninth active part 29, so that the voltage difference between the first power supply terminals in the adjacent pixel circuits can be reduced.

[0082] As in Fig. As shown in Figure 9, the first active layer 105 may be made of, for example, amorphous silicon, polysilicon, etc. Note that the source region and the drain region may be regions doped with n-type or p-type impurities. For example, in one example, the first active layer may be formed from polysilicon material, and accordingly, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be low-temperature p-type polysilicon thin-film transistors.

[0083] For example, a side of the first active layer 105 remote from the base substrate 101 is provided with a metal layer including the scanning signal line, the reset control signal line, the light emission control signal line, and the gate electrodes of the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0084] For example, the display substrate includes a third conductive layer. Fig. For example, Fig. 10 is a partial schematic structure diagram of the third conductive layer in the Fig. 5B. As shown in Fig. 5B and Fig. 10, the third conductive layer 106 includes a second gate line 1061, a light emission control signal line 1062, a second reset signal line 1063, and a second conductive part 1064.

[0085] In combination with Fig. 5B, Fig. 9 and Fig. 10, for example, an orthographic projection of the second gate line 1061 on the base substrate 101 extends along the second direction X and overlaps with an orthographic projection of the fourth active part 24 on the base substrate 101, wherein a partial structure of the second gate line 1061 is used to form the gate electrode of the fourth transistor T4. The second gate line 1061 can be used to connect the second gate drive signal terminal G2 in Fig. 3 to provide.

[0086] In combination with Fig. 5B, Fig. 9 and Fig. 10, for example, an orthographic projection of the light emission control signal line 1062 on the base substrate 101 extends along the second direction X and overlaps with the orthographic projection of the sixth active part 26 on the base substrate 101, wherein a partial structure of the light emission control signal line 1062 is used to form the gate electrode of the sixth transistor T6. The light emission control signal line 1062 can be used to connect the light emission control signal terminal EM in Fig. 3. For example, an orthographic projection of the light emission control signal line 1062 on the base substrate 101 may also overlap with an orthographic projection of the fifth active part 25 on the base substrate 101, wherein a partial structure of the light emission control signal line 1062 is used to form the gate electrode of the fifth transistor T5.

[0087] In combination with Fig. 5B, Fig. 9 and Fig. 10, for example, an orthographic projection of the second reset signal line 1063 on the base substrate 101 extends along the second direction X and overlaps with an orthographic projection of the seventh active part 27 on the base substrate 101. A partial structure of the second reset signal line 1063 is used to form the gate electrode of the seventh transistor T7, and the second gate line 1061 in the pixel circuit 110 of a present row is multiplexed as the second reset signal line 1063 in the pixel circuit 110 of an adjacent row. The second reset signal line 1063 can be used to connect the second reset signal terminal Re2 in Fig. 3. This arrangement can, for example, improve the integration of the pixel circuit and reduce the layout area of ​​the pixel circuit.

[0088] In combination with Fig. 5B and Fig. For example, in FIG. 10, an orthographic projection of the second gate line 1061 on the base substrate 101, an orthographic projection of the light emission control signal line 1062 on the base substrate 101, and an orthographic projection of the second reset signal line 1063 on the base substrate 101 all extend along the second direction X and are substantially parallel to each other. It should be noted that an orthographic projection of a specific pattern on the base substrate extends along a specific direction, which can be understood as an orthographic projection of the pattern on the base substrate extending straight or curved along the direction, and is not limited by the embodiment of the present disclosure.

[0089] In combination with Fig. 5B, Fig. 9 and Fig. 10, for example, an orthographic projection of the second conductive part 1064 on the base substrate 101 and an orthographic projection of the third active part 23 on the base substrate 101 overlap, with the second conductive part 1064 forming the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor C. For example, in the same pixel circuit 110, the orthographic projection of the second conductive part 1064 on the base substrate 101 is located between the orthographic projection of the second gate line 1061 on the base substrate 101 and the orthographic projection of the light emission control signal line 1062 on the base substrate 101.An orthographic projection of the second reset signal line 1063 on the base substrate 101 is located on a side of the orthographic projection of the light emission control signal line 1062 on the base substrate 101 that is remote from the orthographic projection of the second conductive part 1064 on the base substrate 101.

[0090] For example, the display substrate may use the third conductive layer 106 as a mask to perform a conductive treatment on the first active layer 105, that is, a region covered by the third conductive layer 106 in the first active layer 105 may form a channel region of the respective transistor, and a region not covered by the third conductive layer 106 in the first active layer 105 may form a conductor structure.

[0091] For example, the display substrate also includes a conductive film layer. Fig. For example, Fig. 11 is a partial schematic structure diagram of the conductive film layer in the Fig. 5B. As shown in Fig. 5B and Fig. 11, the conductive film layer 107 is located between the third conductive layer 106 and the second conductive layer 103, wherein the conductive film layer 107 includes a first initial signal line 1071, a third reset signal line 1072, a third gate line 1073, and a first conductive part 1074.

[0092] As in Fig. 11, for example, the first initial signal line 1071 is used to connect the first initial signal terminal in Fig. 3, wherein the third reset signal line 1072 is used to connect the first reset signal terminal in Fig. 3, and wherein the third gate line 1073 is used to connect the first gate drive signal terminal G1 in Fig. 3. An orthographic projection of the first initial signal line 1071 on the base substrate 101, an orthographic projection of the third reset signal line 1072 on the base substrate 101, and an orthographic projection of the third gate line 1073 on the base substrate 101 may all extend along the second direction X.

[0093] In combination with Fig. 3 and Fig. 11, for example, the orthographic projection of the first initial signal line 1071 on the base substrate 101 is located on one side of the orthographic projection of the first reset signal line (which is used in the description of Fig. 3) on the base substrate 101, which is away from the orthographic projection of the second conductive part 1064 on the base substrate 101.

[0094] In combination with Fig. 3, Fig. 5B and Fig. 11, for example, the third reset signal line 1072 is connected to the first reset signal line through a through-hole, wherein the orthographic projection of the third reset signal line 1072 on the base substrate 101 overlaps with the orthographic projection of the first active part (contained in the subsequent fourth conductive layer) on the base substrate 101, wherein a partial structure of the third reset signal line 1072 is used to form the lower gate electrode of the first transistor T1. The orthographic projection of the third gate line 1073 on the base substrate 101 overlaps with the orthographic projection of the second active part (contained in the subsequent fourth conductive layer) on the base substrate 101, wherein a partial structure of the third gate line 1073 is used to form the lower gate electrode of the second transistor T2.

[0095] For example in combination with Fig. 3, Fig. 5B and Fig. 11, the first conductive part 1074 comprises a main part 1074a, wherein the storage capacitor C also comprises a second electrode plate Cst2 opposite the first electrode plate Cst1, and wherein the main part 1074a corresponds to two second electrode plates. For example, the first conductive part 1074 further comprises a bridge part 1074b connecting two main parts 1074a adjacent in the second direction X, i.e., connecting two adjacent second electrode plates Cst2, wherein the first conductive part 1074 further comprises a recess 1074c between the two second electrode plates Cst2.

[0096] For example, in combination with Fig. 3, Fig. 5B and Fig. 11, an orthographic projection of the first conductive layer 102 on the base substrate 101 and the orthographic projection of the recess 1074c on the base substrate 101 have no overlapping portion, and the orthographic projection of the second conductive layer 103 on the base substrate 101 and the orthographic projection of the recess 1074c on the base substrate 101 have no overlapping portion, so that the recess 1074c is not obscured by the first conductive layer 102 and the second conductive layer 103 to improve pixel transmittance. It should also be noted that the recess 1074c is also not obscured by another film layer having a light-shielding function.

[0097] For example, in combination with Fig. 3, Fig. 5B and Fig. 11, the first conductive part 1074 is also formed with an opening 1074d, wherein an orthographic projection of a through-hole on the base substrate 101 connected between the gate electrode of the driver transistor T3 and the first connection structure 1021 is located within an orthographic projection of the opening 1074d on the base substrate 101, so that the conductive structure in the through-hole and the first conductive part 1074 are insulated from each other.

[0098] For example, the display substrate also includes a second active layer. Fig. For example, Fig. 12 is a partial schematic structure diagram of the second active layer in the Fig. 5B. As shown in Fig. 5B and Fig. As shown in Figure 12, the second active layer 108 is located between the first active layer 105 and the second conductive layer 103. The second active layer 108 may include a first active portion 311, a second active portion 312, and a twelfth active portion 313 that are connected to each other. The first active portion 311 forms a channel region of the first transistor T1; the second active portion 312 forms a channel region of the second transistor T2; the twelfth active portion 313 is connected to an end of the second active portion 312 remote from the first active portion 311, and the first semiconductor layer includes the second active layer 108.

[0099] For example, in an example as shown in Fig. 12, the second active layer 108 may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.

[0100] For example, the first semiconductor layer forming the channel regions of the first transistor T1 and the second transistor T2 in the pixel circuit 110 may be arranged on a side remote from the base substrate 101 of a layer on which the active semiconductor pattern of the driver transistor T3 is located, wherein the first semiconductor layer may comprise an oxide semiconductor material.For example, in the case where the active layers in the first transistor T1 and the second transistor T2 of the pixel circuit are made of oxide semiconductors, because the oxide semiconductor transistors have the characteristics of good hysteresis characteristics, low leakage current, and low mobility, the oxide semiconductor transistors can be used instead of low-temperature polysilicon materials in the transistors to form a low-temperature polysilicon oxide (LTPO) pixel circuit, so as to realize low leakage current and improve the stability of the gate voltage of the transistors.

[0101] Of course, the embodiment of the present disclosure is not limited to the structure of the second active layer of the pixel circuit as shown in Fig. 12. In other examples, the first semiconductor layer of the channel regions of the first transistor T1 and the second transistor T2 may also be located on the same layer as the semiconductor layer of the channel regions of other transistors, ie, the first active layer may also comprise the channel regions of the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0102] For example, in combination with Fig. 5B, Fig. 11 and Fig. 12, an orthographic projection of the third gate line 1073 on the base substrate 101 may cover an orthographic projection of the second active portion 312 on the base substrate 101, and a partial structure of the third gate line 1073 may be used to form a lower gate electrode of the second transistor T2. An orthographic projection of the third reset signal line 1072 on the base substrate 101 may cover an orthographic projection of the first active portion 311 on the base substrate 101, and a partial structure of the third reset signal line 1072 may be used to form a lower gate electrode of the first transistor T1.

[0103] For example, the display substrate further comprises a fourth conductive layer. Fig. For example, Fig. 13 is a partial schematic structure diagram of the fourth conductive layer in the Fig. 5B. As shown in Fig. 5B and Fig. 13, the fourth conductive layer 109 is located between the second active layer 108 and the second conductive layer 103, and the fourth conductive layer 109 includes a first reset signal line 1091 and a first gate line 1092.

[0104] For example, in combination with Fig. 3, Fig. 5B, Fig. 12 and Fig. 13 an orthographic projection of the first reset signal line 1091 on the base substrate 101 and an orthographic projection of the first gate line 1092 on the base substrate 101 extend along the second direction X. The first reset signal line 1091 can be used to form a first reset signal terminal in Fig. 3. The orthographic projection of the first reset signal line 1091 on the base substrate 101 overlaps with the orthographic projection of the first active part 311 on the base substrate 101, and a partial structure of the first reset signal line 1091 is configured to form an upper gate electrode of the first transistor T1. At the same time, the first reset signal line 1091 can be connected to the third reset signal 1072 through a through-hole located in a wiring area at an edge of the display substrate.

[0105] In combination with Fig. 3, Fig. 5B, Fig. 11, Fig. 12 and Fig. 13, the first gate line 1092 may be used, for example, to connect the first gate drive signal terminal in Fig. 3. An orthographic projection of the first gate line 1092 on the base substrate 101 may cover an orthographic projection of the second active part 312 on the base substrate 101, and a partial pattern of the first gate line 1092 may be used to form an upper gate electrode of the second transistor T2. At the same time, the first gate line 1092 may be connected to the third gate line 1073 through a through-hole located in the wiring area at the edge of the display substrate.

[0106] For example, in combination with Fig. 5B, Fig. 10 and Fig. 13, in the same pixel circuit, the orthographic projection of the first gate line 1092 on the base substrate 101 is arranged between the orthographic projection of the second conductive part 1064 on the base substrate 101 and the orthographic projection of the second gate line 1061 on the base substrate 101, and the orthographic projection of the first reset signal line 1091 on the base substrate 101 is arranged on a side of the orthographic projection of the second gate line 1061 on the base substrate 101 that is away from the orthographic projection of the second conductive part 1064 on the base substrate 101.

[0107] In combination with Fig. 5B, Fig. 10 and Fig. 13, for example, in the same pixel circuit, the orthographic projection of the second conductive part 1064 on the base substrate 101 may be arranged between the orthographic projection of the first gate line 1092 on the base substrate 101 and the orthographic projection of the light emission control signal line 1062 on the base substrate 101. The orthographic projection of the first reset signal line 1091 on the base substrate 101 may be located on the side of the orthographic projection of the first gate line 1092 on the base substrate 101 that is remote from the orthographic projection of the second conductive part 1064 on the base substrate 101.

[0108] For example, in combination with Fig. 5B, Fig. 10 and Fig. 13, in the same pixel circuit, the orthographic projection of the second gate line 1061 on the base substrate 101 may be arranged between the orthographic projection of the first gate line 1092 on the base substrate 101 and the orthographic projection of the first reset signal line 1091 on the base substrate 101. The orthographic projection of the second reset signal line 1063 on the base substrate 101 may be located on a side of the orthographic projection of the light emission control signal line 1062 on the base substrate 101 that is remote from the orthographic projection of the second conductive part 1064 on the base substrate 101.

[0109] For example, in combination with Fig. 3, Fig. 5B, Fig. 7 and Fig. 11, a plurality of third connection structures 1027 included in the first conductive layer 102 are arranged in one-to-one correspondence with the plurality of repeating units, and the third connection structure 1027 is connected to the ninth active part 29 included in the first active layer 105 through a first through-hole connection part H1, and is connected to the bridge part 1074b (a part of the first conductive part 1074) included in the conductive film layer 107 through a second through-hole connection part H2 to connect the first electrode of the fifth transistor T5 and the second electrode plate Cst2 of the capacitor C. That is, the third connection structure 1027 includes a first through-hole connection part H1 for connecting the ninth active part 29. It should be noted that in the embodiments of the present disclosure, only a part of the through-holes is marked.

[0110] In combination with Fig. 5B, Fig. 7 and Fig. 8, for example, the sixth connection structure 1028 included in the first conductive layer 102 and the first electrode transmission line 1032 included in the second conductive layer 103 are connected by a third through-hole connection part H3.

[0111] For example, in combination with Fig. 3, Fig. 5B, Fig. 7, Fig. 8, Fig. 9 and Fig. 12, the third connection part 1026 is connected to an eleventh active part 211 through a fourth through-hole connection part H4, and the third connection part 1026 is connected to a twelfth active part 313 through a fifth through-hole connection part H5 to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driver transistor T3.

[0112] In combination with the Fig. 3, Fig. 5B, Fig. 7, Fig. 8 and Fig. 12, for example, the first connection structure 1021 is connected to a part of the second active layer 108 between the first active part 311 and the second active part 312 by a sixth through-hole connection part H6, and the first connection structure 1021 is connected to the second conductive part 1064 by a seventh through-hole connection part H7 to connect the first electrode of the second transistor T2 and the gate electrode of the driver transistor T3.

[0113] For example, in combination with Fig. 5B, Fig. 10 and Fig. 11, an opening 1074d is formed at the first conductive part 1074, and an orthographic projection of the seventh through-hole connecting part H7 on the base substrate 101 connected between the second conductive part 1064 and the first connecting structure 1021 is located within the orthographic projection of the opening 1074d on the base substrate 101, so that the conductive structure in the seventh through-hole connecting part H7 is isolated from the first conductive part 1074.

[0114] For example, in combination with Fig. 3, Fig. 5B, Fig. 7, Fig. 8, Fig. 11 and Fig. 12, the first connection part 1024 may be connected to a part of the second active layer on a side of the first active part 311 remote from the second active part 312 through an eighth through-hole connection part H8, and the first connection part 1024 may be connected to the first initial signal line 1071 through a ninth through-hole connection part H9 to connect the second electrode of the first transistor T1 and the first initial signal terminal. For example, in two adjacent repeating units in the second direction X, two adjacent pixel circuits may share the same first connection part 1024.

[0115] In combination with Fig. 3, Fig. 5B, Fig. 7 and Fig. 9, the second connection part 1025 may be connected, for example, through a tenth through-hole connection part H10 to a part of the first active layer 105 located on a side of the fourth active part 24 remote from the third active part 23, in order to connect the first electrode of the fourth transistor T4.

[0116] For example, in combination with Fig. 3, Fig. 5B, Fig. 7, Fig. 8 and Fig. 9 the second initial signal line 1022 can be used to connect the second initial signal terminal in Fig. 3, and the second initial signal line 1022 may be connected through an eleventh through-hole connection part H11 to a part of the first active layer 105 located on a side of the seventh active part 27 remote from the sixth active part 26, to connect the second electrode of the seventh transistor T7 and the second initial signal terminal Vinit2.

[0117] For example, the display substrate further includes a plurality of subpixels, and each of the plurality of subpixels includes the pixel circuit 110 and the light-emitting element in any of the above examples. Fig. 14 is a schematic diagram of a partial pixel array structure on a display substrate provided according to an embodiment of the present disclosure, Fig. 15A is a layout diagram of a stack of a pixel circuit and a first electrode of the light-emitting element in Fig. 5B , and Fig. 15B is another layout diagram of a stack of a pixel circuit and a first electrode of the light-emitting element in Fig. 5B. Compared with Fig. 15A is Fig. 15B is additionally provided with a light-shielding layer, and other structural settings are the same. As shown in the Fig. 14 and Fig. 15B, the plurality of subpixels 40 includes, for example, a plurality of first subpixels 401, a plurality of second subpixels 402, and a plurality of third subpixels 403. For example, one of the first subpixels 401 and the third subpixel 403 is a red subpixel that emits red light, the other of the first subpixels 401 and the third subpixel 403 is a blue subpixel that emits blue light, and the second subpixel 402 is a green subpixel that emits green light.

[0118] For example, in one example, the first subpixel 401 is a red subpixel, the third subpixel 403 is a blue subpixel, and the second subpixel 402 is a green subpixel. The area of ​​the light-emitting region of the blue subpixel is larger than the area of ​​the light-emitting region of the red subpixel, and the area of ​​the light-emitting region of the red subpixel is larger than the area of ​​the light-emitting region of the green subpixel.

[0119] For example, the names of the first subpixel, the second subpixel, and the third subpixel may be interchanged, for example, the first subpixel may be a green subpixel, the second subpixel a blue subpixel, and the third subpixel a red subpixel; alternatively, the first subpixel may be a blue subpixel, the second subpixel a red subpixel, and the third subpixel a green subpixel, and so on. Embodiments of the present disclosure are not limited to this.

[0120] For example, as in Fig. 14, a plurality of first subpixels 401 and a plurality of third subpixels 403 are arranged alternately along the second direction X and the first direction Y to form a plurality of first pixel rows R1 and a plurality of first pixel columns C1, and a plurality of second subpixels 402 are arranged in an array along the second direction X and the first direction Y to form a plurality of second pixel rows R2 and a plurality of second pixel columns C2. The plurality of first pixel rows R1 and the plurality of second pixel rows R2 are arranged alternately along the first direction Y and offset in the second direction X. The plurality of first pixel columns C1 and the plurality of second pixel columns C2 are arranged alternately along the second direction X and offset in the first direction Y. The second direction X intersects with the first direction Y.For example, the second direction X and the first direction Y can be perpendicular to each other. For example, the second direction X and the first direction Y can be swapped.

[0121] For example, in Fig. 14, a second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along the second direction X. Two second sub-pixels 402 in a second sub-pixel pair 4020 are each a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, in a second pixel column C2, the first pixel blocks 4020a and the second pixel blocks 4020b are alternately arranged along the first direction Y.

[0122] As in Fig. 14, for example, at least two second pixel rows R2 include a plurality of second sub-pixel pairs 4020 arranged along the second direction X. Two second sub-pixels 402 in the at least two second sub-pixel pairs 4020 are each a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, the first pixel blocks 4020a and the second pixel blocks 4020b in at least two second pixel columns C2 are alternately arranged along the first direction Y.

[0123] As in Fig. 14, for example, every second pixel row R2 includes a plurality of second sub-pixel pairs 4020 arranged along the second direction X. Two second sub-pixels 402 in each second sub-pixel pair 4020 are each a first pixel block 4020a and a second pixel block 4020b, and the first pixel block 4020a and the second pixel block 4020b are alternately arranged along the second direction X. For example, in every second pixel column C2, the first pixel blocks 4020a and the second pixel blocks 4020b are alternately arranged along the first direction Y.

[0124] As in Fig. 14, for example, a plurality of subpixels 40 comprises a plurality of minimum repeat units A, wherein a minimum repeat unit A comprises a first subpixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third subpixel 403. For example, at least two minimum repeat units A comprise a first subpixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third subpixel 403. For example, each minimum repeat unit A comprises a first subpixel 401, a first pixel block 4020a, a second pixel block 4020b, and a third subpixel 403. For example, each minimum repeat unit A comprises two rows and four columns of subpixels 40.

[0125] As in Fig. 14, for example, in a minimum repeat unit A, the first pixel block 4020a and the first subpixel 401 form a first pixel unit A1, and the second pixel block 4020b and the third subpixel 403 form a second pixel unit A2. For example, in at least two minimum repeat units A, the first pixel block 4020a and the first subpixel 401 form a first pixel unit A1, and the second pixel block 4020b and the third subpixel 403 form a second pixel unit A2. For example, in each minimum repeat unit A, the first pixel block 4020a and the first subpixel 401 form a first pixel unit A1, and the second pixel block 4020b and the third subpixel 403 form a second pixel unit A2.

[0126] As mentioned above, the first pixel unit A1 and the second pixel unit A2 are not pixels in the strict sense, i.e., a pixel defined entirely by a first subpixel, a second subpixel, and a third subpixel. The minimum repeat unit here refers to the fact that the structure of the pixel arrangement may include a plurality of the minimum repeat units that are repeatedly arranged.

[0127] For example, Fig. 16 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure. As in Fig. 14 to Fig. 16, the display substrate 100 includes a base substrate 101 and a plurality of subpixels 40 arranged on the base substrate 101. At least a portion of the subpixels 40 includes a light-emitting element 120 and a pixel circuit 110. The light-emitting element 120 includes a light-emitting functional layer 122, and a first electrode 121 and a second electrode 123 located on both sides of the light-emitting functional layer 122 along the direction perpendicular to the base substrate 101. The first electrode 121 is located between the light-emitting functional layer 122 and the base substrate 101.

[0128] For example, in Fig. 16, the display substrate 100 further comprises a pixel definition pattern 50, wherein the direction perpendicular to a main surface of the base substrate 101 is a third direction Z that is perpendicular to the plane in which the first direction Y and the second direction X are arranged, wherein the pixel definition pattern 50 is arranged on a side of the first electrode 121 of the light-emitting element 120 remote from the base substrate 101, and wherein the pixel definition pattern 50 comprises a plurality of pixel openings 51 and defining parts 52 surrounding the plurality of pixel openings 51, wherein a plurality of light-emitting elements 120 are arranged at least partially within the plurality of pixel openings 51. Fig. 16 schematically shows that the side of the first electrode 121 of the light-emitting element 120 remote from the second electrode 123 is provided with a structural layer 011, and the structural layer 011 may include the base substrate 101, a layer in which the active semiconductor pattern is located, a film layer in which the gate line is located, a film layer in which the data line is located, and film layers such as a plurality of insulating layers.

[0129] For example, the defining portion 52 is a structure that defines the pixel opening 51. The material of the defining portion 52 may include, for example, polyimide, acrylic, or polyethylene terephthalate, and so on.

[0130] For example, the pixel opening 51 of the pixel definition pattern 50 is configured to define the light-emitting region 124 of the light-emitting element 120. For example, the light-emitting elements 120 of a plurality of subpixels 40 may be arranged in one-to-one correspondence with a plurality of pixel openings 51. For example, the light-emitting element 120 may include a portion located within the pixel opening 51 and a portion overlapping the defining portion 52 in a direction perpendicular to the base substrate 101.

[0131] For example, the pixel opening 51 of the pixel definition pattern 50 is configured to expose the first electrode 121 of the light-emitting element 120, and the exposed first electrode 121 at least partially contacts the light-emitting functional layer 122 in the light-emitting element 120. For example, at least a part of the first electrode 121 is located between the defining part 52 and the base substrate 101. For example, when the light-emitting functional layer 122 is located in the pixel opening 51 of the pixel definition pattern 50, the first electrode 121 and the second electrode 123 located on both sides of the light-emitting functional layer 122 can drive the light-emitting functional layer 122 in the pixel opening 51 of the pixel definition pattern 50 to emit light.For example, the above-mentioned light-emitting region 124 may refer to an effective light-emitting area of ​​the light-emitting element 120, and the shape of the light-emitting region 124 may refer to a two-dimensional shape. For example, the shape of the light-emitting region 124 may be the same as the shape of the pixel opening 51 of the pixel definition pattern 50. For example, the pixel opening 51 of the pixel definition pattern 50 may have a small dimension on the side near the base substrate 101 and a large dimension on the side far from the base substrate 101. For example, the shape of the light-emitting region 124 may be approximately the same as the size and shape of the pixel opening 51 of the pixel definition pattern 50 on the side near the base substrate 101.

[0132] For example, the first electrode 121 may be an anode, and the second electrode 123 may be a cathode. The cathode may be made of a material with high conductivity and a low work function, for example, and the cathode may be made of a metal material. The anode may be made of a conductive material with a high work function, for example.

[0133] For example, the direction indicated by the first direction arrow Y is upward, and the direction indicated by the second direction arrow X is right. The first pixel block 4020a in the first pixel unit A1 is located at the bottom right of the first subpixel 401, and the second pixel block 4020b in the second pixel unit A2 is located at the bottom right of the third subpixel 403. In the first pixel unit and the second pixel unit of the display substrate provided by the embodiment of the present disclosure, the pixel space and design are optimized by changing the first subpixel and the third subpixel to borrow the second subpixel in different positions, thereby improving the flatness of the first electrode of the light-emitting element, optimizing the pixel space structure, and further reducing the bottom bezel.

[0134] For example, as in Fig. 14 to Fig. As shown in Figure 16, a first subpixel 401 may form a first pixel unit with a second subpixel 402 located at the upper right or lower right of it; similarly, a third subpixel 403 may form a second pixel unit with the second subpixel 402 located at the upper right or lower right of it. In the embodiment of the present disclosure, the fifth transistor T5 is located in the first subpixel 401 in the light-emitting region, and the first subpixel 401 and the second subpixel 402 located at the upper right of the first subpixel 401 form a first pixel unit, so that the design of the pixel circuit is facilitated, the possibility of affecting the flatness of the pixel by changing the shape of the pad having a planarization function in the second conductive layer is reduced, and the occurrence of color shifts can be prevented.In addition, the influence of the capacitance of the node corresponding to the first electrode of the light-emitting element can be reduced, for example, to prevent image quality from being degraded at low gray levels. If the capacitance is larger here, the capacitance of the node corresponding to the first electrode of the light-emitting element must be filled first at low gray levels, resulting in a decrease in the voltage charged at the node at low gray levels, so that the time for the pixel to light up becomes longer (response time), which further degrades image quality. Similarly, in the third subpixel 403, the fifth transistor T5 is located in the light-emitting region, and the third subpixel 403 forms a second pixel unit with the second subpixel 402 located to the upper right of the third subpixel 403, which can facilitate the design of the pixel circuit.

[0135] For example, in Fig. 5A, Fig. 5B and Fig. As shown in Figure 15, two data lines 1031 are arranged on either side of the first subpixel 401 along the second direction X. For example, two data lines 1031 are arranged between the first subpixel 401 and the third subpixel 403, which are adjacent in the second direction X.

[0136] For example, the Fig. 14 may also include a first electrode layer 501 included in the display substrate, wherein the first electrode layer 501 is disposed on a side of the second conductive layer 103 remote from the base substrate 101, and the first electrode layer 501 includes a plurality of electrode parts 502, each of the electrode parts 502 including a body part 5021 and a supplementary part 5022 connected to each other. An orthographic projection of the supplementary part 5022 on the base substrate 101 at least partially overlaps with an orthographic projection of the first electrode transmission line 1032 on the base substrate 101, wherein each of the electrode parts 502 corresponds to one of the first subpixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third subpixel 403.The supplementary part 5022 is arranged on the electrode part 502 to increase the overlap area between the electrode part 502 and the second conductive layer 103, thereby increasing the self-capacitance of the electrode part of the light-emitting unit and further extending the charging time of the light-emitting unit before it emits light. In the embodiment of the present disclosure, the period in which the current output of the driving transistor T3 is unstable may be entirely or at least partially within the charging time of the light-emitting unit. That is, this setting can reduce the time the light-emitting unit emits light during the period in which the current output of the driving transistor T3 is unstable, so this setting can mitigate the flicker problem during operation of the display substrate.

[0137] For example, as in Fig. 14, the plurality of electrode parts 502 includes a first electrode part 502a, a second electrode part 502b and a third electrode part 502c having three different colors, wherein the first electrode part 502a corresponds to the first subpixel 401, the second electrode part 502b corresponds to any one of the first pixel block 4020a and the second pixel block 4020b, and the third electrode part 502c corresponds to the third subpixel 403.

[0138] For example, cover in combination with Fig. 14 and Fig. 15B, the first electrode part 502a and the third electrode part 502c in the first direction Y form a block-shaped part 1033a included in the first power supply signal line 1033, and the second electrode part 502b covers a part of the data line 1031 and a part of the first electrode transmission line 1032, and wherein an orthographic projection of the second electrode part 502b on the base substrate 101 is limited between orthographic projections of two adjacent first electrode transmission lines 1032 on the base substrate 101, so that the orthographic projection of the second electrode part 502b on the base substrate 101 and the orthographic projection of the first power supply signal line 1033 on the base substrate 101 have no overlapping part.The overlap area of ​​the orthographic projection of the first electrode part 502a on the base substrate 101 with the orthographic projection of the first power supply signal line 1033 on the base substrate 101 is larger than the overlap area of ​​the orthographic projection of the second electrode part 502b on the base substrate 101 with the orthographic projection of the first power supply signal line 1033 on the base substrate 101 and larger than the overlap area of ​​the orthographic projection of the third electrode part 502c on the base substrate 101 with the orthographic projection of the first power supply signal line 1033 on the base substrate 101.

[0139] For example, in combination with Fig. 14 and Fig. 15B, the overlap area of ​​the orthographic projection of the third electrode part 502c on the base substrate 101 with the orthographic projection of the first power supply signal line 1033 on the base substrate 101 is also larger than the overlap area of ​​the orthographic projection of the second electrode part 502b on the base substrate 101 with the orthographic projection of the first power supply signal line 1033 on the base substrate 101.

[0140] In combination with Fig. 14 and Fig. 15B, for example, the orthographic projection of the supplementary part 5022 of each of the electrode parts 502 on the base substrate 101 at least partially overlaps the orthographic projection of the second conductive layer 103 on the base substrate 101, and the supplementary part 5022 is electrically connected to the second conductive layer 103 through a corresponding through-hole. For example, the supplementary part 5022a of the first electrode part 502a is connected to the first electrode transmission line 1032 through the first through-hole V1. The supplementary part 5022b of the second electrode part 502b is connected to the first electrode transmission line 1032 through a second through-hole V2. The supplementary part 5022c of the third electrode part 502c is connected to the first electrode transmission line 1032 through a third through-hole V3.

[0141] In combination with Fig. 14 and Fig. 15B, for example, the first electrode part 502a corresponds to a blue subpixel emitting blue light, the second electrode part 502b corresponds to a green subpixel emitting green light, and the third electrode part 502c corresponds to a red subpixel emitting red light.

[0142] The display substrate also includes, for example, a light-shielding layer. For example, Fig. 17 is a schematic partial structure diagram of a light-shielding layer in the Fig. 5B and Fig. 15 B. As shown in Fig. 17, the light-shielding layer 111 may include a plurality of light-shielding parts 111a distributed in the second direction X and the first direction Y, wherein adjacent light-shielding parts 111a are connected to each other in the second direction X, and wherein connection lines connecting adjacent light-shielding parts 111a are located on the same straight line, the extending directions of the connection lines being parallel or substantially parallel to the second direction X. Two adjacent light-shielding parts 111a in the first direction Y are also connected to each other, wherein the light-shielding layer 111 may be a conductor structure, for example, the light-shielding layer 111 may be a light-shielding metal layer.

[0143] For example, in Fig. 3, Fig. 5B, Fig. 15B and Fig. 17, the light shielding layer 111 can be connected to a stable power supply terminal, for example, the light shielding layer 111 can be connected to the first power supply terminal, the first initial signal terminal and the second initial signal terminal in Fig. 3, wherein the light-shielding layer 111 can stabilize the voltage of the second conductive part 1064, thereby reducing the voltage fluctuation of the gate electrode of the driver transistor T3 in the light-emitting stage.

[0144] Fig. For example, Figure 18 is a layout diagram of a stack of a light-shielding layer and a first active layer provided by an embodiment of the present disclosure. As shown in Fig. 18, the orthographic projection of the light-shielding layer 111 on the base substrate 101 can cover the orthographic projection of the third active part 23 on the base substrate 101, and the light-shielding layer 111 can reduce the influence of illumination on the characteristics of the driver transistor T3.

[0145] Fig. For example, Figure 19 is a schematic circuit structure diagram of another pixel circuit provided by an embodiment of the present disclosure. As shown in Fig. 19, the pixel circuit 610 includes a first transistor T1, a second transistor T2, a third transistor (driver transistor) T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor C. That is, the pixel circuit 610 may include eight transistors (the first transistor T1 to the eighth transistor T8), a storage capacitor C, and a plurality of signal lines (data line Data, first scan signal line Gate, second scan signal line GateN, reset control signal line Reset, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, second power supply line VSS, and light emission control signal line EM).

[0146] As in Fig. For example, as shown in Figure 19, the gate electrode of the first transistor T1 is connected to the reset control signal line Reset, the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor T1 is connected to the N5 node. The gate electrode of the second transistor T2 is connected to the first scan signal line Gate, the first electrode of the second transistor T2 is connected to the N5 node, and the second electrode of the second transistor T2 is connected to the N3 node. The gate electrode of the driver transistor T3 is connected to the N1 node, the first electrode of the driver transistor T3 is connected to the N2 node, and the second electrode of the driver transistor T3 is connected to the N3 node.The gate electrode of the fourth transistor T4 is connected to the first scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the N2 node. The gate electrode of the fifth transistor T5 is connected to the light emission control signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the N2 node. The gate electrode of the sixth transistor T6 is connected to the light emission control signal line EM, the first electrode of the sixth transistor T6 is connected to the N3 node, and the second electrode of the sixth transistor T6 is connected to the N4 node (i.e., the first electrode of the light-emitting element).The gate electrode of the seventh transistor T7 is connected to the first scanning signal line Gate or the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the N4 node. The gate electrode of the eighth transistor T8 is connected to the second scanning signal line GateN, the first electrode of the eighth transistor T8 is connected to the N5 node, and the second electrode of the eighth transistor T8 is connected to the N1 node. A first terminal of the storage capacitor C is connected to the first power supply line VDD, and a second terminal of the storage capacitor C is connected to the N1 node.

[0147] Specifically, the gate electrode of the first transistor T1 is connected to the reset control signal line, the first electrode of the first transistor T1 is connected to the first initial signal line, and the second electrode of the first transistor T1 is connected to the first electrode of the eighth transistor T8 and the first electrode of the second transistor T2. The gate electrode of the second transistor T2 is connected to the first scanning signal line, and the second electrode of the second transistor T2 is connected to the second electrode of the driver transistor T3 and the first electrode of the sixth transistor T6.The gate electrode of the driver transistor T3 is connected to the second electrode of the eighth transistor T8 and the first electrode plate Cst1 of the storage capacitor C, the first electrode of the driver transistor T3 is connected to the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5, and the second electrode of the driver transistor T3 is connected to the second electrode of the second transistor T2 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line, the first electrode of the fourth transistor T4 is connected to the data line Data, and the second electrode of the fourth transistor T4 is connected to the first electrode of the driver transistor T3 and the second electrode of the fifth transistor T5.The gate electrode of the fifth transistor T5 is connected to the first light-emitting control signal line, the first electrode of the fifth transistor is connected to the first power supply signal line and the second electrode plate Cst2 of the storage capacitor C, and the second electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4 and the first electrode of the driver transistor T3. The gate electrode of the sixth transistor T6 is connected to the first light-emitting control signal line, the first electrode of the sixth transistor T6 is connected to the second electrode of the driver transistor T3 and the second electrode of the second transistor T2, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element and the second electrode of the seventh transistor T7.The gate electrode of the seventh transistor T7 is connected to the first scanning signal line or the reset control signal line, the first electrode of the seventh transistor T7 is connected to the second initial signal line, and the second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 and the first electrode of the light-emitting element. The gate electrode of the eighth transistor T8 is connected to the second scanning signal line, the first electrode of the eighth transistor T8 is connected to the second scanning signal line, the first electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1 and the first electrode of the second transistor T2, and the second electrode of the eighth transistor T8 is connected to the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor C.The first electrode plate Cst1 of the storage capacitor C is connected to the gate electrode of the driver transistor T3 and the second electrode of the eighth transistor T8, and the second electrode plate Cst2 of the storage capacitor C is connected to the first power supply signal line.

[0148] For example, in some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be N-type thin-film transistors, and the eighth transistor T8 may be a P-type thin-film transistor; alternatively, the first transistor T1 to the seventh transistor T7 may be P-type thin-film transistors, and the eighth transistor T8 may be an N-type thin-film transistor.

[0149] For example, in some example embodiments, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), and the eighth transistor T8 may be an indium gallium zinc oxide (IGZO) thin-film transistor.

[0150] For example, compared to the low-temperature polysilicon thin-film transistor, the indium gallium zinc oxide thin-film transistor generates less leakage current. Therefore, forming the eighth transistor T8 as an indium gallium zinc oxide thin-film transistor can significantly reduce the generation of leakage current, thus improving the problem of flicker at low frequencies and low brightness of the display substrate. The first transistor T1 and the second transistor T2 do not need to be formed as indium gallium zinc oxide thin-film transistors, and since the dimensions of low-temperature polysilicon thin-film transistors are generally smaller than those of indium gallium zinc oxide thin-film transistors, the occupied space of the pixel circuit in the embodiment of the present disclosure will be relatively small, which is beneficial for improving the resolution of the subsequent display panel.

[0151] For example, the Fig. The pixel circuit shown in Figure 19 combines both good switching characteristics of LTPS-TFT and low leakage characteristics of oxide-TFT, enabling low frequency driving (1Hz~60Hz) and greatly reducing the power consumption of the display substrate.

[0152] For example, the display substrate further comprises a light-emitting element EL, wherein the second electrode of the light-emitting element EL is connected to a second power supply line VSS, wherein the signal of the second power supply line VSS is intended to continuously provide a low-level signal and the signal of the first power supply line VDD is intended to continuously provide a high-level signal. The signal of the first scanning signal line Gate is the scanning signal in the pixel circuits of the present display line, and the signal of the reset control signal line Reset is the scanning signal in the pixel circuit of the previous display line, iefor the n-th display line, the first scanning signal line Gate is Gate(n) and the reset control signal line Reset is Gate(n-1), wherein the signal of the reset control signal line Reset of the present display line and the signal of the first scanning signal line Gate in the pixel circuit of the previous display line may be the same in order to reduce the signal lines on the display substrate to realize narrow borders for display substrates.

[0153] For example, in some exemplary embodiments, the first scanning signal line Gate, the second scanning signal line GateN, the reset control signal line Reset, the light emission control signal line EM, the first initial signal line Vinit1 and the second initial signal line Vinit2 all extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD and the data line Data all extend in the vertical direction.

[0154] In some example embodiments, the light-emitting element 620 may be, for example, an organic electroluminescent diode (OLED) comprising a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) arranged one above the other.

[0155] Fig. For example, Fig. 20 is a timing diagram of the respective nodes in a driving process of the pixel circuit in Fig. 19. In the following, an exemplary embodiment of the present disclosure is described based on the working process of the Fig. 20 shown pixel circuit. The pixel circuit in Fig. 19 comprises eight transistors (first transistor T1 to eighth transistor T8) and a storage capacitor C, wherein the first transistor T1 to seventh transistor T7 are, for example, P-type transistors and the eighth transistor T8 is an N-type transistor, wherein the gate electrode of the seventh transistor T7 is connected to the first scanning signal line Gate.

[0156] In combination with Fig. 19 and Fig. 20, the working process of the pixel circuit may, for example, include:

[0157] In the first stage t1, called the reset stage, the signals of the first scanning signal line Gate, the reset control signal line Reset, the second scanning signal line GateN, and the light emission control signal line EM are all high-level signals, and the signal of the reset control signal line Reset is a low-level signal. The high-level signal of the light emission control signal line EM turns off the fifth transistor T5 and the sixth transistor T6, the high-level signal of the second scanning signal line GateN turns on the eighth transistor T8, and the low-level signal of the reset control signal line Reset turns on the first transistor T1, so that the voltage of the N1 node is reset to the first initial voltage Vinit1 provided by the first initial signal line Vinit1. Then, the electric potential of the reset control signal line Reset is raised, and the first transistor T1 is turned off.Since the fifth transistor T5 and the sixth transistor T6 are turned off, the light-emitting element EL does not emit light in this stage.

[0158] In the second stage t2, called the data write stage, the signal of the first scanning signal line Gate is low, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, the data line Data outputs a data voltage, and the voltage of the N4 node is reset to the second initial voltage Vinit2 provided by the second initial signal line Vinit2, thus completing the initialization. In this stage, the third transistor T3 is turned on because the N1 node is low.The fourth transistor T4 and the second transistor T2 are turned on, so that the data voltage output from the data line Data is supplied to the N1 node via the turned-on fourth transistor T4, the N2 node, the turned-on third transistor T3, the N3 node, the turned-on second transistor T2, the N5 node and the eighth transistor T8, and the sum of the data voltage output from the data line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, where the voltage of the second terminal (N1 node) of the storage capacitor C is Vdata+Vth, where Vdata is the data voltage output from the data line Data and Vth is the threshold voltage of the driver transistor T3.The signal of the light emission control signal line EM is a high level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off to ensure that the light-emitting element EL does not emit light.

[0159] In the third stage t3, called the light-emitting stage, the signals of the first scanning signal line Gate and the reset control signal line Reset are high-level signals, and the signals of the light-emitting control signal line EM and the second scanning signal line GateN are low-level signals. The high-level signal of the reset control signal line Reset turns off the seventh transistor T7, and the low-level signal of the light-emitting control signal line EM turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD supplies a drive voltage to the first electrode (i.e., the N4 node) of the light-emitting element EL via the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, and drives the light-emitting element EL to emit light.

[0160] For example, in the Fig. 19, by initializing the N4 node to the signal of the second initial signal line Vinit2 and by initializing the N5 node to the signal of the first initial signal line Vinit1, the reset voltage of the light-emitting element EL and the reset voltage of the N1 node can be adjusted, respectively, thereby achieving a better display effect and improving problems such as low-frequency flicker.

[0161] It should be noted that in the embodiment of the present disclosure, each pixel circuit may be both an 8T1C structure (i.e., eight transistors and one capacitor) as shown in Fig. 19, as well as a structure with a different number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, a 7T1C structure, or a 9T2C structure, which is not limited in the embodiment of the present disclosure.

[0162] For example, the display substrate includes a plurality of repeating units distributed along the first direction and the second direction that intersect with each other, and each of the repeating units includes two pixel circuits including a first pixel circuit and a second pixel circuit distributed along the second direction, wherein the first pixel circuit and the second pixel circuit are arranged substantially mirror-symmetrically, and wherein the pixel circuit described below is described by one of the first pixel circuit and the second pixel circuit.

[0163] For example, one embodiment of the present disclosure provides a display substrate, wherein Fig. 21A is a structural layout diagram of another display substrate provided by an embodiment of the present disclosure, wherein Fig. 21B is a structural layout diagram of another display substrate provided by an embodiment of the present disclosure, wherein Fig. 22 a structural layout diagram of the second conductive layer in Fig. 21B, where Fig. 23 a structural layout diagram of the first conductive layer in Fig. 21B, and where Fig. 24 is a structural layout diagram in which the first conductive layer and the second conductive layer in Fig. 21B are superimposed. Fig. 21A to Fig. 24 only schematically show the schematic diagrams of the stacked structure or single-layer structure of some film layers in the display substrate, and other film layers may also include film layers in which the gate lines are located, film layers in which the light-shielding layer is located, and so on. Compared with Fig. 21A is Fig. 21B is additionally provided with a light-shielding layer, and other structural settings are the same.

[0164] For example, in Fig. 19 and Fig. 21B, the display substrate 600 comprises: a base substrate 601, a pixel circuit 610 arranged on the base substrate 601, the pixel circuit 610 comprising a driver transistor T3 and a storage capacitor C, the display substrate 600 further comprising a first conductive layer 602, a second conductive layer 603 and a first semiconductor layer 604, the first conductive layer 602 comprising a first interconnection structure 6021, the first interconnection structure 6021 comprising a first end 6021a and a second end 6021b that are opposite to each other.The first end 6021a is connected to the first semiconductor layer 604, and the second end 6021b is electrically connected to the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor C; the first conductive layer 602 is located on a side of the first semiconductor layer 604 remote from the base substrate 601, and the second conductive layer 603 is located on a side of the first conductive layer 602 remote from the base substrate 601, and the orthographic projection of the first power supply signal line 6033 on the second conductive layer 603 on the base substrate 601 overlaps with the orthographic projection of the entirety of the first interconnection structure 6021 on the base substrate 601.In this display substrate 600, the orthographic projection of the second conductive layer 603 on the base substrate 601 overlaps with the orthographic projection of the entirety of the first interconnection structure 6021 on the base substrate 601, so that the first power supply signal line 6033 in the second conductive layer 603 (also called SD2) can completely cover the first interconnection structure 6021 (also called N1 node). Because the second conductive layer 603 (SD2) is applied with a stable signal, and a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1), a capacitor is formed between the N1 node and the nearest data line Data, so that the influence of the data signal on the capacitor is small, so that the influence of the nearby data signal on the N1 node can be reduced. can, i.e.The influence of the data signal on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0165] As in Fig. 19 and Fig. As shown in Figure 21, the first semiconductor layer 604 includes, for example, a semiconductor pattern of the later-mentioned eighth transistor T8, wherein the material of the first semiconductor layer 604 is a metal oxide semiconductor such as indium gallium zinc oxide (IGZO) and the like. The first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driver transistor T3.

[0166] For example, with reference to Fig. 21B and Fig. 22, the second conductive layer 603 includes a data line 6031 and a first power supply signal line 6033, wherein the second conductive layer 603 may be a second source-drain metal layer (SD2). The orthographic projection of the first power supply signal line 6033 on the base substrate 601 covers more than 50% of the orthographic projection of the first interconnect structure 6021 on the base substrate 601, i.e., the first power supply signal line 6033 may be used to fully cover the first interconnect structure 6021 and may be used to partially cover the first interconnect structure 6021. In the case that the first power supply signal line 6033 completely covers the first connection structure 6021, the orthographic projection of the first power supply signal line 6033 on the base substrate 601 covers the orthographic projection of the entire first connection structure on the base substrate 601.

[0167] In combination with Fig. 21B and Fig. 22, the second conductive layer 603 includes, for example, a first electrode transmission line 6032, wherein the planar shape of the first electrode transmission line 6032 may be, for example, rectangular. The plurality of first electrode transmission lines 6032 are arranged in one-to-one correspondence with the plurality of electrode parts (not shown in the figure), and the electrode part is connected to a corresponding first electrode transmission line 6032 through a through-hole.

[0168] With reference to Fig. 21B and Fig. 22, for example, the first power supply signal line 6033 includes a block-shaped part 6033a and a strip-shaped part 6033b connecting two adjacent block-shaped parts 6033a in the first direction Y. The strip-shaped part 6033b connects the adjacent block-shaped parts 6033a at the edges of the block-shaped parts 6033a, so that the strip-shaped part 6033b and the block-shaped parts 6033a form a receiving space in which the first electrode transmission line 6032 is formed.

[0169] In combination with Fig. 21B and Fig. 22, for example, the orthographic projection of the entirety of the data line 6031 on the base substrate 601 extends linearly along the first direction Y. In the same repeating unit, the orthographic projections of two data lines 6031 on the base substrate 601 are located between the orthographic projections of two first power supply signal lines 6033 on the base substrate 601.

[0170] For example, in the first direction Y, the second conductive layers 603 of any two adjacent columns of subpixels have a mirror-symmetric structure. In other exemplary embodiments, the second conductive layers 603 of any two adjacent columns of subpixels in the first direction Y may not be mirror-symmetric.

[0171] For example, in Fig. 23, the first conductive layer 602 comprises at least: a second initial signal line Vinit2, a first terminal electrode 6021, a second terminal electrode 6022, a third terminal electrode 6023, a fourth terminal electrode 6024, a fifth terminal electrode 6025 and a sixth terminal electrode 6026, as shown in Fig. 23. In some example embodiments, the first conductive layer 602 may be referred to as a first source-drain metal layer (SD1).

[0172] For example, in combination with Fig. 21B, Fig. 22 and Fig. 23, the extending direction of the data line 6031 is the first direction Y, and the direction perpendicular or substantially perpendicular to the extending direction of the data line 6031 is the second direction X. The first connection structure 6021 has an inverted "L" shape, and the part of the inverted "L" shape extending along the second direction X extends to the side remote from a nearest data line 6031, wherein an end M1 of a part of the inverted "L" shape extending along the second direction and remote from a nearest data line 6031 is connected to the second electrode of the eighth transistor T8.

[0173] For example, as in Fig. 24, the orthographic projection of the block-shaped part 6033a of the first power supply signal line 6033 on the base substrate 601 completely covers the orthographic projection of the first connection structure 6021 on the base substrate 601 and the orthographic projection of the third terminal electrode 6023 on the base substrate 601. The orthographic projection of the first electrode transmission line 6032 on the base substrate 601 overlaps with the orthographic projection of at least a part of the fourth terminal electrode 6024 on the base substrate 601. The orthographic projection of the strip-shaped part 6033b of the first power supply signal line 6033 on the base substrate 601 overlaps with the orthographic projection of at least a part of the fifth terminal electrode 6025 on the base substrate 601 and the orthographic projection of the sixth terminal electrode 6026 on the base substrate 601.The orthographic projection of the data line 6031 on the base substrate 601 overlaps at least partially with the orthographic projection of the second terminal electrode 6022 on the base substrate 601.

[0174] Fig. For example, Fig. 25 is a partial schematic structure diagram of the first active layer in the Fig. 19. As shown in Fig. For example, as shown in Figure 25, pixel circuit 610 includes a first active layer 605 that includes a channel region and a source-drain region of each transistor. The source-drain region may include, for example, a source region and a drain region.

[0175] In Fig. For example, in Figure 25, it is schematically illustrated that the first active layer 605 is formed by patterning a semiconductor material. The first active layer 605 can be used to fabricate the active layers of the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 to form the channel regions of the aforementioned transistors. The first active layer 605 includes an active layer pattern (channel region) and a doped region pattern (source-drain region) of the aforementioned transistor of each subpixel, and the active layer pattern and the doped region pattern of the aforementioned transistor in the same pixel circuit are integrally formed.

[0176] In Fig. For example, in Fig. 25, each dashed rectangular frame shows parts of the above-mentioned metal layer overlapping with the first active layer 605, that is, the first active part 21, the second active part 22, the third active part 23, the fourth active part 24, the fifth active part 25, the sixth active part 26, and the seventh active part 27, to serve as the channel regions of the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively. The parts of the first active layer 605 on both sides of each channel region are conductively treated by a method such as ion doping as the first electrode and second electrode of each transistor, that is, the above-mentioned source-drain region. The first active layer 605 may be an integral structure.The source electrode and drain electrode of each transistor can be symmetrically configured, so that there can be no difference in the physical structure between the source electrode and the drain electrode. In the embodiment of the present disclosure, to distinguish the transistors, except for the gate electrode as the control electrode, one of them is directly referred to as the first electrode and the other as the second electrode. Therefore, the first electrode and the second electrode of all or part of the transistors in the embodiment of the present disclosure can be interchanged as needed.

[0177] As in Fig. 25, for example, the shape of the channel region 23 of the driver transistor T3 may be an “Ω” shape, and the shapes of the channel region 21 of the first transistor T1, the channel region 22 of the second transistor T2, the channel region 24 of the fourth transistor T4, the channel region 25 of the fifth transistor T5, the channel region 26 of the sixth transistor T6, and the channel region 27 of the seventh transistor T7 are all “1” shapes.

[0178] For example, in some example embodiments, the active structure of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0179] In some exemplary embodiments, the first active layer 605 may be made of polysilicon (p-Si), for example, i.e., the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be LTPS thin film transistors.

[0180] Fig. For example, Fig. 26 is a partial schematic structure diagram of a third conductive layer in the Fig. 19. As shown in Fig. 26, the pixel circuit 610 includes, for example, a third conductive layer 606, wherein the third conductive layer 606 includes at least: a first scan signal line 6061 (Gate_P), a reset control signal line 6062 (Reset_P), a light emission control signal line 6063 (EM_P), and a first electrode plate Cst1 of the storage capacitor C. In some example embodiments, the third conductive layer 606 may be referred to as a first gate metal layer (Gate 1).The first scan signal line 6061 can also be used as the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4; the reset control signal line 6062 can also be used as the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7; the reset control signal line 6062 can also be used as the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6; the first electrode plate Cst1 of the storage capacitor C can be used as the gate electrode of the driver transistor T3.

[0181] As in Fig. 26, the third conductive layer 606 of any two adjacent columns of subpixels in the first direction Y is, for example, a mirror-symmetric structure.

[0182] For example, in Fig. 26, the first scanning signal line 6061, the reset control signal line 6062, and the light emission control signal line 6063 all extend along the second direction X. In each subpixel, the reset control signal line 6062 is located on a side of the first scanning signal line 6061 remote from the light emission control signal line 6063, and the first electrode plate Cst1 of the storage capacitor is arranged between the first scanning signal line 6061 and the light emission control signal line 6063.

[0183] For example, in the Fig. 25 and Fig. As shown in Figure 26, the planar shape of the first electrode plate Cst1 is rectangular, and at least one corner of the rectangular shape may be chamfered, and the orthographic projection of the first electrode plate Cst1 on the base substrate 601 and the orthographic projection of the channel region 23 of the third transistor T3 on the base substrate 601 have an overlap area. A region of the first active layer 605 that overlaps with the first electrode plate Cst1 serves as the channel region 23 of the third transistor T3. One end of the channel region 23 of the third transistor T3 is connected to the first region of the active region of the third transistor T3, and the other end is connected to the second region of the active region of the third transistor T3.

[0184] For example, in some example embodiments, a portion of the reset control signal line 6062 (Reset_P) that overlaps with the first active region of the first transistor T1 is used as the gate electrode of the first transistor T1. A portion of the first sensing signal line 6061 (Gate_P) that overlaps with the second active region of the second transistor T2 is used as the gate electrode of the second transistor T2. A portion of the first sensing signal line 6061 (Gate_P) that overlaps with the fourth active region of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. A portion of the light emission control signal line 6063 (EM_P) that overlaps with the fifth active region of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5.A region of the light emission control signal line 6063 (EM_P) that overlaps with the sixth active region of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. A region of the reset control signal line 6063 Reset_P (with the same signal as the first scanning signal line Gate_P in the subpixels of the current row) in the subpixels of the next row of the subpixels of each row, which overlaps with the seventh active region of the seventh transistor T7 in the subpixels of the current row, serves as the gate electrode of the seventh transistor T7.

[0185] Fig. For example, Fig. 27 is a partial schematic structure diagram of a conductive film layer in the Fig. 19. As shown in Fig. 27, for example, the pixel circuit 610 includes a conductive film layer 607 between the third conductive layer 606 and the second conductive layer 603. The conductive film layer 607 includes a second scanning signal line 6071, a first conductive part 6072, and a fifth conductive part 6073. A partial structure of the second scanning signal line 6071 is used to form a lower gate electrode of the eighth transistor T8; the first conductive part 6072 includes two second electrode plates Cst2 of the two storage capacitors C that are adjacent in the first direction Y; the fifth conductive part 6073 is electrically connected to the first conductive layer 602. The conductive film layer 607 may be referred to as a second gate metal layer (Gate 2).

[0186] For example, in Fig. As shown in Figure 27, the first conductive part 6072 includes a main part 6072a, and the storage capacitor C also includes a second electrode plate Cst2 opposite the first electrode plate Cst1, the main part 6072a corresponding to two second electrode plates Cst2. For example, the first conductive part 6072 further includes a bridge part 6072b connecting two main parts 6072a adjacent in the second direction X, i.e., two adjacent second electrode plates Cst2, and the first conductive part 6072 further includes a recess 6072c between the two second electrode plates Cst2.

[0187] In combination with Fig. 19, Fig. 23 and Fig. 27, for example, the orthographic projection of the first conductive layer 602 on the base substrate 601 and the orthographic projection of the recess 6072c on the base substrate 601 do not overlap, and the orthographic projection of the second conductive layer 603 on the base substrate 601 and the orthographic projection of the recess 6072c on the base substrate 601 do not overlap, so that the recess 6072c is not obscured by the first conductive layer 602 and the second conductive layer 603, thereby increasing the pixel transmittance. It should also be noted that the recess 6072c is not obscured by another film layer having a light-shielding function.

[0188] For example, in combination with Fig. 19, Fig. 23 and Fig. 27, the first conductive part 6072 is also formed with an opening 6072d, and the orthographic projection of the through-hole on the base substrate 601 connected between the gate electrode of the driver transistor T3 and the first connection structure 6021 is located within the orthographic projection of the opening 6072d on the base substrate 601, so that the conductive structure in the through-hole and the first conductive part 6072 are insulated from each other.

[0189] The display substrate also includes, for example, a second active layer. For example, Fig. 28 is a schematic partial structure diagram of a second active layer in the Fig. 19. As shown in Fig. 19 and Fig. As shown in Figure 28, the second active layer 608 is located between the first active layer 605 and the second conductive layer 603. The second active layer 608 may include the eighth active portion 38, which forms the channel region of the eighth transistor T8. A first region 381 and a second region 382 of the eighth transistor T8 are formed at both ends of the eighth active portion 38. The first region 381 of the eighth transistor T8 borders the channel region of the first transistor T1, and the second region 382 of the eighth transistor T8 borders the storage capacitor C, and the first semiconductor layer 604 comprises the second active layer 608.

[0190] As in Fig. 19 and Fig. As shown in Figure 28, the second active layer 608 may be made of indium gallium zinc oxide, for example, and the eighth transistor T8 may accordingly be an N-type metal oxide thin-film transistor. The entirety of the eighth active portion 38 and the first region 381 and the second region 382 of the eighth transistor T8 extends along the first direction Y, and the entirety of the eighth active portion 38 and the first region 381 and the second region 382 of the eighth transistor T8 may have a dumbbell shape.

[0191] For example, the first semiconductor layer forming the channel region of the eighth transistor T8 in the pixel circuit may be disposed on a side of a layer on which the active semiconductor pattern of the driver transistor T3 is located, remote from the base substrate 601, and the first semiconductor layer may comprise an oxide semiconductor material. For example, if the active layer of the eighth transistor T8 of the pixel circuit is made of an oxide semiconductor, the oxide semiconductor transistor has the properties of good hysteresis and low leakage current, while also having low mobility. Therefore, the oxide semiconductor transistor may be used instead of the low-temperature polysilicon material transistor to form a low-temperature polysilicon oxide (LTPO) pixel circuit to realize low leakage current and improve the stability of the gate voltage of the transistor.

[0192] Of course, the embodiment of the present disclosure is not limited to the structure of the second active layer of the pixel circuit as shown in Fig. 28. In other examples, the first semiconductor layer with the channel region of the eighth transistor T8 can also be located on the same layer as the semiconductor layers of the channel regions of other transistors, ie the first active layer can also comprise the channel regions of the first transistor T1, the second transistor T2, the driver transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8.

[0193] Fig. For example, Fig. 29 is a partial schematic structure diagram of a fourth conductive layer in the Fig. 19. As shown in Fig. 29, the pixel circuit 610 includes, for example, a fourth conductive layer 609 between the conductive film layer 607 and the second conductive layer 603. The fourth conductive layer 609 includes a first initial signal line Vinit1 and a fourth scanning signal line 6091, and a partial structure of the fourth scanning signal line 6091 is configured to form an upper gate electrode of the eighth transistor T8.

[0194] For example in combination with Fig. 21A to Fig. 29, the second initial signal line Vinit2 included in the first conductive layer 602 extends along the second direction X, and the second initial signal line Vinit2 is connected to the first region of the seventh transistor T7 through a third via hole V3, so that the first electrode of the seventh transistor T7 and the second initial signal line Vinit2 have the same electric potential.

[0195] For example, in combination with Fig. 21A to Fig. 29, the first scanning signal line 6061 has a protruding part 6061a extending along the first direction Y and a part extending along the second direction X. The first end 6021a of the first connection structure 6021 is connected to the first region of the eighth transistor T8 via a fourth through-hole V4, and the second end 6021b of the first connection structure 6021 is electrically connected to the gate electrode of the driver transistor T3 and the first electrode plate Cst1 of the storage capacitor C via a fifth through-hole V5.The orthographic projection of the third end 6021c of the first interconnection structure 6021 on the base substrate 601 overlaps with the orthographic projection of the protruding portion 6061a of the first scanning signal line 6061 on the base substrate 601, so that a coupling capacitor can be formed between the third end 6021c of the first interconnection structure 6021 and the protruding portion 6061a of the first scanning signal line 6061. For example, the first end 6021a of the first interconnection structure 6021 can serve as the second electrode of the eighth transistor T8.

[0196] For example, a part of the inverted "L" shape of the first connection structure 6021 extending along the first direction Y is electrically connected to the fifth conductive part 6073 of the conductive film layer 607; the fifth conductive part 6073 overlaps with the protruding part 6061a of the first scanning signal line extending along the first direction Y.

[0197] In combination with Fig. 21A to Fig. 29, the second terminal electrode 6022 is connected to the first region of the fourth transistor T4, for example, through a sixth via V6. In some exemplary embodiments, the second terminal electrode 6022 may serve as the first electrode of the fourth transistor T4.

[0198] For example, in combination with Fig. 21A to Fig. 29, one end of the third terminal electrode 6023 is connected to the first region of the second transistor T2 (which is also the second region of the first transistor T1) through a seventh via V7, and the other end of the third terminal electrode 6023 is connected to the first region of the eighth transistor T8 through an eighth via V8. In some exemplary embodiments, the third terminal electrode 6023 may serve as the first electrode of the eighth transistor T8, the first electrode of the second transistor T2, and the second electrode of the first transistor T1.

[0199] In combination with Fig. 21A to Fig. 29, for example, the fourth terminal electrode 6024 is connected, on the one hand, to the second region of the sixth transistor T6 (which is also the second region of the seventh transistor T7) via a ninth via V9. In some exemplary embodiments, the fourth terminal electrode 6024 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0200] In combination with Fig. 21A to Fig. 29, the fifth terminal electrode 6025 is connected, for example, to the second electrode plate Cst2 via a tenth through-hole V10 on the one hand, and to the first region of the fifth transistor T5 via an eleventh through-hole V11 on the other hand. The fifth terminal electrode 6025 is also configured to be connected to the subsequently formed first power supply signal line.

[0201] In combination with Fig. 21A to Fig. 29, for example, one end of the sixth terminal electrode 6026 is connected to the first region of the first transistor T1 via a twelfth through-hole V12, and the other end of the sixth terminal electrode 6026 is connected to the first initial signal line, so that the first electrode of the first transistor T1 and the first initial signal line have the same electric potential.

[0202] In the first direction Y, the first conductive layer 602 of any two adjacent columns of subpixels is, for example, a mirror-symmetric structure.

[0203] For example, the display substrate 100 further includes a plurality of subpixels, and each subpixel includes a pixel circuit 610 and a light-emitting element in any of the above examples. Fig. 30 is a schematic diagram of a partial pixel array structure on a display substrate provided according to an embodiment of the present disclosure. Fig. 31A is a layout diagram of a stack of the pixel circuit and a first electrode of the light-emitting element in Fig. 19. Fig. 31B is another layout diagram of a stack of the pixel circuit and a first electrode of the light-emitting element in Fig. 19. Compared to Fig. 31A is Fig. 31B is additionally provided with a light-shielding layer, and other structural settings are the same.

[0204] The partial pixel array structure and the structure of the respective electrode parts 502 on the first electrode layer 501 can be known, for example, from the above-mentioned descriptions of Fig. 14, Fig. 15A and Fig. 15B, and a repetition is omitted here.

[0205] For example, in combination with Fig. 30, Fig. 31A and Fig. 31B, each electrode part 502 on the first electrode layer 501 is connected to a first electrode transmission line 6032.

[0206] For example, the display substrate 610 may also include a light-shielding layer, and the related description of the light-shielding layer may be taken from the related description of Fig. 17, and a repetition is omitted here.

[0207] For example, in some exemplary embodiments, the display substrate may further comprise an encapsulation layer, which may comprise a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that water vapor from the outside cannot penetrate into the light-emitting structure layer.

[0208] Fig. For example, Figure 32 is a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure and is described based on the above-mentioned structure in which the pixel circuit is 7T1C. For example, a first buffer layer 125 is disposed on the base substrate 101, a first active layer 105 is disposed on the first buffer layer 125, a first insulating layer 126 is disposed on the first buffer layer 125, and a third conductive layer 106 is disposed on the first insulating layer 126. A second insulating layer 127 is disposed on the third conductive layer 106, a conductive film layer 107 is disposed on the second insulating layer 127, a third insulating layer 128 is disposed on the conductive film layer 107, and a fourth insulating layer 129 is disposed on the third insulating layer 128.wherein a second active layer 108 is arranged on the fourth insulating layer 129, wherein a fifth insulating layer 130 is arranged on the second active layer 108, wherein a fourth conductive layer 109 is arranged on the fifth insulating layer 130, wherein a sixth insulating layer 131 is arranged on the fourth conductive layer 109, wherein a first conductive layer 102 is arranged on the sixth insulating layer 131, wherein the first conductive layer 102 is electrically connected to the first active layer 105, the third conductive layer 106, and the conductive film layer 107 through the through holes; a seventh insulating layer 132 is arranged on the first insulating layer 102, wherein a second conductive layer 103 is arranged on the seventh insulating layer 132,The second conductive layer 103 is electrically connected to the first conductive layer 102 through a through-hole penetrating the seventh insulating layer 132. A second planarization layer 133 is disposed on the second conductive layer 103, a first electrode layer 501 is disposed on the second planarization layer 133, and the first electrode layer 501 is electrically connected to the second conductive layer 103 through a through-hole penetrating the second planarization layer 133.

[0209] For example, the first buffer layer (BUF1) 125, the first insulating layer 126, the second insulating layer 127, the third insulating layer 128, the fourth insulating layer 129, the fifth insulating layer 130, and the sixth insulating layer 131 may be made of one or more of the following materials: silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first buffer layer (BUF1) may be used to improve the water-oxygen resistance of the base substrate 101. The first insulating layer 126 is referred to as the first gate insulating layer (GI1), the second insulating layer 127 as the second gate insulating layer (GI2), the third insulating layer 128 as the first interlayer insulating layer (ILD1), the fourth insulating layer 129 as the second buffer layer (BUF2), and the fifth insulating layer 130 as the third gate insulating layer (GI3).

[0210] For example, the first planarization layer 132 and the second planarization layer 133 may be made of organic materials, and the transparent conductive film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The first active layer may be made of polysilicon (p-Si), and the second active layer may be made of metal oxide.

[0211] In some example embodiments, the base substrate 101 / 601 may be, for example, a flexible substrate or a rigid substrate. The rigid substrate may be made of, but is not limited to, one or more of the materials glass and quartz, and the flexible substrate may be made of, but is not limited to, one or more of the materials polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some example embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer arranged one above the other.The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film and the like, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx) and the like to improve the water-oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0212] For example, in some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the conductive film layer, and the light-shielding layer may be made of metal materials such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo and the like.

[0213] The Fig. The structure of the display substrate shown in Figure 32 is only an exemplary explanation. In some exemplary embodiments, the corresponding structure may be changed according to actual needs, which is not limited by the embodiment of the present disclosure. The structure of the above display substrate is explained using the example shown in Fig. 3. In other exemplary embodiments, the pixel circuit may also have a structure of 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 8T1C, and the like, and is not limited by the embodiment of the present disclosure.

[0214] Fig. For example, Figure 33 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure, wherein Fig. 33 using the example of the pixel circuit as a 7T1C pixel circuit. As in Fig. 33, the structure of the first conductive layer 102 can be based on the above-mentioned description of Fig. 6, and the structure of the second conductive layer 103 can be referred to the above-mentioned description of Fig. 7, and repetition is omitted here. As in Fig. 3 and Fig. 33, the first conductive layer 102 includes a first interconnection structure 1021, and the orthographic projection of the first electrode transmission line 1032 on the second conductive layer 103 on the base substrate 101 overlaps with the orthographic projection of at least a part of the first interconnection structure 1021 on the base substrate 101, so that the second conductive layer 103 (also called SD2) can obscure at least a part of the first interconnection structure 1021 (also called N1 node), whereby the second conductive layer 103 and the first interconnection structure 1021 located in the first conductive layer 102 directly form a capacitor, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), so that a capacitor is formed between the N1 node and the nearest data line data.Since both the light emission control signal line EM and the second initial signal line Vinit2 transmit stable DC signals, the second conductive layer 103 (SD2) is supplied with a stable signal, and the signal changes only once within the time of one frame. With this construction, the second conductive layer 103 (SD2) can directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node when the N1 node is operating normally, and the second conductive layer 103 (SD2, the upper electrode plate) is supplied with a stable signal. Due to the characteristics of the capacitor itself, the voltages at both ends of the capacitor cannot change suddenly. When the upper electrode plate is supplied with a stable DC signal, the signal at the lower electrode plate, i.e.The first conductive layer 102 (SD1) at the N1 node also remains stable, thereby reducing the influence of the data signal that frequently jumps within the time of one frame on the N1 node. The data signal has little influence on the capacitor, so the influence of nearby data signals on the N1 node can be reduced. That is, the influence of data signals on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0215] In the Fig. For example, in the structure shown in Figure 33, each first conductive part 1074 includes only two main parts 1074a, and the storage capacitor C includes the second electrode plate Cst2, and the main parts 1074a correspond to the two second electrode plates Cst2. For example, the first conductive part 1074 does not include any other structures.

[0216] For the arrangement of other structures in Fig. 33, for example, reference is made to the description of the corresponding parts above, and repetition is omitted here.

[0217] Fig. For example, Figure 34 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure, wherein Fig. 34 using the example of the pixel circuit as an 8T1C pixel circuit. As in Fig. 34, the structure of the first conductive layer 602 can be based on the above-mentioned description of Fig. 23, and the structure of the second conductive layer 603 can be referred to the above-mentioned description of Fig. 22, and a repetition is omitted here. As in Fig. 19 and Fig. 34, the first conductive layer 602 includes a first interconnection pattern 6021, and the orthographic projection of the first power supply signal line 6033 on the second conductive layer 603 on the base substrate 601 overlaps with the orthographic projection of the entire first interconnection pattern 6021 on the base substrate 601, so that the second conductive layer 603 (also called SD2) can completely cover the first interconnection pattern 6021 (also called N1 node). Therefore, the second conductive layer 603 and the first power supply signal line 6033 located in the first conductive layer 602 directly form a capacitor, that is, a capacitor is formed between the second conductive layer 603 (SD2) and the first conductive layer 602 (also called SD1), so that a capacitor is formed between the N1 node and the next data line data.Since both the light emission control signal line EM and the second initial signal line Vinit2 transmit stable DC signals, the second conductive layer 603 (SD2) is supplied with a stable signal, and the signal changes only once within the time of one frame. With this construction, the second conductive layer 603 (SD2) can directly form a capacitor with the first conductive layer 602 (also called SD1) at the N1 node when the N1 node is operating normally, and the second conductive layer 603 (SD2, the upper electrode plate) is supplied with a stable signal. Due to the characteristics of the capacitor itself, the voltages at both ends of the capacitor cannot change suddenly. When the upper electrode plate is supplied with a stable DC signal, the signal at the lower electrode plate, i.e.The first conductive layer 602 (SD1) at the N1 node also remains stable, thereby reducing the influence of the data signal that frequently jumps within the time of one frame on the N1 node. The data signal has little influence on the capacitor, so the influence of nearby data signals on the N1 node can be reduced. That is, the influence of data signals on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0218] In the Fig. For example, in the structure shown in Figure 34, each first conductive part 6074 includes only two main parts 6074a, and the storage capacitor C includes the second electrode plate Cst2, and the main parts 6074a correspond to the two second electrode plates Cst2. For example, the first conductive part 6074 does not include any other structures.

[0219] For the arrangement of other structures in Fig. 34, for example, reference is made to the description of the relevant parts above, and repetition is omitted here.

[0220] Fig. For example, Figure 35 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure, wherein Fig. 35 using the example of the pixel circuit as a 7T1C pixel circuit. As in Fig. 35, the structure of the first conductive layer 102 can be based on the above-mentioned description of Fig. 6, and the structure of the second conductive layer 103 can be referred to the above-mentioned description of Fig. 22, and repetition is omitted here. As in Fig. 3 and Fig. 35, the first conductive layer 102 includes a first interconnection pattern 1021, and the orthographic projection of the first power supply signal line 1033 on the second conductive layer 103 on the base substrate 101 overlaps with the orthographic projection of more than 50% of the area of ​​the first interconnection pattern 1021 on the base substrate 101, so that the second conductive layer 103 (also called SD2) can completely cover the first interconnection pattern 1021 (also called N1). Therefore, the second conductive layer 103 and the first power supply signal line 1033 located in the first conductive layer 102 directly form a capacitor, that is, a capacitor is formed between the second conductive layer 103 (SD2) and the first conductive layer 102 (also called SD1), so that a capacitor is formed between the N1 node and the next data line data.Since both the light emission control signal line EM and the second initial signal line Vinit2 transmit stable DC signals, the second conductive layer 103 (SD2) is supplied with a stable signal, and the signal changes only once within the time of one frame. With this construction, the second conductive layer 103 (SD2) can directly form a capacitor with the first conductive layer 102 (also called SD1) at the N1 node when the N1 node is operating normally, and the second conductive layer 103 (SD2, the upper electrode plate) is supplied with a stable signal. Due to the characteristics of the capacitor itself, the voltages at both ends of the capacitor cannot change suddenly. When the upper electrode plate is supplied with a stable DC signal, the signal at the lower electrode plate, i.e.The first conductive layer 102 (SD1) at the N1 node also remains stable, thereby reducing the influence of the data signal that frequently jumps within the time of one frame on the N1 node. The data signal has little influence on the capacitor, so the influence of nearby data signals on the N1 node can be reduced. That is, the influence of data signals on the N1 node can be shielded, and the problem that the display panel cannot display normally due to the voltage of the N1 node affected by the data signal jump can be alleviated.

[0221] In the Fig. For example, in the structure shown in Figure 35, each first conductive part 6074 includes only two main parts 6074a, and the storage capacitor C includes the second electrode plate Cst2, and the main parts 6074a correspond to the two second electrode plates Cst2. For example, the first conductive part 6074 includes no other structures.

[0222] For example, in Fig. 35, the first electrode transmission line 1032 and the first connection structure 1021 have no overlapping parts.

[0223] For the arrangement of other structures in Fig. 35, for example, reference is made to the description of the relevant parts above, and repetition is omitted here.

[0224] Fig. For example, Figure 36 is a structural layout diagram of another display substrate provided by at least one embodiment of the present disclosure. Fig. The layer structure shown in Figure 36 may also be such that the display substrate comprises a first electrode layer 501 located on the side of the second conductive layer 103 remote from the base substrate 101. This arrangement can flatten the lower part of the first electrode (anode) in the pixel unit and maintain the capacitance balance. As shown in Fig.36, the first electrode layer 501 includes a plurality of electrode parts 502, each electrode part 502 including a body part 5021 and a supplementary part 5022 connected to each other, and each electrode part 502 corresponds to one of the first subpixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third subpixel 403. For example, the first electrodes (anodes) corresponding to the first subpixel 401, the first pixel block 4020a, the second pixel block 4020b, and the third subpixel 403 are all arranged as much as possible above the first power supply signal line 1033 of the second conductive layer 103.

[0225] For example, providing the supplementary part 5022 on the electrode part 502 can increase the overlap area between the electrode part 502 and the second conductive layer 103. For example, the supplementary part 5022 of the electrode part 502 corresponding to the first pixel block 4020a and the second pixel block 4020b can cover the position of the elongated shape at the edge of the first power supply signal line 1033, and the supplementary part 5022 of the electrode part 502 corresponding to the first subpixel 401 and the third subpixel 403 can cover the block-shaped part of the first power supply signal line 1033, so that the overlap area of ​​the electrode part 502 and the second conductive layer 103 is further increased.

[0226] At least one embodiment of the present disclosure also provides a display device including one of the display substrates. The display device may be a mobile phone, a tablet computer, a television, a display, a notebook, a digital photo frame, a navigation device, and other products or components with display functions, and the embodiment of the present invention is not limited to these.

[0227] The following points need to be explained: (1) In the drawings of the embodiment of the present disclosure, only the structure related to the embodiment of the present disclosure is included, and other structures may relate to the general construction. (2) If there is no conflict, features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0228] What has been described above are merely exemplary embodiments of the present disclosure and are not used to limit the scope of the present disclosure, which is determined by the appended claims.

Claims

[1] A display substrate comprising: a base substrate; a pixel circuit arranged on the base substrate and comprising a driver transistor and a storage capacitor; wherein the display substrate further comprises a first conductive layer, a second conductive layer and a first semiconductor layer, wherein the first conductive layer comprises a first connection structure comprising a first end and a second end opposite each other, the first end being connected to the first semiconductor layer, the second end being electrically connected to a gate electrode of the driver transistor and a first electrode plate of the storage capacitor; wherein the first conductive layer is located on a side of the first semiconductor layer remote from the base substrate, wherein the second conductive layer is located on a side of the first conductive layer remote from the base substrate and an orthographic projection of the second conductive layer on the base substrate overlaps with an orthographic projection of at least a portion of the first interconnect structure on the base substrate. [2] The display substrate according to claim 1, further comprising a plurality of sub-pixels, each of the plurality of sub-pixels comprising the pixel circuit and a light-emitting element, wherein the first conductive layer is disposed between a first electrode of the light-emitting element and the first semiconductor layer, and the second conductive layer is disposed between the first conductive layer and the first electrode of the light-emitting element. [3] The display substrate according to claim 2, wherein the second conductive layer comprises a data line, a first electrode transmission line, and a first power supply signal line spaced apart from each other, the first electrode transmission line being connected to the first electrode of the light-emitting element and an orthographic projection of the first electrode transmission line on the base substrate overlapping an orthographic projection of a part of the first connection structure on the base substrate. [4] The display substrate according to claim 3, wherein the first connection structure includes an overlapping part that overlaps with the first electrode transmission line and a non-overlapping part that does not overlap with the first electrode transmission line, and wherein the non-overlapping part is farther away from the data line closest to the first connection structure than the overlapping part. [5] A display substrate according to claim 3 or 4, wherein an extension direction of the data line is a first direction and a direction perpendicular or substantially perpendicular to the extension direction of the data line is a second direction; the first conductive layer further comprises a power supply signal connection line including a main part and a branch part, wherein an extending direction of an entirety of the main part of the power supply signal connection line is parallel to the second direction and an extending direction of the branch part is parallel to the first direction; the first power supply signal line comprises a block-shaped part and a strip-shaped part extending as a whole along the first direction, the strip-shaped part connecting adjacent block-shaped parts and the main part of the power supply signal connecting line being connected to the first power supply signal line to form a lattice shape. [6] The display substrate according to claim 5, wherein the strip-shaped part comprises a first strip-shaped part and a second strip-shaped part arranged opposite to each other, and a third strip-shaped part connecting the first strip-shaped part and the second strip-shaped part, wherein an extending direction of the first strip-shaped part and an extending direction of the second strip-shaped part are parallel to the first direction, and the third strip-shaped part connects central regions of the first strip-shaped part and the second strip-shaped part. [7] The display substrate according to claim 6, wherein the strip-shaped part has a hollow structure. [8] The display substrate according to claim 5, wherein a width of the block-shaped part in the second direction is larger than a width of an entirety of the strip-shaped part in the second direction. [9] The display substrate according to claim 5, wherein the first electrode transmission line extends along the first direction, and the first electrode transmission line conceals a part of the first connection structure at an end position of the first electrode transmission line near the first connection structure. [10] A display substrate according to any one of claims 5 to 9, wherein the pixel circuit further comprises a first transistor, a second transistor, a sixth transistor, and a seventh transistor; a first electrode of the first transistor is connected to a gate electrode of the driver transistor, a second electrode of the first transistor is connected to a first initial signal line, a first electrode of the second transistor is connected to a gate electrode of the driver transistor, a second electrode of the second transistor is connected to a second electrode of the driver transistor, a first electrode of the sixth transistor is connected to the second electrode of the driver transistor, a first electrode of the seventh transistor is connected to a second electrode of the sixth transistor, a second electrode of the seventh transistor is connected to a second initial signal line; the display substrate further comprises: a first active layer between the base substrate and the second conductive layer, wherein the first active layer comprises a third active part, a sixth active part, a seventh active part, a tenth active part, and an eleventh active part, wherein the third active part forms a channel region of the driver transistor, the sixth active part forms a channel region of the sixth transistor, the seventh active part forms a channel region of the seventh transistor, the tenth active part is connected between the seventh active part and the sixth active part, and the eleventh active part is connected between the sixth active part and the third active part; and a second active layer between the first active layer and the second conductive layer, the second active layer comprising a first active portion, a second active portion, and a twelfth active portion, the first active portion forming a channel region of the first transistor, the second active portion being connected to the first active portion to form a channel region of the second transistor, and the twelfth active portion being connected to an end of the second active portion remote from the first active portion. [11] The display substrate according to claim 10, wherein the display substrate comprises a plurality of repeating units distributed along the first direction and the second direction, wherein each of the repeating units comprises two pixel circuits, and the two pixel circuits comprise a first pixel circuit and a second pixel circuit distributed along the second direction, and wherein the first pixel circuit and the second pixel circuit are arranged mirror-symmetrically; wherein each of the pixel circuits further comprises a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is connected to the data line, a second electrode of the fourth transistor is connected to a first electrode of the driver transistor, a first electrode of the fifth transistor is connected to the first power supply signal line, and a second electrode of the fifth transistor is connected to the first electrode of the driver transistor; wherein the first active layer further comprises: a fourth active part connected to one side of the third active part and forming a channel region of the fourth transistor; a fifth active part forming a channel region of the fifth transistor; an eighth active part connected to a side of the fifth active part remote from the third active part; and a ninth active part connected between two eighth active parts in the same repeating unit. [12] The display substrate according to claim 11, wherein the first conductive layer comprises a plurality of third interconnection structures, the plurality of third interconnection structures being arranged in one-to-one correspondence with the plurality of repeating units, and each of the third interconnection structures being connected to the ninth active part through a first through-hole interconnection part. [13] The display substrate of claim 12, further comprising a third conductive layer, the third conductive layer comprising: a second gate line, wherein an orthographic projection of the second gate line on the base substrate extends along the second direction and overlaps with an orthographic projection of the fourth active part on the base substrate, and wherein a partial structure of the second gate line is used to form a gate electrode of the fourth transistor; a light emission control signal line, wherein an orthographic projection of the light emission control signal line on the base substrate extends along the second direction and overlaps with an orthographic projection of the sixth active part on the base substrate, and wherein a partial structure of the light emission control signal line is used to form a gate electrode of the sixth transistor; a second reset signal line, wherein an orthographic projection of the second reset signal line on the base substrate extends along the second direction and overlaps with an orthographic projection of the seventh active part on the base substrate, wherein a partial structure of the second reset signal line is used to form a gate electrode of the seventh transistor, and wherein the second gate line in the pixel circuit of a present row is multiplexed as the second reset signal line in the pixel circuit of an adjacent row; and a second conductive part, wherein an orthographic projection of the second conductive part on the base substrate overlaps with an orthographic projection of the third active part on the base substrate, and the second conductive part forms a gate electrode of the driver transistor and the first electrode plate of the storage capacitor; wherein, in the same pixel circuit, the orthographic projection of the second conductive part on the base substrate is arranged between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the light emission control signal line on the base substrate; wherein the orthographic projection of the second reset signal line on the base substrate is arranged on a side of the orthographic projection of the light emission control line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate. [14] The display substrate according to claim 13, further comprising a fourth conductive layer, wherein the fourth conductive layer is disposed between the second active layer and the second conductive layer, and the fourth conductive layer comprises: a first reset signal line, wherein an orthographic projection of the first reset signal line on the base substrate overlaps with an orthographic projection of the first active part on the base substrate and a partial structure of the first reset signal line forms an upper gate electrode of the first transistor; a first gate line, wherein an orthographic projection of the first gate line on the base substrate overlaps with an orthographic projection of the second active part on the base substrate and a partial structure of the first gate line forms an upper gate electrode of the second transistor; wherein, in the same pixel circuit, the orthographic projection of the first gate line on the base substrate is arranged between the orthographic projection of the second conductive part on the base substrate and the orthographic projection of the second gate line on the base substrate, and wherein the orthographic projection of the first reset signal line on the base substrate is arranged on a side of the orthographic projection of the second gate line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate. [15] The display substrate according to claim 14, further comprising a conductive film layer between the third conductive layer and the fourth conductive layer, the conductive film layer comprising: the first initial signal line, wherein an orthographic projection of the first initial signal line on the base substrate is arranged on a side of the orthographic projection of the first reset signal line on the base substrate that is remote from the orthographic projection of the second conductive part on the base substrate; a third reset signal line connected to the first reset signal line through a through-hole, wherein an orthographic projection of the third reset signal line on the base substrate overlaps with the orthographic projection of the first active part on the base substrate, and wherein a partial structure of the third reset signal line is used to form a lower gate electrode of the first transistor; a third gate line, wherein an orthographic projection of the third gate line on the base substrate overlaps with the orthographic projection of the second active part on the base substrate, and a partial structure of the third gate line is used to form a lower gate electrode of the second transistor; and a first conductive part comprising a main part, wherein the storage capacitor comprises a second electrode plate opposite to the first electrode plate, and wherein the main part corresponds to two second electrode plates. [16] The display substrate according to claim 15, wherein the first conductive part further comprises a bridge part connecting the two second electrode plates, and wherein the first conductive part comprises a recess between the two second electrode plates. [17] The display substrate of claim 2, wherein the second conductive layer comprises a data line and a first power supply signal line, wherein an orthographic projection of the first power supply signal line on the base substrate covers more than 50% of an orthographic projection of the first interconnection structure on the base substrate. [18] A display substrate according to claim 1, wherein the pixel circuit further comprises a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; a gate electrode of the first transistor is connected to a reset control signal line, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a first electrode of the eighth transistor and a first electrode of the second transistor; a gate electrode of the second transistor is connected to a first scanning signal line, and a second electrode of the second transistor is connected to a second electrode of the driver transistor and a first electrode of the sixth transistor; a gate electrode of the driver transistor is connected to a second electrode of the eighth transistor and a first electrode plate of the storage capacitor, a first electrode of the driver transistor is connected to a second electrode of the fourth transistor and a second electrode of the fifth transistor, and the second electrode of the driver transistor is connected to the second electrode of the second transistor and the first electrode of the sixth transistor; a gate electrode of the fourth transistor is connected to the first scanning signal line, a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driver transistor and the second electrode of the fifth transistor; a gate electrode of the fifth transistor is connected to a first light emission control signal line, a first electrode of the fifth transistor is connected to a first power supply signal line and a second electrode plate of the storage capacitor, and a second electrode of the fifth transistor is connected to the second electrode of the fourth transistor and the first electrode of the driver transistor; a gate electrode of the sixth transistor is connected to the first light emission control signal line, a first electrode of the sixth transistor is connected to the second electrode of the driver transistor and the second electrode of the second transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting element and a second electrode of the seventh transistor; a gate electrode of the seventh transistor is connected to the first scanning signal line or the reset control signal line, a first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor and the second electrode of the sixth transistor are connected to the first electrode of the light-emitting element; a gate electrode of the eighth transistor is connected to a second scanning signal line, a first electrode of the eighth transistor is connected to the second electrode of the first transistor and the first electrode of the second transistor, and a second electrode of the eighth transistor is connected to the gate electrode of the driver transistor and the first electrode plate of the storage capacitor; the first electrode plate of the storage capacitor is connected to the gate electrode of the driver transistor and the second electrode of the eighth transistor, and the second electrode plate of the storage capacitor is connected to the first power supply signal line. [19] The display substrate of claim 18, further comprising: a first active layer between the base substrate and the second conductive layer, the first active layer comprising a first active part, a second active part, a third active part, a fourth active part, a fifth active part, a sixth active part, and a seventh active part, the first active part forming a channel region of the first transistor, the second active part forming a channel region of the second transistor, the third active part forming a channel region of the driver transistor, the fourth active part forming a channel region of the fourth transistor, the fifth active part forming a channel region of the fifth transistor, the sixth active part forming a channel region of the sixth transistor, and the seventh active part forming a channel region of the seventh transistor; a second active layer between the first active layer and the second conductive layer, wherein the second active layer comprises an eighth active part and the eighth active part forms a channel region of the eighth transistor. [20] The display substrate according to claim 18 or 19, further comprising a third conductive layer, the third conductive layer comprising: the first scanning signal line, wherein an orthographic projection of the first scanning signal line on the base substrate extends along the second direction, and a partial pattern of the first scanning signal line is used to form gate electrodes of the second transistor and the fourth transistor; the reset control signal line, wherein an orthographic projection of the reset control signal line on the base substrate extends along the first direction and a partial pattern of the reset control signal line is used to form gate electrodes of the seventh transistor and the first transistor; the first light emission control signal line, wherein an orthographic projection of the first light emission control signal line on the base substrate extends along the first direction, and a partial structure of the first light emission control signal line is used to form gate electrodes of the sixth transistor and the fifth transistor; and a third conductive part forming the gate electrode of the driver transistor and the first electrode plate of the storage capacitor; wherein, in the same pixel circuit, an orthographic projection of the third conductive part on the base substrate is arranged between the orthographic projection of the first scanning signal line on the base substrate and the orthographic projection of the first light emission control signal line on the base substrate; wherein the orthographic projection of the reset control signal line on the base substrate is arranged on a side of the orthographic projection of the first light emission control signal line on the base substrate that is remote from the orthographic projection of the third conductive part on the base substrate. [21] The display substrate according to claim 20, further comprising a conductive film layer between the third conductive layer and the second conductive layer, the conductive film layer comprising: the second scanning signal line, wherein a partial structure of the second scanning signal line is used to form a lower gate electrode of the eighth transistor; a first conductive part comprising two second electrode plates of two storage capacitors adjacent in the second direction; and a fifth conductive part electrically connected to the first conductive layer. [22] The display substrate according to claim 21, wherein the first conductive part further comprises a bridge part connecting the two second electrode plates, and wherein the first conductive part comprises a recess between the two second electrode plates. [23] The display substrate according to claim 21 or 22, further comprising a fourth conductive layer, wherein the fourth conductive layer is disposed between the conductive film layer and the second conductive layer, and the fourth conductive layer includes the first initial signal line and a fourth scanning signal line, and a partial structure of the fourth scanning signal line forms an upper gate electrode of the eighth transistor. [24] The display substrate according to any one of claims 21 to 23, wherein an extending direction of the data line is a first direction and a direction perpendicular or substantially perpendicular to the extending direction of the data line is a second direction, wherein the first connection structure has an inverted "L" shape, and wherein an end of a part of the inverted "L" shape extending along the second direction, which is remote from a nearest data line, is connected to the second electrode of the eighth transistor. [25] The display substrate according to claim 24, wherein the part of the inverted "L" shape extending along the first direction is electrically connected to the fifth conductive part of the conductive film layer; wherein the first scanning signal line includes a projecting part extending along the first direction and a part extending along the second direction, and wherein the fifth conductive part overlaps with the projecting part of the first scanning signal line extending along the first direction. [26] The display substrate according to any one of claims 3 to 25, wherein the plurality of subpixels comprises a plurality of first subpixels, a plurality of second subpixels, and a plurality of third subpixels; wherein two second subpixels form a second subpixel pair, the two second subpixels in a second subpixel pair are each a first pixel block and a second pixel block, and the first pixel block and the second pixel block are arranged alternately along the first direction or the second direction; wherein the plurality of subpixels comprises a plurality of minimum repeat units, and a minimum repeat unit comprises a first subpixel, a first pixel block, a second pixel block, and a third subpixel. [27] The display substrate of claim 26, further comprising a first electrode layer, wherein the first electrode layer is located on a side of the second conductive layer remote from the base substrate, and the first electrode layer comprises a plurality of electrode parts, each of the plurality of electrode parts comprising a body part and a supplementary part connected to each other, wherein an orthographic projection of the supplementary part on the base substrate at least partially overlaps the orthographic projection of the first electrode transmission line on the base substrate, and wherein each of the plurality of electrode parts corresponds to one of the first subpixel, the first pixel block, the second pixel block, and the third subpixel. [28] A display substrate according to claim 27, wherein the plurality of electrode parts comprises a first electrode part, a second electrode part, and a third electrode part having three different colors, the first electrode part corresponds to the first subpixel, the second electrode part corresponds to any one of the first pixel block and the second pixel block, and the third electrode part corresponds to the third subpixel; an overlap area of ​​an orthographic projection of the first electrode part on the base substrate with an orthographic projection of the first power supply signal line on the base substrate is larger than an overlap area of ​​an orthographic projection of the second electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate, and is larger than an overlap area of ​​an orthographic projection of the third electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate; the overlap area of ​​the orthographic projection of the third electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate is larger than the overlap area of ​​the orthographic projection of the second electrode part on the base substrate with the orthographic projection of the first power supply signal line on the base substrate. [29] The display substrate according to claim 28, wherein the first electrode part corresponds to a blue subpixel emitting blue light, the second electrode part corresponds to a green subpixel emitting green light, and the third electrode part corresponds to a red subpixel emitting red light. [30] The display substrate according to any one of claims 27 to 29, wherein the second conductive layer further comprises a plurality of first electrode transmission lines, and the plurality of first electrode transmission lines are arranged in one-to-one correspondence with the plurality of electrode parts, and the electrode parts are each connected to a corresponding first electrode transmission line through a through-hole. [31] The display substrate according to any one of claims 1 to 30, wherein the subpixel further comprises a light-shielding layer located on a side of an active semiconductor pattern of the driver transistor that is close to the base substrate, wherein an orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active semiconductor pattern of the driver transistor on the base substrate. [32] A display device comprising the display substrate according to any one of claims 1 to 31.

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