Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate comprises a plurality of subpixels (10) on a base substrate (001) and a plurality of power supply signal lines (300) extending in a first direction and arranged in a second direction; at least some of the subpixels (10) comprising a plurality of first subpixels (010); in a third direction perpendicular to the base substrate (001), at least one power supply signal line (300) comprises a first power supply section (301), wherein the first power supply section (301) comprises a first main section (31) and a second main section (32);In the second direction, the maximum size of the main electrode (1040) of the first subpixel (010) is not smaller than the maximum size of its corresponding first power supply section (301), the maximum size of the first main section (31) is larger than the maximum size of the second main section (32), the connecting line between the two endpoints of the main electrode (1040) of the first subpixel (010) that are furthest apart in the second direction is an endpoint connecting line, and the endpoint connecting line overlaps with the first main section (31). The flatness of the connecting electrode in the light-emitting element is improved, and the probability of chromatic aberration and the like in the display product is reduced.

Description

FIELD OF TECHNOLOGY

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device. STATE OF THE ART

[0002] Currently, active matrix organic light-emitting diode (AMOLED) technology is becoming increasingly mature for flexible displays. These displays have strong development prospects, featuring flexibility, high contrast, and low power consumption. With the continuous development of display technology, optimizing the display effect has become an inevitable trend. To improve display performance, some display products reduce chromatic aberration by optimizing the arrangement between the conductive structure and the light-emitting element in the pixel. SUMMARY

[0003] At least one embodiment of the disclosure provides a display substrate and a display device.

[0004] Embodiments of the disclosure provide a display substrate comprising: a base substrate; a plurality of subpixels on the base substrate, each of at least some of the subpixels comprising a light-emitting element and a pixel circuit, the light-emitting element comprising a light-emitting functional layer and a first electrode and a second electrode provided on two sides of the light-emitting functional layer in a direction perpendicular to the base substrate, the first electrode being provided between the light-emitting functional layer and the base substrate, the light-emitting element being provided at least partially in a light-emitting region, and the first electrode of the light-emitting element comprising a main electrode overlapping with the light-emitting region; a plurality of power supply signal lines,wherein at least some of the plurality of power supply signal lines extend in the first direction and are arranged in a second direction, wherein the plurality of power supply signal lines are provided between the base substrate and the first electrode of the light-emitting element, wherein the first direction intersects the second direction. The at least some of the subpixels comprise a plurality of first subpixels, wherein in a third direction perpendicular to the base substrate, at least one power supply signal line comprises a first power supply section that overlaps with the main electrode of at least one of the plurality of first subpixels, wherein the first power supply section comprises a first main section and a second main section. In the second direction, a maximum size of the main electrode of the first subpixel is not smaller than a maximum size of its corresponding first power supply section.a maximum size of the first main section is larger than a maximum size of the second main section in the first power supply section, a connecting line of two end points of the main electrode of the first subpixel that are farthest apart in the second direction is an end point connecting line, and the end point connecting line overlaps with the first main section in the third direction.

[0005] According to embodiments of the disclosure, for example, the plurality of power supply signal lines includes a first power supply signal line and a second power supply signal line, a maximum size of the first power supply signal line and a maximum size of the second power supply signal line in the second direction are a first size and a second size, respectively, and the second size is smaller than the first size.

[0006] For example, according to embodiments of the disclosure, the plurality of first subpixels include at least one first-type subpixel, wherein the first power supply portion overlapping with the main electrode of the first-type subpixel is a first-type power supply portion, and the first main portion of the first-type power supply portion is an asymmetric structure.

[0007] For example, according to embodiments of the disclosure, the first main portion of the first type power supply portion includes a first protrusion, and the first protrusion is provided on a side of a first symmetrical center line of the second main portion extending in the first direction.

[0008] For example, according to embodiments of the disclosure, an extending direction of a symmetrical center line of the portion of the first type power supply section except for the first protrusion intersects an extending direction of a second symmetrical center line of the main electrode of the first type subpixel.

[0009] For example, according to embodiments of the disclosure, the plurality of first subpixels further includes at least one second-type subpixel, and the first power supply portion overlapping with the main electrode of the second-type subpixel is a second-type power supply portion, wherein the second-type power supply portion includes a third symmetrical center line extending in the first direction, the main electrode of the second-type subpixel has a fourth symmetrical center line extending in the first direction, the third symmetrical center line of the second-type power supply portion is provided in a same column of the power supply signal line, and the fourth symmetrical center line of the second-type subpixel overlapping with the second-type power supply portion is provided in a same plane perpendicular to the base substrate.

[0010] For example, according to embodiments of the disclosure, the main electrode of the first subpixel includes a first corner and a second corner opposite each other, and a third corner and a fourth corner opposite each other, an orthographic projection of at least one of the first corner and the second corner on the base substrate at least partially overlaps with an orthographic projection of the first symmetric center line on the base substrate, and an orthographic projection of the fourth corner on the base substrate at least partially overlaps with an orthographic projection of the first protrusion on the base substrate.

[0011] For example, according to embodiments of the disclosure, the first main portion of the second type power supply portion includes a second protrusion and a third protrusion, and the second protrusion and the third protrusion are symmetrically distributed relative to the third symmetric center line, the main electrode of the second type subpixel includes a first corner and a second corner opposite to each other, and a third corner and a fourth corner opposite to each other, an orthographic projection of the second protrusion on the base substrate at least partially overlaps with an orthographic projection of one of the first corner and the second corner on the base substrate, and an orthographic projection of the third protrusion on the base substrate at least partially overlaps with the orthographic projection of the other of the first corner and the second corner on the base substrate.

[0012] For example, according to embodiments of the disclosure, the light-emitting region of the second type subpixel overlaps in the third direction with at least one of the second protrusion and the third protrusion.

[0013] For example, according to embodiments of the disclosure, in the second direction, a maximum size of the first main portion of the second type power supply portion is larger than a maximum size of the first main portion of the first type power supply portion, and a ratio of a maximum size of the second main portion of the first type power supply portion to a maximum size of the second main portion of the second type power supply portion is 0.9~1.1.

[0014] For example, according to embodiments of the disclosure, the maximum size of the first main portion of the second type power supply portion in the second direction is 1.1-2 times the maximum size of the second main portion of the second type power supply portion in the second direction.

[0015] According to embodiments of the disclosure, for example, each of the adjacent plurality of power supply signal lines includes a plurality of power supply portions arranged in the first direction, and a first connection portion is provided between and electrically connected to two adjacent power supply portions, and the plurality of power supply portions includes the first power supply portion, wherein a ratio of a maximum size of the power supply portion in the second direction to a maximum size of the first connection portion in the second direction is 1.5-5.

[0016] For example, according to embodiments of the disclosure, the first type power supply portion includes a first subtype power supply portion and a second subtype power supply portion, the second main portion of the first type power supply portion includes a first side and a second side opposite to each other in the second direction, the first protrusion of the first subtype power supply portion is disposed on the first side of the second main portion, and the first protrusion of the second subtype power supply portion is disposed on the second side of the second main portion.

[0017] For example, according to embodiments of the disclosure, the main electrode of the first subpixel comprises a plurality of corners, the plurality of corners comprising the first corner, the second corner, the third corner, and the fourth corner, wherein edges or their extension lines of the main electrode are connected sequentially to form a polygon, and each of a plurality of vertex angles of the polygon has an area that does not overlap with the corresponding corner of the main electrode, wherein a non-overlapping area of ​​the third corner and the corresponding vertex angle of the polygon is larger than a non-overlapping area of ​​each of at least some other corners and the corresponding vertex angle of the polygon.

[0018] According to embodiments of the disclosure, the at least some of the subpixels further comprise a plurality of second subpixels, in the third direction, the at least one power supply signal line comprises a second power supply portion overlapping with the main electrode of at least one of the plurality of second subpixels, wherein the second power supply portion comprises a fifth symmetrical centerline extending in the first direction, the main electrode of the second subpixel has a sixth symmetrical centerline extending in the first direction, the fifth symmetrical centerline of the second power supply portion is provided in a same column of the power supply signal line, and the sixth symmetrical centerline of the second subpixel overlapping with the second power supply portion is provided in a same plane perpendicular to the base substrate.

[0019] For example, according to embodiments of the disclosure, an orthographic projection of the main electrode of the second subpixel on the base substrate and an orthographic projection of the second power supply portion on the base substrate overlap, wherein an overlap area is at least 90% of an area of ​​the orthographic projection of the main electrode of the second subpixel on the base substrate.

[0020] For example, according to embodiments of the disclosure, in the second direction, a maximum size of the second power supply section is smaller than a maximum size of the first main section of the first power supply section, and a ratio of the maximum size of the second power supply section and a maximum size of the second main section of the first power supply section is 0.9~1.1.

[0021] According to embodiments of the disclosure, for example, the display substrate further comprises a plurality of data lines extending in the first direction and arranged in the second direction, wherein the plurality of data lines and the plurality of power supply signal lines are provided in a same layer, wherein the data lines provided between two adjacent power supply signal lines include a first data line and a second data line arranged in the second direction, wherein the first data line and the second data line are symmetrically distributed relative to a seventh symmetrical center line provided between the first data line and the second data line;at least some of the subpixels further comprise a plurality of third subpixels, the main electrode of the light-emitting element of at least one of the plurality of third subpixels at least partially overlaps with the data line, and an overlapping region of the main electrode of the third subpixel and the data line is substantially symmetrical relative to the seventh symmetrical center line;

[0022] For example, according to embodiments of the disclosure, the display substrate further comprises a plurality of second connection portions arranged in the same layer as at least some of the plurality of power supply signal lines, each second connection portion comprising a first connector and a second connector; the plurality of second connection portions are arranged in an array in the first direction and the second direction to form a plurality of second connection portion rows and a plurality of second connection portion columns;the power supply signal line comprises a plurality of power supply sections arranged in the first direction, a first connection section is provided between and electrically connected to two adjacent power supply sections, and the power supply sections of the plurality of power supply signal lines are arranged in an array in the first direction and the second direction to form a plurality of power supply section rows and a plurality of power supply section columns; the plurality of second connection section rows and the plurality of power supply section rows are arranged alternately in the first direction, and two adjacent second connection sections in a same second connection section row are arranged on two sides of the data line, respectively;

[0023] For example, according to embodiments of the disclosure, the connection electrode of the light-emitting element and the first connection portion are substantially non-overlapped with each other; in the first direction, a maximum size of the main electrode of the first subpixel is not smaller than a maximum size of the first main portion of the corresponding first power supply portion.

[0024] For example, according to embodiments of the disclosure, the first connector is electrically connected to the connection electrode of the first subpixel or the connection electrode of the second subpixel, and the second connector is electrically connected to the connection electrode of the third subpixel.

[0025] For example, according to embodiments of the disclosure, the first connecting portion includes at least one hollowed portion, and an area of ​​the hollowed portion is 1 / 4-1 / 3 of an area of ​​the first connecting portion.

[0026] Embodiments of the disclosure provide a display device including the display substrate described above. SHORT DESCRIPTION OF THE CHARACTERS

[0027] In order to clearly illustrate the technical solution of the embodiments of the disclosure, the drawings of the embodiments are briefly described below; it is obvious that the described drawings only relate to some embodiments of the disclosure and therefore do not limit the disclosure. Fig. 1A is a schematic view of a local cross-sectional structure of a display substrate. Fig. 1B is a schematic view of a local cross-sectional structure of another display substrate. Fig. 2A is a schematic view showing the overlapping relationship between the pixel array and the conductive layer in a display substrate. Fig. 2B is a schematic view showing the overlapping relationship between the pixel array and the conductive layer in another display substrate. Fig. 3 is a schematic view of the pixel array structure of a display substrate provided by embodiments of the present disclosure. Fig. 4 is a schematic view of the local cross-sectional structure along the Fig. Line AA' shown in Figure 3. Fig. 5 is a schematic view of a stacked structure of a second conductive layer and a first electrode of a light-emitting element in the display substrate provided by the embodiments of the present disclosure. Fig. 6 is a schematic view of a local structure of the second conductive layer in the display substrate provided by the embodiments of the present disclosure. Fig. 7 is a schematic view of a local structure of the first electrode of the light-emitting element of the display substrate provided by the embodiments of the present disclosure. Fig. 8 is an equivalent diagram of a pixel circuit provided by the embodiments of the present disclosure. Fig. 9 is a schematic view of a stacked structure of a light-shielding layer, an active semiconductor pattern, and a first interconnection layer in the pixel circuit provided by the embodiments of the present disclosure. Fig. 10 is a schematic view of a stacked structure of the light-shielding layer, the active semiconductor pattern, the first interconnection layer, a second interconnection layer, a semiconductor layer, and a third interconnection layer in the pixel circuit provided by the embodiments of the present disclosure. Fig. 11 is a schematic view of the local structure of the first conductive layer provided by the embodiments of the present disclosure. Fig. 12 is a schematic view of the stacked structure of the light-shielding layer, the active semiconductor pattern, the first interconnection layer, the second interconnection layer, the semiconductor layer, the third interconnection layer, and the first conductive layer in the pixel circuit provided by the embodiments of the present disclosure. Fig. 13 is a schematic view of the stacked structure of the first conductive layer and the second conductive layer provided by the embodiments of the present disclosure. DETAILED DESCRIPTION OF REVELATION

[0028] To clarify the objects, technical details, and advantages of the embodiments of the disclosure, the technical solutions of the embodiments are described in a clear and fully understandable manner in conjunction with the drawings relating to the embodiments of the disclosure. It is obvious that the described embodiments represent only a part, but not all, of the embodiments of the disclosure. Based on the embodiments described herein, one skilled in the art can, without inventive activity, obtain other embodiments that should fall within the scope of the disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used herein should have a general meaning as understood by one of ordinary skill in the art. In the descriptions and claims of the present disclosure, terms such as "first," "second," and the like do not imply order, quantity, or importance, but are used to distinguish various components. Terms such as "include" or "comprise" and the like mean that elements or objects appearing before the words "include" or "comprise" include the elements or objects, or their equivalents, enumerated after the words "include" or "comprise," not exclusive of other elements or objects.

[0030] The terms such as "vertical", "parallel", and "equal" and the like, as used in the embodiments of the present disclosure, include features such as "vertical", "parallel", and "equal" in the narrow sense, and also include features such as "substantially vertical", "substantially parallel", "substantially equal" that contain certain errors, so that these terms allow a range of deviation of a certain value that is acceptable to those of ordinary skill in the art, taking into account the measurement and the error associated with measuring a certain quantity (ie, taking into account the limitation of the measurement system).The term "center," as used in embodiments of the present disclosure, encompasses a location located exactly at the center of the geometry and also includes a position located in a substantially central region around the center of the geometry. For example, the term "substantially / approximately" means within one or more standard deviations of the value, or within 10% or 5% of the value.

[0031] The performance specifications of organic light-emitting diode display products include power consumption, brightness, and chromatic aberration. Component factors that can affect the chromatic aberration of organic light-emitting diode display products include the flatness of the anode. Optimized design for the flatness of the anode in the light-emitting element can prevent the deviation of the outgoing light from the light-emitting element, thereby reducing chromatic aberration and other phenomena in the display product.

[0032] Fig. Figure 1A is a schematic view showing a local cross-sectional structure of a display substrate. As shown in Fig. 1A, the display substrate includes a film layer 91; the film layer 91 includes, for example, a base substrate, an active semiconductor layer provided on the base substrate, and at least one interconnection layer provided on the side of the active semiconductor layer remote from the base substrate. The display substrate further includes a conductive layer 11 provided on the film layer 91, wherein the conductive layer 11 includes, for example, a data line, a power supply signal line, and the like. The display substrate further includes a planarization layer 12 provided on the side of the conductive layer 11 remote from the film layer 91, an anode 13 provided on the side of the planarization layer 12 remote from the conductive layer 11, and a pixel definition layer 14 provided on the side of the anode 13 remote from the planarization layer 12.The pixel definition layer 14 includes a plurality of openings 15-17 for defining the light-emitting region of the subpixels. Each of the plurality of openings 15-17 exposes a portion of the anode 13; when the subsequent organic light-emitting layer is formed in the openings 15-17 of the above pixel definition layer 14, the organic light-emitting layer is in contact with the anode 13, so that the anode 13 drives the organic light-emitting layer to emit light.

[0033] In the display substrate, for example, the arrangement of the conductive layer 11 has a great influence on the light output effect of the light-emitting element, because, for example, the conductive layer 11 may destroy the flatness of the anode of the light-emitting element and then cause the chromatic aberration of the light-emitting element.

[0034] As in Fig. As shown in Figure 1A, the thickness of the conductive layer 11 is relatively large, for example, the thickness is 0.6-0.9 μm, which causes the surface of the planarization layer 12 provided on the conductive layer 11 facing the anode 13 to be non-flat. For example, the distance between the surface of a part of the planarization layer 12 directly above the conductive layer 11 (e.g., a data line, a power supply signal line, and a pattern of the same material in the same layer) facing away from the film layer 91 and the surface of the film layer 91 facing away from the planarization layer 12 is h1, and the distance between the surface of a part of the planarization layer 12 directly above the area not provided with the conductive layer 11 and the surface of the film layer 91 facing away from the planarization layer 12 is h2, h1>h2.

[0035] As in Fig. 1A, in the opening 16, a part of the planarization layer 12 is overlapped with the conductive layer 11, and the other part of the planarization layer 12 is not overlapped with the conductive layer 11, whereby the surface of the planarization layer 12 facing the anode 13 in the opening 16 is not flat, resulting in a surface of the anode 13 provided on the planarization layer 12 being not flat.For example, for the anode 13 provided in the opening 16, the distance between the surface of a part of the anode 13 facing away from the film layer 91, which is provided directly above the conductive layer 11, and the surface of the film layer 91 facing away from the anode 13 is h3, the distance between the surface of a part of the anode 13 facing away from the film layer 91, which is provided directly above the area not provided with the conductive layer 11, and the surface of the film layer 91 facing away from the anode 13 is h4, h3>h4. In this way, the anode 13 is "tilted" within the opening 16.Similarly, the anode 13 is also "tilted" within the opening 15; and due to the position of the conductive layer 11, the "tilt direction" of the anode 13 within the opening 15 differs from the "tilt direction" of the anode 13 within the opening 16, resulting in uneven light intensities emitted by the subpixels corresponding to the opening 15 and the opening 16 in the respective directions. For example, the X-direction arrow points to the right, and the intensities of the light emitted by the light-emitting regions defined by the opening 15 and the opening 16 are uneven in the left and right directions.Directly below the anode 13 provided in the opening 17, no conductive layer 11 is provided, so that the surface of the anode 13 in the opening 17 is substantially flat, no "tilt" occurs, and the intensities of the light emitted from the light-emitting region defined by the opening 17 are equal in the respective directions.For the light-emitting regions of three adjacent subpixels of different colors defined by openings 15-17, the anode 13 in opening 15 is "tilted" to the left, the anode 13 in opening 16 is "tilted" to the right, and the anode 13 in opening 17 is not tilted. Therefore, the "tilt" directions of the anodes 13 of subpixels of different colors are different, resulting in a mismatch of the light intensities emitted by the light-emitting regions of the three subpixels in the left and right directions. A display device using such a display substrate has a large viewing error, and when viewed by the human eye, a chromatic aberration similar to redness on one side and blue on the other side occurs.

[0036] Fig. Figure 1B is another schematic view showing a local cross-sectional structure of the display substrate. Fig. The display substrate shown in Figure 1B comprises the Fig. 1A, the conductive layer 11, the planarization layer 12, the anode 13 and the pixel definition layer 14. As shown in Fig. As shown in Figure 1B, the planarization layer 12 in the display substrate includes a through-hole 18 so that the anode 13 is electrically connected to the conductive layer 11. The pixel definition layer 14 includes an opening 19 to expose a portion of the anode 13, and when the subsequent organic light-emitting layer is formed in the opening 19, the organic light-emitting layer is in contact with the anode 13 to form the light-emitting region.

[0037] As in Fig. As shown in Fig. 1B, the through-hole 18 is provided outside the light-emitting region; since the anode 13 provided around the through-hole 18 is inclined, a certain distance should be provided between the light-emitting region and the through-hole 18 to ensure the flatness of the anode 13 in the light-emitting region to avoid the chromatic aberration of the display substrate.

[0038] Referring to Fig. 1A-1B, the positional relationship between the conductive layer 11 and the anode 13 and the positional relationship between the through-hole 18 in the planarization layer 12 and the anode 13 both affect the flatness of the anode 13 in the light-emitting region, resulting in the display substrate being susceptible to chromatic aberration.

[0039] Fig. 2A is a schematic view showing the overlapping relationship between the pixel array and the conductive layer in a display substrate; Fig. 2B is a schematic view showing the overlapping relationship between the pixel array and the conductive layer in another display substrate; Fig. 2C is a schematic view showing the overlapping relationship of a subpixel and the conductive layer in a display substrate.

[0040] For reasons of clarity, Fig. 2A and Fig. 2B shows the overlap relationship between the anode of the light-emitting element in the pixel circuit and the conductive layer connected thereto. Referring to the Fig. 2A and Fig. 2B, the conductive layer comprises a plurality of conductive parts, and the anode of the light-emitting element at least partially overlaps with the conductive part of the conductive layer in the direction perpendicular to the base substrate of the display substrate. The display substrate comprises a plurality of subpixels, such as a blue subpixel 01 configured to emit blue light, a red subpixel 02 configured to emit red light, and a green subpixel 03 configured to emit green light; wherein the green subpixel 03 configured to emit green light comprises a first green subpixel 031 and a second green subpixel 032. The light-emitting element of each subpixel comprises a light-emitting region; for example, the light-emitting region is defined by the opening in the pixel definition layer.

[0041] As in Fig. 2A, the light-emitting area corresponding to each subpixel refers to the area shown by the dashed line. For the blue subpixel 01 configured to emit blue light, the light-emitting area includes an overlapping area 0110 and a non-overlapping area 0111, and the area of ​​the non-overlapping area 0111 is larger than the area of ​​the overlapping area 0110; in combination with the display substrate in Fig. 1A, the distance between the surface (not shown in the drawings) of a portion of the anode directly above the conductive layer and the surface of the base substrate facing away from the anode in the overlapping region 0110 corresponds to h3, and the distance between the surface of a portion of the anode directly above the region not provided with the conductive layer and the surface of the base substrate facing away from the anode in the non-overlapping region 0111 corresponds to h4, h3 > h4. Consequently, the anode 13 is "tilted" in the light-emitting region of the blue subpixel 01. At the same time, the distribution of the non-overlapping region 0111 is not symmetrical relative to the overlapping region 0110.

[0042] For example, in some embodiments of the present disclosure, in the case where the non-overlapping region in the light-emitting region is distributed symmetrically relative to the overlapping region, the anode in the light-emitting region exhibits "symmetrical tilt," that is, in the light-emitting region, the tilt directions of the light caused by the non-overlapping region and the overlapping region are symmetrical. In this case, compared with the "tilt only to one side" in Fig. 2A, which is caused by the asymmetric arrangement of the non-overlapping area 0111 and the overlapping area 0110, the chromatic aberration of subpixels is weakened when the non-overlapping area is distributed symmetrically relative to the overlapping area.

[0043] As in Fig. 2B, the display substrate includes a plurality of subpixels, such as a blue subpixel 04 configured to emit blue light, a red subpixel 05 configured to emit red light, and a green subpixel 06 configured to emit green light; wherein the green subpixel 06 configured to emit green light includes a first green subpixel 0061 and a second green subpixel 0062. Compared to Fig. 2A has the conductive layer that connects with the anode in the light-emitting area of ​​subpixel 04 and subpixel 05 in Fig. 2B overlaps, a better flatness. The non-overlapping area of ​​the anode and the conductive layer in the light-emitting area of ​​subpixel 0062 or subpixel 0061 has a certain symmetry compared to the overlapping area. As a result, the chromatic aberration of the display substrate in Fig. 2B relatively weak.

[0044] Thus, in the pixel circuit, the conductive layer overlapping the anode in the light-emitting region of the sub-pixel light-emitting element must maintain a certain level of flatness to prevent the anode from tilting in the sub-pixel light-emitting region. At the same time, the symmetry of the non-overlapping region relative to the overlapping region also affects the luminescence effect when the non-overlapping region is created based on actual patterning requirements.

[0045] The embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a plurality of subpixels, and a plurality of power supply signal lines. The plurality of subpixels are provided on the base substrate, each of at least some of the subpixels comprising a light-emitting element and a pixel circuit. The light-emitting element includes a light-emitting functional layer and a first electrode and a second electrode, each provided on two sides of the light-emitting functional layer in the direction perpendicular to the base substrate. The first electrode is provided between the light-emitting functional layer and the base substrate. The light-emitting element is provided at least partially in a light-emitting region. The first electrode of the light-emitting element includes a main electrode.which overlaps with the light-emitting region; at least some of the plurality of power supply signal lines extend in a first direction and are arranged in a second direction, the plurality of power supply signal lines are provided between the base substrate and the first electrode of the light-emitting element, the first direction intersecting the second direction; the at least some of the subpixels comprise a plurality of first subpixels, at least one power supply signal line comprises a first power supply portion that overlaps with the main electrode of at least one of the plurality of first subpixels along a third direction perpendicular to the base substrate,the first power supply section comprises a first main section and a second main section; in the second direction, the maximum size of the main electrode of the first subpixel is not smaller than the maximum size of its corresponding first power supply section, the maximum size of the first main section is larger than the maximum size of the second main section in the first power supply section, a connecting line of two end points of the main electrode of the first subpixel that are farthest apart in the second direction is an end point connecting line, and the end point connecting line overlaps with the first main section in the third direction. The embodiments of the present disclosure design the matching shape of the pixel circuit and the light-emitting element, which contributes to improving the flatness of the part of the conductive layer that overlaps with the light-emitting element.and contributes to reducing the likelihood of chromatic aberration and other phenomena in the display products.

[0046] The display substrate and the display device provided in the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings.

[0047] Fig. 3 is a schematic view of a pixel array structure of the display substrate provided by the embodiments of the present disclosure; Fig. Figure 4 is a schematic view of a local cross-sectional structure along the AA' line in Fig. 3; Fig. 5 is a schematic view of the stacked structure of a second conductive layer and a first electrode of a light-emitting element in the display substrate provided by the embodiments of the present disclosure; Fig. 6 is a schematic view of a local structure of the second conductive layer of the display substrate provided by the embodiments of the present disclosure; Fig. 7 is a schematic view of a local structure of the first electrode of the light-emitting element in the display substrate provided by the embodiments of the present disclosure.

[0048] With reference to the Fig. 3 and Fig. 4, the display substrate comprises a base substrate 001 and a plurality of subpixels 10, the plurality of subpixels 10 are provided on the base substrate 001, each of at least some of the subpixels 10 comprises a light-emitting element 100 and a pixel circuit 200 (see Fig. 8). For example, the pixel circuit 200 is configured to drive the light-emitting element 100 to emit light. The light-emitting element 100 includes a light-emitting functional layer 101, and a first electrode 102 and a second electrode 1022, each provided on two sides of the light-emitting functional layer 101 in the Z direction perpendicular to the base substrate 001, with the first electrode 102 being provided between the light-emitting functional layer 101 and the base substrate 001.

[0049] With reference to the Fig. 3 and Fig. 4, a structural layer 1004 is provided on a side of the first electrode 102 of the light-emitting element 100 facing away from the second electrode 1022. The structural layer 1004 includes, for example, a film layer such as the base substrate, a layer in which an active semiconductor pattern is located, a film layer in which a gate line is located, a film layer in which a data line is located, and a plurality of insulating layers, etc. The display substrate further includes a pixel definition pattern 150, the pixel definition pattern 150 is provided on the side of the first electrode 102 of the light-emitting element 100 facing away from the base substrate 001, and the pixel definition pattern 150 includes a plurality of openings 160 and definition portions 170 surrounding the plurality of openings 160, and the plurality of light-emitting elements 100 are at least partially provided in the plurality of openings 160.

[0050] For example, the defining portion 170 defines the size of the opening 160. The material of the defining portion 170 includes, for example, polyimide, acrylic, or polyethylene terephthalate, etc.

[0051] With reference to Fig. 3 and Fig. 4, the pixel circuit 200 comprises a light-emitting control transistor T6 (see Fig. 8), wherein the first electrode 102 of the light-emitting element 100 is electrically connected to the light-emitting control transistor T6.

[0052] For example, the light-emitting element 100 is at least partially provided within a light-emitting region 103, and the first electrode 102 of the light-emitting element 100 includes a main electrode 104 that overlaps with the light-emitting region 103. The portion of the light-emitting element 100 provided within the opening 160 is the light-emitting region 103, and the orthographic projection of the light-emitting region 103 on the base substrate 001 lies within the orthographic projection of the first electrode 102 on the base substrate. For example, the main electrode 104 is the portion of the first electrode 102 excluding a connection electrode (see descriptions below).In some embodiments of the present disclosure, the first electrode 102 includes, in addition to the connection electrode and the main electrode, a protrusion electrode (not shown in the drawings), wherein the protrusion electrode protrudes relative to the main electrode of the first electrode 102, for example. The protrusion electrode is configured, for example, to block part of the structure in the pixel circuit 200. For example, the protrusion electrode is configured to form a capacitance with some conductive structures in the pixel circuit 200.

[0053] For example, the shape of the main electrode 104 is the same shape as the opening 160 of the pixel definition pattern 150. For example, the shape of the main electrode 104 differs from the shape of the opening 160 of the pixel definition pattern 150, and the embodiments of the present disclosure are not limited thereto. For example, the main electrode 104 is polygonal. For example, the apex angle of the main electrode 104, which is shaped as a polygon, is a chamfer. The boundary of the main electrode 104 is formed, for example, by connecting the ends of the protrusion electrode with a smooth transition between the edges of the protrusion electrode in the first electrode 102. For example, the first electrode 102 may include a plurality of protrusion electrodes.

[0054] For example, the opening 160 of the pixel definition pattern 150 is configured to define the light-emitting region 103 of the light-emitting element 100. For example, the light-emitting elements 100 of the plurality of subpixels 10 are provided in one-to-one correspondence with the plurality of openings 160. For example, the light-emitting element 100 includes a portion provided in the opening 160 and a portion overlapping with the definition portion 170 in the direction perpendicular to the base substrate 001. For example, the orthographic projection area of ​​the light-emitting element 100 on the base substrate 001 is larger than the orthographic projection area of ​​the opening 160 on the base substrate 001.

[0055] For example, the opening 160 of the pixel definition pattern 150 is configured to expose the first electrode 102 of the light-emitting element 100, and the exposed portion of the first electrode 102 is at least partially in contact with the light-emitting functional layer 101 of the light-emitting element 100. For example, at least a part of the first electrode 102 is provided between the definition portion 170 and the base substrate 001. For example, when the light-emitting functional layer 101 is provided in the opening 160 of the pixel definition pattern 150, the first electrode 102 and the second electrode 102, which are respectively provided on two sides of the light-emitting functional layer 101, are capable of driving the light-emitting functional layer 101 in the opening 160 of the pixel definition pattern 150 to emit light.

[0056] The first electrode 102 is, for example, an anode, and the second electrode 1022 is a cathode. The cathode is made of materials with high conductivity and a low work function, such as metallic materials. The anode is made of a conductive material with a high work function, for example.

[0057] For example, the light-emitting region 103 is the effective light-emitting region of the light-emitting element 100. The shape of the light-emitting region 103 refers to a two-dimensional shape. For example, the shape of the light-emitting region 103 is the same as the shape of the opening 160 of the pixel definition pattern 150. For example, the opening 160 of the pixel definition pattern 150 has a shape with a small size on a side close to the base substrate 001 and a large size on the side facing away from the base substrate 001. For example, the shape of the light-emitting region 103 is approximately the same size and shape as the side of the opening 160 of the pixel definition pattern 150 close to the base substrate 001.

[0058] With reference to Fig. 3, Fig. 4 and Fig. 6, the display substrate further comprises a plurality of power supply signal lines 300, wherein at least some of the plurality of power supply signal lines 300 extend along the first direction N and are arranged along the second direction Y, wherein the plurality of power supply signal lines 300 are provided between the base substrate 001 and the first electrodes 102 of the light-emitting elements 100, wherein the first direction N and the second direction Y intersect with each other. For example, the first direction N is perpendicular to the second direction Y.

[0059] For example, the pixel circuit 200 further comprises a light-emitting control transistor T5 (as shown in Fig. 8), and the light-emitting control transistor T5 is electrically connected to the power supply signal line 300. For example, the plurality of power supply signal lines 300 are arranged in the same conductive layer and configured to supply power supply signals to the pixel circuits.

[0060] With reference to Fig. 3-6, at least some of subpixels 10 comprise a plurality of first subpixels 010, wherein along the third direction Z perpendicular to the base substrate 001, at least one power supply signal line 300 comprises a first power supply portion 301 overlapping with the main electrode 1040 of at least one of the plurality of first subpixels 010.

[0061] As in Fig. 3, the first subpixel 010 is, for example, a blue subpixel configured to emit blue light. The first subpixel 010 may include various types of first subpixels, and the various first subpixels 010 shown in Fig. 3, for example, include four different arrangement types. In some embodiments of the present disclosure, a variety of arrangement types may also be adopted according to the design requirements of the actual layout, and the embodiments of the present disclosure are not limited thereto.

[0062] For example, with reference to Fig. 3-5, the main electrode 1040 is arranged in the first subpixel 010 on the side of the first power supply section 301 facing away from the base substrate 001; and as for each main electrode 1040, the first power supply section 301 and the main electrode 1040 at least partially overlap with each other.

[0063] Referring to Fig. 3-5, each first power supply section 301 includes a first main section 31 and a second main section 32; in the second direction Y, the maximum size M1 of the main electrode 1040 of the first subpixel 010 is not smaller than the maximum size L1 of its corresponding first power supply section 301, and the maximum size L11 of the first main section 301 is larger than the maximum size L12 of the second main section 32 in the first power supply section 301. For example, the first power supply section 301 corresponding to the main electrode 1040 of the first subpixel 010 refers to the first power supply section 301 overlapping with the main electrode 1040 of the first subpixel 010.

[0064] With reference to Fig. 3-5, a connecting line of two end points A1 and A2 of the main electrode 1040 of the first subpixel 010 that are farthest apart in the second direction Y is an end point connecting line L2; and in the third direction Z, the end point connecting line L2 overlaps with the first main portion 31.

[0065] For example, with reference to Fig. 3-5, the first main portion 31 and the second main portion 32 are two adjacent portions of the first power supply portion 301; and in the second direction Y, the maximum size L11 of the first main portion 301 is larger than the maximum size L12 of the second main portion 32 in the first power supply portion 301, and the orthographic projection area of ​​the first main portion 31 on the base substrate 001 is larger than the orthographic projection area of ​​the second main portion 32 on the base substrate 001. By overlapping the endpoint connection line L2 of the main electrode 1040 with the first main portion 31, the larger part of the main electrode 1040 overlaps with the first main portion 31, thereby ensuring that the main electrode 1040 and the first power supply portion 301 have a large overlap area.For example, the extension direction of the endpoint connection line L2 of each main electrode 1040 is determined according to the arrangement direction of the main electrodes 1040. For example, the endpoint connection line L2 extends in the first direction N; for example, the endpoint connection line L2 extends in the second direction Y, and the embodiments of the present disclosure are not limited thereto.

[0066] For example, the first main section 31 and the second main section 32 are an integral structure.

[0067] For example, in the second direction Y, the maximum size L1 of the first power supply portion 301 is equal to the maximum size L11 of the first main portion 31 in the embodiments of the present disclosure; when the maximum size M1 of the main electrode 1040 of the first subpixel 010 is not smaller than the maximum size L1 of the first power supply portion 301, the orthographic projection of the main electrode 1040 of the first subpixel 010 on the base substrate 001 covers the orthographic projection of the first power supply portion 301 on the base substrate 001 as much as possible. In this way, the flatness of the main electrode 1040 corresponding to the light-emitting region 103 is improved.

[0068] For example, the first power supply section 301 further includes a section except for the first main section 31 and the second main section 32, and the embodiments of the present disclosure are not limited thereto.

[0069] In the embodiments of the present disclosure, by designing the matching manner of the pixel circuit and the light-emitting element, the flatness of the first electrode in the light-emitting element is improved, and the possibility of chromatic aberration and the like in the display product is reduced.

[0070] With reference to Fig. 4 - Fig. 6, for example, the plurality of power supply signal lines 300 include a first power supply signal line 300-1 and a second power supply signal line 300-2, wherein the maximum sizes of the first power supply signal line 300-1 and the second power supply signal line 300-2 in the second direction Y are the first size Lm and the second size Ln, respectively, and the second size Ln is smaller than the first size Lm. The maximum sizes of the plurality of power supply signal lines in the second direction Y provided in the embodiments of the present disclosure are not exactly the same, and they can be designed according to the shape and arrangement of the first electrodes 102 of the first subpixels 010 to improve the flatness of the first electrodes 102 in the first subpixels 010.

[0071] For example, in the plurality of power supply signal lines provided in embodiments of the present disclosure, the shape and arrangement of the first power supply portions 301 can be selected according to the type of the first subpixels 010. For example, the display substrate includes the first power supply portions 301 with different sizes in the second direction. For example, the display substrate includes first power supply portions 301 with different maximum sizes in the second direction to correspond to the first subpixels 010 having the main electrode 1040 with different sizes in the second direction, thus meeting the needs of actual patterning. This also allows the main electrodes 1040 of the first subpixels 010 to have good flatness and reduces the risk of chromatic aberration of the display substrate.

[0072] For example, in the embodiments of the present disclosure, the first power supply sections 301 having different sizes in the second direction Y are not limited to two first power supply sections, and the first power supply sections 301 are provided according to the actual design requirements, which are not limited here.

[0073] With reference to Fig. 3, Fig. 5 and Fig. 6, the plurality of first subpixels 010 in the display substrate include, for example, at least one first-type subpixel 111, and the first power supply portion 301 overlapping with the main electrode 1041 of the first-type subpixel 111 is the first-type power supply portion 3010. For example, the overlapping region of the main electrode 1041 of the first-type subpixel 111 and the first main portion 311 of the first-type power supply portion 3010 is an asymmetric region.

[0074] For example, the first main portion 311 of the first-type power supply portion 3010 is an asymmetric structure. For example, the region overlapping with the main electrode 1041 of the first-type subpixel 111 of the first-type power supply portion 3010 is an asymmetric region. "Asymmetric" in the embodiments of the present disclosure refers, for example, to the structure or region being provided non-symmetrically in a direction parallel to the base substrate.

[0075] For example, with reference to Fig. 3 and Fig. 5, the main electrode 1041 of the first-type subpixel 111 has a large overlapping area with the first-type power supply section 3010, and the overlapping area as a whole is asymmetrical. For example, the orthographic projection area of ​​the overlapping area on the base substrate 001 is 60%~95% of the orthographic projection area of ​​the main electrode 1041 on the base substrate 001. The orthographic projection of the light-emitting area 103 of the first-type subpixel 111 on the base substrate lies within the orthographic projection of the main electrode 1041 on the base substrate. At this time, the overlapping area almost coincides with the light-emitting area 103, that is,The portion of the main electrode 1041 that overlaps with the light-emitting region 103 is arranged uniformly and flatly, which can improve the uniformity of the luminous intensity of the first-type subpixel 111 and reduce the likelihood of chromatic aberration. For example, the orthographic projection area of ​​the overlapping region on the base substrate 001 is 65% to 90%, or 70% to 85%, or 75% to 80% of the orthographic projection area of ​​the main electrode 1041 on the base substrate 001.

[0076] For example, as in Fig. 6, in the display substrate, the first main portion 311 of the first type power supply portion 3010 includes a first protrusion 313, the first protrusion 313 being provided on one side of a first symmetrical center line L3 of the second main portion 312 extending along the first direction N.

[0077] For example, with reference to Fig. 5 and Fig. 6, in the display substrate, the extending direction of the symmetrical center line L4 of the portion of the first type power supply section 3010 except the first protrusion 313 intersects the extending direction of the second symmetrical center line L5 of the main electrode 1041 of the first type subpixel 111.

[0078] For example, the first symmetrical centerline L3 coincides with the symmetrical centerline L4. Of course, the embodiments of the present disclosure are not limited thereto, and the two centerlines may be spaced apart from each other.

[0079] For example, with reference to Fig. 3-6, the second main portion 312 of the first-type power supply portion 3010 is distributed symmetrically relative to the first symmetrical center line L3. In the case where the first protrusion 313 is not provided, the maximum size of the first main portion 311 in the second direction is the same as the second main portion 312, and the first-type power supply portion 3010 is also distributed symmetrically with respect to the first symmetrical center line L3. In order to customize the main electrode 1041 of the first type subpixel 111 as much as possible, the first protrusion 313 is provided only on one side of the first main portion 311 relative to the first symmetrical center line L3, so that the first protrusion 313 increases the overlapping area of ​​the main electrode 1041 and the first type power supply portion 3010, which can better flatten the main electrode 1041, thereby increasing the flatness of the main electrode 1041.

[0080] For example, the main electrode 1041 corresponding to the first type power supply section 3010 may be arranged in a variety of shapes. For example, with respect to the Fig. 3 and Fig. 5, the main electrode 1041 is distributed substantially symmetrically with respect to the second symmetrical center line L5. For example, in the embodiments of the present disclosure, the symmetrical center line L4 and the second symmetrical center line L5 are arranged perpendicularly, so that the overlap area of ​​the first-type power supply portion 3010 and the main electrode 1041 is maximized as much as possible, and the protrusion corner of the main electrode 1041 covers the first protrusion 313 of the first-type power supply portion 3010, thereby improving the flatness of the main electrode 1041.

[0081] For example, the included angle between the extension direction of the symmetrical center line L4 and the extension direction of the second symmetrical center line L5 is 20~90 degrees, such as 30~80 degrees, such as 45~60 degrees, etc.

[0082] For example, with reference to Fig. 3, Fig. 5 and Fig. 6, the plurality of first subpixels 010 in the display substrate further includes at least one second type subpixel 112, and the first power supply portion 301 overlapping with the main electrode 1042 of the second type subpixel 112 is a second type power supply portion 3011.

[0083] For example, see Fig. 3, Fig. 5 and Fig. 6, the second-type power supply portion 3011 includes a third symmetrical center line L6 extending along the first direction N; the main electrode 1042 of the second-type subpixel 112 includes a fourth symmetrical center line L7 extending along the first direction N; the third symmetrical center line L6 of the second-type power supply portion 3011 is provided in the same column of the power supply signal line, and the fourth symmetrical center line L7 of the second-type subpixel 112 overlaps with the second-type power supply portion 3011 and is provided in the same plane perpendicular to the base substrate 001. For example, the orthographic projection of the third symmetrical center line L6 on the base substrate coincides with the orthographic projection of the fourth symmetrical center line L7 on the base substrate.

[0084] For example, with reference to Fig. 3, Fig. 5 and Fig. 6, the second-type subpixel 112 is arranged on the side of the second-type power supply portion 3011 facing away from the base substrate, and the second-type power supply portion 3011 is distributed symmetrically relative to the third symmetric center line. For example, according to the different shapes of the first subpixels 010 in the display substrate, the main electrode 1042 of the second-type subpixel 112 can be considered to be obtained by rotating the main electrode 1041 of the first-type subpixel 111 clockwise or counterclockwise by a certain angle. The rotation angle in the embodiments of the present disclosure is, for example, 90°, so that the fourth symmetric center line L7 of the main electrode 1042 of the second-type subpixel 112 is also rotated clockwise or counterclockwise relative to the main electrode 1041 of the first-type subpixel 111.The main electrode 1042 of the second-type subpixel 112 is arranged on the side of the second-type power supply portion 3011 facing away from the base substrate, therefore, the third symmetrical center line L6 of the second-type power supply portion 3011 and the fourth symmetrical center line L7 of the second-type subpixel 112, which overlap with the second-type power supply portion 3011, are arranged parallel and in the same plane perpendicular to the base substrate 001.For example, when the same column of the power supply signal line 300 corresponds to a plurality of second-type sub-pixels 112, the plurality of third symmetrical center lines L6 of the plurality of second-type power supply portions 3011 and the plurality of fourth symmetrical center lines L7 of the plurality of second-type sub-pixels 112, which overlap with the plurality of second-type power supply portions 3011, are provided in the same column of the power supply signal line 300 in the same plane perpendicular to the base substrate 001.

[0085] For example, with reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, the main electrode 1040 of the first subpixel 010 comprises a first corner 141 and a second corner 142 that are opposite to each other, and a third corner 143 and a fourth corner 144 that are opposite to each other, wherein the orthographic projection of the first corner 141 and / or the second corner 142 on the base substrate 001 and the orthographic projection of the first symmetric center line L3 on the base substrate 001 at least partially overlap each other; the orthographic projection of the fourth corner 144 on the base substrate 001 and the orthographic projection of the first protrusion 313 on the base substrate 001 at least partially overlap each other.

[0086] For example, with reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, the lines forming the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 are extended so that the main electrode 1040 is approximately quadrangular. For the main electrode 1041 of the first type subpixel 111, the first corner 141 and the second corner 142 are opposite each other, and the pointing direction of the vertex of the first corner 141 pointing to the vertex of the second corner 142 intersects with the extending direction of the second symmetrical center line L5. For example, in the embodiments of the present disclosure, the pointing direction of the vertex of the first corner 141 pointing to the vertex of the second corner 142 is perpendicular to the extending direction of the second symmetrical center line L5.

[0087] For example, at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is formed by extending the extension lines on both sides of the corner vertex by 1~5 micrometers; for example, the extension length of the extension lines on both sides of the corner vertex is 1 / 10 of the length of the edge between the adjacent two corners in the main electrode 1040. For example, if the vertex angle of at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is rounded, the corresponding corner is formed by extending the arc lines on both sides of the rounded vertex angle by 1~5 micrometers. For example, the angle range of at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is 70°~150°.For example, the angle range of at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is 80°~120°. For example, the angle range of at least one of the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144 is 90°~100°.

[0088] For example, the main electrode 1041 of the first-type subpixels 111 is arranged on the side of the first-type power supply portion 3010 facing away from the base substrate 001. In this case, the pointing direction of the vertex of the first corner 141 pointing to the vertex of the second corner 142 and the extending direction of the symmetrical center line L4 of the first-type power supply portion 3010 are the same, and the pointing direction of the vertex of the third corner 143 pointing to the vertex of the fourth corner 144 substantially coincides with the extending direction of the second symmetrical center line L5. At this time, as shown in Fig. 5, the orthographic projection of the first protrusion 313 on the base substrate 001 coincides with the orthographic projection of the fourth corner 144 on the base substrate 001, so that the overlap area of ​​the first type of power supply portion 3010 and the main electrode 1041 is maximized and the flatness of the main electrode 1041 is improved.

[0089] With reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, for example, the first main portion 314 of the second type power supply portion 3011 includes a second protrusion 317 and a third protrusion 318, and the second protrusion 317 and the third protrusion 318 are symmetrically distributed relative to the third symmetric center line L6.

[0090] For example, with reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, the main electrode 1042 of the second type subpixels 112 includes the first corner 141 and the second corner 142 opposite to each other, and the third corner 143 and the fourth corner 144 opposite to each other, wherein the orthographic projection of the second protrusion 317 on the base substrate 001 at least partially overlaps with the orthographic projection of one of the first corner 141 and the second corner 142 on the base substrate 001, the orthographic projection of the third protrusion 318 on the base substrate 001 at least partially overlaps with the orthographic projection of the other of the first corner 141 and the second corner 142 on the base substrate 001.

[0091] With reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, for example, the arrangement shape of the second-type subpixels 112 differs from that of the first-type subpixel 111, and the main electrode 1042 of the second-type subpixel 112 is rotated 90° counterclockwise relative to the main electrode 1041 of the first-type subpixel 111. For example, the pointing direction of the vertex of the third corner 143, which points to the vertex of the fourth corner 144, substantially coincides with the third symmetrical center line L6.Therefore, for example, the second-type subpixels 112 include two arrangement forms relative to the second-type power supply portion 3011: the orthographic projection of the second protrusion 317 on the base substrate 001 overlaps with the orthographic projection of the first corner 141 on the base substrate 001, and the orthographic projection of the third protrusion 318 on the base substrate 001 overlaps with the orthographic projection of the second corner 142 on the base substrate 001; or the orthographic projection of the second protrusion 317 on the base substrate 001 overlaps with the orthographic projection of the second corner 142 on the base substrate 001, and the orthographic projection of the third protrusion 318 on the base substrate 001 overlaps with the orthographic projection of the first corner 141 on the base substrate 001.According to the above two arrangement forms, in the adjacent two second-type subpixels 112, the pointing directions of the vertex of the third corner 143 pointing to the vertex of the fourth corner 144 are opposite to each other. In this case, the orthographic projections of the second protrusion 317 and the third protrusion 318 in the second-type power supply portion 3011 on the base substrate 001 coincide with the orthographic projection of the main electrode 1042 on the base substrate 001, thereby improving the flatness of the main electrode 1042. The above "adjacent two second-type subpixels" refers, for example, to a direction parallel to the base substrate. No other second-type subpixels are arranged between these adjacent two second-type subpixels, but subpixels of the other type may be arranged.

[0092] For example, with reference to Fig. 3, Fig. 5 and Fig. 6, the direction of the arrow of the N direction, which in Fig. 5, the second-type subpixel 112 includes a first-type subpixel having the third corner 143 provided at the fourth corner 144, and a second-type subpixel having the third corner 143 provided below the fourth corner 144; at least a part of the third corner 143 of the first-type subpixel overlaps with the first main portion 314 of the second-type power supply portion 3011, and at least a part of the third corner 143 of the second-type subpixel overlaps with the second main portion 315 of the second-type power supply portion 3011.For example, the first electrode 102 of each subpixel further includes the connection electrode electrically connected to the pixel circuit 200 (see descriptions below), the third corner 143 is closer to the connection electrode than the fourth corner 144 in the subpixel of the first type, and the fourth corner 144 is closer to the connection electrode than the third corner 143 in the subpixel of the second type.

[0093] In the embodiments of the present disclosure relating to the Fig. 3-6, along the third direction Z, the light-emitting region 1032 of the second type subpixel 112 overlaps with at least one of the second protrusion 317 and the third protrusion 318. The light-emitting region 1032 defines the light output region of the second type subpixel 112; In the case where the second-type subpixels 112 are arranged according to the above two arrangement forms relative to the second-type power supply portion 3011, the orthographic projections of the second protrusion 317 and the third protrusion 318 on the base substrate 001 fall within or partially overlap with the orthographic projection of the emitting region 1032 of the main electrode 1042 on the base substrate 001. In this case, it is ensured that the flatness of the main electrode 1042 corresponding to the emitting region 1032 is improved, which prevents chromatic aberration.

[0094] For example, with reference to Fig. 3 and Fig. 6, according to the arrangement form of the first subpixels 111, the shape design of the first type power supply section 3010 and the shape design of the second type subpixel 3011 are changed accordingly.

[0095] For example, in the second direction Y, the maximum size L13 of the first main section 314 of the second-type power supply section 3011 is larger than the maximum size L11 of the first main section 311 of the first-type power supply section 3010, and the ratio of the maximum size L12 of the second main section 312 of the first-type power supply section 3010 to the maximum size L13 of the second main section 315 of the second-type power supply section 3011 is 0.9~1.1. For example, the maximum size L12 of the second main section 312 of the first-type power supply section 3010 is equal to the maximum size L13 of the second main section 315 of the second-type power supply section 3011.

[0096] For example, with reference to Fig. 5 and Fig. 6, the main electrode 1042 of the second type subpixel 112 is rotated 90° clockwise or counterclockwise relative to the main electrode 1041 of the first type subpixel 111, the main electrode 1042 of the first subpixel 010 has a symmetrical structure, for example, the main electrode 1042 of the second type subpixel 112 is symmetrically distributed relative to the fourth symmetrical center line L7, and the second type power supply portion 3011 is symmetrically distributed with respect to the second symmetrical center line L6, the third symmetrical center line L6 is parallel to the fourth symmetrical center line L7, and the third symmetrical center line L6 and the fourth symmetrical center line L7 are provided in the same plane perpendicular to the base substrate 001.

[0097] For example, the distance between the vertex of the first corner 141 and the vertex of the second corner 142 is smaller than the distance between the vertex of the third corner 143 and the vertex of the fourth corner 144. The first corner 141 and the second corner 142 are distributed on two sides of the fourth symmetrical center line L7 of the main electrode 1042 and are provided on the side of the second-type power supply portion 3011 facing away from the base substrate 001, wherein the first corner 141 and the second corner 142 correspond to the second protrusion 317 and the third protrusion 318, respectively. On the side of the first-type power supply portion 3010 facing away from the base substrate 001, the fourth corner 144 corresponds to the first protrusion 313 of the first-type power supply portion 3010.Thus, the maximum size L13 of the first main section 314 of the second type power supply section 3011 is larger than the maximum size L11 of the first main section 311 of the first type power supply section 3010.

[0098] For example, in Fig. 5, the main electrode 1041 of the first type subpixel 111 includes two portions provided on two sides of the endpoint connection line L2, and in at least one of these two portions, in the direction parallel to the first direction N and gradually away from the endpoint connection line L2, the maximum size of the main electrode 1041 in the second direction Y gradually decreases.

[0099] For example, the second main portion 312 of the first type power supply portion 3010 corresponds to the portion where the maximum size of the main electrode 1041 gradually decreases, therefore, there is no need to provide other protrusion structures on the second main portion 312 to improve the flatness of the main electrode 1041 corresponding to the portion, and the maximum size of the second main portion 312 in the second direction Y is smaller than the maximum size of the first main portion 311 in the second direction Y.

[0100] Similarly, for the second-type subpixel 112, the maximum size L14 of the second main portion 315 of the second-type power supply portion 3011 in the second direction Y is also smaller than the maximum size L13 of the first main portion 314 in the second direction Y.

[0101] In some embodiments of the present disclosure, the difference between the maximum size of the main electrode 1041 of the first-type subpixel 111 in the second direction Y and the maximum size of the main electrode 1042 of the second-type subpixel 112 in the second direction Y is not particularly large, therefore, the difference between the size reduction trend of the main electrode 1041 in the first direction N and the size reduction trend of the main electrode 1042 in the first direction N is not particularly large. For example, the second main portion 312 of the first-type power supply portion 3010 and the second main portion 315 of the second-type power supply portion 3011 are similar in terms of the maximum size in the second direction Y.For example, the ratio of the maximum size L12 of the second main portion 312 of the first-type power supply portion 3010 and the maximum size L13 of the second main portion 315 of the second-type power supply portion 3011 is 0.9~1.1. For example, the ratio is 1, that is, L12 is equal to L13, which ensures the flatness of the main electrode 1041 and / or the main electrode 1042, facilitates product manufacturing, and reduces manufacturing costs.

[0102] For example, the maximum size L13 of the first main section 314 of the second-type power supply section 3011 in the second direction Y is 1.1-2 times the maximum size L14 of the second main section 315 of the second-type power supply section 3011 in the second direction Y. For example, in the second-type power supply section 3011, the maximum size L13 of the first main section 314 is 1.2-1.9 times the maximum size L14 of the second main section. For example, in the second-type power supply section 3011, the maximum size L13 of the first main section 314 is 1.3-1.8 times the maximum size L14 of the second main section. For example, in the second type power supply section 3011, the maximum size L13 of the first main section 314 is 1.4~1.7 times the maximum size L14 of the second main section.For example, in the second type power supply section 3011, the maximum size L13 of the first main section 314 is 1.5~1.6 times the maximum size L14 of the second main section.

[0103] For example, in the first type power supply section, the maximum size of the first main section in the second direction is 1.1~1.8 times the maximum size of the second main section in the second direction, such as 1.2~1.7 times, or 1.3~1.6 times, or 1.4~1.5 times, etc.

[0104] For example, the maximum size L13 of the first main portion 314 of the second-type power supply portion 3011 is designed to be as large as possible in the second direction Y. For example, in some embodiments of the present disclosure, the maximum size L13 of the first main portion 314 in the second direction Y is 1.5 times the maximum size L14 of the second main portion 315 in the second direction Y. This ensures that the first corner 141 and the second corner 142 of the main electrode 1042 of the second-type sub-pixel 112 just cover the first protrusion 317 and the second protrusion 318 of the first main portion 314 to ensure the flatness of the main electrode 1042 of the second-type sub-pixel 112, and at the same time, the relationship between the maximum size L13 and the maximum size L14 is made as uniform as possible to simplify layout design and manufacturing.

[0105] For example, with reference to Fig. 5 and Fig. 6, each power supply signal line 300 in the adjacent plurality of power supply signal lines 300 in the display substrate includes a plurality of power supply portions 300-3 arranged in the first direction N, and a first connection portion 330 is provided between and electrically connected to two adjacent power supply portions 300-3, and the plurality of power supply portions 300-3 includes the first power supply portion 301 as described above, and the ratio of the maximum size of each power supply portion in the second direction Y to the maximum size L30 of the first connection portion 330 in the second direction Y is 1.5-5.

[0106] For example, the ratio of the maximum size of each power supply section 300-3 in the second direction Y to the maximum size L30 of the first connection section 330 in the second direction Y is 2 to 4.5, for example, 2.5 to 4 or 3 to 3.5, etc.

[0107] For example, with reference to Fig. 3-6, the display substrate includes a plurality of power supply signal lines 300 extending in the first direction N, and at least one power supply section 300-3 is provided in each power supply signal line 300. The power supply section 300-3 is one of the first power supply section 301 and the second power supply section 302. The first power supply section 301 corresponds to the first subpixel 110, and the second power supply section 302 corresponds to the second subpixel. The first power supply section 301 further includes the first-type power supply section 3010 corresponding to the first-type subpixel 111 and the second-type power supply section 3011 corresponding to the second-type subpixel 112.For each power supply section 300-3, the orthographic projection of the power supply section 300-3 on the base substrate 001 at least partially overlaps with the orthographic projection of its corresponding main electrode on the base substrate 001. For example, the orthographic projection of each power supply section 300-3 on the base substrate 001 and the orthographic projection of its corresponding main electrode on the base substrate 001 overlap with as large an overlap area as possible, for example, the overlap area is at least 90% of the area of ​​the orthographic projection of the main electrode corresponding to the power supply section 300-3 on the base substrate 001, so that the main electrode corresponding to the power supply section 300-3 has a higher flatness.

[0108] Referring to the Fig. 5 and Fig. 6, the two adjacent power supply sections 300-3 are electrically connected by the first connection section 330, that is, all power supply sections 300-3 of the same power supply signal line 300 are electrically connected to each other. The ratio of the maximum size of the power supply section 300-3 in the second direction Y to the maximum size L30 of the first connection section 330 in the second direction Y is, for example, 1.5-5, such as 4 or 2 or 3, etc. With respect to each power supply section 300-3, the maximum size L30 of the first connection section 330 in the second direction Y is designed smaller under the premise of realizing the electrical connection function, which allows more empty space to be left, the layout is not crowded, and facilitates layout arrangement.

[0109] For example, see Fig. 5 and Fig. 6, the first type power supply section 3010 comprises a first subtype power supply section 3016 and a second subtype power supply section 3017, the second main section 312 of the first type power supply section 3010 comprises a first side K1 and a second side K2 opposite each other in the second direction Y, the first protrusion 3131 of the first subtype power supply section 3016 is arranged on the first side K1 of the second main section 312, the first protrusion 3132 of the second subtype power supply section 3017 is arranged on the second side K2 of the second main section 312.

[0110] For example, as in Fig. 6, the arrow of the Y direction points to the right, the first protrusion 3131 of the power supply section 3016 of the first subtype is provided on the left side of the second main section 312, the first protrusion 3132 of the power supply section 3017 of the second subtype is provided on the right side of the second main section 312.

[0111] For example, the first sub-type power supply section 3016 and the second sub-type power supply section 3017, which are adjacent to each other in the Y direction, are distributed symmetrically with respect to a straight line extending in the N direction. The "first sub-type power supply section 3016 and the second sub-type power supply section 3017 adjacent to each other" may refer to no other first sub-type power supply section 3016 and second sub-type power supply section 3017 being disposed between these two power supply sections, but other types of power supply sections may be provided.

[0112] For example, the plurality of power supply sections of each power supply signal line 300 may be different, for example, the maximum sizes of different power supply sections in the second direction Y may be different, so that it can be flexibly adapted to the arrangement of different main electrodes and meets the flatness requirements of different main electrodes.

[0113] For example, with reference to Fig. 5 and Fig. 6, the subpixel 111 of the first type comprises two arrangement forms. For example, as in Fig. 5 and Fig. 6, the first type subpixel 111 includes a third type subpixel in which the third corner 143 is provided on the left side of the fourth corner 144, and a fourth type subpixel in which the third corner 143 is provided on the right side of the fourth corner 144, wherein the fourth corner 144 of the fourth type subpixel overlaps with the first protrusion 313 of the first subtype power supply portion 3016, and the fourth corner 144 of the fourth type subpixel overlaps with the first protrusion 313 of the second subtype power supply portion 3017.

[0114] As in Fig. For example, as shown in FIG. 5, the main electrode 1041 of the first-type subpixel 111 is arranged symmetrically to the plane P1. The first protrusion 3131 of the first-type power supply portion 3016 and the first protrusion 3132 of the second-type power supply portion 3017 are arranged on opposite sides. In this way, among the two arrangements mentioned above, the orthographic projection of the fourth corner 144 of the main electrode 1041 of the first-type subpixel 111 on the base substrate 001 covers the orthographic projection of the first protrusion 3131 or the second protrusion 3132 on the base substrate 001 to ensure the flatness of the main electrode 1041 at the fourth corner 144.

[0115] For example, with reference to Fig. 5 and Fig. 6, the main electrode 1040 of the first subpixel 010 includes the first corner 141, the second corner 142, the third corner 143, and the fourth corner 144, wherein the edges or their extension lines of the main electrode 1040 are connected to form a polygon H0, each of the plurality of vertex angles of the polygon H0 has a range that does not overlap with the corresponding corner of the main electrode, and the non-overlapping range A12 of the third corner 143 and the corresponding vertex angle of the polygon H0 is larger than the non-overlapping range of each of at least some of the other corners and the corresponding vertex angle of the polygon.

[0116] In Fig. 5 and Fig. 6, for example, the four extension lines H1, H2, H3, and H4 of the main electrode 1040 form the polygon H0. Corresponding to the first corner 141, the vertex angle of the polygon H0 includes a non-overlapping area A10; corresponding to the second corner 142, the vertex angle of the polygon H0 includes a non-overlapping area A11; corresponding to the third corner 143, the vertex angle of the polygon H0 includes a non-overlapping area A12; corresponding to the fourth corner 144, the vertex angle of the polygon H0 includes a non-overlapping area A13.

[0117] For example, the four corners of the main electrode 1040 have chamfers of different sizes. For example, in the embodiments of the present disclosure, the chamfer at the third corner 143 is larger than the chamfer at the other corners, so that the non-overlapping area A12 of the third corner 143 and the corresponding vertex angle of the polygon H0 are larger than the non-overlapping area of ​​the other corner and the corresponding vertex angle of the polygon H0. Of course, in some embodiments, the size of the chamfer of each corner of the main electrode 1040 can be designed according to the size requirements of each light-emitting region. The shape of each main electrode provided in the embodiments of the present disclosure is only exemplary and is not intended to limit the scope of the present disclosure. This ensures flexibility in the shape design of the main electrode.

[0118] For example, the above chamfer refers to the vertex angle formed by a curve, and the curve is a circular arc or an irregular curve, such as a curve formed by an ellipse, a wavy line, etc. The embodiments of the present disclosure show that the curve protrudes outward relative to the center of the subpixel, but it is not limited to this, but may also have a concave shape relative to the center of the subpixel. For example, the curve is a circular arc, the range of the central angle of the circular arc is 10°~150°. The central angle of the circular arc is, for example, between 60° and 120°. For example, the central angle of the circular arc is 90°. The curve length of the rounded chamfer of the third corner 143 is, for example, 10~60 micrometers. For example, the radius of curvature of the chamfer at the third corner 143 is larger than the radius of curvature of the chamfer at the other corners.

[0119] For example, as in Fig. 5 and Fig. 6, the second main portion 32 of the first-type power supply portion 3010 and the second-type power supply portion 3011 includes two straight edges extending in the first direction N. For example, the edge opposite the first protrusion 313 of the first main portion 311 in the first-type power supply portion 3010 is a straight edge extending in the first direction N, and the straight edge lies on the same line as a straight edge of the second main portion 312.

[0120] For example, as in Fig. 5 and Fig. As shown in Figure 6, the first protrusion 313 includes an inclined edge connected to the straight edge of the second main part 312, wherein the included angle between the inclined edge and the first direction N is 10~90 degrees, such as 20~80 degrees, such as 30~70 degrees, such as 40~60 degrees, such as 45 degrees. For example, the included angle between the inclined edge and the connecting line between the fourth corner 144 and the first corner 141 is 0~30 degrees, such as 2~25 degrees, such as 5~20 degrees, such as 7~15 degrees, such as 8~10 degrees. For example, the edge of the first projection 313 facing away from the second main portion 312 is parallel to the second direction Y, the connecting line connecting the end of such an edge facing away from the center line of the second main portion 312 extending along the first direction N and the end of the inclined edge facing away from the center line may comprise a polyline or curve.

[0121] For example, as in Fig. 5 and Fig. 6, one of the second protrusion 317 and the third protrusion 318 has the same shape and size as the first protrusion 313, the second protrusion 317 and the third protrusion 318 are distributed symmetrically with respect to the third symmetrical center line L6 of the second type power supply section 3011 extending along the first direction N.

[0122] For example, as in Fig. 5 and Fig. 6, the shape and size of the second main portion 32 of the first type power supply portion 3010 are the same as those of the second main portion 32 of the second type power supply portion 3011, the first main portion 311 of the first type power supply portion 3010 except for the first protrusion 313, and the first main portion 314 of the second type power supply portion 3011 except for the second protrusion 317 and the third protrusion 318 have the same shape and size.

[0123] For example, as in Fig. 5 and Fig. 6, the first subpixel is a subpixel that emits light of a single color, such as a subpixel that emits blue light; the overlapping regions of the power supply signal line and the first electrodes of different subpixels that emit light of the same color may have different shapes, and the overlapping regions may have different areas.

[0124] For example, the first subpixels 111 having the above four corners are evenly distributed in the display area of ​​the display substrate, but the embodiments of the disclosure are not limited thereto; for example, the display substrate includes a first display area and a second display area, and the first subpixels 111 having the above four corners are distributed only in the first display area. For example, the first display area is an under-screen camera arrangement area, and the second display area is a normal display area; by providing the first subpixels having the four corners in the under-screen camera arrangement area, the light transmittance of the second display area is improved.

[0125] With reference to Fig. 3 - Fig. 6, for example, at least some subpixels further comprise a plurality of second subpixels 020; along the third direction Z, at least one power supply signal line 300 includes a second power supply portion 302 overlapping with the main electrode 1050 of at least one of the plurality of second subpixels 020. The second power supply portion 302 includes a fifth symmetrical center line L32 extending in the first direction N; the main electrode 1050 of the second subpixel 020 includes a sixth symmetrical center line L33 extending along the first direction N; the fifth symmetrical center line L32 of the second power supply portion 302 in the same column of the power supply signal line 300 and the sixth symmetrical center line L33 of the second subpixel overlapping with the second power supply portion 302 are provided in the same plane perpendicular to the base substrate 001.

[0126] For example, with reference to Fig. 3- Fig. 6, the area of ​​the orthographic projection of the main electrode 1050 of the second subpixel 020 on the base substrate 001 is smaller than the area of ​​the orthographic projection of the main electrode 1040 of the first subpixel 010 on the base substrate 001, and the maximum size of the main electrode 1050 of the second subpixel 020 in the first direction N is smaller than the maximum size of the main electrode 1040 of the first subpixel 010 in the first direction N; the maximum size of the main electrode 1050 of the second subpixel 020 in the second direction Y is smaller than the maximum size of the main electrode 1040 of the first subpixel 010 in the second direction Y. The main electrode 1050 of the second subpixel 020 is symmetrically distributed with respect to the sixth symmetrical center line L33 extending in the first direction N, the second power supply section 302 is symmetrical with respect to the fifth symmetrical center line L32 extending along the first direction N,symmetrically distributed, and the main electrode 1050 is arranged on the side of the second power supply section 302 facing away from the base substrate 001. For the same second subpixel 020, the fifth symmetrical center line L32 of the second power supply section 302 and the sixth symmetrical center line L33 of the second subpixel overlapping with the second power supply section 302 are provided in the same plane perpendicular to the base substrate 001. The fifth symmetrical center line L32 is parallel to the sixth symmetrical center line L33, and both are arranged in the same plane perpendicular to the base substrate 001. When the same column of the power supply signal line 300 corresponds to a plurality of second subpixels 020, the fifth symmetrical center line L32 and the sixth symmetrical center line L33 are provided in the same column of the power supply signal line 300 in the same plane perpendicular to the base substrate 001.

[0127] In this way, the orthographic projection of the main electrode 1050 on the base substrate 001 covers the orthographic projection of the second power supply portion 302 on the base substrate 001 as much as possible, so that the main electrode 1050 is flat.

[0128] For example, with reference to Fig. 3-6, for example, the orthographic projection of the main electrode 1050 of the second subpixel 020 on the base substrate 001 and the orthographic projection of the second power supply portion 302 on the base substrate 001 overlap, and the overlap area AS1 is at least 90% of the area of ​​the orthographic projection AS of the main electrode 1050 of the second subpixel 020 on the base substrate 001. For example, the overlap area AS1 is at least 92%, 95%, or 98% of the area of ​​the orthographic projection AS of the main electrode 1050 of the second subpixel 020 on the base substrate 001.

[0129] For example, with reference to Fig. 3-6, compared with the orthographic projection of the second power supply section 302 on the base substrate 001, the orthographic projection of the main electrode 1050 on the base substrate 001 is smaller; and when the overlap area AS1 is more than 90% of the area of ​​the orthographic projection AS of the main electrode 1050 of the second subpixel 020 on the base substrate 001, the main electrode 1050 in the light-emitting regions 1033 of the second subpixel 020 as a whole is almost flat, thereby effectively preventing the generation of chromatic aberration.

[0130] For example, as in Fig. 3-6, the second power supply section 302 and the first power supply section 301 have different shapes. For example, the area of ​​the second power supply section 302 is smaller than the area of ​​the first power supply section 301. For example, the ratio between the maximum size of the second power supply section 302 in the second direction Y and the maximum size of the second main portion 32 of the first power supply section 301 in the second direction Y is 0.9~1.1. For example, the first-type power supply section 3010 has the same shape as the second power supply section 302 except for the first protrusion 313 and has the same area as the second power supply section 302.For example, the second type power supply portion 3011 has the same shape as the second power supply portion 302 except for the second protrusion 317 and the third protrusion 318 and has the same area as the second power supply portion 302.

[0131] For example, as in Fig. 5 and Fig. 6, the plurality of power supply sections 300-3 arranged along the first direction N and enclosed by the power supply signal line 300 includes the first power supply sections 301 and the second power supply sections 302 arranged alternately, wherein the same power supply signal line 300 includes at least two different shapes of the power supply sections 300-3.

[0132] For example, as in Fig. 5 and Fig. As shown in Figure 6, the respective second power supply portions 302 have the same shape and area. For example, the different parts of the power supply signal line 300 that overlap with the first electrodes 102 of different second subpixels 020 have the same shape and area.

[0133] Of course, the embodiments of the present disclosure are not limited thereto. When the shape of the second subpixel 020 is formed to have four corners similar to those of the first subpixel 010, the shapes of the second power supply portions 302 overlapping with different second subpixels 020 may be different. In this case, the shape of the second power supply portions 302 may be determined according to the shape of the first electrode 102 of each second subpixel 020.

[0134] For example, with reference to Fig. 5 and Fig. 6, the display substrate further comprises a plurality of data lines 400, wherein the plurality of data lines 400 extend along the first direction N and are arranged in the second direction Y, wherein the plurality of data lines 400 and the plurality of power supply signal lines 300 are provided in the same layer, the data lines 400 between two adjacent power supply signal lines 300 comprise a first data line 401 and a second data line 402 arranged in the second direction Y, the first data line 401 and the second data line 402 are symmetrically distributed relative to the seventh symmetrical center line L40 between the first data line 401 and the second data line 402.

[0135] For example, in Fig. 6, the maximum size V of the first data line 401 and the second data line 402 between the two adjacent power supply signal lines 300 in the second direction Y is smaller than the maximum size L13 of the power supply signal line 300 in the second direction Y. Each data line further includes a connection block 450 for connecting the data line to a transistor in the pixel circuit 200. For the same power supply signal line 300, the connection block and the power supply portion are arranged side by side and spaced from each other, and the minimum distance between the connection block and the power supply portion is about 1 / 3-2 / 3 of the size of the first connection portion 330 in the second direction Y, which makes it easier to leave a blank space and thus prevents signal interference between the signal lines.The above maximum size V includes, for example, a line width of the first data line 401, a line width of the second data line 402, and the distance between the first data line 401 and the second data line 402.

[0136] As in Fig. For example, as shown in Figure 6, the distances between the first main portion 311 of the first-type power supply portion 3010 and the data lines (except for the connection block) provided on and adjacent to the first main portion 311 of the first-type power supply portion 3010, respectively, are not equal. For example, the distances between the second main portion 312 of the first-type power supply portion 3010 and the data lines (except for the connection block) provided on and adjacent to the second main portion 312 of the first-type power supply portion 3010, respectively, are equal.For example, the distances between the first main section 314 of the second-type power supply section 3011 and the data lines (except for the connection block) provided on and adjacent to the first main section 314 of the second-type power supply section 3011 are equal. For example, the distances between the second main section 315 of the second-type power supply section 3011 and the data lines (except for the connection block) provided on and adjacent to the second main section 315 of the second-type power supply section 3011 are equal. For example, the distances between the second power supply section 302 and the data lines (except for the connection block) provided on and adjacent to the second main section 315 of the second-type power supply section 3011 are equal.

[0137] For example, with reference to Fig. 5 and Fig. 6, at least some subpixels 10 further comprise a plurality of third subpixels 030, the main electrode 1060 of the light-emitting element 100 of at least one of the plurality of third subpixels 030 at least partially overlaps with the data line 400, and the overlapping region AS2 of the main electrode 1060 of the third subpixel 030 and the data line 400 are substantially symmetrical relative to the seventh symmetrical center line L40.

[0138] For example, with reference to Fig. 5 and Fig. 6, the area of ​​the orthographic projection of the main electrode 1060 of the third subpixel 030 on the base substrate 001 is smaller than the area of ​​the orthographic projection of the main electrode 1050 of the second subpixel 020 on the base substrate 001, and the maximum size of the main electrode 1060 of the third subpixel 030 in the first direction N is smaller than the maximum size of the main electrode 1050 of the second subpixel 020 in the first direction N, and the maximum size of the main electrode 1060 of the third subpixel 030 in the second direction Y is smaller than the maximum size of the main electrode 1050 of the second subpixel 020 in the second direction Y. For example, the third subpixels 030 may have two different arrangement forms, and the third subpixels 030 with two different arrangement forms are arranged symmetrically relative to the fourth symmetric center line L7. As shown in Fig. As shown in Figure 5, the overlapping region AS2 of the main electrode 1060 of the third subpixel 030 and the data line 400 includes two parts, and the overlapping region AS2 is substantially symmetrical with respect to the seventh symmetrical center line L40. Thus, by symmetrically distributing the overlapping region AS2 with respect to the seventh symmetrical center line L40, the flatness of the main electrode 1060 of the third subpixel 030 is increased to reduce the chromatic aberration of the third subpixel 030.

[0139] As in Fig. 5, for example, the main electrode 1060 of the third subpixel 030 overlaps with a part of the data line 400 except for the connection block 450.

[0140] For example, with reference to Fig. 5 and Fig. 6, the display substrate further comprises a plurality of second connection portions 500, wherein the plurality of second connection portions 500 and at least some of the plurality of power supply signal lines 300 are arranged in a same layer, each second connection portion 500 comprising a first connector 501 and a second connector 502. The plurality of second connection portions 500 are arranged in an array along a first direction N and a second direction Y to form a plurality of second connection portion rows 503 and a plurality of second connection portion columns 504.

[0141] The power supply signal line 300 includes the plurality of power supply sections arranged in the first direction N, such as the first power supply section 301 and the second power supply section 302; the first connection section 330 is provided between the adjacent two power supply sections and is electrically connected to both of the adjacent two power supply sections; and the plurality of power supply signal lines 300 includes the power supply sections arranged in an array along the first direction N and the second direction Y to form a plurality of power supply section rows 308 and a plurality of power supply section columns 309.

[0142] A plurality of second connection section rows 503 and a plurality of power supply section rows 308 are alternately arranged in the first direction N, and two adjacent second connection sections 500 in the same second connection section row 503 are distributed on two sides of the data line 400.

[0143] For example, as in Fig. 6, the plurality of second connecting portions 500 includes a plurality of first connectors 501 and a plurality of second connectors 502, the plurality of first connectors 501 are arranged in a plurality of first connector columns arranged in the second direction Y, the plurality of second connectors 502 are arranged in a plurality of second connector columns arranged in the second direction Y, the plurality of first connector columns and the plurality of second connector columns are alternately arranged in the second direction Y.

[0144] For example, the first connector 501 and the second connector 502 have the same shape or different shapes.

[0145] For example, in the same second connection section row 503, two adjacent second connection sections 500 are distributed symmetrically with respect to the seventh symmetric center line L40; in the second direction, the minimum distance between the first connector 501 or the second connector 502 and the data line 400 is substantially the same as the minimum distance between the first connector 501 or the second connector 502 and the first connection section 330, whereby the spatial distribution of the layout is uniform and not crowded.

[0146] For example, in some embodiments of the present disclosure, the plurality of power supply signal lines are arranged in different layers and electrically connected in parallel, and accordingly, the plurality of second connection portions 500 are arranged in different layers, although the embodiments of the present disclosure are not limited thereto. For example, the two adjacent second connection portions 500 in the same second connection portion row 503 are not distributed symmetrically and are designed according to the actual layout requirements.

[0147] For example, with reference to Fig. 5 and Fig. 6, the first electrode 102 of the light-emitting element 100 further includes a connection electrode 105 electrically connected to the main electrode 104, wherein the connection electrode 105 does not overlap with the light-emitting region 103 of the light-emitting element 100, and the connection electrode 105 is electrically connected to the light-emitting control transistor T6 through the second connection portion 500.

[0148] For example, with reference to Fig. 5 and Fig. 6, the connection electrode 105, which is electrically connected to the main electrode 104 in each pixel circuit, is arranged on one side of the main electrode 104; for example, the arrow points to the direction Y in Fig. 7 to the right, the connecting electrodes 105 are arranged on the left sides of the center line of the main electrodes 104, each extending along the first direction N. The area of ​​the orthographic projection of the connecting electrode 105 on the base substrate 001 is smaller than the area of ​​the orthographic projection of the main electrode 104 on the base substrate 001.For example, the orthographic projection of the connection electrode 105 on the base substrate 001 and the orthographic projection of the data line 400 on the base substrate 001 do not overlap, and the orthographic projection of the connection electrode 105 on the base substrate 001 and the orthographic projection of the light-emitting region 103 on the base substrate 001 do not overlap, thereby avoiding the interference of the connection electrode 105 on the signals in the data line and the light-emitting region 103 to ensure the performance of the pixel circuit 200.

[0149] For example, with reference to Fig. 5 and Fig. 6, the connection electrode 105 of the light-emitting element 100 does not overlap with the first connection portion 330; and in the first direction N, the maximum size L975 of the main electrode 1040 of the first subpixel 010 is not smaller than the maximum size L985 of the first main portion 31 of the corresponding first power supply portion 301.

[0150] For example, the orthographic projection of the connection electrode 105 of the light-emitting element 100 on the base substrate 001 and the orthographic projection of the first connection portion 330 on the base substrate 001 have almost no overlap area. For example, the overlap area is no larger than 1 / 15 of the area of ​​the orthographic projection of the connection electrode 105 on the base substrate 001, which can reduce the crosstalk phenomenon that may occur between the signal lines.

[0151] For example, with reference to Fig. 5 and Fig. 6, the maximum size L975 of the main electrode 1040 of the first subpixel 010 is larger than the maximum size L985 of the first main portion 31. In some embodiments, the maximum size L985 of the first main portion 31 is 1 / 4-1 / 2 of the maximum size L975 of the main electrode 1040 of the first subpixel 010. For example, the maximum size L985 of the first main portion 31 is 1 / 3-2 / 3 of the maximum size L975 of the main electrode 1040 of the first subpixel 010. For example, the maximum size L975 of the main electrode 1040 of the first subpixel 010 is not smaller than the maximum size L985 of the first main portion 31 of the corresponding first power supply portion 301, which contributes to improving the flatness of the main electrode 1040.

[0152] For example, in the second direction Y, the first connecting portion 330 is arranged between the first connector 501 and the second connector 502 of the same second connecting portion 500, and the first connector 501 and the second connector 502 of the same second connecting portion 500 are spaced from the first connecting portion 330 between the first connector 501 and the second connector 502.

[0153] For example, with reference to Fig. 5 and Fig. 6, the plurality of second connection section rows 503 and the plurality of power supply section rows 308 are arranged alternately in the first direction N, that is, a second connection section row 503 is provided between the adjacent two power supply section rows; in the same second connection section row 503, a first connection section 330 is provided between the first connector 501 and the second connector 502 of each second connection section 500, and the first connection section 330 is spaced apart from the next first connector 501 and the next second connector 502.The connection electrode 105 of the light-emitting element 100 is electrically connected to the first connector 501 and the second connector 502, and the first connector 501 and the second connector 502 of the second connection portion 500 are spaced apart from the adjacent first connection portion 330, thereby reducing signal interference between the connection electrode 105 connected to the second connection portion 500 and the first connection portion 330.

[0154] For example, the orthographic projection of the main electrode 104 of the light-emitting element 100 on the base substrate and the orthographic projection of the second connecting portion 500 on the base substrate are spaced apart from each other as far as possible, thereby preventing the flatness of the main electrode 104 from being affected by the second connecting portion 500. For example, the first connector 501 and the second connector 502 of the same second connecting portion 500 are arranged symmetrically relative to the first connecting portion 330 between the first connector 501 and the second connector 502 of the same second connecting portion 500, which can further facilitate layout arrangement.

[0155] For example, with reference to Fig. 5 and Fig. 6, the maximum size L51 of the first connector 501 or the second connector 502 in the first direction N is smaller than the maximum size L52 of the first connecting portion 330 in the first direction N.

[0156] For example, with reference to Fig. 5 and Fig. 6, the first connecting portion 330 is provided between the first connector 501 and the second connector 502 of the same second connecting portion 500, the maximum size L52 of the first connecting portion 330 is relatively large in the first direction N, namely, it is larger than the maximum size L51 of the adjacent first connector 501 or the adjacent second connector 502 in the first direction N; in this case, it is advantageous to provide a certain distance between the two power supply portions connected at both ends of the first connecting portion 330 in the first direction N and the first connector 501 and the second connector 502, and then the main electrodes 104 arranged on the two power supply portions also have a certain distance from the first connector 501 and the second connector 502, thereby preventing signal interference.

[0157] For example, with reference to Fig. 5 and Fig. 6, the first connector 501 is electrically connected to the connection electrode 1051 of the first subpixel 010 or the connection electrode 1051 of the second subpixel 020, and the second connector 502 is electrically connected to the connection electrode 1061 of the third subpixel 030.

[0158] For example, with reference to Fig. 5 and Fig. 6, for example, in the first direction, the connecting electrode 1051 of the first subpixel 010, the connecting electrode 1051 of the second subpixel 020, and the connecting electrode 1051 of the third subpixel 030, which are adjacent to each other, are arranged sequentially and spaced from each other, and the connecting electrode 1051 of the first subpixel 010 and the connecting electrode 1051 of the second subpixel 020 are arranged on the side of the second connecting portion 500 near the first connector 501; the connecting electrode 1061 of the third subpixel 030 is arranged on the side of the second connecting portion 500 near the second connector 502, in this case, they are also spaced from each other in the second direction. In this way, it is conducive to the utilization and design of the layout space.

[0159] Of course, in some embodiments, the number and position of the connectors in the second connecting portion 500 may also vary according to the actual structuring, and the embodiments of the present disclosure are not limited thereto.

[0160] For example, as in Fig. As shown in Figure 7, the plurality of subpixels 10 includes a plurality of first subpixels 010, a plurality of second subpixels 020, and a plurality of third subpixels 030. For example, one of the first subpixel 010 and the second subpixel 020 is a blue subpixel that emits blue light, the other of the first subpixel 010 and the second subpixel 020 is a red subpixel that emits red light, and the third subpixel 030 is a green subpixel that emits green light. For example, the first subpixel 010 is the blue subpixel, the second subpixel 020 is the red subpixel, and the area of ​​the light-emitting region of the blue subpixel is larger than the area of ​​the light-emitting region of the red subpixel. For example, the area of ​​the light-emitting region of the blue subpixel is larger than the area of ​​the light-emitting region of the green subpixel.Of course, the embodiments of the present disclosure are not limited thereto; the names of the first subpixel, the second subpixel, and the third subpixel may be interchangeable, for example, the first subpixel is the green subpixel, the second subpixel is the blue subpixel, and the third subpixel is the red subpixel; alternatively, the first subpixel is the blue subpixel, the second subpixel is the red subpixel, the third subpixel is the green subpixel, or the like.

[0161] As in Fig. 7, for example, the plurality of first sub-pixels 010 and the plurality of second sub-pixels 020 are alternately arranged along the first direction N and the second direction Y to form a plurality of first pixel rows 061 and a plurality of first pixel columns 062, and the plurality of third sub-pixels 030 are arranged along the first direction N and the second direction Y to form a plurality of second pixel rows 071 and a plurality of second pixel columns 072.

[0162] The plurality of first pixel rows 061 and the plurality of second pixel rows 071 are arranged alternately along the first direction N and offset from each other in the second direction Y; and the plurality of first pixel columns 062 and the plurality of second pixel columns 072 are arranged alternately along the second direction Y and offset from each other in the first direction N.

[0163] The first direction and the second direction intersect. For example, the first direction is perpendicular to the second direction. For example, the first direction and the second direction are interchangeable.

[0164] For example, the centers of the light-emitting regions of the adjacent first subpixel 010 and the second subpixel 020 in the first pixel row 061 and the centers of the light-emitting regions of the first subpixel 010 and the second subpixel 020 adjacent to the adjacent first subpixel 010 and the second subpixel 020 in the column direction are four vertices of a virtual quadrilateral, and the center of the light-emitting region of the third subpixel 030 is provided within the virtual quadrilateral.

[0165] For example, as in Fig. 7, the second pixel row 071 includes a plurality of third sub-pixel pairs 035 arranged along the second direction Y, two third sub-pixels 030 in each third sub-pixel pair 035 are the first pixel block 0301 and the second pixel block 0302, respectively, and the first pixel blocks 0301 and the second pixel blocks 0302 are alternately arranged along the second direction Y. For example, the first pixel blocks 0301 and the second pixel blocks 0302 in the second pixel column 072 are alternately arranged in the first direction N.

[0166] For example, at least two second pixel rows 071 include a plurality of third subpixel pairs 035 arranged in the first direction, at least two third subpixels 030 in each third subpixel pair 035 are the first pixel block 0301 and the second pixel block 0302, respectively, and the first pixel blocks 0301 and the second pixel blocks 0302 are alternately arranged along the second direction Y. For example, the first pixel blocks 0301 and the second pixel blocks 0302 in at least two second pixel columns 072 are alternately arranged in the first direction N.

[0167] As in Fig. 7, the plurality of subpixels 10 comprises, for example, a plurality of smallest repeating units 700, wherein each smallest repeating unit 700 comprises a first subpixel 010, a first pixel block 0301, a second pixel block 0302, and a second subpixel 020. For example, at least two smallest repeating units 700 comprise a first subpixel 010, a first pixel block 0301, a second pixel block 0302, and a second subpixel 020. Each smallest repeating unit 700 comprises, for example, a first subpixel 010, a first pixel block 0301, a second pixel block 0302, and a second subpixel 020. For example, each smallest repeating unit 700 comprises subpixels 10 consisting of two rows and four columns.

[0168] As in Fig. 7, for example, in a smallest repetition unit 700, the first pixel block 0301 and the first subpixel 010 form a first pixel unit 701, the second pixel block 0302 and the second subpixel 020 form a second pixel unit 702.

[0169] For example, in at least two smallest repetition units 700, the first pixel block 0301 and the first subpixel 010 form the first pixel unit 701, the second pixel block 0302 and the second subpixel 020 form the second pixel unit 702.

[0170] The above first pixel unit and the above second pixel unit are not pixels in the strict sense, that is, the above first pixel unit and the above second pixel unit are not a pixel defined by the first subpixel 010, the second subpixel 020, and the third subpixel 030. The smallest repeating unit 700 here means that the structure of the pixel arrangement may include a plurality of smallest repeating units 700 that are repeatedly arranged.

[0171] For example, the first subpixel 010 and the second subpixel 020 are shared subpixels, and through the virtual algorithm, four subpixels can be displayed in two virtual pixel units.

[0172] It should be noted that the pixel array structure provided in the embodiments of the present disclosure is only exemplary and is not intended to limit the scope of the disclosure. In some embodiments of the present disclosure, the pixel array structure can be flexibly changed according to actual layout design requirements.

[0173] With reference to the Fig. 3 and Fig. 5, the connection electrodes 1051 of the plurality of first subpixels 010 and the connection electrodes 1051 of the plurality of second subpixels 020 are electrically connected to the corresponding second connection ports 500 through a plurality of first connection holes D0, respectively, and the plurality of first connection holes D0 are provided in a plurality of first connection lines X1.

[0174] The connection electrodes 1061 of the plurality of third subpixels 030 are electrically connected to the corresponding second connection portions 500 through a plurality of second connection holes D1, and the plurality of second connection holes D1 are provided in a plurality of second connection lines X2, wherein the first connection line X1 and the second connection line X2 extend along the second direction Y and are spaced from each other.

[0175] For example, in Fig. 3, the connection electrode 1051 of each of the plurality of first subpixels 010 and the connection electrode 1051 of each of the plurality of second subpixels 020 are distributed on one side of the end of the first connector, and the first connection line X1 extends along the second direction Y. The connection electrode 1061 of each of the plurality of third subpixels 030 is distributed near the center of the second connector, and the second connection line X2 also extends along the second direction Y. The first connection line X1 and the second connection line X2 are spaced from each other in the first direction N, so that the plurality of first subpixels 010, the plurality of second subpixels 020, and the plurality of third subpixels 030 are spaced from each other in the first direction N, so that the layout space is more uniform.

[0176] For example, in some embodiments of the present disclosure, the plurality of first via holes D0 may also have a certain deviation relative to the first connection line X1, i.e., the plurality of first via holes D0 may not be completely distributed in the first connection line X1. For example, at least one first via hole D0 has a deviation of 1-2 micrometers relative to the first connection line X1. For example, at least one first via hole D0 has a deviation of 2-3 micrometers relative to the first connection line X1. Similarly, the plurality of second via holes D1 may have a certain deviation from the second connection line X2. For example, at least one second via hole D1 has a deviation of 1-2 micrometers relative to the second connection line X2.For example, at least a second connection hole D1 has a deviation of 2-3 micrometers relative to the second connection line X21.

[0177] With reference to Fig. 3 - Fig. 6, for example, in some embodiments of the present disclosure, in the same smallest repeating unit 700, the first connection holes D0 corresponding to the first subpixel 010 and the second subpixel 020, respectively, are provided in the same first connection line X1, and the second connection holes D1 corresponding to the first pixel block 0301 and the second pixel block 0302, respectively, are provided in the same second connection line X2. In some embodiments of the present disclosure, in the same smallest repeating unit 700, the first connection hole D0 corresponding to the first subpixel 010, the first connection hole D0 corresponding to the second subpixel 020, and the second connection hole D1 corresponding to the first pixel block 0301 are provided in the same first connection line X1, and the second connection hole D1 corresponding to the second pixel block 0302 is provided in the same second connection line X2.For example, in the same smallest repeating unit 700, the first connection hole D0 corresponding to the first subpixel 010 is provided in the first connection line X1, the first connection hole D0 corresponding to the second subpixel 020, the second connection hole D1 corresponding to the first pixel block 0301, and the second connection hole D1 corresponding to the second pixel block 0302 are provided in the second connection line X2, but the embodiments of the present disclosure are not limited thereto.

[0178] For example, the first connection hole D0 corresponding to the first subpixel 010, the first connection hole D0 corresponding to the second subpixel 020, the second connection hole D1 corresponding to the first pixel block 0301, and the second connection hole D1 corresponding to the second pixel block 0302 are arranged at equal intervals. For example, according to actual layout design requirements, the first connection hole D0 corresponding to the first subpixel 010, the first connection hole D0 corresponding to the second subpixel 020, the second connection hole D1 corresponding to the first pixel block 0301, and the second connection hole D1 corresponding to the second pixel block 0302 are arranged at unequal intervals, and the embodiments of the present disclosure are not limited to this.

[0179] As in Fig. 6, the first connecting portion 330 includes at least one hollowed portion 380, and the area of ​​the hollowed portion 380 is 1 / 4-1 / 3 of the area of ​​the first connecting portion 330.

[0180] In some embodiments of the present disclosure, the hollowed portion 380 of the first connection portion 330 is, for example, a through-hole or an opening penetrating the first connection portion 330 in the direction perpendicular to the base substrate, such that the hollowed portion 380 exposes the pattern of the pixel circuit 200 provided on the side of the first connection portion 330 facing the base substrate 001, and for example, the first connection portion 330 has a hollowed pattern. For example, the hollowed portion 380 of the first connection portion 330 and the first electrode 102 substantially do not overlap each other. For example, the display product is provided with the hollowed portion 380 to improve its transmittance.For example, the first connecting portion 330 is provided with the hollowed portion 380, which facilitates the light transmission of the display substrate, so that the display effect is excellent. For example, the number of hollowed portions 380 of the first connecting portion is determined according to the actual layout design requirements, and the embodiments of the present disclosure are not limited thereto. For example, the hollowed portion 380 is designed to have a regular shape, for example, the hollowed portion 380 is designed as a polygon, oval, regular polygon, and circle, etc. For example, the hollowed portion 380 is formed as an irregular shape. For example, the shapes of the plurality of hollowed portions 380 are the same. For example, the shapes of the plurality of hollowed portions 380 are designed to be different.Embodiments of the present disclosure do not limit the shape of the hollowed portion 380.

[0181] For example, the hollowed portion 380 of the same first connecting portion 330 is distributed symmetrically with respect to the symmetrical center line of the first connecting portion 330. For example, the position of the hollowed portion 380 of the first connecting portion 330 is determined according to the design requirements of the actual layout, and the embodiments of the present disclosure are not limited thereto.

[0182] For example, in the same first connecting portion 330, the boundary between the hollowed portion 380 and the edge of the first connecting portion 330 is not smaller than 1 micrometer to prevent the first connecting portion 330 from being broken.

[0183] Fig. 8 is an equivalence diagram of the pixel circuit provided by the embodiments of the present disclosure.

[0184] For example, as in Fig. 8, the light-emitting control transistor T6 in the pixel circuit 200 is a first light-emitting control transistor T6, the pixel circuit 200 further includes a second reset transistor T1, a threshold compensation transistor T2, a driver transistor T3, a data write transistor T4, a second light-emitting control transistor T5, a first reset control transistor T7, and a storage capacitor C.

[0185] The display substrate further includes, for example, reset power supply signal lines, scanning signal lines, power supply signal lines, reset control signal lines, light-emitting control signal lines, and data lines.

[0186] For example, the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driver transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the driver transistor T3; the first electrode of the first reset control transistor T7 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, and the second electrode of the first reset control transistor T7 is electrically connected to the first electrode of the light-emitting element 100 (ie, N4 node);The first electrode of the data write transistor T4 and the second electrode of the driver transistor T3 are electrically connected to each other; the second electrode of the data write transistor T4 and the data line are electrically connected to receive the data signal Data, and the gate electrode of the data write transistor T4 is electrically connected to the scanning signal line to receive the scanning signal Gate; the first electrode of the storage capacitor C is electrically connected to the power supply signal line, and the second electrode of the storage capacitor C is electrically connected to the gate electrode of the driver transistor T3; the gate electrode of the threshold compensation transistor T2 is electrically connected to the scanning signal line to receive the compensation control signal;the gate electrode of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first electrode of the second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, the second electrode of the second reset transistor T1 is electrically connected to the gate electrode of the driver transistor T3, and the gate electrode of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); the gate electrode of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM;The first electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the driver transistor T3, and the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 100; the first electrode of the second light-emitting control transistor T5 is electrically connected to the power supply signal line for receiving the first power supply signal VDD, and the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driver transistor T3;The gate electrode of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line for receiving the light-emitting control signal EM, and the second electrode of the light-emitting element 100 is connected to the voltage terminal VSS. The above power supply signal line refers to the signal line for outputting the voltage signal VDD, which is connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0187] For example, the sampling signal and the compensation control signal are identical, that is, the gate electrode of the data write transistor T4 and the gate electrode of the threshold compensation transistor T2 are electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate electrode of the data write transistor T4 and the gate electrode of the threshold compensation transistor T2 are electrically connected to different signal lines, respectively, that is,The gate electrode of the data write transistor T4 is electrically connected to the first scanning signal line, and the gate electrode of the threshold compensation transistor T2 is connected to the second scanning signal line, and the signals transmitted by the first scanning signal line and the second scanning signal line may be the same or different, so that the gate electrode of the data write transistor T4 and the threshold compensation transistor T2 can be controlled separately, which increases the flexibility of control of the pixel circuit 200.

[0188] For example, the light-emitting control signals input to the first light-emitting control transistor T6 and the second light-emitting control transistor T5 are the same, that is, the gate electrode of the first light-emitting control transistor T6 and the gate electrode of the second light-emitting control transistor T5 are electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate electrode of the first light-emitting control transistor T6 and the gate electrode of the second light-emitting control transistor T5 are electrically connected to different light-emitting control signal lines, and different light-emitting control signal lines transmit the same signal or different signals.

[0189] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 are the same, meaning that the gate electrode of the first reset transistor T7 and the gate electrode of the second reset transistor T1 are electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate electrode of the first reset transistor T7 and the gate electrode of the second reset transistor T1 are electrically connected to different reset control signal lines, and the signals on different reset control signal lines are the same or different.

[0190] For example, as in Fig. As shown in Figure 8, during the operation of the display substrate, in the first stage of image display, the second reset transistor T1 is turned on, so that the voltage of the N1 node is initialized; in the second stage of image display, the data signal Data is stored in the N1 node by the data write transistor T4, the driver transistor T3, and the threshold compensation transistor T2. In the third light-emitting stage, the second light-emitting control transistor T5, the driver transistor T3, and the first light-emitting control transistor T6 are turned on, and the light-emitting element 100 is forwarded to emit light.

[0191] It should be noted that in the embodiments of the present disclosure, in addition to the Fig. 8 (i.e., seven transistors and one capacitor), the pixel circuit may have other structures, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, although the embodiments of the present disclosure are not limited thereto. The equivalent diagram of the pixel circuit of the display substrate may be the same as the equivalent diagram of the pixel circuit shown in Fig. 8 shown pixel circuit 200.

[0192] Fig. 9 is a schematic view of a stacked structure of a light-shielding layer, an active semiconductor pattern, and a first interconnection layer in the pixel circuit provided in the embodiments of the present disclosure. Fig. 10 is a schematic view of a stacked structure of the light-shielding layer, the active semiconductor pattern, the first interconnection layer, a second interconnection layer, a semiconductor layer, and a third interconnection layer in the pixel circuit provided in the embodiments of the present disclosure.

[0193] As in Fig. As shown in Figure 9, the active semiconductor pattern LY1 is disposed on the light-shielding layer LY0, and the active semiconductor pattern LY1 is formed by patterning a semiconductor layer. The active semiconductor pattern LY0 and the first interconnection layer LY2 can be used to form the active layers of the driver transistor T3, the data write transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7, and the active layers are used to form channel regions of these transistors. The active semiconductor pattern LY0 includes the active layer patterns (channel regions) and the patterns of the doped regions (source regions and drain regions) of the transistors of the different subpixels, and the active layer patterns and the patterns of the doped regions of the transistors in the same pixel circuit are formed as an integral structure.

[0194] The active semiconductor pattern LY1 consists, for example, of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the source and drain regions described above can be regions doped with n-type or p-type impurities.

[0195] For example, a metal layer, such as a gate metal layer, is disposed on the side of the active semiconductor pattern LY1 facing away from the base substrate, wherein the metal layer comprises the scanning signal line, the reset control signal line, the light-emitting control signal line, and the gate electrodes of the driver transistor T3, the data write transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7. The dashed rectangular boxes in Fig. 9 shows the parts where the metal layer overlaps with the active semiconductor pattern LY1 as the channel region of the respective transistors. The portions of the active semiconductor pattern LY1 on two sides of the channel region are converted into the first and second electrodes of the transistor (i.e., the source region and drain region described above) by a method such as ion doping. The source electrode and drain electrode of the transistor are symmetrically constructed, so that the source electrode and drain electrode are physically indistinguishable from each other.In the embodiments of the present disclosure, for describing the transistor, in addition to the gate electrode as a control electrode, one electrode is directly referred to as a first electrode and the other electrode is directly referred to as a second electrode, so that the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure are interchangeable as needed.

[0196] For example, the semiconductor layer LY4 for forming the channel regions of the second reset transistor T1 and the threshold compensation transistor T2 in the pixel circuit is provided on the side of the active semiconductor pattern LY1 facing away from the base substrate, and the semiconductor layer LY4 comprises oxide semiconductor material.

[0197] Fig. For example, Fig. 10 shows the pixel circuit including the light-shielding layer LY0, the active semiconductor pattern LY1, the first interconnection layer LY2, the second interconnection layer LY3, the semiconductor layer LY4, and the third interconnection layer LY5 arranged layer by layer according to embodiments of the present disclosure.

[0198] As in Fig. As shown in Figure 10, the dashed rectangular boxes indicate the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, the second interconnection layer LY3 provides lower gate structures for the second reset transistor T1 and the threshold compensation transistor T2, the semiconductor layer LY4 overlaps with the second interconnection layer LY3, and the third interconnection layer LY5 is arranged on the side of the semiconductor layer LY4 facing away from the base substrate as the upper gate structures of the second reset transistor T1 and the threshold compensation transistor T2.

[0199] For example, when oxide semiconductors are used to form the active layer of the second reset transistor T1 and the active layer of the threshold compensation transistor T2 of the pixel circuit, the transistors using oxide semiconductors have the characteristics of good hysteresis, low leakage current, and low mobility, oxide semiconductor is used to replace low-temperature polysilicon material in the transistors to form a low-temperature polysilicon oxide (LTPO) pixel circuit to achieve low leakage current and improve the stability of the gate voltages of the transistors.

[0200] Of course, the embodiments of the present disclosure are not limited to the active semiconductor pattern LY1 of the pixel circuit as shown in Fig. 9A, the semiconductor layer of the channel regions of the second reset transistor T1 and the threshold compensation transistor T2 may be provided in a same layer as the channel regions of other transistors, that is, the active semiconductor pattern includes the channel regions of the second reset transistor T1, the threshold compensation transistor T2, the driver transistor T3, the data write transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, and the first reset control transistor T7.

[0201] Fig. 11 is a schematic view of a local structure of the first conductive layer provided by the embodiments of the present disclosure; Fig. 12 is a schematic view of the stacked structure of the light-shielding layer, the active semiconductor pattern, the first interconnection layer, the second interconnection layer, the semiconductor layer, the third interconnection layer, and the first conductive layer in the pixel circuit provided by the embodiments of the present disclosure; Fig. 13A is a schematic view of the stacked structure of the first conductive layer and the second conductive layer provided by the embodiments of the present disclosure; Fig. 13B is a schematic view of the stacked structure of the first conductive layer, the second conductive layer, and the light-emitting element provided by the embodiments of the present disclosure.

[0202] With reference to Fig. 11A, Fig. 12, for example, the display substrate includes the first conductive layer LY6 (e.g., SD1 layer) provided between the first electrode of the light-emitting element and the third interconnection layer LY5, and the first conductive layer LY6 includes a reset power supply signal line 801, the reset power supply signal line 801 being electrically connected to the first electrode of the first reset transistor T7 to provide the reset signal.For example, the above reset power supply signal line 801 is a first reset power supply signal line electrically connected to the first electrode of the first reset transistor T7, the display substrate further includes a second reset power supply signal line, a first portion of the second reset power supply signal line is provided between a film layer in which the first conductive layer LY6 is located and a film layer in which the gate electrode of the first reset transistor T7 is located, and is configured to be electrically connected to the first electrode of the second reset transistor T1 to provide the reset signal.

[0203] For example, see Fig. 6, Fig. 11 and Fig. 12, the first conductive layer LY6 further comprises a connection structure 802, the second conductive layer LY7 further comprises the connection block 450, the second electrode of the data write transistor T4 is connected to the connection block 450 via the connection structure 802 and is then electrically connected to the data line 400 to receive the data signal.

[0204] For example, with reference to Fig. 6, Fig. 11 and Fig. 12, the first conductive layer LY6 further comprises an interconnection structure 803, and the second reset transistor T1 is electrically connected to the second reset signal line via the interconnection structure 803.

[0205] For example, with reference to Fig. 6, Fig. 7, Fig. 11, Fig. 12 and Fig. 13, the first conductive layer LY6 further includes an interconnection structure 804, the first electrode of the first control light-emitting transistor T6 and the second electrode of the first reset transistor T7 are electrically connected to the interconnection electrode 105 in the light-emitting element LY8 via the interconnection structure 804 and the second interconnection portion 500 in the second conductive layer LY7, and the interconnection structure 804 is electrically connected to the interconnection electrode 105.

[0206] For example, with reference to Fig. 6, Fig. 11, Fig. 12 and Fig. 13, the first conductive layer LY6 further includes an interconnection structure 805, the interconnection structure 805 includes a first interconnection structure 805A and a second interconnection structure 805B, the first electrode of the second control light-emitting transistor T5 is electrically connected to the first interconnection structure 805A, and the second interconnection structure 805B is electrically connected to the first interconnection portion 330 in the second conductive layer LY7, thus the first electrode of the second control light-emitting transistor T5 is electrically connected to the power supply signal line 300.

[0207] For example, with reference to Fig. 6 and Fig. 12, the first conductive layer LY6 further comprises an interconnection structure 806, wherein the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driver transistor T3 and the second electrode of the first light-emitting control transistor T6 through the interconnection structure 806.

[0208] With reference to Fig. 6 and Fig. 12, for example, the first conductive layer LY6 further comprises a connection structure 807 for establishing an electrical connection between the second electrode of the second reset transistor T1, the second electrode of the threshold compensation transistor T2 and the gate electrode of the driver transistor T3.

[0209] With reference to Fig. 3, Fig. 6, Fig. 7, Fig. 11, Fig. 12 and Fig. 13, the orthographic projection of the interconnection structure 804 on the base substrate 001 substantially coincides with the orthographic projection of the interconnection block 450 on the base substrate 001, and the orthographic projection of the interconnection structure 804 on the base substrate 001 and the orthographic projection of the light-emitting element 100 on the base substrate 001 do not overlap, which is conducive to layout design and reduces signal interference between the light-emitting elements 100.

[0210] With reference to the Fig. 12 and Fig. 13, the connection structure 805 further comprises a third connection structure 805C, wherein the first connection structure 805A and the second connection structure 805B are spaced from each other in the first direction N and are electrically connected by the third connection structure 805C, so that the first electrode of the second light-emitting control transistor T5 is connected to the power supply signal line 300, wherein the connection path is flexibly adapted to the current layout arrangement and minimizes the wiring congestion with other transistors.

[0211] With reference to Fig. 3 and Fig. 13, the orthographic projection of the first subpixel 010 on the base substrate 001 is overlapped with each of the orthographic projection of the reset power supply signal line 801 on the base substrate 001 and the orthographic projection of the connection pattern 807 on the base substrate 001, and the overlapping area is distributed substantially symmetrically with respect to the symmetrical center line W1 of the main electrode 1040 of the first subpixel 010, thereby facilitating the flatness of the main electrode 1040 to reduce chromatic aberration.Similarly, the orthographic projection of the second subpixel 020 on the base substrate 001 overlaps with each of the orthographic projection of the reset power supply signal line 801 on the base substrate 001 and the orthographic projection of the connection structure 807 on the base substrate 001, and the overlapping area is distributed symmetrically with respect to the symmetrical center line W2 of the main electrode 1050 of the second subpixel 020, so that the flatness of the main electrode 1050 is good.

[0212] With reference to Fig. 3, Fig. 5, Fig. 6 and Fig.13, the orthographic projection of the first connection structure 805A on the base substrate 001 falls within the overlapping region AS2 of the main electrode 1060 of the third subpixel 030 and the data line 400 and is substantially symmetrical relative to the seventh symmetrical center line L40, thereby ensuring that the flatness of the third subpixel 030 is good to reduce the degree of chromatic aberration.

[0213] The embodiments of the present disclosure further provide a display device comprising any of the above-mentioned display substrates. The display device provided by the embodiments of the present disclosure is achieved by designing the pixel circuit and matching the shape of the pixel circuit and the light-emitting element, which contributes to improving the flatness of the first electrode of the light-emitting element and reducing the chromatic aberration of the display device.

[0214] For example, the display device provided by the embodiments of the present disclosure is an organic light-emitting diode display device.

[0215] For example, the display device further comprises a cover plate provided on the display side of the display substrate.

[0216] The display device is, for example, a mobile phone with a camera under the screen, a tablet computer, a laptop, a navigation device, and other products or components with display functions, and the embodiments of the present disclosure are not limited thereto.

[0217] The following points need to be clarified: (1) The accompanying drawings of the embodiments of the present disclosure refer only to the structures associated with the embodiments of the present disclosure, and other structures may be referred to the usual embodiments. (2) Features of the same embodiment and different embodiments of the present disclosure may be combined without conflict.

[0218] The above embodiments are merely exemplary embodiments of the disclosure and are not intended to define the scope of the disclosure. The scope of the disclosure is determined by the appended claims.

Claims

[1] A display substrate comprising: a base substrate; a plurality of subpixels on the base substrate, each of at least some of the subpixels comprising a light-emitting element and a pixel circuit, the light-emitting element comprising a light-emitting functional layer and a first electrode and a second electrode provided on two sides of the light-emitting functional layer in a direction perpendicular to the base substrate, the first electrode being provided between the light-emitting functional layer and the base substrate, the light-emitting element being provided at least partially in a light-emitting region, and the first electrode of the light-emitting element comprising a main electrode overlapping with the light-emitting region; a plurality of power supply signal lines, wherein at least some of the plurality of power supply signal lines extend in the first direction and are arranged in a second direction, wherein the plurality of power supply signal lines are provided between the base substrate and the first electrode of the light-emitting element, wherein the first direction intersects the second direction, wherein at least some of the subpixels comprise a plurality of first subpixels, wherein in a third direction perpendicular to the base substrate, at least one power supply signal line comprises a first power supply section overlapping with the main electrode of at least one of the plurality of first subpixels, wherein the first power supply section comprises a first main section and a second main section, in the second direction, a maximum size of the main electrode of the first subpixel is not smaller than a maximum size of its corresponding first power supply section, a maximum size of the first main section is larger than a maximum size of the second main section in the first power supply section, a connecting line of two end points of the main electrode of the first subpixel that are farthest apart from each other in the second direction is an end point connecting line, and the end point connecting line overlaps with the first main section in the third direction. [2] The display substrate according to claim 1, wherein the plurality of power supply signal lines include a first power supply signal line and a second power supply signal line, a maximum size of the first power supply signal line and a maximum size of the second power supply signal line in the second direction are a first size and a second size, respectively, and the second size is smaller than the first size. [3] The display substrate according to claim 1, wherein the plurality of first sub-pixels include at least one first-type sub-pixel, the first power supply portion overlapping with the main electrode of the first-type sub-pixel is a first-type power supply portion, and the first main portion of the first-type power supply portion is an asymmetric structure. [4] The display substrate according to claim 3, wherein the first main portion of the first type power supply portion includes a first protrusion, and the first protrusion is provided on a side of a first symmetrical center line of the second main portion extending in the first direction. [5] The display substrate according to claim 4, wherein an extending direction of a symmetrical center line of the portion of the first type power supply section except for the first protrusion intersects with an extending direction of a second symmetrical center line of the main electrode of the first type sub-pixel. [6] Display substrate according to any one of claims 4-5, wherein the plurality of first subpixels further comprise at least one subpixel of a second type, and the first power supply section overlapping with the main electrode of the second type subpixel is a second type power supply section, the second-type power supply portion includes a third symmetrical centerline extending in the first direction, the main electrode of the second-type sub-pixel includes a fourth symmetrical centerline extending in the first direction, the third symmetrical centerline of the second-type power supply portion is provided in a same column of the power supply signal line, and the fourth symmetrical centerline of the second-type sub-pixel, which overlaps with the second-type power supply portion, is provided in a same plane perpendicular to the base substrate. [7] A display substrate according to any one of claims 4-5, wherein the main electrode of the first subpixel comprises a first corner and a second corner opposite each other, and a third corner and a fourth corner opposite each other, an orthographic projection of at least one of the first corner and the second corner on the base substrate at least partially overlaps with an orthographic projection of the first symmetrical centerline on the base substrate, and an orthographic projection of the fourth corner on the base substrate at least partially overlaps with an orthographic projection of the first protrusion on the base substrate. [8] A display substrate according to claim 6, wherein the first main portion of the second type power supply portion comprises a second projection and a third projection, and the second projection and the third projection are symmetrically distributed relative to the third symmetrical center line, the main electrode of the subpixel of the second type comprises a first corner and a second corner opposite each other, and a third corner and a fourth corner opposite each other, an orthographic projection of the second protrusion on the base substrate at least partially overlaps with an orthographic projection of one of the first corner and the second corner on the base substrate, and an orthographic projection of the third protrusion on the base substrate at least partially overlaps with the orthographic projection of the other of the first corner and the second corner on the base substrate. [9] The display substrate according to claim 8, wherein in the third direction, the light-emitting region of the second type sub-pixel overlaps with at least one of the second protrusion and the third protrusion. [10] The display substrate according to claim 6 or 8, wherein, in the second direction, a maximum size of the first main portion of the second type power supply portion is larger than a maximum size of the first main portion of the first type power supply portion, and a ratio of a maximum size of the second main portion of the first type power supply portion to a maximum size of the second main portion of the second type power supply portion is 0.9~1.

1. [11] The display substrate according to any one of claims 6 and 8-10, wherein the maximum size of the first main portion of the second type power supply portion in the second direction is 1.1-2 times the maximum size of the second main portion of the second type power supply portion in the second direction. [12] A display substrate according to any one of claims 1-11, wherein each of the adjacent plurality of power supply signal lines comprises a plurality of power supply sections arranged in the first direction, and a first connecting section is provided between two adjacent power supply sections and is electrically connected thereto, and the plurality of power supply sections comprises the first power supply section, a ratio of a maximum size of the power supply portion in the second direction to a maximum size of the first connection portion in the second direction is 1.5-5. [13] The display substrate according to claim 7, wherein the first type power supply section comprises a first sub-type power supply section and a second sub-type power supply section, the second main section of the first type power supply section comprises a first side and a second side opposite to each other in the second direction, the first protrusion of the first sub-type power supply section is arranged on the first side of the second main section, and the first protrusion of the second sub-type power supply section is arranged on the second side of the second main section. [14] A display substrate according to claim 7 or 8, wherein the main electrode of the first subpixel comprises a plurality of corners, the plurality of corners comprise the first corner, the second corner, the third corner and the fourth corner, edges or their extension lines of the main electrode are sequentially connected to form a polygon, and each of a plurality of vertex angles of the polygon has an area that does not overlap with the corresponding corner of the main electrode, a non-overlapping area of the third corner and the corresponding vertex angle of the polygon is greater than a non-overlapping area of each of at least some of the other corners and the corresponding vertex angle of the polygon. [15] A display substrate according to any one of claims 1-11, wherein the at least some of the subpixels further comprise a plurality of second subpixels, in the third direction the at least one power supply signal line comprises a second power supply section overlapping with the main electrode of at least one of the plurality of second subpixels, the second power supply section includes a fifth symmetrical center line extending in the first direction, the main electrode of the second sub-pixel includes a sixth symmetrical center line extending in the first direction, the fifth symmetrical center line of the second power supply section is provided in a same column of the power supply signal line and the sixth symmetrical center line of the second sub-pixel, which overlaps with the second power supply section, is provided in a same plane perpendicular to the base substrate. [16] The display substrate according to claim 15, wherein an orthographic projection of the main electrode of the second sub-pixel on the base substrate overlaps with an orthographic projection of the second power supply region on the base substrate, an overlapping area being at least 90% of an area of the orthographic projection of the main electrode of the second sub-pixel on the base substrate. [17] The display substrate according to claim 15 or 16, wherein in the second direction, a maximum size of the second power supply section is smaller than a maximum size of the first main section of the first power supply section, and a ratio of the maximum size of the second power supply section and a maximum size of the second main section of the first power supply section is 0.9~1.

1. [18] A display substrate according to any one of claims 15-17, further comprising: a plurality of data lines extending in the first direction and arranged in the second direction, wherein the plurality of data lines and the plurality of power supply signal lines are provided in a same layer, wherein the data lines provided between two adjacent power supply signal lines comprise a first data line and a second data line arranged in the second direction, wherein the first data line and the second data line are distributed symmetrically relative to a seventh symmetrical center line between the first data line and the second data line, at least some of the subpixels further comprise a plurality of third subpixels, the main electrode of the light-emitting element of at least one of the plurality of third subpixels at least partially overlaps with the data line, and an overlapping region of the main electrode of the third subpixel and the data line is substantially symmetrical relative to the seventh symmetrical center line. [19] The display substrate of claim 18, further comprising: a plurality of second connecting portions arranged in the same layer as at least some of the plurality of power supply signal lines, each second connecting portion comprising a first connector and a second connector, wherein the plurality of second connecting portions are arranged in an array in the first direction and the second direction to form a plurality of second connecting portion rows and a plurality of second connecting portion columns, the power supply signal line comprises a plurality of power supply sections arranged in the first direction, a first connecting section is provided between two adjacent power supply sections and is electrically connected thereto, and the power supply sections of the plurality of power supply signal lines are arranged in an array in the first direction and the second direction to form a plurality of power supply section rows and a plurality of power supply section columns, the plurality of second connection section rows and the plurality of power supply section rows are arranged alternately in the first direction, and two adjacent second connection sections in the same second connection section row are arranged on two sides of the data line, respectively. [20] A display substrate according to claim 19, wherein the connecting electrode of the light-emitting element does not substantially overlap with the first connecting portion, in the first direction, a maximum size of the main electrode of the first subpixel is not smaller than a maximum size of the first main portion of the corresponding first power supply portion. [21] The display substrate according to any one of claims 19-20, wherein the first connector is electrically connected to the connection electrode of the first sub-pixel or the connection electrode of the second sub-pixel, and the second connector is electrically connected to the connection electrode of the third sub-pixel. [22] The display substrate according to any one of claims 12 and 18-21, wherein the first connecting portion includes at least one hollowed portion, and an area of the hollowed portion is 1 / 4-1 / 3 of an area of the first connecting portion. [23] A display device comprising the display substrate according to any one of claims 1-22.

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