DEVICE AND METHOD FOR MEASURING PHASE NOISE

Abstract

A device for measuring phase noise, comprising a sampler for sampling an input signal, an input filter for receiving an input signal from the sampler, a noise generator for generating a noise signal, and a combiner for receiving an input signal from the input filter or the noise generator, wherein the combiner provides an integrated noise output measurement. The input filter can operate in either the time domain or the frequency domain. The noise generator can use a noise signal to generate the output signal of the sampler or a noise estimate to generate the output signal of the sampler.

Description

RELATED PATENT APPLICATION

[0001] This application claims priority to commonly owned U.S. Patent Application No. 63 / 348,397, filed June 2, 2022, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD

[0002] The present disclosure relates to an apparatus and method for measuring phase noise through a communication channel. BACKGROUND

[0003] In a digital communication channel, a clock signal contains a noise component, commonly referred to here as phase noise. This phase noise propagates throughout the communication channel H(s). The communication channel can modify the frequency content of the phase noise. This communication channel can be known or unknown. The phase noise at the receiver end (after the communication channel) can be modified by the communication channel and exhibit a different frequency spectrum than the original phase noise. Different communication protocols may have different clock phase noise requirements. To ensure compliance with communication standards, it is important to accurately measure the phase noise at the receiver end.

[0004] In a method for measuring phase noise in a digital communications channel, a clock signal may be sampled to obtain digital samples of the clock signal. The phase noise may be included in the digital samples of the clock signal. The sampling may be performed in the time domain, and a time-to-frequency converter may transform the time-domain signal into the frequency domain. The frequency-domain signal may be passed through a communications channel, either a physical channel or a model, to produce an output that includes the channel's influence on the phase noise of the clock signal. The output of this channel also includes frequency peaks introduced by the sampling of the clock signal.

[0005] One complication of measuring clock phase noise at the receiver end is that the channel bandwidth may exceed the clock sampling rate. For phase noise below half the sampling rate, simple noise integration can be performed to calculate the phase noise. However, for frequencies above half the clock sampling rate, existing solutions may use a spectrum expansion technique or other method to estimate the high-frequency content. Spectrum expansion can be performed using a technique including spectral replication or convolution, harmonic replication, a neural network training model, slope-adaptive modulation, or a hidden Markov model (HMM), among others. These estimates can be affected by spurious signal frequencies introduced by the sampling.Furthermore, the accuracy of spectrum expansion is limited because it involves assumptions about how to estimate the higher frequency components, which may not be 100% accurate. Furthermore, out-of-band noise can be unpredictable, and any spectrum expansion introduces errors.

[0006] There is a need for an improved measurement of phase noise in clock signals used in a communication system. SUMMARY

[0007] According to one aspect, an apparatus for measuring phase noise is provided, including a sampler for sampling an input signal, an input filter for receiving an input signal from the sampler, a noise generator for generating a noise signal, a combiner for receiving an input signal from the input filter or the noise generator, and a combiner for outputting an integrated noise output measurement.

[0008] One aspect provides an apparatus for measuring phase noise, comprising a time-to-frequency domain converter for receiving the sampled input signal and generating first and second output signals at least in part as a result of the received sampled input signal, a first communication channel for receiving the first output signal from the time-to-frequency domain converter, a low-pass filter for receiving an output signal from the first channel communication channel, an interference rejection filter for receiving an output signal from the low-pass filter, the interference rejection filter outputting a signal to the combiner.

[0009] One aspect provides an apparatus for measuring phase noise, including a noise spectrum generator for receiving the second output signal from the time-to-frequency domain converter, a second communication channel for receiving an output signal from the noise spectrum generator, a high-pass filter for receiving an output signal from the second communication channel, the high-pass filter outputting a signal to the combiner.

[0010] According to another aspect, a method for measuring phase noise is provided, including sampling an input signal to generate a sampled input signal, filtering the sampled input signal to generate a filtered input signal, generating a noise signal, and combining the filtered input signal and the noise signal to generate an integrated noise output.

[0011] One aspect includes a method for measuring phase noise, wherein the sampled input signal is transformed from the time domain to the frequency domain, thereby generating a frequency domain representation of the sampled input signal, the frequency domain representation of the sampled input signal is passed through a first communication channel, the output signal of the first communication channel is filtered with a low-pass filter to generate a low-frequency filtered signal, and noise in the low-frequency filtered signal is suppressed with a noise suppression filter; One aspect provides a method for measuring phase noise, including generating a noise signal based at least in part on the frequency domain representation of the sampled input signal, passing the frequency domain representation of the sampled input signal through a second communication channel, and filtering the output signal of the second communication channel with a high-pass filter to generate a high-frequency filtered signal; SHORT DESCRIPTION OF THE CHARACTERS

[0012] The figures illustrate example circuits and systems for measuring phase noise. Fig. 1 illustrates an apparatus for measuring phase noise of an input clock. Fig. Figure 2 illustrates an apparatus for measuring phase noise of an input clock in the frequency domain. Fig. Figure 3 illustrates a circuit for an interference suppression filter. Fig. Figure 4 illustrates a technique for estimating a noise level in the frequency domain. Fig. Figure 5 illustrates an alternative apparatus for measuring phase noise of an input clock signal in the frequency domain. Fig. Figure 6 illustrates a method for estimating a noise level in the time domain. Fig. Figure 7 illustrates an apparatus for measuring phase noise of an input clock in the time domain. Fig. Figure 8 illustrates an alternative apparatus for measuring phase noise of an input clock in the time domain. DESCRIPTION

[0013] Fig. Figure 1 illustrates one of various examples of an apparatus for measuring phase noise. The apparatus 100 may be a digital signal processor (DSP), with the individual components in Fig. 1 may represent specific functions implemented on the DSP. The device 100 may be a microcontroller, with the individual components of Fig. 1 may represent certain functions implemented on the microcontroller. The device 100 may be a field-programmable gate array (FPGA) in which individual components of the Fig. 1 may represent certain functions implemented on the FPGA. The device 100 may be a combination of several individual computing elements that together implement the Fig. 1. The device 100 may include a clock input 110. The clock input 110 may receive a clock signal from a phase-locked loop (PLL), a delay-locked loop (DLL), or other clock source. The clock input 110 may be sampled by a sampler 130. The output of the sampler 130 may be a sampled clock signal 135. The sampled clock signal 135 may be input to the input filter 150. The input filter 150 may include a plurality of computation blocks to filter the sampled clock signal 135. The computation blocks may include, but are not limited to, low-pass filters, communication channels, band-pass filters, high-pass filters, spurious rejection filters, noise generators, equalizers, and transforms.

[0014] The input filter 150 may provide a filtered output signal 155 to the combiner 190. The input filter 150 may optionally provide an output signal 160 to the noise generator 170. The noise generator 170 may include one or more computational blocks to generate a noise signal. The noise generator 170 may include other computational blocks, including, but not limited to, low-pass filters, communication channels, band-pass filters, high-pass filters, spurious signal rejection filters, equalizers, and transforms. The noise generator 170 may provide a noise output 175 to the combiner 190. The combiner 190 may combine the filtered output 155 and the noise output 175 using one of various methods. The combiner 190 may include adders, integrators, multipliers, and other computational blocks to combine the filtered output signal 155 and the noise output signal 175.The combiner 190 can output an integrated phase noise measurement 199.

[0015] Fig. Figure 2 illustrates one of various examples of an apparatus for measuring phase noise. The apparatus 200 may be a digital signal processor (DSP), with the individual components in Fig. 2 may represent specific functions implemented on the DSP. The device 200 may be a microcontroller, with the individual components of Fig. 2 may represent specific functions implemented on the microcontroller. Device 200 may be a field-programmable gate array (FPGA), with individual components of Fig. 2 may represent specific functions implemented on the FPGA. The device 200 may be a combination of several individual computing elements that together implement the Fig. 2. The device 200 may include a clock input 110. The clock input 110 may receive a clock signal from a phase-locked loop (PLL), a delay-locked loop (DLL), or other clock source. The clock input 110 may be sampled by a sampler 130. The output of the sampler 130 may be a sampled clock signal 135. The sampled clock signal 135 may be input to the time-to-frequency converter 250. The time-to-frequency converter 250 may convert the time-domain sampled clock signal 135 into a frequency-domain representation 255. The frequency-domain representation 255 may be input to the first communication channel 260. The first communication channel 260 may be a physical channel or a model of a channel defined by the frequency-domain response H(s).The first communication channel 260 may modify the frequency content of the frequency domain representation 255 in accordance with the frequency domain representation H(s). The first communication channel 260 may be a model defined by a frequency domain model H(f). The first communication channel 260 may modify the frequency content of the frequency domain representation 255 in accordance with the frequency domain representation H(f). The output signal of the first communication channel 260 may be input to a low-pass filter 265 defined by an s-domain response H1(s). The low-pass filter 265 may be defined by a frequency domain response H1(f). The output signal of the low-pass filter 265 may be input to the noise cancellation filter 280.The noise rejection filter 280 may filter the low-pass filtered input signal to remove frequency peaks originating from the sampler 130, the first communication channel 260, the low-pass filter 265, or other sources. The time-to-frequency converter 250, the first communication channel 260, the low-pass filter 265, and the noise rejection filter 280 may include the input filter 150, as shown in FIG. Fig. 1 illustrates.

[0016] The frequency domain representation 255 may be input to the noise spectrum generator 270. The noise spectrum generator 270 may generate an output noise spectrum 271 whose noise intensity is at least partially controlled by the frequency domain representation 255, as explained in more detail in later sections of this specification. The output noise spectrum 271 of the noise spectrum generator 270 may be input to the second communication channel 272. The second communication channel 272 may be a physical channel or a model of a channel defined by the frequency domain response H(s). The second communication channel 272 may be defined by a frequency domain model H(f). The second communication channel 272 and the first communication channel 260 may have identical responses H(s). The second communication channel 272 and the first communication channel 260 may have identical responses H(f).The output signal of the second communication channel 272 may be input to the high-pass filter 275, which is defined by a frequency-domain response 1-H1(s). The high-pass filter 275 may be defined by a frequency-domain response 1-H1(f). The noise spectrum generator 270, second communication channel 272, and high-pass filter 275 components may include the noise generator 170, as shown in FIG. Fig. 1 illustrates.

[0017] The output signal of the noise rejection filter 280 or the output signal of the high-pass filter 275 can be inputs to the adder 285. The output signal of the adder 285 can serve as an input to the integrator 290. The integrator 290 can integrate the output signal of the adder 285 over a predetermined frequency bandwidth to determine an integrated phase noise measurement 299. The integrator 290 and the adder 285 can control the combiner 190 of the Fig. 1.

[0018] Fig. 3 illustrates one of various examples of a noise suppression filter 280. The input signal 310 may be input to the noise frequency search block 320. The input signal 310 may be the output signal of the low-pass filter 265 of Fig. 2. The search block 320 may locate the position of an interference signal frequency according to the following method. The interference signal frequency may be determined based on finding a peak in the frequency spectrum of the input signal 310 between a first frequency f spur_in - BW spur and a second frequency f spur_in + BW spur be determined, where f spur_in the frequency of the sampler 130 of Fig. 1 represents and BW spur represents a given bandwidth of the interference signal.

[0019] The interference signal frequency, also known as f spur_can be input into the linear interpolation block 330. The linear interpolation block 330 can calculate harmonics of the noise signal frequency f according to the following procedure spur_ up to a given maximum frequency f max suppress. A branch line starting frequency f stant can be used as k*f spur - BW spur and a noise stop frequency can be defined as k*f spur + BW spur where k can be an integer from 1 to N, where N is defined as f max / f spur can be defined. For any value of k from 1 to N, the frequency content of the input signal 310 between the noise start frequency and the noise stop frequency can be suppressed according to the following interpolation equation, where I(f) represents the interpolated frequency content at each of the N positions between the noise start frequency and the noise stop frequency: I(f)=I(fstartk)+(I(fstopk)−I(fstartk)fstopk−fstartk)(f−fstartk)

[0020] The example of Fig. 3 is one of several examples of noise suppression and is not intended to limit other noise suppression techniques.

[0021] Back to Fig. 2: The noise spectrum generator 270 from Fig. 2 may generate a noise signal based on any of the various methods. The frequency domain representation 255 may be represented as S(f). S(f) may include N spectral bins numbered from bin 0 to bin N-1, and the spectral magnitude of S(f) may be defined as |S(t)|. According to one of various examples, the last M spectral bins (bins NM to N-1) may be analyzed. From the last M spectral bins, the K bins with the smallest spectral amplitude are selected. The values ​​of N, M, and K may be predetermined values, where NM and M>K. The array S min can contain the K bins with the smallest spectral amplitude, defined as S min (1) to S min (K). The size of the output noise spectrum 271 is called NL and can be defined as the mean of these K bins of the smallest spectral size as follows: NL=1K∗∑kSmin(k).

[0022] The generation of the noise spectrum in the noise spectrum generator 270 is still in Fig. 4. The frequency domain representation 255 is illustrated as a spectral magnitude 410, with the magnitude on the y-axis and the spectral range on the x-axis. For the purposes of this illustration, N, the total number of spectral bins, may be 128. This number is not intended as a limit but is for illustrative purposes only. The shape and size of the spectral magnitude 410 are not intended as a limit and are for illustrative purposes only. For the purposes of this illustration, M may be set to 16. The last M=16 bins of the spectral magnitude 410 are illustrated in the exploded view 420. For the purposes of this illustration, K may be set to 4. According to the previously described method, the 4 bins with the smallest size are selected from the last 16 bins. The 4 smallest sizes are labeled Smin(1), Smin(2), Smin(3) and Smin(4).These four amplitude values ​​are used in the previous equation to determine the amplitude of the generated noise spectrum: . NL=1K∗∑kSmin(k).

[0023] Fig. Figure 5 illustrates an alternative device for measuring phase noise. The device 500 may be a digital signal processor (DSP), with the individual components in Fig. 5 can represent specific functions implemented on the DSP. The device 500 can be a microcontroller, with the individual components in Fig. 5 may represent specific functions implemented on the microcontroller. Device 500 may be a field-programmable gate array (FPGA), with individual components of Fig. 5 may represent specific functions implemented on the FPGA. The device 500 may be a combination of several individual computing elements that together implement the Fig. 5. The device 500 may include a clock input 110. The clock input 110 may receive a clock signal from a PLL (Phase-Locked Loop), DLL (Delay-Locked Loop), or other clock source. The clock input 110 may be sampled by a sampler 130. The output of the sampler 130 may be a sampled clock signal 135. The sampled clock signal 135 may be input to the time-to-frequency converter 550. The time-to-frequency converter 550 may convert the sampled clock signal 135 into a frequency domain representation 555. The frequency domain representation 555 may be input to a communication channel 560. The communication channel 560 may be a physical channel or a model of a channel defined by the frequency response H(s).The communication channel 560 may modify the frequency content of the frequency domain representation 555 in accordance with the frequency domain representation H(s). The communication channel 560 may be defined by a frequency domain model H(f). The communication channel 560 may modify the frequency content of the frequency domain representation 555 in accordance with the frequency domain representation H(f). The output signal of the communication channel 560 may be input to a low-pass filter 565 defined by a frequency domain response H1(s). The low-pass filter 565 may be defined by a frequency domain response H1(f). The output signal of the low-pass filter 565 may be input to an interference suppression filter 580. The noise rejection filter 580 may filter the input signal to remove noise in the signal that originates from the sampler 130, the communication channel 560, the low-pass filter 565, or other sources.The integrator 590 can integrate the output signal of the noise suppression filter 580.

[0024] The time-frequency converter 550, the communication channel 560, the low-pass filter 565 and the noise suppression filter 580 may be the input filter 150 of the Fig. 1.

[0025] An output signal of the integrator 590 may be an input signal to an adder 585. The noise estimate 595 may be a second input signal of the adder 585. The output signal of the adder 585 may be the integrated phase noise measurement 599. The integrator 590 and the adder 585 may control the combiner 190 of the Fig. 1.

[0026] The size of the noise estimate 595 can be calculated in the frequency domain according to the Fig. 4 illustrated procedures.

[0027] The size of the noise estimate 595 can be determined according to the Fig. 6 can be determined in the time domain.

[0028] Fig. 6 illustrates a method for determining a noise level NL in the time domain, where NL represents the magnitude of a generated noise signal. At operation 610, a noise level NL may be initialized to zero and the index n may be initialized to zero. The input x(n) may be the sampled input signal 135. At operation 630, a comparison may be made between the current sample of input x(n) and the current value of the noise level NL. If the magnitude of the input signal sample exceeds the magnitude of the noise level, or |x(n)| > NL, the method may proceed to operation 640. At operation 640, the value of the noise level NL may be updated based on the following equation: NL = NL + s1 * (|x(n)| - NL). The parameter si may be a predetermined value between 0 and 1, which may control the rate of change of the noise level NL.As one of several examples, at a value of s1=0.9, the noise level NL will change rapidly to approach the value of |x(n)|, while at a value of si=0.1, the noise level NL will change slowly to approach the value of |x(n)|. Returning to operation 630, if the magnitude of the input signal does not exceed the magnitude of the noise level, or |x(n)| < NL, execution proceeds to operation 650, and the value of the noise level may be updated to a value NL based on the following equation: NL = NL + s2 * (|x(n)| - NL), (|x(n) - NL) is a negative value. The parameter s2 may be a predetermined value between 0 and 1, which can be used to control the rate of change of the updated noise level NL.As one of several examples, for a value of s2=0.9, the updated noise level may change rapidly to approach the value of |x(n)|, while for a value of s2=0.1, the updated noise level may change very slowly to approach the value of |x(n)|.

[0029] In one of the various examples, s2 can be set to a value much larger than s1, and the noise level can decrease much faster than it increases. The values ​​of s1 and s2 can be adjusted so that the noise level NL increases and decreases at a specific rate as the input variable |x(n)| changes.

[0030] At operation 660, if more data remains to be processed, the method returns to operation 620 and the next sample of x(n) is analyzed. If there is no more data to be processed, the method ends, and the noise level may not continue to be updated.

[0031] Fig. Figure 7 illustrates one of various examples of an apparatus for measuring phase noise in the time domain. The apparatus 700 may be a digital signal processor (DSP), with the individual components in Fig. 7 can represent specific functions implemented on the DSP. The device 700 can be a microcontroller, with the individual components in Fig. 7 may represent certain functions implemented on the microcontroller. Device 700 may be a field-programmable gate array (FPGA), with individual components of Fig. 7 may represent specific functions implemented on the FPGA. The device 700 may be a combination of several individual computing elements that together implement the Fig. 7. The device 700 may include a clock input 110. The clock input 110 may receive a clock signal from a phase-locked loop (PLL), a delay-locked loop (DLL), or other clock source. The clock input 110 may be sampled by a sampler 130. The output of the sampler 130 may be the sampled clock signal 135. The sampled clock signal 135 may be input to the first communication channel 760. The first communication channel 760 may be a physical channel or a model of a channel defined by the time-domain response h(t). The first communication channel 760 may modify the content of the sampled clock signal 135 in accordance with the time-domain representation h(t). The output signal of the first communication channel 760 may be input to a low-pass filter 765 defined by a time domain response h1(t).The output signal of the low-pass filter 765 can be input to the noise rejection filter 780. The noise rejection filter 780 can filter the low-pass filtered input signal to remove frequency peaks originating from the sampler 130, the first communication channel 760, the low-pass filter 765, or other sources. The first communication channel 760, low-pass filter 765, and noise rejection filter 780 components can include the input filter 150, as shown in FIG. Fig. 1 illustrates.

[0032] The sampled clock signal 135 may be input to the noise signal generator 770. The noise signal generator 770 may generate an output noise signal 771 whose noise level is at least partially controlled by the sampled clock signal 135. The output noise signal 771 of the noise signal generator 770 may be input to the second communication channel 772. The second communication channel 772 may be a physical channel or a model of a channel defined by the time-domain response h(t). The second communication channel 772 and the first communication channel 760 may have identical responses h(t). The output signal of the second communication channel 772 may be input to the high-pass filter 775, which is defined by a time-domain response 1-h1(t). The components noise signal generator 770, second communication channel 772, and high-pass filter 775 may illustrate the noise generator 170, as shown in Fig. 1 illustrates.

[0033] The noise suppression filter 780 may suppress noise in the output signal of the low-pass filter, as described in the previous parts of this disclosure. The noise suppression filter 780 may suppress noise in the output signal of the low-pass filter by another method.

[0034] The noise signal generator 770 may generate a noise signal as described in the previous sections of this disclosure. The noise signal generator 770 may generate a noise signal using a different method.

[0035] The output of noise rejection filter 780 and the output of high-pass filter 775 may each be inputs to adder 785. The output of adder 785 may be input to integrator 790. Integrator 790 may integrate the output of adder 785 over a predetermined period to determine an integrated phase noise measurement 799.

[0036] Fig. Figure 8 illustrates an alternative device for measuring phase noise in the time domain. The device 800 may be a digital signal processor (DSP), with the individual components in Fig. 8 can represent specific functions implemented on the DSP. The device 800 can be a microcontroller, with the individual components of Fig. 8 may represent specific functions implemented on the microcontroller. Device 800 may be a field-programmable gate array (FPGA), with individual components of Fig. 8 may represent specific functions implemented on the FPGA. The device 800 may be a combination of several individual computing elements that together implement the Fig. 8. The device 800 may include a clock input 110. The clock input 110 may receive a clock signal from a phase-locked loop (PLL), a delay-locked loop (DLL), or other clock source. The clock input 110 may be sampled by a sampler 130. The output of the sampler 130 may be a sampled clock signal 135. The sampled clock signal 135 may be input to the communication channel 860. The communication channel 860 may be a physical channel or a model of a channel defined by the time-domain response h(t). The communication channel 860 may modify the content of the sampled clock signal 135 in accordance with the time-domain representation h(t). The output of the communication channel 860 may be input to a low-pass filter 865 defined by a time-domain response h1(t).The output signal of low-pass filter 865 can be input to a spurious signal rejection filter 880. The spurious signal rejection filter 880 can filter the input signal to remove spurious signals from the sampler 130, the communication channel 860, the low-pass filter 865, or other sources. The integrator 890 can integrate the output signal of the spurious signal rejection filter 880.

[0037] An output signal of the integrator 890 may be an input to an adder 885. The noise estimate 895 may be a second input of the adder 885. The output signal of the adder 885 may be the integrated phase noise measurement 599.

[0038] The size of the noise estimate 895 can be calculated in the frequency domain according to the Fig. 4 illustrated procedures.

[0039] The size of the noise estimate 895 can be calculated in the time domain according to the Fig.6 illustrated procedures.

[0040] Although the examples have been described above, other variations and examples may be derived from this disclosure without departing from the spirit and scope of these disclosed examples. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 348,397

[0001]

Claims

[1] Device comprising: a sampler for sampling an input signal; an input filter for receiving an input signal from the scanner; a noise generator for generating a noise signal; and a combiner for receiving inputs from the input filter and the noise generator, respectively, the combiner outputting an integrated noise output measurement. [2] The apparatus of claim 1, wherein the input filter comprises: a time-to-frequency domain converter for receiving the sampled input signal and for generating first and second output signals at least partially as a result of the received sampled input signal; a first communication channel for receiving the first output signal from the time-to-frequency domain converter; a low-pass filter to receive an output signal from the first communication channel; and a noise rejection filter for receiving an output signal from the low-pass filter, the noise rejection filter outputting a signal to the combiner. [3] The apparatus of claim 2, wherein the noise suppression filter suppresses the output of the low-pass filter at calculated noise frequency positions. [4] Apparatus according to any one of claims 2 to 3, wherein the noise generator comprises: a noise spectrum generator to receive the second output signal from the time-to-frequency domain converter; a second communication channel to receive an output signal of the noise spectrum generator; and a high-pass filter for receiving an output signal of the second communication channel, the high-pass filter outputting a signal to the combiner. [5] The apparatus of claim 4, wherein the noise spectrum generator outputs a noise spectrum based at least in part on the amplitude of a predetermined number of bins in the spectrum of the second output signal of the time-to-frequency converter. [6] The apparatus of claim 4, wherein the noise spectrum generator is to output a noise spectrum based at least on an average spectral amplitude of a predetermined number of bins in the output signal of the time-frequency converter. [7] Apparatus according to any one of claims 4 to 6, wherein the combiner comprises: a summer to receive the output signal of the noise suppression filter or the output signal of the high-pass filter and generate a sum signal; and an integrator to receive the sum signal from the summer, the integrator outputting an integrated phase noise measurement. [8] Apparatus according to any one of claims 2 to 6, wherein the combiner comprises: an integrator to receive an output signal of the noise suppression filter; and a summer for receiving at a first input an output signal from the integrator and for receiving at a second input a noise estimate signal from the noise generator, the summer producing an integrated noise measurement at the summer output. [9] The apparatus of claim 8, wherein the noise estimation signal is based on the average spectral magnitude of a predetermined number of bins in the frequency domain representation of the sampled input signal. [10] Device according to one of claims 1 to 9, wherein the input filter comprises: a first communication channel to receive the sampled input signal; a low-pass filter to receive an output signal from the first communication channel; and a noise suppression filter for receiving an output signal from the low-pass filter, the noise suppression filter outputting a signal to the combiner. [11] The apparatus of claim 10, wherein the noise suppression filter suppresses the output of the low-pass filter at calculated noise frequency positions. [12] Apparatus according to any one of claims 10 to 11, wherein the noise generator comprises: a noise generator to generate a noise signal; a second communication channel to receive an output signal from the noise generator, and a high-pass filter for receiving an output signal of the second communication channel, the high-pass filter outputting a signal to the combiner. [13] The apparatus of claim 12, wherein the noise generator outputs a noise signal based at least in part on the amplitude of the sampled input signal. [14] Apparatus according to any one of claims 12 to 13, wherein the combiner comprises: a summer to receive the output signal of the noise suppression filter or the output signal of the high-pass filter and generate a sum signal; and an integrator to receive the sum signal from the summer, the integrator outputting an integrated phase noise measurement. [15] The apparatus of claim 10, wherein the combiner comprises: an integrator to receive an output signal of the noise suppression filter; and a summer to receive at a first input an output signal from the integrator and a second input signal from a noise estimate signal of the noise generator, the summer producing an integrated noise measurement at the summer output. [16] The apparatus of claim 15, wherein the noise estimation signal is based on a predetermined number of samples of the sampled input signal. [17] Method comprising: Sampling an input signal to generate a sampled input signal; Filtering the sampled input signal to produce a filtered input signal; generating a noise signal; and Combining the filtered input signal and the noise signal to produce an integrated noise output. [18] The method of claim 17, wherein filtering the sampled input signal comprises: Transforming the sampled input signal from the time domain to the frequency domain, thereby generating a frequency domain representation of the sampled input signal; Passing the frequency domain representation of the sampled input signal through a first communication channel; Filtering the output signal of the first communication channel with a low-pass filter to generate a low-frequency filtered signal; and Suppressing interference signals in the low-frequency filtered signal with an interference signal suppression filter, [19] The method of claim 18, wherein the noise suppression filter suppresses the low frequency filtered signal at calculated noise frequency positions. [20] A method according to any one of claims 18 to 19, wherein generating a noise signal comprises: generating a noise signal based at least in part on the frequency domain representation of the sampled input signal; Passing the frequency domain representation of the sampled input signal through a second communication channel; and Filtering the output signal of the second communication channel with a high-pass filter to generate a high-frequency filtered signal; [21] The method of claim 20, wherein generating a noise signal comprises generating a noise estimate based on the average spectral magnitude of a predetermined number of bins in the frequency domain representation of the sampled input signal and passing the noise estimate through a communication channel and filtering the output signal of the communication channel with a high-pass filter. [22] The method of any one of claims 20 to 21, wherein combining the filtered input signal and the noise signal comprises: summing the output signal of the noise suppression filter and the high-frequency filtered signal, thereby generating a summation signal; and Integrate the summation signal to calculate an integrated noise measurement output signal. [23] A method according to any one of claims 18 to 22, wherein combining the filtered input signal and the noise signal comprises: Integrating the output signal of the noise suppression filter; and Summing an output signal of the integrator or a noise estimate signal of the noise generator at a summer, wherein the summer serves to generate an integrated noise measurement at the summer output. [24] The method of claim 23, wherein the noise estimation signal is based on the average spectral magnitude of a predetermined number of bins in the frequency domain representation of the sampled input signal. [25] A method according to any one of claims 17 to 24, wherein filtering the sampled input signal comprises: Passing the sampled input signal through a first communication channel; Filtering the output signal of the first communication channel with a low-pass filter to generate a low-frequency filtered signal; and Suppressing noise in the low-frequency filtered signal with a noise suppression filter. [26] The method of claim 25, wherein the noise suppression filter suppresses the low frequency filtered signal at calculated noise frequency positions. [27] A method according to any one of claims 25 to 26, wherein generating a noise signal comprises: generating a noise signal based at least in part on the samples of the sampled input signal; Passing the noise signal through a second communication channel; and Filtering the output signal of the second communication channel with a high-pass filter to generate a high-frequency filtered signal. [28] The method of claim 27, wherein generating a noise signal comprises generating a noise estimate based on the amplitude of individual samples of the sampled input signal. [29] The method of any one of claims 27 to 28, wherein combining the filtered input signal and the noise signal comprises: summing the output signal of the noise suppression filter and the high-frequency filtered signal, thereby generating a summation signal; and Integrate the summation signal to calculate an integrated noise measurement output signal. [30] The method of any one of claims 25 to 29, wherein combining the filtered input signal and the noise signal comprises: Integrating the output signal of the noise suppression filter; and Summing an output signal of the integrator or a noise estimate signal at a summer, wherein the summer serves to generate an integrated noise measurement at the summer output. [31] The method of claim 30, wherein the noise estimation signal is based on a predetermined number of samples of the sampled input signal.

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