Wireless connection method and system for digital circuit JATG debugging, medium and equipment

Abstract

The invention provides a wireless connection method and system for digital circuit JATG debugging, a medium and equipment, and the method comprises the steps: 1, achieving the wireless connection through employing a JATG interface signal wireless unvarnished transmission A-end part and a B-end part, enabling the A-end part to be connected with an adapter through a JATG interface flat cable, enabling the B-end part to be connected with a JATG interface of target equipment, and enabling the A-end part to be connected with the adapter through a JATG interface flat cable; data transmission is carried out between the A-end component and the B-end component through WIFI signals. The adapter is connected with the debugging computer through a USB data line and communicates with target equipment through a wireless signal; 2, setting a multi-bit dial switch to set a unique matching address for each B-end component; and step 3, controlling the A-end component and the corresponding B-end component to be wirelessly matched and connected through a dial switch or a USB serial port command after power-on, and performing online debugging, testing and program updating on target equipment by using IDE software interface operation after wireless connection is completed.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a wireless connection method, system, medium and device for JATG debugging of a digital circuit. Background Art

[0002] During the development of the towed array, after each functional circuit unit has completed the functional debugging test, it is necessary to conduct an array integration test. At this time, the circuit unit has been installed in a sealed barrel, and all functional modules have been installed in the structural support. The towed array segment has even been placed inside the PU sheath and has been filled with oil. It is inconvenient to debug and connect the relevant functional circuits online. If a problem is found and online testing, detection, program update and other debugging are required, the equipment sheath usually needs to be removed, and the internal oil needs to be released and connected to the relevant functional circuits through a dedicated connector for debugging and testing. This debugging method is not only time-consuming, labor-intensive and inefficient, but also because the working environment of the equipment circuit has changed, the debugging test results are inconsistent with the actual use, and there is insufficient test verification. A remote non-contact debugging method and means are needed to solve the above problems.

[0003] There are two main existing remote contactless debugging methods. Method 1: Use internal and external resources of the chip to integrate some remote communication functions on the target device to build a dedicated debugging system. Method 2: Integrate a dedicated wireless JTAG debugger into the target device to build a JATG debugging connection. Method 1 requires adding additional hardware to the target device, and the complexity of system construction will inevitably increase costs and debugging cycles, and the workload of debugging designers will also increase. Method 2 integrates a dedicated wireless JATG debugging adapter. Although JATG is a dedicated test interface standard, the internal access design of each chip manufacturer is different. The dedicated JATG debugging adapter usually provided by the chip manufacturer is used for online program debugging, signal monitoring, firmware updates, etc. This wireless JATG debugging connection method is usually designed for chips and IDE development software, and lacks versatility.

[0004] Considering the limited space of the towed linear array and the large number of related digital circuits in the array, the above two existing methods are not suitable for the integrated debugging and testing of towed linear array equipment.

[0005] Patent application document CN101102566A discloses a design method and debugging method of a mobile phone JTAG debugging interface signal, wherein: only a clock signal, a conversion signal, a data input signal and a data output signal are set; and a diode is multiplexed with a system reset signal as a core reset signal. In any operating state of the target board, an online connection is used to connect to the target board for debugging operations. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of the present invention. Summary of the invention

[0006] In view of the defects in the prior art, the object of the present invention is to provide a wireless connection method, system, medium and device for JATG debugging of digital circuits.

[0007] The wireless connection method for JATG debugging of a digital circuit provided by the present invention comprises:

[0008] Step 1: Use JATG interface signal to wirelessly transmit the two components of end A and end B to achieve wireless connection, where the end A component is connected to the adapter through the JATG interface cable, and the end B component is connected to the JATG interface of the target device. The A-end component and the end B component use WIFI signals for data transmission; the adapter is connected to the debugging computer through a USB data cable and communicates with the target device through wireless signals;

[0009] Step 2: Set the multi-position DIP switch to set a unique matching address for each B-end component;

[0010] Step 3: After power-on, control the A-end component to wirelessly match and connect with the corresponding B-end component through the DIP switch or USB serial port command. After the wireless connection is completed, use the IDE software interface to perform online debugging, testing and program update on the target device.

[0011] Preferably, the A-end and B-end components include a single-chip control circuit, a wireless transparent transmission circuit and a power supply circuit, which are used to construct a small circuit module, realize the wireless transmission of JATG interface signals, and configure the pairing address by setting a multi-bit DIP switch to support node-to-point connection; the single-chip control circuit, the wireless transparent transmission circuit and the power supply circuit are connected in pairs;

[0012] The single-chip control circuit adopts a small-volume single-chip microcomputer circuit, which is used to initialize the wireless transmission circuit, read the data interface and perform transmission control; the wireless transparent transmission circuit adopts a WIFI module for wireless node pairing and data transmission and reception; the power supply circuit is responsible for converting the working voltage and selecting the reference voltage according to the requirements of the JATG debugger.

[0013] Preferably, the wireless transmission distance is controlled. Under the preset data transmission rate, an integrated wireless transmission module with an integrated antenna is used. The TCK, TMS, TDI, TDO, and TRST signals are directly connected to the EMCA data input and output interface of the wireless transparent transmission circuit according to the input and output relationship between the A and B ends. The single-chip control circuit provides a data input and output interface enable signal for the wireless transparent transmission circuit. The enable signal frequency is greater than 2 times the TCK clock frequency, and a high-multiple locking of the TCK, TMS, TDI, TDO, and TRST signal levels is completed, thereby realizing wireless transmission conversion, wherein TDI, TMS, TCK, and TRST are adapter output signals, and TDO is a feedback signal of the target device.

[0014] Preferably, the JATG interface signal wireless transparent transmission A-end component is connected to the adapter, completes the reception of the four signals TDI, TMS, TCK and TRST and converts them into wireless data and sends them to the B-end, and at the same time, wirelessly receives the feedback data sent by the B-end and converts them into TDO signals and outputs them to the adapter;

[0015] The JATG interface signal wireless transparent transmission B-end component is connected to the target device, receives the data sent by the A-end and converts it into four signal timing signals of TDI, TMS, TCK and TRST and outputs it to the target device. At the same time, it receives the TDO signal fed back by the target device and converts it into wireless data and sends it to the A-end.

[0016] The wireless connection system for JATG debugging of a digital circuit provided by the present invention comprises:

[0017] Module M1: The wireless connection is realized by using JATG interface signal wireless transparent transmission between the A-end and B-end components. The A-end component is connected to the adapter through the JATG interface cable, and the B-end component is connected to the JATG interface of the target device. The A-end component and the B-end component use WIFI signals for data transmission; the adapter is connected to the debugging computer through a USB data cable and communicates with the target device through wireless signals;

[0018] Module M2: Set the multi-position DIP switch to set a unique matching address for each B-end component;

[0019] Module M3: After power-on, the A-end component is controlled to wirelessly match and connect with the corresponding B-end component through the DIP switch or USB serial port command. After the wireless connection is completed, the IDE software interface is used to perform online debugging, testing and program update of the target device.

[0020] Preferably, the A-end and B-end components include a single-chip control circuit, a wireless transparent transmission circuit and a power supply circuit, which are used to construct a small circuit module, realize the wireless transmission of JATG interface signals, and configure the pairing address by setting a multi-bit DIP switch to support node-to-point connection; the single-chip control circuit, the wireless transparent transmission circuit and the power supply circuit are connected in pairs;

[0021] The single-chip control circuit adopts a small-volume single-chip microcomputer circuit, which is used to initialize the wireless transmission circuit, read the data interface and perform transmission control; the wireless transparent transmission circuit adopts a WIFI module for wireless node pairing and data transmission and reception; the power supply circuit is responsible for converting the working voltage and selecting the reference voltage according to the requirements of the JATG debugger.

[0022] Preferably, the wireless transmission distance is controlled. Under the preset data transmission rate, an integrated wireless transmission module with an integrated antenna is used. The TCK, TMS, TDI, TDO, and TRST signals are directly connected to the EMCA data input and output interface of the wireless transparent transmission circuit according to the input and output relationship between the A and B ends. The single-chip control circuit provides a data input and output interface enable signal for the wireless transparent transmission circuit. The enable signal frequency is greater than 2 times the TCK clock frequency, and a high-multiple locking of the TCK, TMS, TDI, TDO, and TRST signal levels is completed, thereby realizing wireless transmission conversion, wherein TDI, TMS, TCK, and TRST are adapter output signals, and TDO is a feedback signal of the target device.

[0023] Preferably, the JATG interface signal wireless transparent transmission A-end component is connected to the adapter, completes the reception of the four signals TDI, TMS, TCK and TRST and converts them into wireless data and sends them to the B-end, and at the same time, wirelessly receives the feedback data sent by the B-end and converts them into TDO signals and outputs them to the adapter;

[0024] The JATG interface signal wireless transparent transmission B-end component is connected to the target device, receives the data sent by the A-end and converts it into four signal timing signals of TDI, TMS, TCK and TRST and outputs it to the target device. At the same time, it receives the TDO signal fed back by the target device and converts it into wireless data and sends it to the A-end.

[0025] According to the computer-readable storage medium storing a computer program provided by the present invention, when the computer program is executed by a processor, the steps of the wireless connection method for JATG debugging of a digital circuit are implemented.

[0026] The electronic device provided according to the present invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the wireless connection method for JATG debugging of a digital circuit are implemented.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) The present invention applies wireless transmission technology and single-chip microcomputer control technology, adopts a standardized JATG connection interface, and completes the wireless design of the JATG interface signal transmission line. The difference between the solution and the dedicated JATG debugging adapter is that there is no need to consider the firmware driver problem of the target hardware, and it can adapt to most JATG debugging scenarios. The wireless JATG debugging connection method is more versatile;

[0029] (2) The present invention is simple to connect and build, and can be dismantled after debugging is complete. The dismantling has no impact on the original system. It is suitable for integrated debugging and testing during the development process of the towed linear array, and online testing and program updating of related digital circuits after the array is formed. It can improve the efficiency of integrated debugging of the towed linear array, and can effectively avoid the problems of equipment debugging cost, quality, insufficient test verification, etc. caused by repeated disassembly during the integrated debugging of the towed linear array;

[0030] (3) The present invention realizes wireless connection for JATG debugging without considering the compatibility issues between the target device and the IDE integrated development software, and has better applicability and versatility. Through this solution, without replacing the existing adapter, the wireless connection for JATG debugging can be realized by adding the JATG interface signal non-transparent transmission A and B end modules in the present invention, and the debugging process can be connected with the wired connection method without distinction, thereby reducing the workload of debugging designers. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0032] Figure 1 This is a schematic diagram of wireless JATG debugging connection for debugging a towed linear array according to the present invention;

[0033] Figure 2 This is a comparison diagram before and after the JATG debugging improvement of the present invention;

[0034] Figure 3a and Figure 3b They are respectively the principle block diagrams of the A and B end circuits for wireless transparent transmission of JATG interface signals of the present invention;

[0035] Figure 4a and Figure 4b They are respectively schematic diagrams of the functional signal interfaces of the A and B ends of the JATG interface signal wireless transparent transmission of the present invention;

[0036] Figure 5 This is a working diagram of the wireless transparent transmission of JATG interface signals between A and B ends of the present invention;

[0037] Figure 6 An integrated debugging embodiment of a towed line array using the present invention is provided. DETAILED DESCRIPTION

[0038] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0039] Example

[0040] The invention provides a wireless connection method for JATG debugging of related digital circuits after a towed linear array is formed.

[0041] The wireless connection method can wirelessly connect the relevant digital circuits in the towed linear array without removing the sheath of the towed linear array, carry out JATG debugging and testing, and improve the debugging and testing efficiency of the digital circuits related to the towed linear array. The wireless connection method can carry out debugging and testing without destroying the working environment of the digital circuits related to the towed linear array, making the debugging and testing verification of the digital circuits related to the towed linear array closer to the actual working environment.

[0042] The adapter of the present invention is connected to the debugging computer through a USB data cable, and the adapter and the target device transmit data through wireless signals. The wireless JATG debugging connection method provided is independent of the target device hardware and IDE development software, and the wireless JATG debugging connection method is more versatile. The JATG debugging process and effect of the digital circuit related to the towed linear array device are consistent with the wired connection JATG debugging method.

[0043] The present invention designs JATG interface signal wireless transparent transmission A and B end components to complete wireless connection, replacing the physical connection between the JTAG adapter and the target device. The A end is used to connect with the JATG interface of the debug adapter, and the B end is used to connect with the JATG interface of the target device. The A and B ends use wireless WIFI signals for transmission connection.

[0044] The present invention is not only applicable to the integrated debugging of towed linear arrays, but also applicable to the integrated debugging of short-distance, non-electromagnetic shielding equipment.

[0045] The present invention uses a standard JATG debugging method. After the equipment is finalized and debugged, the B-end component of the equipment can be removed without affecting the function, performance and use of the equipment.

[0046] The present invention provides a remote non-contact debugging method suitable for debugging a towed linear array, which solves the problems of difficulty in online debugging and connection of related circuits after the towed linear array is formed, complex procedures, low efficiency, insufficient circuit working environment change test verification, and poor versatility and adaptability of a dedicated wireless JATG debugging adapter that is not suitable for integrated installation of the towed linear array. Figure 1The present invention is a schematic diagram of the wireless JATG debugging connection for debugging the towed line array. The debugging computer is connected to the JATG adapter via a USB data cable to realize the identification connection of the adapter, the adapter is connected to the JATG interface signal wireless transparent transmission A-end component via a standard JATG cable, the JATG interface signal wireless transparent transmission A-end component is reliably connected to the JATG interface signal wireless transparent transmission B-end component via wireless signals, and the JATG interface signal wireless transparent transmission B-end component is connected to the target device towed line array via a standard JATG cable, thereby realizing the wireless JATG debugging connection for debugging the towed line array.

[0047] Usually, one end of the JATG debug adapter is connected to the debug computer via a USB data cable, and the other end is physically connected to the target hardware circuit via a flat cable, thereby achieving two-way data transmission between the debug computer and the target hardware. This connection method requires cables to connect, which is suitable for short-distance single-board debugging. It cannot meet the application scenarios with remote non-contact debugging, detection, and update requirements. In view of the connection relationship between the traditional JATG debug adapter, debug computer, and target device, the connection line between the adapter and the target device is improved to wireless. Figure 2 This is a comparison chart before and after the JATG debugging improvement of the present invention. Referring to the existing standard wired JATG connection method, the connection cable between the adapter and the target device is improved to wireless, completing the wireless design and application of the JATG interface signal transmission line, and realizing the wireless JATG debugging connection between the debugging computer and the target device.

[0048] The main working principle of the present invention. Design the two functional components of the JATG interface signal wireless transparent transmission A and B ends, and connect the five basic signal lines for transmission between the adapter and the target device: TDI (Test Data Input) input test data, TDO (Test Data Output) output test results, TMS (Test Mode Select) startup mode selection, TCK (TestClock) clock signal, and optional TRST test reset signal for wireless transparent transmission. Figure 3 is a block diagram of the circuit principle of the JATG interface signal wireless transparent transmission A and B ends of the present invention. Apply wireless transmission technology, single-chip control technology and JATG debugging technology, connect the five basic signal lines for transmission between the adapter and the target device: TDI, TDO, TMS, TCK and TRST signals, and perform wireless transparent transmission. The single-chip control circuit adopts a small-volume single-chip circuit (STM32F103) to complete the initialization setting of the wireless transmission circuit, the data interface reading control function and other transmission controls. The wireless transparent transmission circuit adopts a WIFI module (ESP32-S3-N16R8 module) to complete the wireless node pairing and data wireless transceiver functions. The power supply circuit completes the module working voltage conversion, thereby realizing the wireless transmission conversion function of the five timing signals TDI, TDO, TMS, TCK and TRST, and selecting the reference voltage input and output voltage values ​​through relay control according to the commonly used JATG debugger reference voltage requirements.

[0049] Fig. 4 is a schematic diagram of the functional signal interface of the A and B ends of the JATG interface signal wireless transparent transmission of the present invention. According to the JATG signal interface standard, TDI, TMS, TCK and TRST are adapter output signals, and TDO is the target device feedback signal. The A-end component of the JATG interface signal wireless transparent transmission is connected to the adapter, completes the reception of the four signals TDI, TMS, TCK and TRST and converts them into wireless data and sends them to the B end. At the same time, the feedback data sent by the B end is wirelessly received and converted into a TDO signal and output to the adapter. The B-end component of the JATG interface signal wireless transparent transmission is connected to the target device, receives the data sent by the A end and converts it into the four signal timing signals of TDI, TMS, TCK and TRST and outputs them to the target device. At the same time, the TDO signal fed back by the target device is received and converted into wireless data and sent to the A end.

[0050] The two dedicated functional components at the A and B ends are constructed into a small circuit module using a single-chip control circuit, a wireless transparent transmission circuit, and a power supply circuit to realize the wireless transmission function of the JATG interface signal line. The pairing address is set by setting a multi-bit dip switch to achieve node-to-point connection. The A end is connected to the adapter and the B end is connected to the target device. The reference level of the input and output signals can be set to adapt to application requirements with different reference levels.

[0051] The single-chip control circuit uses a small-volume single-chip microcomputer circuit to complete the initialization setting of the wireless transmission circuit, the data interface reading control function and other transmission controls. The wireless transparent transmission circuit uses a WIFI module to complete the wireless node pairing and wireless data transmission and reception functions. The power supply circuit completes the module working voltage conversion, and selects the reference voltage input and output voltage values ​​through relay control according to the commonly used JATG debugger reference voltage requirements. To control the wireless transmission distance, while ensuring a certain data transmission rate, the wireless transmission module uses an integrated wireless transmission module with an integrated antenna. The TCK, TMS, TDI, TDO, and TRST signals are directly connected to the EMCA data input and output interface of the wireless transmission circuit according to the input and output relationship of the A and B ends. The single-chip control circuit provides a data input and output interface enable signal for the wireless transparent transmission circuit. The enable signal frequency is greater than 2 times the TCK clock frequency, completing the high-multiple locking of the TCK, TMS, TDI, TDO, and TRST signal levels, thereby realizing wireless transmission conversion. Figure 5 The following is a flowchart of the wireless transparent transmission of the JATG interface signal to the A and B ends of the present invention. After the single-chip microcomputer program completes the local power-on initialization, the A and B ends and the related matching settings are identified according to the local dial settings. The A-end component is connected to the debugging computer via a USB data cable, and the wireless pairing connection with the B-end node is completed through serial port command control, and the test data is used to verify the wireless data transmission. After a reliable connection is established, the timing signal conversion process is entered, and the program controls the data input and output interface enable signal. The enable signal frequency is greater than 2 times the TCK clock frequency, and the TCK, TMS, TDI, TDO, and TRST signal levels are locked at a high multiple and converted into wireless data for wireless transmission.

[0052] In order to be suitable for more integrated debugging of dragged linear arrays, full consideration is given to the debugging needs of several conventional (drag linear array diameter range φ36mm~φ89mm) sizes of dragged linear arrays, and circuit miniaturization design is carried out to control the circuit scale size within the space of 25mm*40mm circuit layout, combined with special application scenarios of dragged linear array debugging.

[0053] Figure 6 To use the towed linear array integrated debugging embodiment of the present invention, the debugging is carried out according to the following steps.

[0054] Step 1: Consider the integrated test requirements when designing the towed linear array. Add a JATG interface signal wireless transparent transmission B-end component to the target functional module that needs online debugging and testing in the array segment, connect it to the JATG debugging interface of the target functional module, select a suitable reference voltage according to the reference voltage requirements of the target functional module, and set a unique matching address for the B-end component by setting a multi-bit DIP switch;

[0055] Step 2: The A-end component selects a suitable reference voltage according to the adapter reference voltage requirements, connects to the adapter using a dedicated JATG interface cable, and the debugging computer and adapter are connected via a USB transmission cable for normal recognition and use;

[0056] Step 3: Power on the debugging system, control the A-end component through the DIP switch or USB serial port command to achieve wireless matching connection with the B-end component of the corresponding target functional module;

[0057] Step 4: After the A and B end components have completed reliable wireless connection, refer to the JATG wired connection debugging method of the prior art, and operate the device development IDE software interface to perform online debugging, testing, program update and other operations on the target functional module;

[0058] Step 5: Repeat steps 2 to 4 according to different target functional modules and corresponding adapter debugging requirements to complete the wireless JATG debugging connection under different requirements.

[0059] In the embodiment, the drag line array integrates two target functional modules that need online debugging and testing. Each target functional module is installed with a JATG interface signal wireless transparent transmission B-end component nearby, and a unique matching address is set for the B-end component by setting a multi-position dial switch. In order to verify the universality of the wireless JTAG debugging connection method of the present invention, the JATG debugging target devices of the two functional modules are different. The target device of module 1 is the FPGA device of Xilinx Company, and the JATG adapter used is the XILINX Platform Cable USB II downloader. The target device of module 2 is the single-chip device, and the JATG adapter used is the JLINK V9 ARM downloader. The debugging test process established by testing the wireless JTAG debugging connection through the embodiment is consistent with the effect of the adapter directly connecting to the target device.

[0060] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0061] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A wireless connection method for JATG debugging of digital circuits, characterized in that: include: Step 1: Use JATG interface signal to wirelessly transmit the two components of end A and end B to achieve wireless connection, where the end A component is connected to the adapter through the JATG interface cable, and the end B component is connected to the JATG interface of the target device. The A-end component and the end B component use WIFI signals for data transmission; the adapter is connected to the debugging computer through a USB data cable and communicates with the target device through wireless signals; Step 2: Set the multi-position DIP switch to set a unique matching address for each B-end component; Step 3: After power-on, control the A-end component to wirelessly match and connect with the corresponding B-end component through the DIP switch or USB serial port command. After the wireless connection is completed, use the IDE software interface to perform online debugging, testing and program update on the target device.

2. The wireless connection method for JATG debugging of a digital circuit according to claim 1, characterized in that: The A-end and B-end components include a single-chip control circuit, a wireless transparent transmission circuit and a power supply circuit, which are used to construct a small circuit module, realize the wireless transmission of JATG interface signals, and configure the pairing address by setting a multi-bit DIP switch to support node-to-point connection; the single-chip control circuit, the wireless transparent transmission circuit and the power supply circuit are connected in pairs; The single-chip control circuit adopts a small-volume single-chip microcomputer circuit, which is used to initialize the wireless transmission circuit, read the data interface and perform transmission control; the wireless transparent transmission circuit adopts a WIFI module for wireless node pairing and data transmission and reception; the power supply circuit is responsible for converting the working voltage and selecting the reference voltage according to the requirements of the JATG debugger.

3. The wireless connection method for JATG debugging of a digital circuit according to claim 2, characterized in that: To control the wireless transmission distance, under the preset data transmission rate, an integrated wireless transmission module with an integrated antenna is used. The TCK, TMS, TDI, TDO, and TRST signals are directly connected to the EMCA data input and output interface of the wireless transparent transmission circuit according to the input and output relationship of the A and B ends. The single-chip control circuit provides a data input and output interface enable signal for the wireless transparent transmission circuit. The enable signal frequency is greater than 2 times the TCK clock frequency, and the high-multiple locking of the TCK, TMS, TDI, TDO, and TRST signal levels is completed, thereby realizing wireless transmission conversion. Among them, TDI, TMS, TCK, and TRST are adapter output signals, and TDO is the feedback signal of the target device.

4. The wireless connection method for JATG debugging of a digital circuit according to claim 3, characterized in that: The JATG interface signal wireless transparent transmission A-end component is connected to the adapter, completes the reception of four signals TDI, TMS, TCK and TRST and converts them into wireless data and sends them to the B-end. At the same time, the feedback data sent by the B-end is wirelessly received and converted into TDO signal and output to the adapter; The JATG interface signal wireless transparent transmission B-end component is connected to the target device, receives the data sent by the A-end and converts it into four signal timing signals of TDI, TMS, TCK and TRST and outputs it to the target device. At the same time, it receives the TDO signal fed back by the target device and converts it into wireless data and sends it to the A-end.

5. A wireless connection system for JATG debugging of digital circuits, characterized in that: include: Module M1: The wireless connection is realized by using JATG interface signal wireless transparent transmission between the A-end and B-end components. The A-end component is connected to the adapter through the JATG interface cable, and the B-end component is connected to the JATG interface of the target device. The A-end component and the B-end component use WIFI signals for data transmission; the adapter is connected to the debugging computer through a USB data cable and communicates with the target device through wireless signals; Module M2: Set the multi-position DIP switch to set a unique matching address for each B-end component; Module M3: After power-on, the A-end component is controlled to wirelessly match and connect with the corresponding B-end component through the DIP switch or USB serial port command. After the wireless connection is completed, the IDE software interface is used to perform online debugging, testing and program update of the target device.

6. The wireless connection system for JATG debugging of digital circuits according to claim 5, characterized in that: The A-end and B-end components include a single-chip control circuit, a wireless transparent transmission circuit and a power supply circuit, which are used to construct a small circuit module, realize the wireless transmission of JATG interface signals, and configure the pairing address by setting a multi-bit DIP switch to support node-to-point connection; the single-chip control circuit, the wireless transparent transmission circuit and the power supply circuit are connected in pairs; The single-chip control circuit adopts a small-volume single-chip microcomputer circuit, which is used to initialize the wireless transmission circuit, read the data interface and perform transmission control; the wireless transparent transmission circuit adopts a WIFI module for wireless node pairing and data transmission and reception; the power supply circuit is responsible for converting the working voltage and selecting the reference voltage according to the requirements of the JATG debugger.

7. The wireless connection system for JATG debugging of digital circuits according to claim 6, characterized in that: To control the wireless transmission distance, under the preset data transmission rate, an integrated wireless transmission module with an integrated antenna is used. The TCK, TMS, TDI, TDO, and TRST signals are directly connected to the EMCA data input and output interface of the wireless transparent transmission circuit according to the input and output relationship of the A and B ends. The single-chip control circuit provides a data input and output interface enable signal for the wireless transparent transmission circuit. The enable signal frequency is greater than 2 times the TCK clock frequency, and the high-multiple locking of the TCK, TMS, TDI, TDO, and TRST signal levels is completed, thereby realizing wireless transmission conversion. Among them, TDI, TMS, TCK, and TRST are adapter output signals, and TDO is the feedback signal of the target device.

8. The wireless connection system for JATG debugging of digital circuits according to claim 7, characterized in that: The JATG interface signal wireless transparent transmission A-end component is connected to the adapter, completes the reception of four signals TDI, TMS, TCK and TRST and converts them into wireless data and sends them to the B-end. At the same time, the feedback data sent by the B-end is wirelessly received and converted into TDO signal and output to the adapter; The JATG interface signal wireless transparent transmission B-end component is connected to the target device, receives the data sent by the A-end and converts it into four signal timing signals of TDI, TMS, TCK and TRST and outputs it to the target device. At the same time, it receives the TDO signal fed back by the target device and converts it into wireless data and sends it to the A-end.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the wireless connection method for JATG debugging of a digital circuit according to any one of claims 1 to 4 are implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of the wireless connection method for JATG debugging of a digital circuit according to any one of claims 1 to 4 are implemented.

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