Display panel and display device

Abstract

A display panel and a display device are provided. The display panel comprises a substrate, a circuit pattern layer, a light-emitting pattern layer, and a plurality of transparent conductive layers. The transparent conductive layers are located between the circuit pattern layer and the light-emitting pattern layer and comprise a plurality of conductive lines of a first type and a plurality of conductive lines of a second type. An orthographic projection of a portion of the conductive line of the first type extending along a first direction on the substrate overlaps with an orthographic projection of a shield electrode (60) on the substrate, and an orthographic projection of a portion of the conductive line of the second type extending along the first direction on the substrate does not overlap with the orthographic projection of the shield electrode (60) on the substrate.At least one first light-emitting means of a first type is connected to at least one first pixel driver circuit (QD1) via at least one conductive line of a first type, and at least one first light-emitting means of a second type is connected to at least one first pixel driver circuit (QD1) via at least one conductive line of the second type. The first light-emitting means of the first type is configured to emit a first colored light, and the first light-emitting means of the second type is configured to emit a second colored light, the second colored light being different from the first colored light.

Description

FIELD OF TECHNOLOGYEmbodiments of the present disclosure relate to the field of display technologies, and more particularly, to a display panel and a display device, but are not limited thereto.PRIOR ARTAn organic light emitting diode (OLED) and a quantum dot light emitting diode (QLED) are active light emitting display means and have advantages of self-lighting, a wide viewing angle, a high contrast ratio, a low power consumption, an extremely high response speed, a low weight and thickness, flexibility and low cost, etc. An under-screen camera is a new-fire technology that is proposed to increase the screen-to-body ratio of a display device.SUMMARYThe following is a summary of the subject matter described in detail herein. The summary is not intended to limit the scope of the claims.In one aspect, an embodiment of the present disclosure provides a display panel including: a substrate, a circuit pattern layer and a light emitting pattern layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit pattern layer and the light emitting pattern layer; wherein, the substrate comprises: a first display area and a second display area, the second display area being disposed on at least one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; the circuit pattern layer comprises: a first gate signal line located in the second display area, a constant voltage line, a plurality of shield electrodes, and a plurality of pixel circuits, the pixel circuit comprising a driving transistor comprising a gate electrode, the plurality of pixel circuits comprising a plurality of first pixel driving circuits; the first gate signal line being connected to the gate electrode of the driving transistor; the constant voltage line being configured to supply a first constant voltage to the plurality of pixel circuits; wherein the shield electrode is connected to the constant voltage line and an orthographic projection of the first gate signal line on the substrate falls within an orthographic projection of the shield electrode on the substrate; the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines include: a plurality of conductive lines of a first type and a plurality of conductive lines of a second type, wherein an orthographic projection of a part of the conductive line of the first type extending along a first direction on the substrate overlaps with an orthographic projection of at least one of the plurality of shield electrodes on the substrate, and an orthographic projection of a part of the conductive line of the second type extending along the first direction on the substrate does not overlap with an orthographic projection of the plurality of shield electrodes on the substrate; the light emitting structure layer comprises: a plurality of first light emitting means arranged in the first display area, wherein the plurality of first light emitting means comprise a plurality of first light emitting means of a first type and a plurality of first light emitting means of a second type, wherein at least one of the plurality of first light emitting means of the first type is connected to at least one of the plurality of first pixel driving circuits via at least one of the plurality of first type conductive lines, wherein at least one of the plurality of first light emitting means of the second type is connected to at least one of the plurality of first pixel driving circuits via at least one of the plurality of second type conductive lines, wherein the first pixel driving circuit is configured to drive the first light emitting means to emit light, wherein the first light emitting means of the first type is configured to emit light, emitting a first color light, and wherein the first light emitting means of the second type is configured to emit a second color light, wherein the second color light is different from the first color light.In another aspect, an embodiment of the present disclosure further provides a display device including: the display panel described in the above embodiment.Other features and advantages of the present disclosure will be set forth in the description which follows, and in addition, will be set forth in part in the description or may be learned by practice of the present disclosure. Other advantages of the present disclosure may be achieved and obtained by the solutions described in the specification and drawings.Other aspects will become apparent upon reading and understanding the accompanying drawings and the detailed description.BRIEF DESCRIPTION OF THE FIGURESThe drawings are for understanding the technical solutions of the present disclosure, form a part of the description, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, but do not represent limitations of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the drawings do not reflect the true relationship and are only for schematically describing the content of the present disclosure. FIG. 1 is a schematic diagram of a structure of a display panel in an embodiment of the present disclosure; FIG. 2 is a schematic plan view of a display panel in an embodiment of the present disclosure; FIG. 3 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure; FIG. 4 is a first partial schematic illustration of a display panel in an embodiment of the present disclosure; FIG. 5 is a schematic illustration of a conductive line passing through a shield electrode in a first display area in some technologies; FIG. 6A is a second partial schematic illustration of a display panel in an embodiment of the present disclosure; FIG. 6B is a third partial schematic illustration of a display panel in an embodiment of the present disclosure; FIG. 6C is a fourth partial schematic illustration of a display panel in an embodiment of the present disclosure; FIG. 7 is a schematic illustration of a first connection between a first light emitting means and a first pixel driver circuit in an exemplary embodiment of the present disclosure; FIG. 8 is a schematic diagram of connection of a first transparent conductive line of a first transparent conductive layer in FIG. 7 ; FIG. 9 is a schematic diagram of connection of a second transparent conductive line of a second transparent conductive layer in FIG. 7 ; FIG. 10 is a schematic diagram of connection of a third transparent conductive line of a third transparent conductive layer in FIG. 7 ; FIG. 11 is a schematic diagram of connection of a metal conductive line of a metal conductive layer in FIG. 7 ; FIG. 12 is a schematic illustration of a second connection between a first light emitting means and a first pixel driver circuit in an exemplary embodiment of the present disclosure; FIG. 13 is a schematic illustration of a third connection between a first light emitting means and a first pixel driver circuit in an exemplary embodiment of the present disclosure; FIG. 14 is a schematic illustration of an embodiment of the present disclosure after forming a semiconductor layer; FIG. 15A is a schematic illustration of an embodiment of the present disclosure after forming a first conductive layer; FIG. 15B is a schematic plan view of the first conductive layer in FIG. 15A ; FIG. 16A is a schematic illustration of an embodiment of the present disclosure after forming a second conductive layer; FIG. 16B is a schematic plan view of the second conductive layer in FIG. 16A ; FIG. 17 is a schematic illustration of an embodiment of the present disclosure after forming a fourth insulation layer; FIG. 18A is a schematic illustration of an embodiment of the present disclosure after formation of a third conductive layer; FIG. 18B is a schematic plan view of the third conductive layer in FIG. 18A ; FIG. 19 is a schematic illustration of an embodiment of the present disclosure after forming a fifth insulation layer; FIG. 20A is a schematic illustration of an embodiment of the present disclosure after forming a fourth conductive layer; FIG. 20B is a schematic plan view of the fourth conductive layer in FIG. 20A ; FIG. 21A is a schematic illustration of an embodiment of the present disclosure after forming a first transparent conductive layer; FIG. 21B is a schematic plan view of the first transparent conductive layer in FIG. 21A ; FIG. 22A is a schematic illustration of an embodiment of the present disclosure after forming a second transparent conductive layer; FIG. 22B is a schematic plan view of the second transparent conductive layer in FIG. 22A ; FIG. 23A is a schematic illustration of an embodiment of the present disclosure after formation of a third transparent conductive layer; FIG. 23B is a schematic plan view of the third transparent conductive layer in FIG. 23A ; FIG. 24A is a first schematic illustration of an embodiment of the present disclosure after formation of an anode layer; FIG. 24B is a schematic plan view of the anode layer in FIG. 23A ; FIG. 24C is a second schematic illustration of an embodiment of the present disclosure after formation of an anode layer; FIG. 25 is a schematic illustration of an embodiment of the present disclosure after forming a pixel definition layer.DETAILED DESCRIPTION OF THE DISCLOSUREMany embodiments are described herein, but the description is exemplary and not limiting, and there may be more embodiments and implementation solutions within the scope included in the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in example embodiments, many other combinations of the disclosed features are possible. Unless expressly limited, each feature or element of the embodiment may be used in combination with or replace each other feature or element in each other embodiment.In the drawings, the size of one or more constituent elements, the thickness of a layer or region is sometimes exaggerated for clarity. Therefore, an embodiment of the present disclosure is not necessarily limited to the size, and a shape and a size of one or more parts in the drawings do not reflect the true ratio. Moreover, the drawings schematically show ideal examples, and an embodiment of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.Ordinal numbers such as "first", "second", and "third" in the specification are used to avoid confusion of constituent elements, but not to set a quantity limitation. In the present disclosure, "plurality" means two or more.In the specification, for convenience, terms indicating the orientation or positional relationships are used, such as "center", "above", "below", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", and "outside", to illustrate the positional relationships between the constituent elements with reference to the drawings, and are merely for convenience of explanation of the description and simplification of the description, rather than indicating or implying that a device or element to be referred to has a certain orientation and needs to be constructed and operated in the certain orientation. Therefore, they cannot be understood as limitations of the present disclosure. The positional relationships between the constituent elements are changed accordingly depending on the direction in which the constituent elements are described. Therefore, appropriate substitutions may be made depending on the situation without being limited to the formulations described in the specification.In the specification, the terms "mount", "connect" and "connect" are to be understood in the broadest sense unless expressly stated and defined otherwise. For example, it may be a fixed connection, a detachable connection or an integrated connection; it may be a mechanical connection or a connection; it may be a direct connection, an indirect connection via an intermediate element or a communication within two elements. Those skilled in the art can understand the meaning of the above-mentioned terms in the present disclosure depending on the situation.In the specification, "electrical connection" includes the case where constituent elements are connected to each other by an element having a certain electrical function. The "member having a certain electrical function" is not particularly limited as long as electrical signals can be transmitted between the connected components. Examples of an "element having a certain electrical function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having a plurality of functions, etc.In the specification, a transistor refers to an element having at least three terminals, i.e., a gate electrode (gate electrode or control electrode), a drain electrode (drain electrode terminal, drain region or drain), and a source electrode (source electrode terminal, source region or source). A transistor has a channel region between a drain electrode and a source electrode, and a current can flow through the drain electrode, the channel region, and the source electrode. Note that, in the description, the channel region refers to a region through which the current mainly flows.In the description, in order to distinguish two electrodes of a transistor other than a gate electrode (gate electrode or control electrode), one of the two electrodes is directly referred to as a first electrode while the other is referred to as a second electrode. The first electrode may be a drain electrode and the second electrode may be a source electrode. Or, the first electrode may be a source electrode and the second electrode may be a drain electrode. In cases where transistors having opposite polarity are used, the current direction changes during operation of a circuit, or the like, the functions of the "source electrode" and the "drain electrode" are sometimes interchangeable. Therefore, the "source electrode" and the "drain electrode" are interchangeable in the description.The transistors in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (FET), or other devices having the same characteristics. For example, a thin film transistor used in the embodiments of the present disclosure may be, but is not limited to, an oxide transistor or a low temperature polysilicon (TFT, LTPS TFT), or the like. Here, no limitations are imposed on the embodiments of the present disclosure.In the specification, the term "parallel" refers to a state in which an angle formed by two straight lines is -10° or more than -10° and 10° or less than 10°, and thus also includes a state in which the angle is -5° or more than -5° and 5° or less than 5°. Moreover, "perpendicular" refers to a state in which an angle formed by two lines is 80° or more than 80° and 100° or less than 100°, and thus also includes a state in which the angle is 85° or more than 85° and 95° or less than 95°.In the present disclosure, "about", "about", and "approximately" refer to the case that a boundary is not defined as being so strict and a process and measurement error within a range is allowed. For example, "substantially equal" in the present disclosure refers to a case where the values deviate from each other by less than 10%.Triangle, rectangle, trapezoid, pentagonal, hexagon, or the like are not strictly defined in the specification, and may be approximately triangle, rectangle, trapezoid, pentagonal, hexagon, or the like. There may be a small tolerance deformation, a taper, an arcuate edge, a deformation, etc.In the embodiments of the present disclosure, a first direction X may refer to an extending direction of a gate line in a display area or a horizontal direction, a second direction Y may refer to an extending direction of a data line in the display area or a vertical direction, and a third direction Z may refer to a direction perpendicular to a plane of a display panel or a thickness direction of a display panel, etc. Here, the first direction X and the second direction Y may be perpendicular to each other, and the first direction X and the third direction Z may be perpendicular to each other.As display technology has evolved, products with full screens or narrow edges have gradually evolved to the trend of development for display products having a large screen to body ratio and extremely narrow edges. In the case of products such as intelligent terminals, sensors such as camera sensors, fingerprint sensors or the like are generally installed. To increase the screen-to-body ratio, full-screen or narrow-edge products typically employ Full Display with Camera (FDC) technology or under-screen fingerprint technology, and sensors such as cameras are housed in the area of camera under the Under Display Camera (UDC) of the display panel. The area of camera under the screen has not only a certain light transmittance but also a display function, so that the area "full display in camera" (FDC) is achieved.FIG. 1 is a schematic diagram of a structure of a display panel. As shown in FIG. 1, a display area AA of the display panel on a plane parallel to the display panel may include a first display area AA 1 and a second display area AA 2, and the second display area AA 2 may be disposed on at least one side of the first display area AA 1. For example, the second display area AA 2 may at least partially surround the first display area AA 1. The second display area AA 2 may include, for example, a transition display area AAG adjacent to the first display area AA 1. For example, the position of the first display area AA 1 may correspond to the position of the sensor and be configured to display an image and transmit light, and the transmitted light is received by the sensor. The first display area AA 1 may also be referred to as a sensor corresponding area, a camera under-screen display area, a light transmissive display area, or the like. The second display area AA 2 is configured to display an image, for example, and may also be referred to as a normal resolution display area, a normal subpixel area, a low transmittance display area, or the like. For example, the transition display area AAG is configured to display an image and configure signal wirings connected to signal lines in the light transmissive display area to take out these signal lines, and the transition display area AAG may also be referred to as a dummy subpixel area.In an exemplary embodiment, the light transmittance of the first display area AA 1 is higher than the light transmittance of the second display area AA 2. The light transmittance of the first display area AA 1 is higher than the light transmittance of the transition display area AAG. A "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, and is a percentage of the luminous flux passing through a transparent or semitransparent body relative to its incident luminous flux. Since the position of the first display area AA 1 may correspond to the position of the sensor, an orthographic projection of the sensor on the display panel and the first display area AA 1 have an overlap area, so more light can pass through the display panel and be received by the sensor. For example, "an orthographic projection of the sensor on the display panel and the first display area AA 1 have an overlap area" may mean that a part of the orthographic projection of the sensor on the display panel is within the first display area AA 1, or the entire orthographic projection of the sensor on the display panel is within the first display area AA 1, or an orthographic projection of the light-sensitive window of the sensor on the display panel is within the first display area AA 1, etc. Here, no limitations are provided in this regard in the embodiments of the present disclosure.In an exemplary embodiment, the resolution of the first display area AA 1 and the second display area AA 2 may be the same, or the resolution of the first display area AA 1 may be lower than the resolution of the second display area AA 2. The resolution (pixel per inch, PPI) refers to the number of pixels per unit area and may also be referred to as pixel density. The higher the PPI value, the denser an image can be displayed on the display panel and the more detailed the image is.In an exemplary embodiment, the first display area AA 1 may be located at an upper position, lower position, or edge position, or the like of the display area of the display panel. For example, the first display area AA 1 may be located at the center of the upper part of the display area of the display panel, and the second display area AA 2 may surround the first display area AA 1. Alternatively, the first display area AA 1 may be located at other locations, e.g., at an upper left corner or an upper right corner of the display area of the display panel, and the second display area AA 2 may surround at least one side of the first display area AA 1 (e.g., a side, upper and lower sides, or left and right sides, etc.). In the embodiments of the present disclosure, no limitations are provided in this respect.In an exemplary embodiment, the shape of the first display area AA 1 in a plane parallel to the display panel may be one or more of the following: square, rectangle, polygon, circle, ellipse, semicircle, pentagonal, etc. For example, the shape of the display area of the display panel may be rectangular, such as a rounded rectangle, and the first display area AA 1 may be circular. In the embodiments of the present disclosure, no limitations are provided in this respect.In an exemplary embodiment, the shape of the outer contour of the transition display area AAG in a plane parallel to the display panel may be one or more of the following shapes: rectangle, polygon, circle, ellipse, and the like. In the embodiments of the present disclosure, no limitations are provided in this respect.In an exemplary embodiment, the sensors may include, but are not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, an ultrasonic sensor, a light detection and ranging (LIDAR) sensor, or a radar sensor, etc. In the embodiments of the present disclosure, no limitations are provided in this respect.In an exemplary embodiment, the first display region AA 1 may include, in a plane perpendicular to the display panel, a first circuit pattern layer disposed on a substrate and a first light emitting pattern layer disposed on a side of the first circuit pattern layer away from the substrate. The second display region AA 2 may include a second circuit pattern layer disposed on a substrate and a second light emitting pattern layer disposed on a side of the second circuit pattern layer away from the substrate.In an exemplary embodiment, the first circuit pattern layer of the first display region AA 1 includes a plurality of insulation layers stacked on top of each other, and the first circuit pattern layer may be referred to as a composite insulation layer. The first light emitting structure layer of the first display area AA 1 may include a plurality of functional sub-pixels, wherein the functional sub-pixels may include a first light emitting means sp 1, wherein the first light emitting means sp 1 may include at least a first anode, wherein the first anode of at least one functional sub-pixel is connected to at least a first pixel driving circuit QD 1 in the transition display area AAG in the second display area AA 2 via a conductive line (e.g., a transparent conductive line). The first pixel driver circuit QD1 is configured to output a corresponding current to the connected first light emitting means sp1 via the conductive line, and the first light emitting means sp1 is configured to emit light having a corresponding brightness in response to the current output from the connected pixel driver circuit.In an exemplary embodiment, the second circuit pattern layer of the second display region AA 2 may include a plurality of first pixel driving circuits QD 1 and a plurality of second pixel driving circuits QD 2, and the second circuit pattern layer may be referred to as a driving pattern layer. A region in the second display region AA 2 where the first pixel driving circuit QD 1 is provided may be referred to as a transient display region AAG. The second light emitting structure layer of the second display area AA 2 may include a plurality of normal sub-pixels, wherein the normal sub-pixel may include a second light emitting means sp 2, wherein the second light emitting means sp 2 may include at least one second anode, wherein the second anode of at least one normal sub-pixel is connected to at least one second pixel driving circuit QD 2. The second pixel driver circuit QD2 is configured to directly output a corresponding current to the connected second light emitting means sp2, and the second light emitting means sp2 is configured to emit light having a corresponding brightness in response to the current output from the connected pixel driver circuit.For example, the first light emitting means sp 1 is located in a different display area than the first pixel driving circuit QD 1 that it drives, so that the first light emitting means sp 1 may be referred to as a light emitting means without in situ driving and the first pixel driving circuit QD 1 may be referred to as a non-in situ pixel driving circuit. For example, the second light emitting means sp 2 and the second pixel driving circuit QD 2 that it drives are both located in the second display area AA 2, so that the second light emitting means sp 2 may be referred to as an in situ driving light emitting means and the second pixel driving circuit QD 2 may be referred to as an in situ pixel driving circuit.In an exemplary embodiment, the display area of the display panel may include: a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P may include: a plurality of sub-pixels. A subpixel may be a smallest portion with controllable brightness. At least one sub-pixel may comprise a light emitting means and a pixel driver circuit connected to the light emitting means, the pixel driver circuit being configured to drive the connected light emitting means to emit light.In an exemplary embodiment, the light emitting means may be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diodes (QLED), a micro LED (including a mini LED or a micro LED), and the like. For example, the light emitting means may be an OLED, and the light emitting means emits red light, green light, blue light or white light, etc. under driving by its corresponding pixel driving circuit.In an exemplary embodiment where the light emitting agent is an OLED, the light emitting agent may include an anode, a cathode, and an organic light emitting layer located between the anode and the cathode. The anode of the light emitting means may be electrically connected to the corresponding pixel driving circuit.In an exemplary embodiment, the color in which the light emitting means emits light may be determined by one skilled in the art depending on the actual application scenario. For example, at least one of the plurality of pixel units P may include three sub-pixels, which may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. As another example, at least one of the plurality of pixel units P may include four subpixels, and the four subpixels may be a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, respectively. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the shape of the light emitting means may be a rectangle, a diamond, a pentagonal, a hexagon, or the like.In an exemplary embodiment, the plurality of sub-pixels may be arranged in the pixel unit horizontally side by side, vertically side by side, in an X shape, in a cross shape, in a pyramid shape, or the like. For example, taking a pixel unit including three sub-pixels as an example, the three sub-pixels may be arranged horizontally side by side, vertically side by side, in a pyramid-like shape, or the like. For example, taking a pixel unit having four sub-pixels as an example, the four sub-pixels may be arranged horizontally side by side, vertically side by side, square or diamond, etc. As shown in FIG. 2, for example, four sub-pixels including a red sub-pixel, a blue sub-pixel, and two green sub-pixels may be arranged diamond to form an RGGB pixel array. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the arrangement of the pixel units in the first display area AA 1 and the arrangement of the pixel units in the second display area AA 2 may be the same or different. The number of subpixels included in the pixel units in the first display area AA 1 and the number of subpixels included in the pixel units in the second display area AA 2 may be the same or different. The arrangement of the subpixels included in the pixel units in the first display area AA 1 and the arrangement of the subpixels included in the pixel units in the second display area AA 2 may be the same or different. In the embodiments of the present disclosure, no limitations are provided in this respect.In an exemplary embodiment, the pixel driver circuit may have a structure of 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C.In an exemplary embodiment, the pixel driving circuit having a 7T1C structure of the present exemplary embodiment will be described as an example. FIG. 3 is an equivalent circuit diagram of the pixel driving circuit in the embodiment of the present disclosure. As illustrated in FIG. 3, the pixel driving circuit may include seven transistors (first transistor T 1 to seventh transistor T 7) and a storage capacitor Cst. The pixel driving circuit may be connected to eight signal lines (scan signal line GL, data signal line DL, first power supply line PL 1, second power supply line PL 2, light emission control line EML, first initial signal line INIT 1, second initial signal line INIT 2, first reset control line RST 1, and second reset control line RST 2). The third transistor T 3 may also be referred to as a driver transistor, the fourth transistor T 4 as a data write transistor, the second transistor T 2 as a threshold compensation transistor, the fifth transistor T 5 as a first control light emitting transistor, the sixth transistor T 6 as a second control light emitting transistor, the first transistor T 1 as a first reset transistor, and the seventh transistor T 7 as a second reset transistor.In an exemplary embodiment, transistors may be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, its turn-on voltage is a low-level voltage (e.g., 0 V, -5 V, -10 V, or other suitable voltages) and its turn-off voltage is a high-level voltage (e.g., 5 V, 10 V, or other suitable voltages). When the transistor is an N-type transistor, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages) and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).In an exemplary embodiment, the first transistor T 1 to the seventh transistor T 7 may be P-type transistors or N-type transistors. Using the same type of transistor in a pixel driver circuit can simplify the process flow, reduce the process difficulties of a display panel, and improve the product yield. In some possible implementations, the first transistor T 1 to the seventh transistor T 7 may include P-type transistors and N-type transistors.In an exemplary embodiment, the first transistor T 1 to the seventh transistor T 7 may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of a low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of an oxide thin-film transistor is made of an oxide semiconductor (oxides). A low-temperature polysilicon thin film transistor has advantages such as high mobility and rapid charge, while an oxide thin film transistor has advantage such as low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated into a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel, and the advantages of both the low-temperature polysilicon thin film transistor and the oxide thin film transistor can be utilized, thereby achieving low-frequency driving, reducing power consumption, and improving display quality.In an exemplary embodiment, as shown in FIG. 3, a display panel may include a scan signal line GL, a data signal line DL, a first power supply line PL 1, a second power supply line PL 2, a light emission control line EML, a first initial signal line INIT 1, a second initial signal line INIT 2, a first reset control line RST 1, and a second reset control line RST 2. In exemplary embodiments, the first power supply line PL 1 may be configured to supply a constant first voltage signal VDD to the pixel driving circuit, the second power supply line PL 2 may be configured to supply a constant second voltage signal VSS to the pixel driving circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan signal line GL may be configured to provide a scan signal SCAN to the pixel driving circuit, the data signal line DL may be configured to provide a data signal DATA to the pixel driving circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel driving circuit, the first reset control line RST 1 may be configured to provide a first reset control signal RESET 1 to the pixel driving circuit, and the second reset control line RST 2 may be configured to provide a second reset control signal RESET 2 to the pixel driving circuit. In an exemplary embodiment, in an n-th row pixel driving circuit, a first reset control line RST 1 may be electrically connected to a scan signal line GL of an (n-1)-th row pixel driving circuit to input a scan signal SCAN(n-1) to the first reset control line RST 1, i.e., a first reset control signal RESET 1(n) is the same as the scan signal SCAN(n-1). A second reset control line RST 2 may be electrically connected to a scan signal line GL of the n-th row pixel driving circuit to input a scan signal SCAN(n) to the second reset control line RST 2, i.e., a second reset control signal RESET 2(n) is the same as the scan signal SCAN(n). In an exemplary embodiment, the second reset control line RST 2 to which the pixel driving circuit of the n-th row is electrically connected and a first reset control line RST 1 to which a pixel driving circuit of an (n+1)-th row is electrically connected may be in an integral structure. Here, n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced to reach narrow edges of the display panel. However, no limitations are provided in this regard in the embodiment.In an exemplary embodiment, the first initial signal line INIT 1 may be configured to provide a first initial signal to the pixel driver circuit, the second initial signal line INIT 2 may be configured to provide a second initial signal to the pixel driver circuit. The first initial signal may be different from the second initial signal, for example. The first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal may be the same, and only a first initial signal line may be provided to provide the first initial signal.In an exemplary embodiment, the first power supply line PL 1 may be used as a constant voltage line to save wiring. For example, in other examples, the first initial signal line INIT 1 may also be used as a constant voltage line to save wiring. Examples of the constant voltage line are not limited to the first power supply line PL 1 and the first initial signal line INIT 1, and as long as the signal line supplying a constant voltage in the pixel circuit can be used as the constant voltage line.In an exemplary embodiment, the scan signal line GL, the light emission control line EML, the first initial signal line INIT 1, the second initial signal line INIT 2, the first reset control line RST 1, and the second reset control line RST 2 may extend in a horizontal direction, and the first power supply line PL 1, the second power supply line PL 2, and the data signal line DL may extend in a vertical direction.In an exemplary embodiment, as shown in FIG. 3, the third transistor T 3 is electrically connected to the light emitting means EL, and outputs a driving current under control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS, etc., to drive the light emitting means EL to emit light. A gate electrode of the fourth transistor T 4 is electrically connected to the scan signal line GL, a first electrode of the fourth transistor T 4 is electrically connected to the data signal line DL, and a second electrode of the fourth transistor T 4 is electrically connected to the first electrode of the third transistor T 3. A gate electrode of the second transistor T 2 is electrically connected to the scan signal line GL, a first electrode of the second transistor T 2 is electrically connected to the gate electrode of the third transistor T 3, and a second electrode of the second transistor T 2 is electrically connected to a second electrode of the third transistor T 3. A gate electrode of the fifth transistor T 5 is electrically connected to the light emission control line EML, a first electrode of the fifth transistor T 5 is electrically connected to the first power supply line PL 1, and a second electrode of the fifth transistor T 5 is electrically connected to the first electrode of the third transistor T 3. A gate electrode of a sixth transistor T 6 is electrically connected to the light emission control line EML, a first electrode of the sixth transistor T 6 is electrically connected to the second electrode of the third transistor T 3, and a second electrode of the sixth transistor T 6 is electrically connected to an anode of the light emitting means EL. A first transistor T 1 is electrically connected to the gate electrode of the third transistor T 3 and is configured to reset the gate electrode of the third transistor T 3, and a seventh transistor T 7 is electrically connected to the anode of the light emitting device EL and is configured to reset the anode of the light emitting device EL. A gate electrode of the first transistor T 1 is electrically connected to a first reset control line RST 1, a first electrode of the first transistor T 1 is electrically connected to a first initial signal line INIT 1, and a second electrode of the first transistor T 1 is electrically connected to the gate electrode of the third transistor T 3. A gate electrode of the seventh transistor T 7 is electrically connected to a second reset control line RST 2, a first electrode of the seventh transistor T 7 is electrically connected to a second initial signal line INIT 2, and a second electrode of the seventh transistor T 7 is electrically connected to the anode of the light emitting means EL. A first capacitor electrode plate of the storage capacitor Cst is electrically connected to the gate electrode of the third transistor T 3, and a second capacitor electrode plate of the storage capacitor Cst is electrically connected to the first power supply line PL 1.In an exemplary embodiment, as shown in FIG. 3, the pixel driving circuit may include a first node N 1, a second node N 2, a third node N 3, and a fourth node N 4, wherein the first node N 1 is a connection point of the storage capacitor Cst, the first transistor T 1, the third transistor T 3, and the second transistor T 2, the second node N 2 is a connection point of the fifth transistor T 5, the fourth transistor T 4, and the third transistor T 3, the third node N 3 is a connection point of the third transistor T 3, the second transistor T 2, and the sixth transistor T 6, and the fourth node N 4 is a connection point of the sixth transistor T 6, the seventh transistor T 7 and the light emitting means EL. The fourth node N 4 is an anode connection node.In an exemplary embodiment, the light emitting agent EL may be an organic electroluminescent diode (OLED) including an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.The operation process of the pixel driving circuit illustrated in FIG. 3 will be described below with reference to an example in which a plurality of transistors in the pixel driving circuit illustrated in FIG. 3 are all P-type transistors.In an exemplary embodiment, the operation process of the pixel driving circuit during an image display period may include a first stage S 1, a second stage S 2, and a third stage S 3.The first stage S 1 is referred to as a reset stage. A first reset control signal RESET 1 provided from the first reset control line RST 1 is a low level signal so that the first transistor T 1 is turned on, and a first initial signal provided from the first initial signal line INIT 1 is supplied to the first node N 1 to initialize the first node N 1 and clear an original data voltage in the storage capacitor Cst. The scan signal SCAN provided from the scan signal line GL is a high level signal, and the light emission control signal EM provided from the light emission control line EML is a high level signal that turns off the fourth transistor T 4, the second transistor T 2, the fifth transistor T 5, the sixth transistor T 6, and the seventh transistor T 7. At this stage, the light emitting means EL emits no light.The second stage S2 is referred to as a data write stage or a threshold compensation stage. A scan signal SCAN provided from the scan signal line GL is a low level signal, a first reset control signal RESET 1 provided from the first reset control line RST 1, and a light emission control signal EM provided from the light emission control line EML are both high level signals, and the data signal line DL outputs a data signal DATA. In this stage, the third transistor T3 is turned on because the first capacitor electrode plate of the storage capacitor Cst is at a low level. The scan signal SCAN is a low level signal, so that the second transistor T 2, the fourth transistor T 4, and the seventh transistor T 7 are turned on. The second transistor T 2 and the fourth transistor T 4 are turned on, so that a data voltage Vdata output from the data signal line DL is supplied to the first node N 1 via the second node N 2, the turned-on third transistor T 3, the third node N 3, and the turned-on second transistor T 2, and the storage capacitor Cst is charged with a difference between the data voltage Vdata output from the data signal line DL and a threshold voltage of the third transistor T 3. A voltage of the first capacitor electrode plate (i.e., the first node N 1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output from the data signal line DL and Vth is the threshold voltage of the third transistor T 3. The seventh transistor T 7 is turned on so that a second initial signal provided from the second initial signal line INIT 2 is supplied to the anode of the light emitting means EL to initialize (reset) the anode of the light emitting means EL and erase a voltage stored therein to complete the initialization, thereby ensuring that the light emitting means EL does not emit light. The first reset control signal RESET 1 provided from the first reset control line RST 1 is a high level signal, so that the first transistor T 1 is turned off. The light emission control signal EM provided from the light emission control signal line EML is a high level signal, so that the fifth transistor T 5 and the sixth transistor T 6 are turned off.The third stage S 3 is referred to as a light emission stage. A light emission control signal EM provided from the light emission control signal line EML is a low level signal, and a scan signal SCAN provided from the scan signal line GL and a first reset control signal RESET 1 provided from the first reset control line RST 1 are high level signals. The light emission control signal EM provided from the light emission control signal line EML is a low level signal such that the fifth transistor T 5 and the sixth transistor T 6 are turned on, and the first voltage signal VDD output from the first power supply line PL 1 supplies a driving voltage to the anode of the light emitting means EL via the turned-on fifth transistor T 5, the third transistor T 3 and the sixth transistor T 6 to drive the light emitting means EL to emit light.In a driving process of the pixel circuit, a driving current flowing through the third transistor T 3 is determined by a voltage difference between the gate electrode and the first electrode of the third transistor T 3. Since the voltage of the first node N 1 is Vdata-|Vth|, the driving current of the third transistor T 3 is as follows:Here, I is the driving current flowing through the third transistor T 3, i.e., a driving current for driving the light emitting means EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T 3, Vth is the threshold voltage of the third transistor T 3, VDATA is the data voltage output from the data signal line DL, and VDD is the first voltage signal output from the first power supply line PL 1.From the above formula, it can be seen that a current flowing through the light emitting means EL is independent of the threshold voltage of the third transistor T 3. Therefore, the pixel driving circuit according to the present embodiment can more effectively compensate for the threshold voltage of the third transistor T 3.FIG. 4 is a first partial schematic illustration of a display panel in an embodiment of the present disclosure. It is an enlarged view of the Q region in FIG. 1, illustrating the planar structure of the region near the transition display region AAG in the first display region AA 1 and the planar structure of the transition display region AAG and its vicinity in the second display region AA 2.In an exemplary embodiment, as shown in FIG. 4, the first display area AA 1 may be provided with only a first light emitting means sp 1 without providing the first pixel driving circuit QD 1 for driving the first light emitting means sp 1 so that the first display area AA 1 may display as well as transmit light. For example, the first light emitting means sp 1 may include at least one first anode, and at least one first pixel driving circuit QD 1 in the transition display area AAG in the second display area AA 2 is connected to the first anode of the at least one first light emitting means sp 1 through a conductive line L (for example, a transparent conductive line). The conductive line L may extend from the first display area AA 1 to a transition display area AAG in the second display area AA 2. In this way, by arranging the first pixel driving circuit QD 1 for driving the first light emitting agent sp 1 in the transient display region AAG in the second display region AA 2, it is possible to reduce the shielding of light by the pixel driving circuit, so that the transmission rate of the first display region AA 1 can be increased. For example, taking the first pixel driving circuit QD 1 as the pixel driving circuit of 7T 1C illustrated in FIG. 3, one terminal of the conductive line L (e.g., a transparent conductive line) may be electrically connected to the fourth node N 4 (i.e., an anode connection node) of the first pixel driving circuit QD 1, and the other terminal of the conductive line L may be electrically connected to the first anode of the first light emitting means sp 1.In an exemplary embodiment, as shown in FIG. 4, the second display area AA 2 may include a plurality of first pixel driving circuits QD 1, a plurality of second pixel driving circuits QD 2, and a plurality of second light emitting means sp 2, wherein at least one of the plurality of second pixel driving circuits QD 2 is configured to be connected to at least one second light emitting means sp 2 in the second display area AA 2. The second pixel driver circuit QD2 is configured to output a corresponding current directly to the connected second light emitting means sp2 so that the second light emitting means sp2 emits light with corresponding brightness. That is, both the second light emitting means sp 2 electrically connected to the second pixel driving circuit QD 2 and the second pixel driving circuit QD 2 may be located in the second display area AA 2, and all or a part of the second light emitting means sp 2 may be located in the second display area AA 2. For example, an orthographic projection of the at least one second pixel driver circuit QD 2 on the substrate and an orthographic projection of the at least one second light emitting agent sp 2 on the substrate may at least partially overlap.In an exemplary embodiment, as shown in FIG. 4, the transition display area AAG in the second display area AA 2 may include a plurality of first pixel driver circuits QD 1, wherein at least one of the plurality of first pixel driver circuits QD 1 may be connected to at least one first light emitting means sp 1 in the first display area AA 1 via a conductive line L, and the at least one first pixel driver circuit QD 1 is configured to output a corresponding current to the connected first light emitting means sp 1 via the conductive line L, such that the first light emitting means sp 1 emits light having a corresponding brightness. That is, the first light emitting means sp 1 electrically connected to the first pixel driving circuit QD 1 may be located in a different display region than the first pixel driving circuit QD 1. For example, it may be that an orthographic projection of the at least one first pixel driver circuit QD 1 on the substrate and an orthographic projection of the at least one first light emitting agent sp 1 on the substrate do not overlap. In an exemplary embodiment, as shown in FIG. 4, the transient display region AAG may further include a plurality of second pixel driving circuits QD 2 and a plurality of second light emitting means sp 2. At least one of the plurality of second pixel driving circuits QD 2 may be connected to at least one second light emitting means sp 2 in the transient display area AAG, and the second pixel driving circuit QD 2 is configured to directly output a corresponding current to the connected second light emitting means sp 2 such that the second light emitting means sp 2 emits light having a corresponding brightness. In an exemplary embodiment, one or more second pixel driver circuits QD 2 may be provided between adjacent first pixel driver circuits QD 1, for example, two second pixel driver circuits QD 2 may be provided between adjacent first pixel driver circuits QD 1, or, as shown in FIG. 4, four second pixel driver circuits QD 2 may be provided between adjacent first pixel driver circuits QD 1, etc. No limitations are provided in this regard in the embodiments of the present disclosure.In an exemplary embodiment, as shown in FIG. 4, the transition display region AAG may further include an invalid pixel driving circuit QD 0, which may facilitate improving uniformity of components of a plurality of film layers in the etching process and ensuring uniformity of the display panel. For example, the structure of the invalid pixel driving circuit may be substantially the same as that of the first pixel driving circuit QD 1 or the second pixel driving circuit QD 2 of the row or column in which the invalid pixel driving circuit is located, except that the invalid pixel driving circuit is not electrically connected to a light emitting means.In an exemplary embodiment, the conductive line L may be made of a transparent conductive material. For example, the transparent conductive material may be an oxide conductive material such as indium tin oxide (ITO), or the like. In the embodiments of the present disclosure, no limitations are provided in this respect.The pixel driving circuit in an exemplary embodiment of the present disclosure is a region divided according to a substrate pattern layer, and the light emitting means in the present disclosure is a region divided according to a light emitting pattern layer. For example, the position of the light emitting means and the position of the pixel driving circuit driving the light emitting means may coincide, or the position of the light emitting means and the position of the pixel driving circuit driving the light emitting means may not coincide. For example, a plurality of second light emitting means sp2 of the junction display area AAG may normally be arranged in a conventional pitch arrangement, while a part of the second pixel driving circuits QD2 of the junction display area AAG may be compactly arranged in a small pitch arrangement, thereby leaving an arrangement space for the first pixel driving circuit QD1 driving the first light emitting means sp1. Here, the position of the second light emitting means sp 2 of the transient display area AAG and the position of the second pixel driving circuit QD 2 do not match. In another example, a plurality of first light emitting means sp 1 are provided in the first display area AA 1, and the first pixel driving circuit QD 1 is provided in the transient display area AAG. Here, the position of the first light emitting means sp 1 of the first display area AA 1 and the position of the first pixel driving circuit QD 1 driving the first light emitting means sp 1 do not match.In an exemplary embodiment, in the transition display area AAG, an area where the first pixel driving circuit QD 1 is provided may be obtained by reducing the size of the second pixel driving circuit QD 2. For example, the region where the first pixel driving circuit QD 1 is provided may be obtained by reducing the size of the second pixel driving circuit QD 2 in the first direction X; alternatively, the region where the first pixel driving circuit QD 1 is provided may be obtained by reducing the size of the second pixel driving circuit QD 2 in the second direction Y; alternatively, the region where the first pixel driving circuit QD 1 is provided may be obtained by reducing the size of the second pixel driving circuit QD 2 in the first direction X and the second direction Y. In the embodiments of the present disclosure, no limitations are provided in this respect.For example, taking the obtaining of the region where the first pixel driving circuit QD 1 is provided by reducing the size of the second pixel driving circuit QD 2 in the first direction X as an example, as shown in FIG. 4, the original pixel driving circuit per a column may be compressed in the first direction X, thereby adding an arrangement space to a column of pixel driving circuits, and the space occupied by the a column of pixel driving circuits before compression and the (a+1) column of pixel driving circuits after compression may be the same, where "a" may be an integer greater than 1, for example, "a" may be 2, 3, or 4, and the like. For example, the second pixel driving circuit QD 2 and the first pixel driving circuit QD 1 may be typically arranged compressed from 2-in-1, compressed from 3-in-1, or compressed from 4-in-1 in the first direction X. 2, 3 or 4 of the second pixel driving circuits QD2 in the first direction X are compressed, leaving a position for the provision of the first pixel driving circuit QD1. Here, no limitations are imposed on the embodiments of the present disclosure. Here, the size of the second pixel driving circuit QD 2 in the first direction X may be smaller than the size of the second light emitting agent sp 2 in the first direction X.For example, taking the obtaining of the region where the first pixel driving circuit QD 1 is provided by reducing the size of the second pixel driving circuit QD 2 in the second direction Y as an example, the original pixel driving circuit of the b-line may be compressed in the second direction Y, thereby adding an arrangement space of one line of pixel driving circuits, and the space occupied by the b-line of pixel driving circuits before compression and the (b+1)-line of pixel driving circuits after compression may be the same, where "b" may be an integer greater than 1, for example, "b" may be 2, 3, or 4, and the like. Here, the size of the second pixel driving circuit QD 2 in the second direction Y may be smaller than the size of the second light emitting means sp 2 in the second direction Y.In an exemplary embodiment, since the transition display area AAG is provided not only with the first pixel driving circuit QD 1 electrically connected to the first light emitting means sp 1 but also with the second pixel driving circuit QD 2 electrically connected to the second light emitting means sp 2, the number of pixel driving circuits of the transition display area AAG may be larger than the number of the first light emitting means sp 1 of the first display area AA 1.In an exemplary embodiment, a shield electrode 60 is provided in the display panel to reduce crosstalk on the first node N 1 by the capacitance between conductive lines (e.g., ITO wirings). FIG. 5 is a schematic diagram of a conductive line passing through a shield electrode in a first display area AA 1 in some technologies. As shown in FIG. 5, the shield electrode 60 below the conductive line has an irregular shape, and the shield electrode 60 reflects light, resulting in unequal critical dimensions of a plurality of conductive lines L (1 to 7) passing through the shield electrode 60, the critical dimensions of the conductive lines passing through wider locations of the shield electrode 60 being thinner and the critical dimensions of the conductive lines passing through narrower locations of the shield electrode 60 being wider. In this way, the difference in capacitance between conductive lines of adjacent pixels in the same row will be large, resulting in the problem of uneven display (mura).As shown in FIG. 5, the present inventors, using the example of the conductive line passing through the wider locations of the shield electrode 60 as the conductive line 7 and the conductive line passing through the narrower locations of the shield electrode 60 as the conductive line 3, measured the critical dimension of the conductive line passing through the wider locations of the shield electrode 60 and the critical dimension of the conductive line passing through the narrower locations of the shield electrode 60 by implementation as shown in Table 1. In Table 1, CD (7) refers to the critical dimension of the conductive line 7 of various display panels passing through the shield electrode 60 and denotes the critical dimension of the conductive line passing through the widest location of the shield electrode 60; CD (3) refers to the critical dimension of the conductive line 3 of various display panels passing through the shield electrode 60 and denotes the critical dimension of the conductive line passing through the narrowest location of the shield electrode 60. Table 1 Measured critical dimension of the conductive line L passing through the shield electrode Table 1 Measured critical dimension of the conductive line L passing through the shield electrodeField 11,851,90Field 21,762,03Field 31,671,89Field 41,711,94Field 51,821,98Field 61,851,98Field 71,801,98Average critical dimension1,781,96From the analysis of the data shown in Table 1, it is understood that due to the irregular shape of the shield electrode 60, i.e., the non-uniform width of the shield electrode 60, the critical dimension (CD) of the conductive lines deviates by about 0.2 μm (micron), resulting in a capacitance difference of about 0.1 fF between the conductive lines (e.g., ITO wirings) in one pixel unit. Taking the pixel driving circuit 7T 1C illustrated in FIG. 3 as an example, one terminal of the conductive line L may be electrically connected to the fourth node N 4 (i.e., the anode connection node) of the first pixel driving circuit QD 1, and the other terminal of the conductive line L may be electrically connected to the anode of the first light emitting means sp 1. Since the conductive line L extends from the first display area AA1 to the transition display area AAG to establish the electrical connection between the first pixel driving circuit QD1 and the first light emitting means sp1, the length of the conductive line L is large, and finally, the capacitance between the conductive lines (such as ITO wirings) in a pixel unit may differ by about several hundred fF. In this way, at low gray levels, the capacitance of the fourth node N 4 (i.e., the anode connection node) is large due to the long illumination time, and the capacitance difference between the conductive lines (e.g., ITO wirings) of the same row and adjacent pixels is large, which greatly deteriorates the illumination time and leads to Mura problems.In some examples, the capacitance of the conductive lines in the display panel varies greatly. Different lengths of the conductive lines of a plurality of light emitting means located in the first display area AA1 result in different changes in capacitance difference of the light emitting means emitting light in different colors. As compared with the difference in capacitance of the conductive lines connected to the light emitting means emitting red light and the difference in capacitance of the conductive lines connected to the light emitting means emitting blue light, the difference in capacitance of the conductive lines connected to the light emitting means emitting green light is larger. Since the difference in capacitance of the conductive lines connected to the light emitting means emitting green light is larger, the lighting time of the light emitting means emitting green light is decreased, whereby the difference in brightness of the display panel appears, resulting in display deficiencies. At a low gray level, the degree of failure of the light emitting means emitting green light is larger than that of the light emitting means emitting red light, and the degree of failure of the light emitting means emitting red light is larger than that of the light emitting means emitting blue light. For example, with the same gray level, the driving current for driving a light emitting agent emitting blue light may be larger than the driving current for driving a light emitting agent emitting red light, and the driving current for driving a light emitting agent emitting red light may be larger than the driving current for driving a light emitting agent emitting green light. The driving current for driving the light emitting means emitting green light is the smallest of the three primary-color light emitting means, and therefore, the light emitting means emitting green light lights later than the light emitting means emitting red light and the light emitting means emitting blue light when the capacity of the fourth node N 4 (i.e., the anode connection node) of the light emitting means emitting different light is the same. At a low gray level, the near-far connection mode causes some light emitting means emitting green light not to be turned on, which deteriorates the display effect.An embodiment of the present disclosure provides a display panel that may include: a substrate, a circuit pattern layer, and a light emitting pattern layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit pattern layer and the light emitting pattern layer; wherein the substrate includes: a first display region and a second display region, wherein the second display region is disposed on at least one side of the first display region, and the light transmittance of the first display region is greater than the light transmittance of the second display region; wherein the circuit pattern layer comprises: a first gate signal line located in the second display area, a constant voltage line, a plurality of shield electrodes, and a plurality of pixel circuits, the pixel circuit comprising a driver transistor comprising a gate electrode, the plurality of pixel circuits comprising a plurality of first pixel driver circuits; wherein the first gate signal line is connected to the gate electrode of the driver transistor; wherein the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; wherein the shield electrode is connected to the constant voltage line and an orthographic projection of the first gate signal line on the substrate falls within an orthographic projection of the shield electrode on the substrate; wherein the plurality of conductive layers comprise: a plurality of conductive lines, wherein the plurality of conductive lines comprise: a plurality of conductive lines of a first type and a plurality of conductive lines of a second type, wherein an orthographic projection of a part of the conductive line of the first type extending along a first direction on the substrate overlaps with an orthographic projection of at least one of the plurality of shield electrodes on the substrate, and an orthographic projection of a part of the conductive line of the second type extending along the first direction on the substrate does not overlap with an orthographic projection of the plurality of shield electrodes on the substrate; wherein the light emitting structure layer comprises: a plurality of first light emitting means arranged in the first display area, wherein the plurality of first light emitting means comprise a plurality of first light emitting means of a first type and a plurality of first light emitting means of a second type, wherein at least one of the plurality of first light emitting means of the first type is connected to at least one of the plurality of first pixel driver circuits via at least one of the plurality of first conductive lines of the first type, wherein at least one of the plurality of first light emitting means of the second type is connected to at least one of the plurality of first pixel driver circuits via at least one of the plurality of conductive lines of the second type, wherein the first pixel driver circuit is configured to drive the first light emitting means to emit light, wherein the first light emitting means of the first type is configured to emit a first color light, and wherein the first light emitting means of the second type is configured to emit a second color light, wherein the second color light is different from the first color light.Thus, in the display panel provided by the exemplary embodiment of the present disclosure, on the one hand, the critical dimension uniformity of first type conductive lines can be maintained by providing that the first type conductive lines connected to the first light emitting means of the first type and an orthographic projection of the shield electrode overlap on the substrate, and a small capacitance difference of first type conductive lines can be achieved. On the other hand, the uniformity of the critical dimension of the second type conductive line can be maintained by providing that the second type conductive lines connected to the first second type light emitting means and an orthographic projection of the shield electrode on the substrate do not overlap, and a small capacitance difference of second type conductive lines can be obtained. In this way, by optimizing the wiring setting, the brightness difference can be improved and the display effect can be improved.In an exemplary embodiment, the shape of the shield electrode may have a regular shape, for example, the shape of the shield electrode may be rectangular. In this way, by setting the shape of the shield electrode as a rectangle, it can be ensured that the wiring environment of first type conductive lines is consistent, uniformity of the critical dimension of first type conductive lines can be improved, and a small capacitance difference of first type conductive lines can be achieved.In an exemplary embodiment, the plurality of first light emitting means of the first display area may comprise: a plurality of groups of first light emitting means, wherein the first light emitting means may be arranged in each of a plurality of groups of first light emitting means along the first direction X, the plurality of groups of first light emitting means may be arranged along a second direction Y. The second direction intersects the first direction, for example the second direction and the first direction are perpendicular to each other. In at least one group of first light emitting means, a plurality of first pixel driving circuits QD 1 electrically connected to the plurality of first light emitting means of the first type are closer to the first display region than each of a plurality of first pixel driving circuits QD 1 electrically connected to the plurality of first light emitting means of the second type. In this way, the difference in length of the conductive line to which the first light emitting means of the first type is connected can be reduced, so that the display deficits can be mitigated or avoided.In an exemplary embodiment where the conductive layer is a transparent conductive layer, the display panel may include three transparent conductive layers, and the three transparent conductive layers may include a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer, which are sequentially arranged along a side away from the substrate. The first transparent conductive layer may include a plurality of first transparent conductive lines, the second transparent conductive layer may include a plurality of second transparent conductive lines, and the third transparent conductive layer may include a plurality of third transparent conductive lines. For example, an orthographic projection of a portion of the first transparent conductive line extending along the first direction on the substrate may not overlap an orthographic projection of a portion of the second transparent conductive line extending along the first direction on the substrate and an orthographic projection of a portion of the third transparent conductive line extending along the first direction on the substrate, i.e., there are no overlapping wirings. For example, an orthographic projection of a part of the third transparent conductive line extending along the first direction on the substrate and an orthographic projection of a part of the second transparent conductive line extending along the first direction on the substrate may not overlap, i.e., there are no overlapping wirings. For example, the size of the portion of the first transparent conductive line extending along the first direction X in the second direction Y, the size of the portion of the second transparent conductive line extending along the first direction X in the second direction Y, and the size of the portion of the third transparent conductive line extending along the first direction X in the second direction Y may be substantially the same.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits of the second display area via the first transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits of the second display area via the first transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the center of the first display area is of the same type as the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the center of the first display area, or the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the edge of the first display area is of the same type as the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the edge of the first display area.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the center of the first display area is of a different type than the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the center of the first display area, or the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the edge of the first display area is of a different type than the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the edge of the first display area.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the first type disposed between the plurality of first light emitting means of the first type near the center of the first display area and the plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line; and in at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the second type disposed between the plurality of first light emitting means of the second type near the center of the first display area and the plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line.In an exemplary embodiment, in at least one group of first light emitting means of the first display region, the transparent conductive line electrically connected to the plurality of first light emitting means of the first type is disposed on a side of the transfer electrode of the group of first light emitting means in the second direction.In an exemplary embodiment, in at least one group of first light emitting means of the first display region, the transparent conductive line electrically connected to the plurality of first light emitting means of the second type is disposed on the other side of the transfer electrode of the group of first light emitting means in the second direction.In an exemplary embodiment, the first display region includes: a first portion and a second portion, the second portion being disposed on at least one side of the first portion and adjacent to the second display region; at least one of the plurality of first light emitting means located in the first portion is connected to at least one of the plurality of first pixel driving circuits via conductive lines of the plurality of conductive layers; and at least one of the plurality of first light emitting means located in the second portion is connected to at least one of the plurality of first pixel driving circuits via a conductive line of a metallic conductive layer in the circuit pattern layer.In an exemplary embodiment, the metallic conductive layer and the shield electrode are in the same film layer.In an exemplary embodiment, the shape of the shield electrode may be rectangular.In an exemplary embodiment, the light emitting structure layer may further include: a plurality of second light emitting means located in the second display region; the plurality of pixel circuits further include: a plurality of second pixel driving circuits, wherein at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light emitting means, and the at least one second pixel driving circuit is configured to drive the at least one second light emitting means to emit light.In an exemplary embodiment, the second display region may include: a transition display region and a normal display region, the transition display region being disposed on at least one side of the normal display region and adjacent to the first display region; the transition display region may include: a plurality of first pixel driving circuits; and the normal display region includes: at least parts of the plurality of second light emitting means and at least parts of the plurality of second pixel driving circuits, at least parts of the plurality of second light emitting means being connected to at least parts of the plurality of second pixel driving circuits.In an exemplary embodiment, the transition display region may include a plurality of sub-transition regions; the light emitting structure layer may further include a plurality of second light emitting means located in at least one sub-transition region of the plurality of sub-transition regions, the at least one sub-transition region being proximate to the first display region; the circuit structure layer may further include a plurality of second pixel driver circuits located in at least one sub-transition region of the plurality of sub-transition regions, the at least one sub-transition region being proximate to the first display region; at least one of the plurality of second pixel driver circuits is electrically connected to at least one of the plurality of second light emitting means, and the at least one second pixel driver circuit is configured to drive the at least one second light emitting means to emit light.In an exemplary embodiment, the light emitting structure layer may further include a plurality of second light emitting means located in the second display region; the circuit structure layer may further include a plurality of second pixel driving circuits located in the second display region, wherein at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light emitting means, and the at least one second pixel driving circuit is configured to drive the at least one second light emitting means to emit light.In an exemplary embodiment, the first color light may be green light and the second color light may include at least one of red light and blue light. For example, the first light emitting means of the first type may comprise a green first light emitting means sp1_g, the green first light emitting means sp1_g being configured to emit green light; the first light emitting means of the second type may comprise a blue first light emitting means sp1_b being configured to emit blue light and a red first light emitting means sp1_r being configured to emit red light.The display panel in the embodiment of the present disclosure will be described below with reference to the drawings as an example of the display panel including three transparent conductive layers, the first light emitting means of the first type including a green first light emitting means sp 1_g, and the first light emitting means of the second type including a blue first light emitting means sp 1_b and a red first light emitting means sp 1_r.In an exemplary embodiment, the capacitance of the anode connection node of the green first light emitting agent sp 1_g may be reduced by reducing the length of the conductive line connected to the anode connection node of the green first light emitting agent sp 1_g, thereby ensuring that the green first light emitting agent sp 1_g may be normally turned on. In the following example, the first pixel driving circuit QD 1 electrically connected to the green first light emitting means sp 1_g is closest to the first display area AA 1, i.e., the first pixel driving circuit QD 1 electrically connected to the green first light emitting means sp 1_g is preferably disposed near the first display area AA 1. In an exemplary embodiment of the present disclosure, "an element A is near an element B" may mean that there are no other elements A or no other elements B between the element A and the element B, but there may be other elements other than elements A and elements B. For example, the "first pixel driving circuit QD 1 electrically connected to the green first light emitting means sp 1_g is disposed near the first display area AA 1" described in the exemplary embodiment of the present disclosure may mean that, between the first pixel driving circuit QD 1 electrically connected to the green first light emitting means sp 1_g and the first display area AA 1, there is no first pixel driving circuit QD 1 electrically connected to the red first light emitting means sp 1_r or the blue first light emitting means sp 1_b, but other pixel driving circuits such as the second pixel driving circuit QD 2 or the invalid pixel driving circuit QD 0 may be present.In an exemplary embodiment, the plurality of first light emitting means sp 1 of the first display area AA 1 may include a plurality of green first light emitting means sp 1_g, a plurality of blue first light emitting means sp 1_b, and a plurality of red first light emitting means sp 1_r. The green first light emitting means sp1_g is configured to emit green light, the blue first light emitting means sp1_b is configured to emit blue light, and the red first light emitting means sp1_r is configured to emit red light. In at least one group of first light emitting means sp 1, a plurality of second pixel driving circuits QD 2 electrically connected to the green first light emitting means sp 1_g are closer to the first display area AA 1 than each of the plurality of second pixel driving circuits QD 2 electrically connected to the blue first light emitting means sp 1_b or the red first light emitting means sp 1_r. In this way, the difference in length of the conductive line electrically connected to the green first light emitting means sp 1_g can be reduced, and thus display deficiencies can be reduced or avoided.FIG. 6A is a second partial schematic illustration of a display panel in an embodiment of the present disclosure. FIG. 6B is a third partial schematic illustration of a display panel in an embodiment of the present disclosure. FIG. 6C is a fourth partial schematic illustration of a display panel in an embodiment of the present disclosure, showing a part of the display area. As shown in FIGS. 6A to 6C, the first display area AA 1 may have a center line CL extending in the second direction Y, the first display area AA 1 may be divided into a left half area and a right half area along the center line CL, and conductive lines to which the first light emitting means in the left half area and the right area are connected may be substantially symmetric with respect to the center line CL. In addition to a part of the light emitting means in the first display area AA 1, a part of the light emitting means in the sub-transition area near the first display area AA 1 in the transition display area AAG are also illustrated in FIGS. 6A to 6C.In an exemplary embodiment, as shown in FIGS. 6A and 6B, the first display area AA 1 may include a first partial area AA 1 aand a second partial area AA 1 b. The second partial region AA 1 bmay surround the first partial region AA 1 aand adjoin the transition display region AAG. That is, the second partial region AA 1 bmay be located between the first partial region AA 1 aand the transition display region AAG. The second portion AA 1 bmay be an edge portion of the first display region AA 1, and the first portion AA 1 amay be a center portion of the first display region AA 1.In an exemplary embodiment, as shown in FIG. 6A, the shape of the first display area AA 1 may be approximately circular, the shape of the first portion AA 1 amay be a circle having a smaller diameter than that of the first display area AA 1, and the second portion AA 1 bmay be a ring around the first portion AA 1 a. As shown in FIG. 6B, the shape of the first display area AA 1 may be approximately circular, the first portion AA 1 amay be approximately circular having a diameter smaller than that of the first display area AA 1, and the second portion AA 1 bmay be approximately a ring around the first portion AAla. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, as shown in FIGS. 6A and 6B, the film layer in which the conductive line connected to at least one first light emitting means of a plurality of first light emitting means located in the first partial region AA 1 ais located is different from the film layer in which the conductive line connected to at least one first light emitting means of a plurality of first light emitting means located in the first partial region AA 1 ais located. For example, at least one first light emitting means of the plurality of first light emitting means located in the first partial region AA 1 ais electrically connected to at least one of the plurality of first light emitting means through a conductive line of the transparent conductive layer; at least one first light emitting means of the plurality of first light emitting means located in the first partial region AA 1 ais connected to at least one first pixel driving circuit of the plurality of first pixel driving circuits through a conductive line of a metallic conductive layer in the circuit pattern layer. For example, the conductive line of the metallic conductive layer may be the conductive line of the first source-drain metal layer (SD 1) or the conductive line of the second source-drain metal layer (SD 2). Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the conductive line of the metallic conductive layer is in the same film layer as the shield electrode. For example, the shield electrode and the conductive line of the metallic conductive layer may be disposed in the second source-drain metal layer.In an exemplary embodiment, as shown in FIGS. 6A and 6B, in a group of first light emitting means, the number of green first light emitting means sp 1_g within the first partial region AA 1 amay be greater than or equal to the number of green first light emitting means sp 1_g within the second partial region AA 1 b.In an exemplary embodiment, the transition display area AAG in the second display area AA 2 may include a plurality of sub-transition areas; the light emitting structure layer may further include a plurality of second light emitting means in at least a sub-transition area of the plurality of sub-transition areas located near the first display area; the circuit structure layer may further include a plurality of second pixel driving circuits in at least a sub-transition area of the plurality of sub-transition areas located near the first display area; at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light emitting means, and the at least one second pixel driving circuit is configured to drive the at least one second light emitting means to emit light.For example, 48 columns of light emitting means on two sides of the center line CL are schematically shown in FIGS. 6A and 6B, wherein on the left side of the center line CL, the first to 39th columns of light emitting means may be arranged in the first sub-region AA 1 a, the 40th to 44th columns of light emitting means may be arranged in the second sub-region AA 1 b, wherein the first to 39th columns of light emitting means and the 40th to 44th columns of light emitting means are first light emitting means sp1 and extend laterally from the first display area AA1 to a transition display area AAG in the second display area AA2 through a conductive line L and may be connected to a first pixel driving circuit QD1 in the transition display area AAG. For example, the film layers in which the conductive lines used in the first to 39th columns of the light emitting agents are located may be different from the film layers in which the conductive lines used in the 40th to 44th columns of the light emitting agents are located. For example, for the light emitting agents in the first display area AA 1, as shown in FIGS. 6A to 13, the first to 39th columns of the light emitting agents in the first partial area AA 1 amay be driven in a cross arrangement of conductive lines in the transparent conductive layer, and the 40th to 44th columns of the light emitting agents in the second partial area AA 1 bmay be driven in a cross arrangement of conductive lines in a metallic conductive layer (such as the second source-drain metal layer SD 2) after the use of the arrangement space of the transparent conductive layer is completed. In the light emitting means in the transition display area AAG near the first display area AA 1, for example, the 45th to 48th columns of the light emitting means may be disposed in the sub transition area AAGn of the transition display areas AAG closest to the first display area AA 1. The 45th to 48th columns of light emitting means may be second light emitting means sp2and be driven in situ. The 45th to 48th columns of the light emitting means are directly connected to the second pixel driving circuit QD2 which is located in the transient display area AAG, so that the transmittance is not deteriorated and a good transition from the transient display area AAG to the first display area AA1 is ensured.In an exemplary embodiment, as shown in FIG. 6C, the first display area AA 1 may include a first cable area AA 1- 1, a second cable area AA 1- 2, a third cable area AA 1- 3, and a fourth cable area AA 1- 4 that are sequentially arranged away from the center of the first display area AA 1. The first wire area AA 1- 1 may be an area of the first display area AA 1 that is relatively close to the geometric center of the first display area AA 1, and the fourth wire area AA 1- 4 may be an area of the first display area AA 1 that is relatively close to the edge of the first display area AA 1. For example, taking the shape of the first display area AA 1 as an approximate circle, the shapes of the first cable area AA 1- 1, the second cable area AA 1- 2, the third cable area AA 1- 3, and the fourth cable area AA 1- 4 may be part of an approximate semicircle. The size of the first cable portion AA 1- 1 in the second direction Y may be larger than the size of the second cable portion AA 1- 2 in the second direction Y, the size of the second cable portion AA 1- 2 in the second direction Y may be larger than the size of the third cable portion AA 1- 3 in the second direction Y, and the size of the second cable portion AA 1- 2 in the second direction Y may be larger than the size of the fourth cable portion AA 1- 4 in the second direction Y. Here, no limitations are provided in this respect in the embodiments of the present disclosure.In an exemplary embodiment, as shown in FIG. 6C, the first light emitting means sp 1 in the first cable region AA 1- 1 may be electrically connected using a first conductive line L 1 of the first transparent conductive layer, the second cable region AA 1- 2 may be electrically connected using a second conductive line L 2 of the second transparent conductive layer, the third cable region AA 1- 3 may be electrically connected using a third conductive line L 3 of the third transparent conductive layer, and the fourth cable region AA 1- 4 may be electrically connected using a conductive line of a metallic conductive layer (such as a second source-drain metal layer).For example, 48 columns of light emitting means on two sides of the center line CL are schematically illustrated in FIG. 6C, wherein for the left side of the center line CL, the first to 13th columns of light emitting means may be arranged in the first cable area AA1-1, the 14th to 26th columns of light emitting means may be arranged in the second cable area AA1-2, the 27th to 39th columns of light emitting means may be arranged in the third cable area AA1-3, the 40th to 44th columns of light emitting means may be arranged in the fourth cable area AA1-4, the first to 39th columns of light emitting means, and the 40th to 44th columns of light emitting means are first light emitting means sp1, The first display area AA 1 may extend laterally to the transition display area AAG in the second display area AA 2 via a conductive line L and may be connected to the first pixel driving circuit QD 1 in the transition display area AAG. For example, for the light emitting means in the first display area AA 1, as shown in FIG. 6C, the first to 13th columns of the light emitting means located in the first cable area AA 1- 1 may be driven in a cross arrangement of first transparent conductive lines in the first transparent conductive layer. The 14th to 26th columns of the light emitting means located in the second cable region AA1-2 may be driven in a transverse arrangement of second transparent conductive lines in the second transparent conductive layer after the use of the arrangement space of the first transparent conductive layer is completed. The 27th to 39th columns of the light emitting means located in the third cable region AA1-3 can be driven in a transverse arrangement of third transparent conductive lines in the third transparent conductive layer after the use of the arrangement space of the second transparent conductive layer is completed. The 40th to 44th columns of the light emitting means located in the fourth cable region AA1-4 may be driven in a cross arrangement of conductive lines in the metallic conductive layer (such as the second source-drain metal layer SD2) after the utilization of the arrangement space of the transparent conductive layer is completed. In the light emitting means in the transition display area AAG near the first display area AA 1, for example, the 45th to 48th columns of the light emitting means may be disposed in the sub transition area AAGn in the transition display area AAG closest to the first display area AA 1. The 45th to 48th columns of light emitting means may be second light emitting means sp2and be driven in situ. The 45th to 48th columns of the light emitting means are directly connected to the second pixel driving circuit QD2 which is located in the transient display area AAG, so that the transmittance is not deteriorated and a good transition from the transient display area AAG to the first display area AA1 is ensured.In this example, the first light emitting means sp 1 near the center of the first display area AA 1 may be electrically connected by using a conductive line of a transparent conductive layer, and the first light emitting means sp 1 near the edge of the first display area AA 1 may be electrically connected by using a conductive line of a metallic conductive layer (such as a second source-drain metal layer) after the use of the wiring arrangement space of the transparent conductive layer is completed. In this way, the aperture can be unchanged, the wiring environment is uniform, and no mask (mask electrode plate) is added. Moreover, the effect on the peripheral wiring environment is small due to the light load by the metallic conductive layer (e.g., the second source-drain metal layer). Since the light emitting means is electrically connected at the boundary position by a conductive line of a metallic conductive layer (e.g., a second source-drain metal layer), the influence on the transmittance of the first display region AA 1 is small.The connection mode of the light emitting means in the first display area AA 1 will be described with reference to the layout illustrated in FIGS. 6A to 6C in conjunction with the drawings. In the following example, the connection relationship between a part of a group of first light emitting means in the left half region of the first display region AA 1 and a row of first pixel driving circuits QD 1 in the transition display region AAG in the second display region AA 2 is exemplified, and other configurations are omitted. Transparent conductive lines of different layers are shown in different line types, the first transparent conductive line L1 being shown as a solid line, the second transparent conductive line L2 being shown as a dotted line, and the third transparent conductive line L3 being shown as a dot-and-dash line.FIG. 7 is a schematic diagram of a first connection between a first light emitting means and a first pixel driving circuit QD 1 in an exemplary embodiment of the present disclosure. FIG. 8 is a schematic diagram of connection of a first transparent conductive line L 1 of a first transparent conductive layer in FIG. 7, FIG. 9 is a schematic diagram of connection of a second transparent conductive line L 2 of a second transparent conductive layer in FIG. 7, FIG. 10 is a schematic diagram of connection of a third transparent conductive line L 3 of a third transparent conductive layer in FIG. 7, FIG. 11 is a schematic diagram of connection of a metallic conductive line L 4 of a metallic conductive layer in FIG. 7, FIG. 12 is a schematic diagram of a second connection between a first light emitting agent and a first pixel driving circuit QD 1 in an exemplary embodiment of the present disclosure. FIG. 13 is a schematic diagram of a third connection between a first light emitting means and a first pixel driving circuit QD 1 in an exemplary embodiment of the present disclosure. The connection mode of the light emitting means will be described below with reference to FIGS. 6A to 13.In an exemplary embodiment, as shown in FIGS. 7 and 8, the green first light emitting means sp 1_g in the first partial region AA 1 aof the first display region AA 1 may be electrically connected to the first pixel driving circuit QD 1 in the transition display region AAG in the second display region AA 2 through the first transparent conductive line L 1 located in the first transparent conductive layer. As shown in FIGS. 7 and 9, the green first light emitting means sp 1_g in the first partial region AA 1 amay be electrically connected to the first pixel driving circuit QD 1 in the transition display region AAG through the second transparent conductive line L 2 located in the second transparent conductive layer. As shown in FIGS. 7 and 10, the green first light emitting means sp 1_g in the first partial region AA 1 amay be electrically connected to the first pixel driving circuit QD 1 of the junction display region AAG through a third transparent conductive line L 3 located in the third transparent conductive layer. As shown in FIG. 7, a plurality of green first light emitting means sp 1_g near the center of the first display area AA 1 are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via a first transparent conductive line L 1, and a plurality of green first light emitting means sp 1_g near the edge of the second display area AA 1 are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via a third transparent conductive line L 3. That is, a plurality of green first light emitting means sp 1_g that are away from the transition display area AAG in the first direction X are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via the first transparent conductive line L 1, and a plurality of green first light emitting means sp 1_g near the transition display area AAG are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via the third transparent conductive line L 3. As shown in FIG. 7, the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 to which the green first light emitting agents sp 1_g are electrically connected are located on the same side, for example, the upper surface, of the anode connection electrodes of the group of first light emitting agents in the second direction Y. As shown in FIG. 7, an orthographic projection of the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 on the display panel plane to which the green first light emitting agents sp 1_g are electrically connected and an orthographic projection of the shield electrode 60 on the display panel plane may overlap. The shield electrode 60 is configured to shield the crosstalk of the capacitance between the conductive lines to the first node N 1.In an exemplary embodiment, as shown in FIGS. 7 and 8, the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ bmay be electrically connected to the first pixel driving circuit QD 1 of the junction display area AAG within the first partial area AA 1 avia the first transparent conductive line L 1 located in the first transparent conductive layer. As shown in FIGS. 7 and 9, the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ bin the first partial region AA 1 amay be electrically connected to the first pixel driving circuit QD 1 of the junction display region AAG through the second transparent conductive line L 2 located in the second transparent conductive layer. As shown in FIGS. 7 and 10, the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ bin the first partial region AA 1 amay be electrically connected to the first pixel driving circuit QD 1 of the junction display region AAG via a third transparent conductive line L 3 located in the third transparent conductive layer. As shown in FIGS. 7 to 10, a plurality of red first light emitting means sp 1_ rand blue first light emitting means sp 1_ bin the first partial region AA 1 atoward the transition display region AAG may be electrically connected to the first pixel driving circuit QD 1 of the transition display region AAG via a third transparent conductive line L 3 located in the third transparent conductive layer, and a plurality of red first light emitting means sp 1_ rand blue first light emitting means sp 1_ bin the first partial region AA 1 away from the transition display region AAG may be electrically connected to the first pixel driving circuit QD 1 of the transition display region AAG via the first transparent conductive line L 1 located in the first transparent conductive layer. As shown in FIG. 7, the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 to which the red first light emitting means sp 1_ rare electrically connected are located on the same side, for example, the lower side, of the transfer electrodes of the group of first light emitting means in the second direction Y. As shown in FIG. 7, the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 to which the blue first light emitting means sp 1_ bare electrically connected are located on the same side, for example, the lower side, of the group of first light emitting means in the second direction Y. As shown in FIG. 7, the first transparent conductive line L 1 is located, the second transparent conductive line L 2 and the third transparent conductive line L 32 to which the red first light emitting means sp 1_ rare electrically connected, and the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 to which the blue first light emitting means sp 1_ bare electrically connected, on the same side, for example, the lower side, of the transfer electrodes of the first light emitting means group in the second direction Y. As shown in FIG. 7, it is possible that an orthographic projection of the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 on the display panel plane electrically connected to the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ bis possible, and do not overlap an orthographic projection of the shielding electrode 60 on the display panel plane.In an exemplary embodiment, as shown in FIG. 7, the second transparent conductive line L 2 to which the green first light emitting means sp 1_g is electrically connected and the second transparent conductive line L 2 to which the blue first light emitting means sp 1_b is electrically connected are located on two sides of the transfer electrodes of the group of first light emitting means in the second direction Y. The second transparent conductive line L 2 to which the green first light emitting means sp 1_g is electrically connected and the second transparent conductive line L 2 to which the red first light emitting means sp 1_r is electrically connected are located on two sides of the transfer electrodes of the group of first light emitting means in the second direction Y.In an exemplary embodiment, as shown in FIGS. 7 and 11, the green first light emitting means sp 1_g within the second partial region AA 1 bmay be electrically connected to the first pixel driving circuit QD 1 of the junction display region AAG through the metallic conductive line L 4 located in the metallic conductive layer. As shown in FIGS. 7 and 11, the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ bin the second partial region AA 1 bmay be electrically connected to the first pixel driving circuit QD 1 of the junction display region AAG through a metallic conductive line L 4 located in the metallic conductive layer. As shown in FIGS. 7 and 11, the metallic conductive line L 4 to which the green first light emitting means sp 1_ g, the red first light emitting means sp 1_ r, and the blue first light emitting means sp 1_ bare electrically connected are located on the same side, for example, the lower side, of the transfer electrodes of the group of first light emitting means in the second direction Y. As shown in FIGS. 7 and 11, it is possible that an orthographic projection of the metallic conductive line L 4 on the display panel plane to which the first light emitting means sp 1 is electrically connected and an orthographic projection of the shield electrode 60 on the display panel plane do not overlap. As shown in FIGS. 7 and 11, an orthographic projection of the metal conductive line L 4 on the display panel plane electrically connected to the first light emitting means sp 1 may overlap with an orthographic projection of the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 on the display panel plane electrically connected to the red first light emitting means sp 1_ rand the blue first light emitting means sp 1_ b. As shown in FIGS. 7 and 11, it is possible that an orthographic projection of the metal conductive line L 4 on the display panel plane electrically connected to the first light emitting means sp 1 and an orthographic projection of the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3 on the display panel plane electrically connected to the green first light emitting means sp 1_g do not overlap.In an exemplary embodiment, about 10 to 15 first transparent conductive lines L 1 may be disposed in the wiring arrangement space of the first transparent conductive layer, for example, as shown in FIGS. 7 and 8, 13 first transparent conductive lines L 1 may be disposed in the wiring arrangement space of the first transparent conductive layer. About 10 to 15 second transparent conductive lines L2 may be disposed in the wiring arrangement space of the second transparent conductive layer, for example, as shown in FIGS. 7 and 9, 13 second transparent conductive lines L2 may be disposed in the wiring arrangement space of the second transparent conductive layer. About 10 to 15 third transparent conductive lines L 3 may be disposed in the wiring arrangement space of the third transparent conductive layer, for example, as shown in FIGS. 7 and 10, 13 third transparent conductive lines L 3 may be disposed in the wiring arrangement space of the third transparent conductive layer. For example, as shown in FIGS. 7 and 11, about 5 metallic conductive lines L 4 may be disposed in the wiring arrangement space of the metallic conductive layer. Here, no limitations are imposed on the embodiments of the present disclosure.For example, the metallic conductive layer may be a first source-drain metal layer (SD 1) or a second source-drain metal layer (SD 2). The first source-drain metal layer (SD 1) may include, for example, first electrodes and second electrodes of a plurality of transistors in the pixel driving circuit, data signal lines, first power supply lines, or the like. The second source-drain metal layer (SD 2) may include a shield electrode 60, for example.In an exemplary embodiment, as shown in FIGS. 7, 12, and 13, the second light emitting means sp 2 in the second display area AA 2 that is relatively close to the first display area AA 1 uses an in situ driving mode, that is, the second light emitting means sp 2 relatively close to the first display area AA 1 in the transient display area and the second pixel driving circuit QD 2 that drives the second light emitting means sp 2 are both in the transient display area AAG. For example, as shown in FIG. 7, the 45th to 48th columns of light emitting means use an in situ drive mode.In an exemplary embodiment, as shown in FIG. 12, a plurality of green first light emitting means sp 1_g near the center of the first display area AA 1 are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via a first transparent conductive line L 1, and a plurality of green first light emitting means sp 1_g near the edge of the first display area AA 1 (i.e., in the first display area and relatively near the second display area AA 2) are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via a second transparent conductive line L 2 of the second transparent conductive layer. A plurality of red first light emitting means sp1_r and blue first light emitting means sp1_b near the center of the first display area AA1 are electrically connected to a first pixel driving circuit QD1 in the transition display area AAG via a first transparent conductive line L1, and a plurality of red first light emitting means sp1_r and blue first light emitting means sp1_b near the edge of the first display area AA1 (i.e., in the first display area and relatively near the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via a second transparent conductive line L2 of the second transparent conductive layer.In an exemplary embodiment, as shown in FIG. 13, a plurality of green first light emitting means sp 1_g near the center of the first display area AA 1 are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via the second transparent conductive line L 2 of the second transparent conductive layer, and a plurality of green first light emitting means sp 1_g near the edge of the first display area AA 1 (i.e., in the first display area and relatively close to the second display area AA 2) are electrically connected to the first pixel driving circuit QD 1 in the transition display area AAG via the first transparent conductive line L 1 of the first transparent conductive layer. A plurality of red first light emitting means sp1_r and blue first light emitting means sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via a first transparent conductive line L1, and a plurality of red first light emitting means sp1_r and blue first light emitting means sp1_b near the edge of the first display area AA1 (i.e., in the first display area and relatively near the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transition display area AAG via a third transparent conductive line L3 located in the third transparent conductive layer.In this example, for the first light emitting means sp 1 of the first display area AA 1, the first light emitting means sp 1 may be electrically connected near the center in the first partial area AA 1 ausing a first transparent conductive line L 1 of the first transparent conductive layer, the second transparent conductive line L 2 of the second transparent conductive layer may be used for the electrical connection after the use of the wiring arrangement space of the first transparent conductive layer is completed, the first light emitting means sp 1 in the first partial area AA 1 athat is relatively close to the transition display area AAG may be electrically connected using the third transparent conductive line L 3 of the third transparent conductive layer after the use of the wiring arrangement space of the second transparent conductive layer is completed, and the metallic conductive line L 4 of the metallic conductive layer may be used for electrical connection in the second partial region AA 1 bafter the use of the wiring arrangement space of the third transparent conductive layer is completed. Of course, other arrangements may be used; for example, the first light emitting means sp 1 may be electrically connected in the vicinity of the transition display region AAG using the second transparent conductive line L 2 of the second transparent conductive layer. Here, no limitations are imposed on the embodiments of the present disclosure.The structure of the display panel will now be described with reference to an example of a manufacturing process of the display panel. The "patterning process" mentioned in the embodiments of the present disclosure includes processes such as resist coating, mask exposure, development, etching, and peeling of the resist for metallic materials, inorganic materials, or transparent conductive materials, and includes organic material coating, mask exposure, and organic material development, or the like. The deposition may be performed by one or more of sputtering, vapor deposition, and chemical vapor deposition. The coating may be one or more of the following methods: spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, which are not limited in the present disclosure. A "thin film" refers to a thin film of a particular material that is deposited on a substrate by a process such as deposition, coating, etc. If the "thin film" does not require patterning throughout the manufacturing process, the "thin film" may also be referred to as a "layer.". When the "thin film" requires patterning throughout the manufacturing process, it is referred to as a "thin film" before patterning and a "layer" after patterning. The "layer" after the patterning includes at least one "pattern".In an exemplary embodiment, the display panel may include, in the second display area AA 2 and the first display area AA 1, a substrate, a circuit pattern layer disposed on the substrate, a first transparent conductive layer, a second transparent conductive layer, a third transparent conductive layer, and a light emitting pattern layer in a direction perpendicular to the display panel. The circuit pattern layer of the first display region AA 1 may include a plurality of insulation layers. The circuit pattern layer of the second display region AA 2 may include a plurality of first pixel driving circuits and a plurality of second pixel driving circuits. A first planarization layer may be disposed between the first transparent conductive layer and the second transparent conductive layer, and a second planarization layer may be disposed between the second transparent conductive layer and the third transparent conductive layer. A third planarization layer may be disposed between the third transparent conductive layer and the light emitting structure layer. The first planarization layer to the third planarization layer may be organic material layers, for example. The light emitting structure layer may include an anode layer, a pixel defining layer, an organic light emitting layer, and a cathode. The anode layer may include an anode of a first light emitting agent located in the first display area AA 1 and an anode of a second light emitting agent located in the second display area AA 2. For example, the area of the anode of the first light emitting agent may be smaller than the area of the anode of the second light emitting agent that emits light of the same color to increase the light transmittance of the first display area AA 1. In some other examples, the display panel may include two or more transparent conductive layers. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the manufacturing process of the display panel may include the following steps. A first pixel driving circuit QD 1 and a second pixel driving circuit QD 2 of the second display area AA 2 will be described below as examples, and the first pixel driving circuit QD 1 of the transient display area AAG may be a pixel driving circuit as shown in FIG. 3. Moreover, the structure of the second pixel driving circuit QD 2 and the first pixel driving circuit QD 1 may be substantially the same, and the structure of the invalid pixel driving circuit and the first pixel driving circuit QD 1 may be substantially similar, but the invalid pixel driving circuit does not have a through hole connection and a signal, which will be understood by those skilled in the art with reference to the relevant description. In the embodiments of the present disclosure, no detailed description will be given here.(1) A substrate is provided.In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, for example, one or more of the following materials: glass and quartz, without being limited thereto. The flexible substrate may include, for example, one or more of the following materials: polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylester, polyimide, polyvinyl chloride, polyethylene, and textile fibers, without being limited thereto. The flexible substrate may include, for example, a first layer of flexible material, a first layer of inorganic material, a semiconductor layer, a second layer of flexible material, and a second layer of inorganic material, which are stacked on top of each other. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a soft polymer film with surface treatment or the like. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, to improve water and oxygen resistance of the substrate, and a material of the semiconductor layer may be amorphous silicon (a-si).(2) A pattern of the semiconductor layer is formed on the substrate.In an exemplary embodiment, forming the pattern of the semiconductor layer on the substrate may include: a first insulating thin film and a semiconductor thin film are sequentially deposited on the substrate, and the semiconductor thin film is patterned by a patterning process to form a first insulating layer covering the substrate and the semiconductor layer disposed on the first insulating layer, as shown in FIG. 14.In an exemplary embodiment, the first isolation layer may be referred to as a buffer layer and is configured to improve water and oxygen resistance of the substrate. The semiconductor layer may be referred to as an active layer (ACT).In an exemplary embodiment, as shown in FIG. 14, the semiconductor layer of the second display region AA 2 may include at least active layers of multiple transistors of the pixel driver circuit, for example, a first active layer 11 of the first transistor T 1, a second active layer 12 of the second transistor T 2, a third active layer 13 of the third transistor T 3, a fourth active layer 14 of the fourth transistor T 4, a fifth active layer 15 of the fifth transistor T 5, a sixth active layer 16 of the sixth transistor T 6, and a seventh active layer 17 of the seventh transistor T 7.In an exemplary embodiment, as illustrated in FIG. 14, the active layers (e.g., the first active layer 11 to the seventh active layer 17) of a plurality of transistors of a pixel driving circuit may have an integral structure connected to each other.In an exemplary embodiment, as illustrated in FIG. 14, the second active layer 12 and the sixth active layer 16 may be disposed on a first direction X side of the third active layer 13, and the fourth active layer 14 and the fifth active layer 15 may be disposed on the opposite side of the first direction X of the third active layer 13. The fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 are located on a side of the second direction Y of the third active layer 13, and the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on the opposite side of the second direction Y of the third active layer 13.In an exemplary embodiment, as illustrated in FIG. 14, the shape of the first active layer 11 may be an "n" shape. The shape of the second active layer 12 may be an inverted "L" shape. The shape of the third active layer 13 may be an "Ω" shape. The fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may all have an "I" shape.In an exemplary embodiment, an active layer of each transistor may include at least one channel region, and a first region and a second region located on two sides of the channel region. The channel region may not be doped with an impurity, for example, and has the characteristics of a semiconductor. The first region and the second region may be disposed on two sides of the channel region and doped with impurities and are therefore conductive. The impurities may be changed depending on the type of the transistor. In some examples, a doped region of the active layer may be interpreted as a source or drain of a transistor. A portion of the active layer between the transistors may be interpreted as an impurity-doped wiring and may be configured for the electrical connection of the transistor.In an exemplary embodiment, as shown in FIG. 14, the first region 11- 1 of the first active layer 11, the first region 14- 1 of the fourth active layer 14, the first region 15- 1 of the fifth active layer 15, and the first region 17- 1 of the seventh active layer 17 may be separately disposed. The second region 11- 2 of the first active layer 11 may simultaneously serve as the first region 12- 1 and the second gate signal portion SL 2 of the second active layer 12, the first region 13- 1 of the third active layer 13 may simultaneously serve as the second region 14- 2 of the fourth active layer 14 and the second region 15- 2 of the fifth active layer 15, the second region 13- 2 of the third active layer 13 may simultaneously serve as the second region 12- 2 of the second active layer 12 and the first region 16- 1 of the sixth active layer 16, and the second region 16- 2 of the sixth active layer 16 may simultaneously serve as the second region 17- 2 of the seventh active layer 17.In an exemplary embodiment, the semiconductor layer may be made of a metal oxide material. The metal oxide material may include, for example, but is not limited to, an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten, indium, and zinc, an oxide including titanium and indium, an oxide including titanium, indium, and tin, an oxide including indium and zinc, an oxide including silicon, indium, and tin, or an oxide including indium, gallium, and zinc, etc. The semiconductor layer may be made of, for example, a material such as an indium gallium zinc oxide amorphous material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), In the present disclosure, amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene or the like can be applied to transistors manufactured based on oxide technology, silicon technology or organic technology. The semiconductor layer may be, for example, a single layer, a double layer or a multi layer, etc. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the first insulation layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.(3) A pattern of a first conductive layer is formed.In an exemplary embodiment, forming the pattern of the first conductive layer may include depositing a second insulating thin film and a first conductive thin film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the first conductive thin film by a patterning process to form a second insulating layer covering the pattern of the semiconductor layer and the pattern of the first conductive layer disposed on the second insulating layer, as shown in FIGS. 15A and 15B, and FIG. 15B is a schematic plan view of the first conductive layer in FIG. 15A.In an exemplary embodiment, the second isolation layer may be referred to as a gate isolation layer (GI) and the first conductive layer may be referred to as a first gate metal layer (Gate 1).In an exemplary embodiment, as shown in FIGS. 15A and 15B, the first conductive layer of the second display region AA 2 may include at least: a scan signal line 21, a first reset control line 22, a light emission control line 23, a first electrode plate 24 of the storage capacitor Cst, and a second reset control line 25.In an exemplary embodiment, the shape of the first electrode plate 24 of the storage capacitor may be rectangular, the corners of the rectangle may be chamfered, and an orthographic projection of the first electrode plate 24 on the substrate at least partially overlaps an orthographic projection of the third active layer 13 on the substrate. In an exemplary embodiment, the first electrode plate 24 may simultaneously serve as the first electrode plate of the storage capacitor and the gate electrode of the third transistor T 3. The transistors used in the embodiments of the present disclosure may have, for example, a plurality of structures such as a top gate type, a bottom gate type, or a double gate structure. In an exemplary embodiment, the second transistor T 2 and the first transistor T 1 connected to the gate electrode of the third transistor T 3 may be a double-gate thin film transistor, which may help reduce the leakage current of the gate electrode of the third transistor T 3.In an exemplary embodiment, the shapes of the scan signal line 21, the first reset control line 22, the second reset control line 25, and the light emission control line 23 may be line shapes in which the main body portion extends along the first direction X. The scan signal line 21 and the light emission control line 23 may be located on two sides of the first electrode plate 24 in the second direction Y. The first reset control line 22 may be located on a side of the sensing signal line 21 remote from the first electrode plate 24. The second reset control line 25 may be located on a side of the sensing signal line 21 remote from the first electrode plate 24.In an exemplary embodiment, the region where the scan signal line 21 overlaps with the second active layer 12 may serve as a gate electrode of the second transistor T 2, and an orthographic projection of the scan signal line 21 on the substrate and an orthographic projection of the second active layer 12 on the substrate have a first overlap region. For example, the scan signal line 21 is provided with a gate block 21- 1 protruding toward the first reset control line 22 side, a region where the gate block 21- 1 overlaps with the second active layer 12 may serve as another gate electrode of the second transistor T 2, and an orthographic projection of the gate block 21- 1 on the substrate and an orthographic projection of the second active layer 12 on the substrate have a second overlap region, so that a second transistor T 2 having a double gate structure may be formed. For example, the scan signal line 21 and the gate electrode of the second transistor T 2 of the pixel driving circuit may be connected to each other in the same row and have an integral structure.In an exemplary embodiment, the region where the scan signal line 21 overlaps with the fourth active layer 14 may serve as a gate electrode of the fourth transistor T 4, and there is an overlapping region between an orthographic projection of the scan signal line 21 on the substrate and an orthographic projection of the fourth active layer 14 on the substrate. For example, the scan signal line 21 and the gate electrode of the fourth transistor T 4 of the pixel driving circuit may be connected to each other in the same row and have an integral structure.In an exemplary embodiment, the region where the first reset control line 22 overlaps with the first active layer 11 may serve as a gate electrode of the first transistor T 1 having a double gate structure, and there is an overlapping region between an orthographic projection of the first reset control line 22 on the substrate and an orthographic projection of the first active layer 11 on the substrate. For example, the first reset control line 22 and the gate electrode of the first transistor T 1 of the pixel driving circuit may be connected to each other in the same row and have an integral structure.In an exemplary embodiment, the region where the second reset control line 25 overlaps with the seventh active layer 17 serves as a gate electrode of the seventh transistor T 7, and there is an overlapping region between an orthographic projection of the second reset control line 25 on the substrate and an orthographic projection of the second active layer 12 on the substrate. For example, the second reset control line 25 and the gate electrode of the seventh transistor T 7 of the pixel driving circuit may be connected to each other in the same row and have an integral structure.In an exemplary embodiment, a portion of the light emission control line 23 overlapping the fifth active layer 15 serves as a gate electrode of the fifth transistor T 5, and a portion of the light emission control line 23 overlapping the sixth active layer 16 serves as a gate electrode of the sixth transistor T 6. An orthographic projection of the light emission control line 23 on the substrate and an orthographic projection of the fifth active layer 15 on the substrate have an overlap region, and an orthographic projection of the light emission control line 23 on the substrate and an orthographic projection of the sixth active layer 16 on the substrate have an overlap region. For example, the light emission control line 23 and the gate electrodes of the fifth transistor T 5 and the gate electrodes of the sixth transistor T 6 of the pixel driving circuit may be connected to each other in the same row and have an integral structure.In an exemplary embodiment, after the pattern of the first conductive layer is formed, the semiconductor layer may be subjected to conductive treatment by using the first conductive layer as a shield. A region of the semiconductor layer shielded by the first conductive layer forms channel regions of the first transistor T1 to the seventh transistor T7, and a region of the semiconductor layer not shielded by the first conductive layer is made conductive, i.e., first regions and second regions of the first active layer to first regions and second regions of the seventh active layer are all made conductive.In an exemplary embodiment, the second conductive layer may be made of a metal material. The metal material may include, for example, but is not limited to, one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The second conductive layer may be, for example, a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo, or the like.In an exemplary embodiment, the second isolation layer may use one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.(4) A pattern of a second conductive layer is formed.In an exemplary embodiment, forming a pattern of the second conductive layer may include: a third insulating thin film and a second conductive thin film are sequentially deposited on the substrate on which the aforementioned patterns are formed, and the second conductive thin film is patterned by a patterning process to form a third insulating layer covering the first conductive layer and the pattern of the second conductive layer disposed on the third insulating layer, as shown in FIGS. 16A and 16B. FIG. 16B is a schematic plan view of the second conductive layer in FIG. 16A.In an exemplary embodiment, the third isolation layer may be referred to as a gate isolation layer (GI) and the second conductive layer may be referred to as a second gate metal layer (Gate 2).In an exemplary embodiment, as shown in FIGS. 16A and 16B, the second conductive layer of the second display region AA 2 may include at least a first initial signal line 31, a second initial signal line 32, a second electrode plate 33 of the storage capacitor Cst, a stopper 34, and an electrode plate connection line 35.In an exemplary embodiment, the second electrode plate 33 of the storage capacitor may be disposed between the scan signal line 21 and the light emission control line 23 of the pixel driving circuit, and the second electrode plates 33 of the adjacent pixel driving circuits in the first direction X or the opposite direction of the first direction X may be connected by an electrode plate connection line 35 with the first terminal of the electrode plate connection line 35 connected to the second electrode plate 33 of the pixel driving circuit. After the second terminal of the electrode plate connection line 35 extends along the first direction X or the opposite direction to the first direction X, it is connected to the second electrode plate 33 of the adjacent pixel driving circuit. That is, the electrode plate connection line 35 is configured to connect the second electrode plates 33 of adjacent pixel driving circuits in a unit row to each other.In an exemplary embodiment, the second electrode plates of a plurality of pixel driving circuits in a unit row are connected to each other via the electrode plate connection line and form an integrated structure, and the second electrode plates having the integrated structure may be multiplexed as a power supply connection line, thereby ensuring that a plurality of second electrode plates in a unit row have the same potential, which is advantageous for improving the uniformity of the panel, preventing the display deficiencies of the display panel, and ensuring a display effect of the display panel.In an exemplary embodiment, a profile of the second electrode plate 33 may have the shape of a rectangle, corners of which may be chamfered. There is at least partially an overlap region between an orthographic projection of the second electrode plate 33 on the substrate and an orthographic projection of the first electrode plate 24 on the substrate, the first electrode plate 24 and the second electrode plate 33 forming the storage capacitor of the pixel driving circuit.In an exemplary embodiment, the second electrode plate 33 is provided with an opening 36, and the opening 36 may be disposed at the center of the second electrode plate 33. The opening 36 may be rectangular, for example, and the second electrode plate 33 forms an annular structure. For example, the opening 36 exposes the third insulating layer covering the first electrode plate 24, and an orthographic projection of the first electrode plate 24 on the substrate includes an orthographic projection of the opening 36 on the substrate. For example, the opening 36 may be configured to receive a subsequently formed first through hole. The first through hole is located in the opening 36 and exposes the first electrode plate 24 such that the second electrode of the subsequently formed first transistor T 1 is connected to the first electrode plate 24 through the first through hole.In an exemplary embodiment, the shape of the first initial signal line 31 and the second initial signal line 32 may be a line shape in which the main body portion extends along the first direction X.In an exemplary embodiment, the stopper 34 may be disposed between the sensing signal line 21 and the first initial signal line 31. The stopper 34 may have the shape of a polyline, for example. For example, the stopper 34 may include a first electrode portion extending in a first direction X and a second electrode portion extending in a second direction Y. For example, an orthographic projection of the stopper 34 on the substrate overlaps, at least in part, with an orthographic projection of the subsequently formed data signal line 45 on the substrate, so that the stopper 34 can shield the influence of the data surge on the key node, prevent the data surge from affecting the potential of the key node of the pixel driving circuit, and improve the display effect. For example, an orthographic projection of the stopper 34 on the substrate overlaps, at least in part, with an orthographic projection of the second region 11- 2 of the first active layer 11 (also, the first region 12- 1 of the second active layer 12 and the second gate signal portion SL 2) on the substrate, so that the stopper 34 can cover and shield the second gate signal portion SL 2, thereby shielding the influence of the surge on the key nodes, and avoiding the surge from affecting the potential of the key nodes of the pixel driving circuit, and improving the display effect. For example, the second electrode portion of the left stopper 34 may extend to the left pixel driving circuit (not shown in the figure) to shield the conductive connection portion of its second transistor T 2, and the first electrode portion of the right stopper 34 may extend to the left pixel driving circuit in the figure to shield the conductive connection portion of its second transistor T 2. Of course, in other embodiments, no stopper 34 may be provided or an orthographic projection of the stopper 34 on the substrate does not overlap an orthographic projection of the second gate signal line SL 2 on the substrate.(5) A pattern of a fourth insulation layer is formed.In an exemplary embodiment, forming a pattern of a fourth insulating layer may include depositing a fourth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of through holes are provided on the fourth insulating layer, as shown in FIG. 17.In an exemplary embodiment, the fourth isolation layer may be referred to as an interlayer dielectric (ILD).In an exemplary embodiment, as shown in FIG. 17, the plurality of through holes may include a first through hole V 1, a second through hole V 2, a third through hole V 3, a fourth through hole V 4, a fifth through hole V 5, a sixth through hole V 6, a seventh through hole V 7, an eighth through hole V 8, a ninth through hole V 9, a tenth through hole V 10, and an eleventh through hole V 11.In an exemplary embodiment, an orthographic projection of the first through hole V 1 on the substrate is within a range of an orthographic projection of the opening 36 of the second electrode plate 33 on the substrate, the fourth insulating layer and the third insulating layer within the first through hole V 1 are etched away to expose a surface of the first electrode plate 24, and the first through hole V 1 is configured such that a second electrode of the subsequently formed first transistor T 1 is connected to the first electrode plate 24 through the through hole V 1.In an exemplary embodiment, an orthographic projection of the second through hole V 2 on the substrate is within a range of an orthographic projection of the second electrode plate 33 on the substrate, the fourth insulating layer within the second through hole V 2 is etched away to expose a surface of the second electrode plate 33, and the second through hole V 2 is configured such that a first electrode of the subsequently formed fifth transistor T 5 is connected to the second electrode plate 33 through the through hole V 2.In an exemplary embodiment, an orthographic projection of the third via V 3 on the substrate is within a range of an orthographic projection of the first region of the fifth active layer 55 on the substrate. The fourth insulation layer, the third insulation layer, and the second insulation layer in the third through hole V 3 are etched away to expose a surface of the first region of the fifth active layer 55, and the third through hole V 3 is configured such that a first electrode of the subsequently formed fifth transistor T 5 is connected to the first region of the fifth active layer 55 through the through hole V 3.In an exemplary embodiment, an orthographic projection of the fourth via V 4 on the substrate is within a range of an orthographic projection of the second region of the sixth active layer 66 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth via V 4 are etched away, thereby exposing the surface of the second region of the sixth active layer 16 (also, the second region of the seventh active layer). The fourth through hole V 4 is configured such that a second electrode of the subsequently formed sixth transistor T 6 (also the second electrode of the seventh transistor T 7) is connected to the second region of the sixth active layer 16 through the through hole V 4.In an exemplary embodiment, an orthographic projection of the fifth via V 5 on the substrate is within a range of an orthographic projection of the first region of the fourth active layer 14 on the substrate. The fourth insulation layer, the third insulation layer, and the second insulation layer in the fifth through hole V 5 are etched away to expose a surface of the first region of the fourth active layer 14, and the fifth through hole V 5 is configured such that a first electrode of the fourth transistor T 4 formed subsequently is connected to the first region of the fourth active layer 14 through the through hole V 5.In an exemplary embodiment, an orthographic projection of the sixth through hole V 6 on the substrate is within a range of an orthographic projection of the second region of the first active layer 11 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth through hole V 6 are etched away to expose the surface of the second region of the first active layer 11 (also, the first region of the second active layer 12), and the sixth through hole V 6 is configured such that the second electrode of the subsequently formed first transistor T 1 (and also the first electrode of the second transistor T 2) is connected to the second region of the first active layer 11 through this through hole.In an exemplary embodiment, an orthographic projection of the seventh via V 7 on the substrate is within a range of an orthographic projection of the first region of the seventh active layer 17 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh through hole V 7 are etched away to expose a surface of the first region of the seventh active layer 17. The seventh through hole V 7 is configured such that a first electrode of the subsequently formed seventh transistor T 7 is connected to the first region of the seventh active layer through the through hole V 7.In an exemplary embodiment, an orthographic projection of the eighth through hole V 8 on the substrate is within a range of an orthographic projection of the first region of the first active layer 11 on the substrate. The fourth insulation layer, the third insulation layer, and the second insulation layer in the eighth through hole V 8 are etched away, thereby exposing the surface of the first region of the first active layer 11. The eighth through hole V 8 is configured such that a first electrode of the subsequently formed first transistor T 1 is connected to the first region of the first active layer 11 through the through hole V 8.In an exemplary embodiment, an orthographic projection of the ninth via hole V 9 on the substrate is within a range of an orthographic projection of the first initial signal line 31 on the substrate. The fourth insulation film in the ninth through hole V 9 is etched away, thereby exposing the surface of the first initial signal line 31. The ninth through hole V 9 is configured such that a first electrode of the subsequently formed first transistor T 1 is connected to the first initial signal line 31 through the through hole V 9.In an exemplary embodiment, an orthographic projection of the tenth via hole V 10 on the substrate is within a range of an orthographic projection of the second initial signal line 32 on the substrate. The fourth insulation layer in the tenth through hole V 10 is etched away, thereby exposing the surface of the second initial signal line 32. The tenth through hole V 10 is configured such that a first electrode of the subsequently formed seventh transistor T 7 is connected to the second initial signal line 32 through the through hole V 10.In an exemplary embodiment, an orthographic projection of the eleventh through hole V 11 on the substrate is within a range of an orthographic projection of the stopper 34 on the substrate. The fourth insulation layer in the eleventh through hole V11 is etched away, thereby exposing the surface of the stopper 34. The eleventh through hole V 11 is configured so that the subsequently formed first power supply line is connected to the stopper 34 through the through hole V 11.In an exemplary embodiment, the pattern of the through-holes of the second pixel driving circuit QD 2 or the invalid pixel driving circuit may be substantially the same as the pattern of the through-hole of the first pixel driving circuit QD 1.(6) A pattern of a third conductive layer is formed.In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the third conductive thin film by a patterning process to form the third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 18A and 18B, and FIG. 18B is a schematic plan view of the third conductive layer in FIG. 18A.In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal layer (SD 1).In an exemplary embodiment, the third conductive layer of the second display region AA 2 may include a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a data signal line 45, and a first power supply line 46.In an exemplary embodiment, the shape of the first connection electrode 41 may be a strip shape in which the main body portion extends along the second direction Y. In an exemplary embodiment, the first connection electrode 41 may be used as the first gate signal line SL 1, and the first gate signal line SL 1 is connected to the gate electrode of the third transistor T 3. In an exemplary embodiment, the first connection electrode 41 may simultaneously serve as the first gate signal line SL 1, the second electrode of the first transistor T 1, and the first electrode of the second transistor T 2. The first terminal of the first connection electrode 41 is connected to the first electrode plate 24 (also, the gate electrode of the third transistor T 3) through the first through hole V 1 and the opening 36, so that the first gate signal line SL 1 and the gate electrode of the third transistor T 3 are connected. The second terminal of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via the sixth through hole V 6, so that the second electrode of the first transistor T 1 of the first electrode plate 24 (also the gate electrode of the third transistor T 3) and the first electrode of the second transistor T 2 have the same potential, so that the second electrode of the first transistor T 1, the first electrode of the second transistor T 2 and the gate electrode of the third transistor T 3 are connected, and the second gate signal line SL 2 is connected to the first gate signal line SL 1.The materials of the first gate signal line SL 1 and the second gate signal line SL 2 are different, for example. For example, the material of the first gate signal line SL 1 may include a metal and the material of the second gate signal line SL 2 may include a conductive material formed by conductive of a semiconductor material.For example, the first gate signal line SL 1, the second gate signal line SL 2, and the gate electrode of the third transistor T 3 are connected to form a first node N 1 (also referred to as a gate signal portion). The potential at the first node N 1 is the same. Of course, in other embodiments, the second gate signal line SL 2 may not be provided, in which case the gate electrode of the third transistor T 3 and the first gate signal line SL 1 constitute the first node N 1. The second gate signal line SL 2 may be, for example, a second electrode of the first transistor T 1 or a first electrode of the second transistor T 2.In an exemplary embodiment, the shape of the second connection electrode 42 may be a strip shape in which the main body portion extends along the second direction Y. The first terminal of the second connection electrode 42 is connected to the first region of the first active layer 11 through the eighth through hole V 8, and the second terminal of the second connection electrode 42 is connected to the first initial signal line 31 through the ninth through hole V 9. In an exemplary embodiment, the second connection electrode 42 may serve as the first electrode of the first transistor T 1, whereby the first initial signal line 31 may write the first initial signal to the first transistor T 1.In an exemplary embodiment, the shape of the third connection electrode 43 may be a strip shape in which the main body portion extends along the second direction Y, the first terminal of the third connection electrode 43 is connected to the first region of the seventh active layer 17 through the seventh through hole V 7, and the second terminal of the third connection electrode 43 is connected to the second initial signal line 32 through the tenth through hole V 10. In an exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the seventh transistor T 7 so that the second initial signal line 32 may write the second initial signal to the seventh transistor T 7.In an exemplary embodiment, the fourth connection electrode 44 may have a rectangular shape and is connected to a second region of the sixth active layer 16 (also a second region of the seventh active layer 17) via the fourth through hole V 4 such that the second region of the sixth active layer 16 and the second region of the seventh active layer 17 have the same potential. For example, the fourth connection electrode 44 may be used as a second electrode of the sixth transistor T 6 (or as a second electrode of the seventh transistor T 7), and the fourth connection electrode 44 is configured to be connected to a subsequently formed anode electrode.In an exemplary embodiment, the shape of the data signal line 45 may be a line shape in which the main body portion extends along the second direction Y. The data signal line 45 is connected to the first region of the fourth active layer 14 through the fifth through hole V 5, so that the data signal line 45 can serve as the first electrode of the fourth transistor T 4, enabling the data signal line 45 to write a data signal to the first electrode of the fourth transistor T 4. For example, an orthographic projection of the data signal line 45 on the substrate overlaps with an orthographic projection of the stopper 34 on the substrate.In an exemplary embodiment, the shape of the first power supply line 46 may be a line shape in which the main body portion extends along the second direction Y. The first power supply line 46 is connected to the first region of the fifth active layer 15 through the third through hole V 3, and the first power supply line 46 is connected to the second electrode plate 33 through the second through hole V 2. Since the first power supply line 46 is simultaneously connected to the second electrode plate 33 and the first region of the fifth active layer 15, the first power supply line 46 is made to write the first current signal into the first electrode of the fifth transistor T 5 and makes the second electrode plate 33 and the first region of the fifth active layer have the same potential. For example, the first power supply line 46 may serve as a first electrode of the fifth transistor T 5. An orthographic projection of the first power supply line 46 on the substrate overlaps an orthographic projection of the stopper 34 on the substrate, and the first power supply line 46 is connected to the stopper 34 through the eleventh through hole V 11. Since the first power supply line 46 is configured to supply a constant voltage to the pixel driving circuit, the voltage at the stopper 34 can be stabilized and a shielding effect can be obtained.In an exemplary embodiment, the first power supply line 46 may have an uneven width, and the first power supply line 46 having the uneven width may not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance generated by the first power supply line.In an exemplary embodiment, the third conductive layer may be made of a metal material. For example, the metal material may include, but is not limited to, one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc. The third conductive layer may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo, or the like.(7) A pattern of a fourth conductive layer is formed.In an exemplary embodiment, forming a pattern of a fourth conductive layer may include: depositing a fifth insulating thin film and a fourth conductive thin film on a substrate on which the aforementioned patterns are formed; patterning the fourth conductive thin film using a patterning process to form a fifth insulating layer covering the third conductive layer as shown in FIG. 19 and form a fourth conductive layer disposed on the fifth insulating layer as shown in FIGS. 20A and 20B, where FIG. 20B is a schematic plan view of the fourth conductive layer in FIG. 20A.In an exemplary embodiment, the fifth insulation layer may include a plurality of through holes, and the plurality of through holes may include a twenty-first through hole V 21 and a twenty-second through hole V 22. For example, an orthographic projection of the twenty-first through hole V 21 on the substrate overlaps an orthographic projection of the first power supply line 46 on the substrate, and is configured to expose the surface of the first power supply line 46. For example, an orthographic projection of the twenty-second through hole V 22 on the substrate overlaps an orthographic projection of the fourth connection electrode 44 on the substrate, and is configured to expose the surface of the fourth connection electrode 44.In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal layer (SD 2).In an exemplary embodiment, the fourth conductive layer of the second display region AA 2 may include at least: a shield electrode 60 and a fifth connection electrode 50.In an exemplary embodiment, an orthographic projection of the shield electrode 60 on the substrate overlaps an orthographic projection of the first gate signal line SL 1 on the substrate, a shield block 60- 1 is provided on one side of the shield electrode 60 in the first direction X, an orthographic projection of the shield block 60- 1 on the substrate overlaps, at least in part, an orthographic projection of the first power supply line 46 on the substrate, the shield block 60- 1 is connected to the first power supply line 46 through the twenty-first through hole V 21, the shield block 60- 1 is configured such that the shield electrode 60 is connected to the first power supply line 46 through the twenty-second through hole V 21, the first power supply line 46 is configured to supply a constant voltage to the pixel driving circuit, so that the voltage across the shield electrode 60 is stable and a shield effect can be obtained. Since the light emitting signal of the anode is led out through the conductive line L in the first display area AA 1, the shield electrode 60 can avoid the influence of the conductive line L on a key node (such as the first node N 1) and improve the display effect. For example, an orthographic projection of the first gate signal line SL 1 on the substrate falls completely within the range of the boundary of an orthographic projection of the shield electrode 60 on the substrate, so that the shield electrode 60 can achieve a better shield effect. For example, in order to reduce display deficiencies (Mura) and improve the display effect, the distance between an orthographic projection of the first gate signal line SL 1 on the substrate and the boundary of an orthographic projection of the shield electrode 60 on the substrate is greater than or equal to 1.75 μm. Since the area of the area occupied by the pixel unit is limited, the distance of the shield electrode 60 beyond the first gate signal line SL 1 can be limited. In some embodiments, for example, the distance between an orthographic projection of the first gate signal line SL 1 on the substrate and the boundary of an orthographic projection of the shield electrode SE on the substrate is greater than or equal to 2.33 μm to achieve a better shield effect.In an exemplary embodiment, in a case where the display panel includes the second gate signal line SL 2, the second gate signal line SL 2 is connected to the first gate signal line SL 1 to form the first node N 1, so that an orthographic projection of the shield electrode 60 on the substrate and an orthographic projection of the second gate signal line SL 2 on the substrate overlap.In an exemplary embodiment, an orthographic projection of the shield electrode 60 on the substrate overlaps, at least in part, with an orthographic projection of the first electrode plate 24 (also the gate electrode of the third transistor T 3) on the substrate, an orthographic projection of the first gate signal line SL 1 (also the second electrode of the first transistor T 1 and the first electrode of the second transistor T 2) on the substrate, and an orthographic projection of the second gate signal line SL 2 (also the second region of the first active layer 11, the first region of the second active layer 12) on the substrate.In an exemplary embodiment, an orthographic projection of the shield electrode 60 on the substrate partially overlaps an orthographic projection of the second gate signal line SL 2 on the substrate, and an orthographic projection of the stopper 34 on the substrate partially overlaps an orthographic projection of the second gate signal line SL 2 on the substrate. Thus, in the display panel shown in FIG. 20A, the shield electrode 60 and the stopper 34 form a two-layer shield for the second gate signal line SL 2.In an exemplary embodiment, an orthographic projection of the shield electrode 60 on the substrate partially overlaps with an orthographic projection of the stopper 34 on the substrate.In an exemplary embodiment, an orthographic projection of the shield electrode 60 on the substrate partially overlaps an orthographic projection of the first gate signal line SL 1 on the substrate, and an orthographic projection of the stopper 34 on the substrate partially overlaps an orthographic projection of the second gate signal line SL 2 on the substrate, so that the shield electrode 60 and the shield electrode SE and the stopper 34 together act as a shield for the first node N 1.Of course, in other embodiments, the stopper 34 may not be provided, or an orthographic projection of the stopper 34 on the substrate and an orthographic projection of the second gate signal line SL 2 on the substrate may not overlap.In an exemplary embodiment, the shape of the shield electrode 60 may be a regular shape, for example, the shape of the shield electrode 60 may be a rectangular shape. By the regular shape of the shield electrode 60, it is possible to make the width of the shield electrode 60 uniform at different positions, so that the line width of the transparent line passing above the shield electrode 60 is uniform and the influence on the line width of the transparent line can be reduced. Moreover, it is advantageous for improving the uneven brightness problem.In an exemplary embodiment, the shape of the fifth connection electrode 50 may be a rectangular shape. An orthographic projection of the fifth connection electrode on the substrate at least partially overlaps an orthographic projection of the fourth connection electrode 44 on the substrate. The fifth connection electrode 50 may serve as an anode connection electrode. The fifth connection electrode 50 is connected to the fourth connection electrode 44 through the twenty-second through hole V 22, and is configured to be connected to the anode electrode formed subsequently.In an exemplary embodiment, the circuit pattern layer of the second display region AA 2 may include, in a plane perpendicular to the display panel, a substrate, and a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer stacked one after another on the substrate. The semiconductor layer may include active layers of a plurality of transistors in a first pixel driving circuit QD 1 and a second pixel driving circuit QD 2. The first conductive layer may include gate electrodes of a plurality of transistors, a first electrode plate of a storage capacitor, a scan signal line, a first reset control line, a light emission control line, and a second reset control line. The second conductive layer may include a second electrode plate of a storage capacitor, an electrode plate connection line, a stopper, a first initial signal line, and a second initial signal line. The third conductive layer may include first and second electrodes of a plurality of transistors, a data signal line, and a first power supply line. The fourth conductive layer may include an anode connection electrode and a shield electrode. That is, the circuit pattern layer of the second display region AA 2 may include a first pixel driving circuit QD 1 and a second pixel driving circuit QD 2.In an exemplary embodiment, the light transmissive region of the first display region AA 1 may include, in a plane perpendicular to the display panel, a substrate, and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked one after another on the substrate. The opaque region of the first display region AA 1 may include: a substrate; and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, which are sequentially stacked on the substrate. That is, the circuit pattern layer of the first display area AA 1 is not provided with a pixel driving circuit.In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metal materials such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo, etc.In an exemplary embodiment, the first insulation layer, the second insulation layer, the third insulation layer, the fourth insulation layer, and the fifth insulation layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.Hitherto, the circuit pattern layer is formed on the substrate.(8) A first transparent conductive layer is formed.In an exemplary embodiment, a sixth insulating thin film and a first transparent conductive thin film are deposited on a substrate on which the aforementioned patterns are formed, and the first transparent conductive thin film is patterned by a patterning process to form a sixth insulating layer covering the fourth conductive layer and a first transparent conductive layer disposed on the sixth insulating layer, as shown in FIGS. 21A and 21B.In an exemplary embodiment, the first transparent conductive layer may include a sixth connection electrode 61.In an exemplary embodiment, the shape of the sixth connection electrode 61 may be a rectangular shape. An orthographic projection of the sixth connection electrode 61 on the substrate overlaps at least partially with an orthographic projection of the fifth connection electrode 50 on the substrate. When the first light emitting means is electrically connected to the first pixel driving circuit QD 1 of the junction display area AAG via the first transparent conductive line L 1 located in the first transparent conductive layer, the sixth connection electrode 61 may serve as a transfer electrode of the first light emitting means. The sixth connection electrode 61 is connected to the fifth connection electrode 50 via a through hole of the sixth insulation layer, and is configured to be connected to the anode electrode formed subsequently.In an exemplary embodiment, the first transparent conductive layer may further include a first transparent conductive line L 1. For example, one terminal of the first transparent conductive line L 1 may be connected to a sixth connection electrode 61 located in the first display area AA 1, and the other terminal of the first transparent conductive line L 1 may be connected to a sixth connection electrode 61 in the first pixel driving circuit QD 1 located in the transition display area AAG in the second display area AA 2, so that the anode electrode formed subsequently may be connected to the first pixel driving circuit QD 1 in the transition display area AAG.(9) A second transparent conductive layer is formed.In an exemplary embodiment, a first planarization thin film is deposited on a substrate on which the aforementioned patterns are formed, and a first planarization layer is formed by a patterning process. Subsequently, a second transparent conductive thin film is deposited and patterned by a patterning process to form a second transparent conductive layer disposed on the first planarization layer, as shown in FIGS. 22A and 22B.In an exemplary embodiment, the second transparent conductive layer may include a seventh connection electrode 71.In an exemplary embodiment, the shape of the seventh connection electrode 71 may be a rectangular shape. An orthographic projection of the seventh connection electrode 71 on the substrate overlaps at least partially with an orthographic projection of the sixth connection electrode 61 on the substrate. When the first light emitting means is electrically connected to the first pixel driving circuit QD 1 of the transition display area AAG via the second transparent conductive line L 2 located in the second transparent conductive layer, the seventh connection electrode 71 may serve as a transfer electrode of the first light emitting means. The seventh connection electrode 71 is connected to the sixth connection electrode 61 via a through hole of the first planarization layer, and is configured to be connected to the anode electrode formed subsequently.In an exemplary embodiment, the second transparent conductive layer may further include a second transparent conductive line L 2. For example, one terminal of the second transparent conductive line L 2 may be connected to a seventh connection electrode 71 located in the first display area AA 1, and the other terminal of the second transparent conductive line L 2 may be connected to a seventh connection electrode 71 located in the transition display area AAG in the second display area AA 2 in the first pixel driving circuit QD 1, so that the anode electrode formed subsequently may be connected to the first pixel driving circuit QD 1 in the transition display area AAG.(10) A third transparent conductive layer is formed.In an exemplary embodiment, a second planarization thin film is deposited on a substrate on which the aforementioned patterns are formed, and a second planarization layer is formed by a patterning process. Subsequently, a third transparent conductive thin film is deposited and patterned by a patterning process to form a third transparent conductive layer disposed on the second planarization layer, as shown in FIGS. 23A and 23B.In an exemplary embodiment, the third transparent conductive layer may include an eighth connection electrode 81.In an exemplary embodiment, the shape of the eighth connection electrode 81 may be a rectangular shape. An orthographic projection of the eighth connection electrode 81 on the substrate overlaps at least partially with an orthographic projection of the seventh connection electrode 71 on the substrate. When the first light emitting means is electrically connected to the first pixel driving circuit QD 1 located in the transition display area AAG in the second display area AA 2 through the third transparent conductive line L 3 located in the third transparent conductive layer, the eighth connection electrode 81 may serve as a transfer electrode of the first light emitting means. The eighth connection electrode 81 is connected to the seventh connection electrode 71 through a through hole of the second planarization layer, and is configured to be connected to the anode electrode formed subsequently.In an exemplary embodiment, the third transparent conductive layer may further include a third transparent conductive line L 3. For example, one terminal of the third transparent conductive line L 3 may be connected to an eighth connection electrode 81 located in the first display area AA 1, and the other terminal of the second transparent conductive line L 2 may be connected to an eighth connection electrode 81 located in the first pixel driving circuit QD 1 located in the transition display area AAG in the second display area AA 2, so that the anode electrode formed subsequently may be connected to the first pixel driving circuit QD 1 in the transition display area AAG.In an exemplary embodiment, the conductive line L may include one or more of a first transparent conductive line L 1, a second transparent conductive line L 2, and a third transparent conductive line L 3. For example, an orthographic projection of the conductive line L 1 on the substrate partially overlaps with an orthographic projection of the first pixel driving circuit QD 1 on the substrate. For example, an orthographic projection of the conductive line L 1 on the substrate partially overlaps with an orthographic projection of the first gate signal line SL 1 in the first pixel driving circuit QD 1 on the substrate. The shield electrode 60 is located between the conductive line L 1 and the first gate signal line SL 1. In the embodiment of the present disclosure, after the formation of the pixel driving circuit, the shield electrode 60 is formed, and then the conductive line L 1 (such as the first transparent conductive line L 1, the second transparent conductive line L 2, and the third transparent conductive line L 3) is formed, and then the light emitting means is formed such that the film layer in which the shield electrode 60 is located is between the film layer in which the conductive line L 1 is located and the film layer in which the first gate signal line SL 1 is located, and the film layer in which the shield electrode 60 is located is between the film layer in which the conductive line L 1 is located and the film layer in which the gate electrode of the third transistor T 3 is located.(11) A light emitting structure layer is formed.In an exemplary embodiment, a third planarization thin film is deposited on a substrate on which the aforementioned patterns are formed, and a third planarization layer is formed by a patterning process. Subsequently, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode layer disposed on the third planarization layer, as shown in FIGS. 24A and 24B. Subsequently, a pixel defining thin film is deposited on the substrate on which the above-mentioned patterns are formed, and a pixel define layer (PDL) is formed by masking, exposure and development processes. The pixel defining layer is formed with a plurality of pixel openings exposing the anode layer, and the pixel openings are configured to define a light emitting region of the pixel unit, as shown in FIG. 25. An organic light emitting layer is formed in the above-mentioned formed pixel openings, and the organic light emitting layer is connected to an anode. Then, a cathode thin film is deposited and patterned by a patterning process to form a pattern of a cathode. The cathode is electrically connected to each of the organic light emitting layer and the second power supply line. Then, an encapsulation layer is formed on the cathode. The encapsulation layer may include a stacked structure of an inorganic material / an organic material / an inorganic material. In FIGS. 24A, 24B, and 25, eight light emitting means are schematically illustrated in the second display area AA 2 as an example, with the second pixel driving circuit QD 2 partially omitted. FIG. 24C schematically illustrates the connection of the second anode of a second light emitting agent in the second display area AA 2 to the second pixel driving circuit QD 2 as an example. The structure of the light emitting means in the first display area AA 1 may be substantially similar and will be understood by those skilled in the art with reference to the relevant description, and will not be described in detail herein in the embodiments of the present disclosure.In an exemplary embodiment, the anode layer may include a first anode electrode 91, a second anode electrode 92, and a third anode electrode 93.In an exemplary embodiment, the first anode electrode 91 may serve as an anode of the green light emitting agent. An orthographic projection of the first anode electrode 91 on the substrate may partially overlap with an orthographic projection of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.In an exemplary embodiment, the second anode electrode 92 may serve as an anode of the red light emitting agent. An orthographic projection of the second anode electrode 92 on the substrate may partially overlap with an orthographic projection of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.In an exemplary embodiment, the third anode electrode 93 may serve as an anode of the blue light emitting agent. An orthographic projection of the third anode electrode 93 on the substrate may partially overlap with an orthographic projection of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.In an example embodiment, the plurality of pixel openings may include a first pixel opening 94, a second pixel opening 95, and a third pixel opening 96.In an exemplary embodiment, the shape of the first pixel opening 94 may be pentagonal. An orthographic projection of the first pixel opening 94 on the substrate falls within the boundary of an orthographic projection of the first anode electrode 91 on the substrate.In an exemplary embodiment, the shape of the second pixel opening 95 may be hexagonal. An orthographic projection of the second pixel opening 95 on the substrate falls within the boundary of an orthographic projection of the second anode electrode 92 on the substrate.In an exemplary embodiment, the shape of the third pixel opening 96 may be hexagonal. An orthographic projection of the third pixel opening 96 on the substrate falls within the boundary of an orthographic projection of the third anode electrode 93 on the substrate.In an exemplary embodiment, the first transparent conductive layer to the third transparent conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO). The sixth insulating layer, the first planarization layer to the third planarization layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate, or the like. The pixel defining layer may be made of an organic material such as polyimide, acrylic or polyethylene terephthalate, or the like. The anode layer may be made of a reflective material, e.g., a metal or the like, and the cathode may be made of a transparent conductive material. Here, no limitations are imposed on the embodiments of the present disclosure.The structure and the manufacturing method of the display panel in the embodiment of the present disclosure are merely illustrative. In an exemplary embodiment, changes to the respective structures and the addition or omission of patterning processes may be made according to the actual application scenarios. The manufacturing process in this exemplary embodiment can be implemented using a mature manufacturing apparatus and can be well compatible with an existing manufacturing process, and is simple in process implementation, easy to implement, high in production efficiency, low in production cost, and high in yield.In an exemplary embodiment, the display panel may include four or more transparent conductive layers. The transparent conductive lines to which the first light emitting means of the first type and the first light emitting means of the second type are electrically connected in the first portion of the first display region may be arranged in two different transparent conductive layers, and at least one transparent conductive layer may be arranged between the two different transparent conductive layers.In the display panel provided by an embodiment of the present disclosure, the uniformity of the conductive lines can be ensured by adjusting the wiring mode of the transparent conductive lines electrically connected to the first first type light emitting means and the first second type light emitting means in the first display region, thereby improving the display uniformity of the first display region and the display effect of the first display region.An embodiment of the present disclosure also provides a display device. The display device may comprise the display panel in one or more of the above-mentioned exemplary embodiments.In an exemplary embodiment, the display device may further include a sensor located on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel overlaps with a first display area of the display panel.The display device may be a product having a function of displaying an image (including a static image or a dynamic image, the dynamic image may be a video).In an exemplary embodiment, the display device may include, but is not limited to, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital still, an advertising board, a laser printer with display functionality, a character screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigation device, a vehicle, a wide area wall, an information retrieval device (such as a business retrieval device of E-government, banks, hospitals, power supplies, and other departments), or any product or component with display functionality, such as a monitor. Here, no limitations are imposed on the embodiments of the present disclosure.In an exemplary embodiment, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, or an ultrasonic sensor, or the like. Here, no limitations are imposed on the embodiments of the present disclosure.The above descriptions of the embodiments of the display device are similar to the above descriptions of the embodiments of the display panel, and the embodiments of the display device have similar advantageous effects to the embodiments of the display panel. Technical details not disclosed in the embodiments of the display device of the present disclosure can be understood by those skilled in the art with reference to the descriptions in the embodiments of the display panel of the present disclosure that are not to be repeated here.Although embodiments of the present disclosure are disclosed above, the above contents are only embodiments for easy understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure relates can make any modifications and variations in the form and details of the embodiment without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure is still within the scope defined by the appended claims.

Claims

A display panel, comprising: a substrate, a circuit pattern layer and a light emitting pattern layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit pattern layer and the light emitting pattern layer; wherein the substrate comprises: a first display region and a second display region, wherein the second display region is disposed on at least one side of the first display region, and the light transmittance of the first display region is greater than the light transmittance of the second display region; the circuit pattern layer comprises: a first gate signal line located in the second display region, a constant voltage line, a plurality of shield electrodes, and a plurality of pixel circuits, wherein the pixel circuit comprises a driving transistor comprising a gate electrode, and the plurality of pixel circuits comprise a plurality of first pixel driving circuits; the first gate signal line is connected to the gate electrode of the driving transistor; the constant voltage line is configured to supply a first constant voltage to the plurality of pixel circuits; the shield electrode is connected to the constant voltage line, and an orthographic projection of the first gate signal line on the substrate falls within an orthographic projection of the shield electrode on the substrate; the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines include a plurality of conductive lines of a first type and a plurality of conductive lines of a second type, an orthographic projection of a part of the conductive line of the first type extending along a first direction on the substrate overlaps with an orthographic projection of at least one of the plurality of shield electrodes on the substrate, and an orthographic projection of a part of the conductive line of the second type extending along the first direction on the substrate does not overlap with an orthographic projection of the plurality of shield electrodes on the substrate; and the light emitting structure layer includes: a plurality of first light emitting means arranged in the first display area, the plurality of first light emitting means comprise a plurality of first light emitting means of a first type and a plurality of first light emitting means of a second type, at least one of the plurality of first light emitting means of the first type is connected to at least one of the plurality of first pixel driving circuits via at least one of the plurality of first conductive lines of the first type, at least one of the plurality of first light emitting means of the second type is connected to at least one of the plurality of first pixel driving circuits via at least one of the plurality of conductive lines of the second type, the first pixel driving circuit is configured to drive the first light emitting means to emit light, the first light emitting means of the first type is configured to emit a first color light, the light emitting means of the second type is configured to emit a second color light, and the second color light is different from the first color light.The display panel according to claim 1, wherein the plurality of first light emitting means of the first display area comprises: a plurality of groups of first light emitting means, the first light emitting means are arranged in each of a plurality of groups of first light emitting means along the first direction, the plurality of groups of first light emitting means are arranged along a second direction, and the second direction intersects the first direction; and in at least one group of first light emitting means, a plurality of first pixel driving circuits electrically connected to the plurality of first light emitting means of the first type are closer to the first display area than each of a plurality of first pixel driving circuits electrically connected to the plurality of first light emitting means of the second type.The display panel of claim 2, wherein the plurality of conductive layers comprise: a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer, which are sequentially arranged along a side away from the substrate; and the first transparent conductive layer comprises a plurality of first transparent conductive lines, the second transparent conductive layer comprises a plurality of second transparent conductive lines, and the third transparent conductive layer comprises a plurality of third transparent conductive lines.The display panel according to claim 3, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.The display panel according to claim 3, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the first type near an edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line.The display panel according to claim 3, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits of the second display area via the first transparent conductive line.The display panel according to claim 3, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area via the first transparent conductive line.The display panel according to any one of claims 4 to 7, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.The display panel according to any one of claims 4 to 7, wherein in the at least one group of first light emitting means of the first display area, the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the center of the first display area is of the same type as the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the center of the first display area or the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the edge of the first display area is of the same type as the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the edge of the first display area.The display panel according to any one of claims 4 to 7, wherein in the at least one group of first light emitting means of the first display area, the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the center of the first display area is of a different type than a plurality of first light emitting means of the first type near the center of the first display area, or the transparent conductive line electrically connected to a plurality of first light emitting means of the second type near the edge of the first display area is of a different type than the transparent conductive line electrically connected to a plurality of first light emitting means of the first type near the edge of the first display area.The display panel according to any one of claims 4 to 7, wherein in at least one group of first light emitting means in the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, and a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line.The display panel according to any one of claims 4 to 7, wherein in the at least one group of first light emitting means of the first display area, the conductive line electrically connected to the plurality of first light emitting means of the first type is disposed on a side of the transfer electrode of the group of first light emitting means in a second direction.The display panel according to claim 12, wherein in the at least one group of first light emitting means of the first display area, the conductive line electrically connected to the plurality of first light emitting means of the second type is arranged in a second direction on the other side of the transfer electrode of the group of first light emitting means.The display panel according to claim 3, wherein in the at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the first type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, a plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the first type disposed between the plurality of first light emitting means of the first type near the center of the first display area and the plurality of first light emitting means of the first type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line; and in the at least one group of first light emitting means of the first display area, a plurality of first light emitting means of the second type near the center of the first display area are electrically connected to a plurality of first pixel driving circuits via the first transparent conductive line, a plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the third transparent conductive line, and a plurality of first light emitting means of the second type disposed between the plurality of first light emitting means of the second type near the center of the first display area and the plurality of first light emitting means of the second type near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits via the second transparent conductive line.The display panel according to any one of claims 1 to 7, wherein the first display area comprises: a first portion and a second portion, the second portion being disposed between the first portion and the second display area; at least one first light emitting means of the plurality of first light emitting means located in the first portion is connected to at least one of the plurality of first pixel driving circuits via conductive lines of the plurality of conductive layers; and at least one first light emitting means of the plurality of first light emitting means located in the second portion is connected to at least one first pixel driving circuit of the plurality of first pixel driving circuits via a conductive line of a metallic conductive layer in the circuit pattern layer.The display panel of claim 15, wherein the metallic conductive layer and the shield electrode are in the same film layer.The display panel according to any one of claims 1 to 7, wherein the light emitting structure layer further comprises: a plurality of second light emitting means located in the second display area; the plurality of pixel circuits further comprises: a plurality of second pixel driving circuits, at least one of the plurality of second pixel driving circuits is electrically connected to at least one of the plurality of second light emitting means, and the at least one second pixel driving circuit is configured to drive the at least one second light emitting means to emit light.The display panel of claim 17, wherein the second display area comprises: a transition display area and a normal display area, the transition display area being disposed between the first display area and the normal display area; the transition display area comprises: a plurality of first pixel driving circuits; and the normal display area comprises: at least parts of the plurality of second light emitting means and at least parts of the plurality of second pixel driving circuits, wherein at least parts of the plurality of second light emitting means are connected to at least parts of the plurality of second pixel driving circuits.The display panel of any one of claims 1 to 7, wherein the first color light is green light, and the second color light comprises at least one of blue light and red light.A display device comprising the display panel according to any one of claims 1 to 19.The display device of claim 20, further comprising: a sensor, wherein the sensor is disposed on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel overlaps with the first display area of the display panel.

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