Shift register unit, driver control circuit, display device and driver method

Abstract

Embodiments of the present disclosure provide a shift register unit, a driver control circuit, a display device, and a driver method.The sliding register unit includes: an input circuit configured to supply an input signal to a first node in response to a first clock signal; a reset circuit configured to supply a first reference signal to a second node in response to a second clock signal; a first control circuit configured to supply the second clock signal to the second node in response to a first control signal; an output circuit configured to supply a third clock signal to a driver output terminal in response to a signal of the first node and to supply a second reference signal to the driver output terminal in response to a signal of the second node; wherein a duration of an active level of the first control signal is greater than a duration of an active level of a signal of the driver output terminal.

Description

FIELD OF TECHNOLOGY

[0001] The present disclosure relates to the field of display technology, more particularly to a shift register unit, a drive control circuit, a display device and a drive method. STATE OF THE ART

[0002] With the rapid development of display technology, display devices are increasingly moving toward high integration and low cost. GOA (Gate Driver on Array) technology integrates a TFT (Thin Film Transistor) driver control circuit on the array substrate of the display device to drive the display device. The driver control circuit generally includes multiple cascaded shift register units. However, the output of the shift register unit is unstable, resulting in abnormal display. SUMMARY

[0003] An embodiment of the present disclosure provides a shift register unit comprising: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a driver output terminal in response to a signal from the first node and to provide a second reference signal to the driver output terminal in response to a signal from the second node; wherein a duration of an active level of the first control signal is greater than a duration of an active level of a signal of the driver output terminal.

[0004] In some examples, the duration of the active level of the first control signal is approximately equal to twice the duration of the active level of the signal of the driver output terminal.

[0005] In some examples, the first control circuit includes a first transistor; wherein a control electrode of the first transistor is configured to receive the first control signal, wherein a first electrode of the first transistor is configured to receive the second clock signal, and wherein a second electrode of the first transistor is coupled to the second node.

[0006] In some examples, the input circuit includes a second transistor; wherein a control electrode of the second transistor is configured to receive the first clock signal, wherein a first electrode of the second transistor is configured to receive the input signal, and wherein a second electrode of the second transistor is coupled to the first node.

[0007] In some examples, the input circuit further comprises a third transistor; wherein the second electrode of the second transistor is coupled to the first node via the third transistor; wherein a control electrode of the third transistor is configured to receive the first clock signal, wherein a first electrode of the third transistor is coupled to the second electrode of the second transistor, and wherein a second electrode of the third transistor is coupled to the first node.

[0008] In some examples, the shift register unit further comprises: a first noise suppression circuit; wherein the first noise suppression circuit is configured to supply the third clock signal to the first electrode of the third transistor in response to the signal of the driver output terminal.

[0009] In some examples, the first noise suppression circuit comprises: a fourth transistor; wherein a control electrode of the fourth transistor is coupled to the driver output terminal, wherein a first electrode of the fourth transistor is configured to receive the third clock signal, and wherein a second electrode of the fourth transistor is coupled to the first electrode of the third transistor.

[0010] In some examples, the first control circuit is coupled to the first electrode of the third transistor and a signal of the first electrode of the third transistor is the first control signal.

[0011] In some examples, the first control circuit is coupled to the first node and the signal of the first node is the first control signal.

[0012] In some examples, the output circuit comprises: a fifth transistor, a sixth transistor, and a first capacitor; wherein a control electrode of the fifth transistor is coupled to the first node, wherein a first electrode of the fifth transistor is configured to receive the third clock signal, and wherein a second electrode of the fifth transistor is coupled to the driver output terminal; wherein a control electrode of the sixth transistor is coupled to the second node, wherein a first electrode of the sixth transistor is configured to receive the second reference signal, and wherein a second electrode of the sixth transistor is coupled to the driver output terminal; wherein a first electrode plate of the first capacitor is coupled to the first node, and wherein a second electrode plate of the first capacitor is coupled to the driver output terminal.

[0013] In some examples, the output circuit further comprises: a second capacitor; wherein a first electrode plate of the second capacitor is coupled to the second node, and wherein a second electrode plate of the second capacitor is configured to receive the second reference signal.

[0014] In some examples, the shift register unit further comprises: a second control circuit; wherein the second control circuit is configured to provide the second reference signal to the first node in response to the signal from the second node.

[0015] In some examples, the second control circuit comprises: a seventh transistor; wherein a control electrode of the seventh transistor is coupled to the second node, wherein a first electrode of the seventh transistor is configured to receive the second reference signal, and wherein a second electrode of the seventh transistor is coupled to the first node.

[0016] In some examples, the second control circuit further comprises: an eighth transistor; wherein the second electrode of the seventh transistor is coupled to the first node via the eighth transistor; wherein a control electrode of the eighth transistor is coupled to the second node, wherein a first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and wherein a second electrode of the eighth transistor is coupled to the first node.

[0017] In some examples, the shift register unit further comprises: a second noise suppression circuit; wherein the second noise suppression circuit is configured to provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node.

[0018] In some examples, the second noise suppression circuit comprises: a ninth transistor; wherein a control electrode of the ninth transistor is coupled to the first node, wherein a first electrode of the ninth transistor is configured to receive the first reference signal, and wherein a second electrode of the ninth transistor is coupled to the first electrode of the eighth transistor.

[0019] In some examples, the reset circuit includes a tenth transistor; wherein a control electrode of the tenth transistor is configured to receive the second clock signal, wherein a first electrode of the tenth transistor is configured to receive the first reference signal, and wherein a second electrode of the tenth transistor is coupled to the second node.

[0020] An embodiment of the present disclosure provides a driver control circuit comprising a plurality of cascaded shift register units described above; wherein an input signal of a first-stage shift register unit is provided by a frame trigger signal terminal; wherein, for shift register units of two adjacent stages, an input signal of a shift register unit of the next stage is provided by the driver output terminal of a shift register unit of the previous stage.

[0021] An embodiment of the present disclosure provides a display device including the above driver control circuit.

[0022] An embodiment of the present disclosure provides a driving method for the above shift register unit, comprising: an input phase in which the input circuit provides the input signal to the first node in response to the first clock signal; the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal from the first node; an output phase in which the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal from the first node; a reset phase in which the reset circuit provides the first reference signal to the second node in response to the second clock signal; and the output circuit provides the second reference signal to the driver output terminal in response to the second node signal. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1 is a schematic diagram of some structures of a shift register in the related art; Fig. 2 is a timing diagram of some signals of the shift register in the related art; Fig. 3 is a schematic diagram of some structures of a shift register provided by an embodiment of the present disclosure; Fig. 4 is a schematic diagram of other structures of the shift register provided by an embodiment of the present disclosure; Fig. 5 is a timing diagram of some signals of the shift register provided by an embodiment of the present disclosure; Fig. 6 is a flowchart of a driving method provided by an embodiment of the present disclosure; Fig. 7 is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 8 is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 9 is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 10 is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 11 is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 12a is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 12b is a schematic diagram of further structures of the shift register unit provided by an embodiment of the present disclosure; Fig. 13 is a timing diagram of other signals of the shift register provided by an embodiment of the present disclosure; Fig. 14a is a schematic diagram of further structures of the shift register provided by an embodiment of the present disclosure; Fig. 14b is a schematic diagram of further structures of the shift register unit provided by an embodiment of the present disclosure; Fig. 15 is a timing diagram of additional signals of the shift register provided by an embodiment of the present disclosure; Fig. 16 is a schematic diagram of some structures of a driver control circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF REVELATION

[0023] In order to clarify the objects, technical objects, and advantages of the embodiments of the present disclosure, the technical objects of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It is obvious that the described embodiments represent only a part of the embodiments of the present disclosure, but not all of the embodiments of the present disclosure. Also, the embodiments and the features contained therein can be combined with each other in the present disclosure, provided they do not contradict each other. Starting from the embodiments of the present disclosure described here, one of ordinary skill in the art can obtain all other embodiments falling within the scope of the present disclosure without inventive work.

[0024] Unless otherwise defined, the technical and scientific terms used in this disclosure have the general meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," or the like, as used in this disclosure, do not represent an order, quantity, or importance, but are used to distinguish different components. The terms "comprise," "include," or the like, are intended to indicate that the elements or items listed before these terms include the elements or items listed after these terms, as well as their equivalents, without excluding other elements or items. The terms "connect," "attach," or the like, are not limited to physical or mechanical connection, but may also include direct or indirect electrical connection.

[0025] It should be noted that the size and shape of the individual diagrams in the accompanying drawings do not reflect true proportions, but are merely intended to schematically illustrate the content of the present disclosure. Furthermore, the same or similar reference numerals always represent the same or similar elements or elements with the same or similar functions.

[0026] As in Fig. 1, a shift register unit may comprise transistors M01 to M010 and capacitors C01 to C02. The timing diagram of the corresponding signals is shown in Fig. 2, where GCK1 to GCK3 represent clock signals, GIP represents an input signal, n01 represents a signal of a node N01, n02 represents a signal of a node N02, and gso represents a signal of a driver output terminal GSO.

[0027] In an input phase T01, the clock signal GCK1 is at a low level, the transistors M01 and M02 are turned on, and the input signal GIP at the low level is supplied to the node N01 to control the transistors M05 and M09 to turn on. The turned-on transistor M09 supplies a low-level signal VGL to a node N03. The turned-on transistor M05 supplies a high-level clock signal GCK2 to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is at a high level and controls the transistor M03 to turn off. The clock signal GCK3 is at a high level and the transistor M010 is turned off. The input signal GIP is at a low level, the transistor M04 is turned on, and a high-level signal VGH is supplied to the node N02 to control the transistor M06 to turn off.

[0028] In an output phase T02, the clock signal GCK1 is at a high level, and transistors M01 and M02 are turned off. The clock signal GCK3 is at a high level, and transistor M010 is turned off. The input signal GIP is at a high level, and transistor M04 is turned off. Therefore, both node N01 and node N02 are in a floating state. Due to the action of capacitor C01, node N01 can be kept at a low level to control transistors M05 and M09 to turn on. The turned-on transistor M05 supplies the low level of the clock signal GCK2 to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is at a low level.Due to the bootstrap effect of capacitor C01, the level of node N01 can be further pulled down to control transistor M05, so that transistor M05 is turned on as fully as possible to supply the low level of clock signal GCK2 to driver output terminal GSO, so that the signal gso output from driver output terminal GSO is at the low level and controls transistor M03 to turn on. The turned-on transistor M03 can supply the low level of signal gso to node N04. Due to the effect of capacitor C02, node N02 can be kept high to control transistor M06 to turn off.

[0029] However, in the above shift register unit, since the signal received by the gate of transistor M04 is the input signal GIP, transistor M04 can only be turned on in the input phase t01 and cannot be turned on in other phases. Specifically, in the output phase t02, no high-level signal is input to node N02, but node N02 is held at the high level by capacitor C02. However, due to the leakage current of transistor M010, the high level of node N02 held by capacitor C02 is pulled down (as shown in Fig. 2, the part shown by the solid line in the signal n01 is the actual level of the node N02 in the phase t02, and the part shown by the dashed line is the ideal level of the node N02 in the phase t02), so the signal gso output from the driver output terminal GSO is unstable (as shown in Fig. 2, the part of the signal gso shown by the solid line is the actual level of the signal gso in phase t02, and the part shown by the dashed line is the ideal level of the signal gso in phase t02).

[0030] Although the capacitor C02 is arranged in the above shift register unit, the stability of the node N02 in practical applications can only be determined by the voltage component c 02 / (c 02 +c gd(M06) +c N02(andere) ) of capacitor C02. The larger the voltage component, the more stable node N02 is. To ensure that node N02 is not pulled down, capacitor C02 can be chosen to be relatively large. However, if, for example, the width of the channel region of transistor M06 is 400 μm and the capacitance of capacitor C02 is 500 fF, node N02 will still jump down by about 1 V. As shown in Fig. As shown in Figure 2, due to the effect of the output jump in the output phase T02, node N02 can jump down from 7 V to 4.9 V. With the increase in the size of the capacitor C02, the jump range of node N02 can decrease, but the level of node N02 cannot reach 7 V. Therefore, even if the capacitor C02 is selected to be relatively large, it is not possible to completely prevent node N02 from being pulled down, and the shift register unit may also occupy a relatively large space.

[0031] To solve the above problems, an embodiment of the present disclosure provides a shift register unit that can improve the stability of nodes.

[0032] In one embodiment of the present disclosure, as shown in Fig. 3, the shift register unit may include: an input circuit 10, a reset circuit 20, a first control circuit 30, and an output circuit 40. Here, the input circuit 10 is configured to supply an input signal GIP to a first node N1 in response to a first clock signal CK1. The reset circuit 20 is configured to supply a first reference signal VREF1 to a second node N2 in response to a second clock signal CK2. The first control circuit 30 is configured to supply the second clock signal CK2 to the second node N2 in response to a first control signal CS1.The output circuit 40 is configured to provide a third clock signal CK3 to a driver output terminal GSO in response to a signal from the first node N1 and to provide a second reference signal VREF2 to the driver output terminal GSO in response to a signal from the second node N2, and wherein a duration of an active level of the first control signal CS1 is greater than a duration of an active level of a signal from the driver output terminal GSO.

[0033] In the shift register unit provided by an embodiment of the present disclosure, the duty cycle of the first control circuit can be increased by setting the active level duration of the first control signal to be longer than the active level duration of the signal of the driver output terminal, that is, the duration for which the second clock signal is supplied to the second node is increased to stabilize the level of the second node by the input signal. In this way, the level stability of the second node can be realized without additionally disposing a large capacitor, which not only improves output stability but also reduces the occupied area.

[0034] In some embodiments of the present disclosure, as in Fig. As shown in Figure 4, the first control circuit 30 includes a first transistor M1. A control electrode of the first transistor M1 is configured to receive the first control signal CS1, a first electrode of the first transistor M1 is configured to receive the second clock signal CK2, and a second electrode of the first transistor M1 is coupled to the second node N2.

[0035] For example, the first transistor M1 is turned on under the control of an active level of the first control signal CS1 and turned off under the control of an inactive level of the first control signal CS1. For example, the first transistor M1 is a P-type transistor, so that the active level of the first control signal CS1 is a low level and the inactive level is a high level. Alternatively, the first transistor M1 may be an N-type transistor, so that the active level of the first control signal CS1 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the first transistor can be determined according to the requirements of practical applications, which is not limited here.

[0036] In some embodiments of the present disclosure, as in Fig. As shown in Figure 4, the input circuit 10 may include a second transistor M2. A control electrode of the second transistor M2 is configured to receive the first clock signal CK1, a first electrode of the second transistor M2 is configured to receive the input signal GIP, and a second electrode of the second transistor M2 is coupled to the first node N1.

[0037] For example, the second transistor M2 is turned on under the control of an active level of the first clock signal CK1 and turned off under the control of an inactive level of the first clock signal CK1. For example, the second transistor M2 is a P-type transistor, such that the active level of the first clock signal CK1 is a low level and the inactive level is a high level. Alternatively, the second transistor M2 may be an N-type transistor, such that the active level of the first clock signal CK1 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the second transistor can be determined according to the requirements of practical applications, which is not limited here.

[0038] In some embodiments of the present disclosure, as in Fig. 4, the output circuit 40 includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. A control electrode of the fifth transistor M5 is coupled to the first node N1, a first electrode of the fifth transistor M5 is configured to receive the third clock signal CK3, and a second electrode of the fifth transistor M5 is coupled to the driver output terminal GSO. A control electrode of the sixth transistor M6 is coupled to the second node N2, a first electrode of the sixth transistor M6 is configured to receive the second reference signal VREF2, and a second electrode of the sixth transistor M6 is coupled to the driver output terminal GSO. A first electrode plate of the first capacitor C1 is coupled to the first node N1, and a second electrode plate of the first capacitor C1 is coupled to the driver output terminal GSO.

[0039] For example, the fifth transistor M5 is turned on under the control of the active level of the signal of the first node N1 and turned off under the control of the inactive level of the signal of the first node N1. For example, the fifth transistor M5 is a P-type transistor, so the active level of the signal of the first node N1 is a low level and the inactive level is a high level. Alternatively, the fifth transistor M5 may be an N-type transistor, so the active level of the signal of the first node N1 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the fifth transistor can be determined according to the requirements of practical applications, which is not limited here.

[0040] For example, the sixth transistor M6 is turned on under the control of the active level of the signal of the second node N2 and turned off under the control of the inactive level of the signal of the second node N2. For example, the sixth transistor M6 is a P-type transistor, so the active level of the signal of the second node N2 is a low level and the inactive level is a high level. Alternatively, the sixth transistor M6 may be an N-type transistor, so the active level of the signal of the second node N2 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the sixth transistor can be determined according to the requirements of practical applications, which is not limited here.

[0041] In some embodiments of the present disclosure, as in Fig. 4, the shift register unit further includes: a second control circuit 50. The second control circuit 50 is configured to provide the second reference signal VREF2 to the first node N1 in response to the signal from the second node N2. For example, the second control circuit 50 includes: a seventh transistor M7. A control electrode of the seventh transistor M7 is coupled to the second node N2, a first electrode of the seventh transistor M7 is configured to receive the second reference signal VREF2, and a second electrode of the seventh transistor M7 is coupled to the first node N1.

[0042] For example, the seventh transistor M7 is turned on under the control of the active level of the signal of the second node N2 and turned off under the control of the inactive level of the signal of the second node N2. For example, the seventh transistor M7 is a P-type transistor, so that the active level of the signal of the second node N2 is a low level and the inactive level is a high level. Alternatively, the seventh transistor M7 may be an N-type transistor, so that the active level of the signal of the second node N2 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the seventh transistor can be determined according to the requirements of practical applications, which is not limited here.

[0043] In some embodiments of the present disclosure, as in Fig. As shown in Figure 4, the reset circuit 20 includes a tenth transistor M10. A control electrode of the tenth transistor M10 is configured to receive the second clock signal CK2, a first electrode of the tenth transistor M10 is configured to receive the first reference signal VREF1, and a second electrode of the tenth transistor M10 is coupled to the second node N2.

[0044] For example, the tenth transistor M10 is turned on under the control of the active level of the second clock signal CK2 and turned off under the control of the inactive level of the second clock signal CK2. For example, the tenth transistor M10 is a P-type transistor, so the active level of the second clock signal CK2 is a low level and the inactive level is a high level. Alternatively, the tenth transistor M10 may be an N-type transistor, so the active level of the second clock signal CK2 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the tenth transistor can be determined according to the requirements of practical applications, which is not limited here.

[0045] In some embodiments of the present disclosure, a signal timing diagram corresponding to the Fig. 4 shown shift register unit, in Fig. 5. GIP represents the input signal, CK1 represents the first clock signal, CK2 represents the second clock signal, CK3 represents the third clock signal, n1 represents the signal of the first node N1, n2 represents the signal of the second node N2, gso represents the signal of the driver output terminal GSO, and CS1 represents the first control signal. Here, the low-level duration ts2 of the first control signal CS1 is greater than the low-level duration ts1 of the gso signal of the driver output terminal GSO when the active level is a low level. For example, the low-level duration ts2 of the first control signal CS1 may be approximately equal to twice the low-level duration ts1 of the gso signal of the driver output terminal GSO. Alternatively, the duration ts2 of the high level of the first control signal CS1 is greater than the duration ts1 of the high level of the signal gso of the driver output terminal GSO when the active level is a high level.For example, the duration ts2 of the high level of the first control signal CS1 may be approximately equal to twice the duration ts1 of the high level of the signal gso of the driver output terminal GSO. In practical applications, the specific embodiment can be determined according to the requirements of the practical application, which is not limited here.

[0046] It should be noted that in actual processes, due to limitations in process conditions or other factors, the above equal ratio may not be completely equal, and some deviations may occur. Therefore, as long as the above equal ratio approximately satisfies the above condition, the above equal ratio belongs to the scope of the present disclosure. For example, the above equal ratio may be equal within an allowable error range.

[0047] In a specific embodiment, the control electrode of the above transistor can be used as the gate. Furthermore, depending on the signal flow direction, the first electrode of the above transistor can be used as its source and the second electrode of the transistor as its drain; or the first electrode can be used as its drain and the second electrode as its source, which is not differentiated here.

[0048] It should be noted that the transistor mentioned in the above embodiments of the present disclosure may be a TFT or a metal oxide semiconductor field effect transistor (MOS), which is not limited here.

[0049] To simplify the manufacturing process, in a specific implementation, all transistors in embodiments of the present disclosure may be P-type transistors, as shown in Fig. 4. Of course, all transistors can also be N-type transistors, which is not restricted here.

[0050] The above is merely an example to illustrate the specific structure of the shift register unit provided by embodiments of the present disclosure. In a specific embodiment, the specific structures of the above circuits are not limited to the above structures provided by embodiments of the present disclosure and may also be other structures known to those skilled in the art, which are not limited here.

[0051] An embodiment of the present disclosure further provides a driving method for a shift register unit as described in Fig. 6, which may include the following steps:

[0052] S10. an input phase in which the input circuit provides the input signal to the first node in response to the first clock signal; the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal from the first node.

[0053] S20. an output phase in which the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal of the first node.

[0054] S30. a reset phase in which the reset circuit provides the first reference signal to the second node in response to the second clock signal; and the output circuit provides the second reference signal to the driver output terminal in response to the second node signal.

[0055] In the driving method provided by an embodiment of the present disclosure, the duty cycle of the first control circuit can be increased by setting the active level duration of the first control signal to be greater than the active level duration of the signal of the driver output terminal, that is, the duration for which the second clock signal is supplied to the second node is increased to stabilize the level of the second node by the input signal. In this way, the level stability of the second node can be realized without additionally disposing a large capacitor, which not only improves output stability but also reduces the occupied area.

[0056] In some embodiments of the present disclosure, when the shift register unit further comprises a second control circuit, the second control circuit may provide the second reference signal to the first node in the reset phase in response to the signal of the second node.

[0057] Using the example of Fig. 4, the working process of the above shift register unit provided by embodiments of the present disclosure will be described below in conjunction with the shift register unit shown in Fig. 5 shown signal timing diagram.

[0058] Specifically, the input phase T1, the output phase T2 and the reset phase T3 are Fig. 5 shown signal timing diagram. It should be noted that the Fig. The signal timing diagram shown in Figure 5 only represents the operation of a specific shift register unit within a frame. The operation of the shift register unit in other frames is essentially the same as the operation in this frame and will not be repeated here.

[0059] In the input phase T1, the first clock signal CK1 is low, the second transistor M2 is turned on, and the low-level input signal GIP is supplied to the first node N1 to control the fifth transistor M5 to turn on. The turned-on fifth transistor M5 supplies the high-level third clock signal CK3 to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is high. The second clock signal CK2 is high, and the tenth transistor M10 is turned off. The first control signal CS1 is low, the first transistor M1 is turned on, and the high-level second reference signal VREF2 is supplied to the second node N2 to control the sixth transistor M6 and the seventh transistor M7 to turn off.

[0060] In the output phase T2, the first clock signal CK1 is high, and the second transistor M2 is turned off. The second clock signal CK2 is high, and the tenth transistor M10 is turned off. The first control signal CS1 is low, the first transistor M1 is turned on, and the second reference signal VREF2 at the high level is supplied to the second node N2 to control the sixth transistor M6 and the seventh transistor M7 to turn off. Therefore, the first node N1 is in a floating state. Due to the action of the first capacitor C1, the first node N1 can be kept low to control the fifth transistor M5 to turn on. The turned-on fifth transistor M5 supplies the low level of the third clock signal CK3 to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is low.Due to the bootstrap effect of the first capacitor C1, the level of the first node N1 can be further pulled down to control the fifth transistor M5, so that the fifth transistor is turned on as fully as possible to supply the low level of the third clock signal CK3 to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is at the low level.

[0061] In the reset phase T3, the first clock signal CK1 is high, and the second transistor M2 is turned off. The first control signal CS1 is high, and the first transistor M1 is turned off. The second clock signal CK2 is low, the tenth transistor M10 is turned on, and the first reference signal VREF1 at the low level is supplied to the second node N2 to control the sixth transistor M6 and the seventh transistor M7 to turn on. The turned-on seventh transistor M7 supplies the second reference signal VREF2 at the high level to the first node N1 to control the fifth transistor M5 to turn off. The turned-on sixth transistor M6 supplies the second reference signal VREF2 at the high level to the driver output terminal GSO, so that the signal gso output from the driver output terminal GSO is high.

[0062] It should be noted that the first transistor M1 is turned on under the control of the first control signal CS1 in both the input phase T1 and the output phase T2, and the second reference signal VREF2 at the high level can be supplied to the second node N2 in these two phases to prevent the second node N2 from floating in these two phases, so that the second node N2 can be stabilized in the output phase (e.g., at 7 V). In addition, since the second reference signal VREF2 at the high level is supplied to the second node N2 in both the input phase T1 and the output phase T2, it is not necessary to dispose a capacitor on the control electrode of the sixth transistor M6, thereby further reducing the space occupied by the shift register unit.For example, when no capacitor is arranged on the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be larger than 50 µm or 100 µm, that is, the stable output of the shift register unit can be realized.

[0063] An embodiment of the present disclosure provides a schematic diagram of other structures of the shift register unit as shown in Fig. 7, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be explained, and similarities will not be repeated here.

[0064] In some embodiments of the present disclosure, as in Fig. As shown in Figure 7, the output circuit 40 further includes a second capacitor C2. A first electrode plate of the second capacitor C2 is coupled to the second node N2, and a second electrode plate of the second capacitor C2 is configured to receive the second reference signal VREF2. Thus, the level of the second node N2 can be further stabilized by the second capacitor C2.

[0065] It should be noted that the signal timing diagram corresponding to the Fig. 7 shown shift register unit, as shown in Fig. 5. In addition, the work process of the Fig. 7 shown shift register unit in combination with the one in Fig. 5 may refer to the working process of the above shift register unit, which is not repeated here.

[0066] Note that the signal stability of the second node N2 can be further improved by disposing the second capacitor C2. In practical applications, the width of the channel region of the sixth transistor M6 can be less than 400 μm, and the capacitance of the second capacitor can be as low as 50fF-200fF, so that the shift register unit can output stably.

[0067] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 8, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be illustrated, and the similarities will not be repeated here.

[0068] In some embodiments of the present disclosure, as in Fig. As shown in Figure 8, the input circuit 10 further includes a third transistor M3; and the second electrode of the second transistor M2 is coupled to the first node N1 via the third transistor M3. A control electrode of the third transistor M3 is configured to receive the first clock signal CK1, a first electrode of the third transistor M3 is coupled to the second electrode of the second transistor M2, and a second electrode of the third transistor M3 is coupled to the first node N1.

[0069] For example, the third transistor M3 is turned on under the control of the active level of the first clock signal CK1 and turned off under the control of the inactive level of the first clock signal CK1. For example, the third transistor M3 is a P-type transistor, so that the active level of the first clock signal CK1 is a low level and the inactive level is a high level. Alternatively, the third transistor M3 may be an N-type transistor, so that the active level of the first clock signal CK1 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the third transistor can be determined according to the requirements of the practical applications, which is not limited here.

[0070] It should be noted that the signal timing diagram corresponding to the Fig. 8 shown shift register unit, as shown in Fig. 5. In addition, the third transistor M3 is turned on in the input phase T1 under the control of the first clock signal CK1, so that the input signal GIP at the low level can be supplied to the first node N1 in conjunction with the turned-on second transistor M2. The third transistor M3 is turned off in the output phase T2 and the reset phase T3 under the control of the first clock signal CK1. In addition, the other working process of the Fig. 8 shown shift register unit in combination with the one in Fig. 5 may refer to the working process of the above shift register unit, which is not repeated here.

[0071] It should be noted that the arrangement of two transistors in the input circuit 10 can reduce the influence of the leakage current of the first node N1 on the signal of the first node N1 and improve the signal stability of the first node N1.

[0072] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 9, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be illustrated, and the similarities will not be repeated here.

[0073] In some embodiments of the present disclosure, as in Fig. 9, the shift register unit further includes: a first noise suppression circuit 60. The first noise suppression circuit 60 is configured to supply the third clock signal CK3 to the first electrode of the third transistor M3 in response to the signal from the driver output terminal GSO. The first noise suppression circuit 60 includes, for example: a fourth transistor M4. A control electrode of the fourth transistor M4 is coupled to the driver output terminal GSO, a first electrode of the fourth transistor M4 is configured to receive the third clock signal CK3, and a second electrode of the fourth transistor M4 is coupled to the first electrode of the third transistor M3.

[0074] For example, the fourth transistor M4 is turned on under the control of the active level of the signal from the driver output terminal GSO and turned off under the control of the inactive level of the signal from the driver output terminal GSO. For example, the fourth transistor M4 is a P-type transistor, so the active level of the signal from the driver output terminal GSO is a low level and the inactive level is a high level. Alternatively, the fourth transistor M4 may be an N-type transistor, so the active level of the signal from the driver output terminal GSO is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the fourth transistor can be determined according to the requirements of the practical applications, which is not limited here.

[0075] In some embodiments of the present disclosure, when the shift register unit further comprises a first noise suppression circuit, the first noise suppression circuit may, in the output phase, supply the third clock signal to the first electrode of the third transistor in response to the signal of the driver output terminal.

[0076] It should be noted that the signal timing diagram corresponding to the Fig. 9 shown shift register unit, as shown in Fig. 5. In addition, the fourth transistor M4 is turned on under the control of the signal gso of the driver output terminal GSO in the output phase T2 and supplies the low level of the third clock signal CK3 to the first electrode of the third transistor M3. The fourth transistor M4 is turned off under the control of the signal gso of the driver output terminal GSO in the input phase T1 and the reset phase T3. In addition, the other working process of the Fig. 9 shown shift register unit in combination with the Fig. 5 may refer to the working process of the above shift register unit, which is not repeated here.

[0077] It should be noted that by arranging the first noise suppression circuit 60, the low level of the third clock signal CK3 can be supplied to the first electrode of the third transistor M3 in the output phase, so that the influence of the leakage current of the first node N1 on the signal of the first node N1 can be further reduced and the signal stability of the first node N1 can be further improved.

[0078] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 10, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be explained, and similarities will not be repeated here.

[0079] In some embodiments of the present disclosure, as in Fig. 10, the second control circuit 50 may further include an eighth transistor M8; and the second electrode of the seventh transistor M7 is coupled to the first node N1 via the eighth transistor M8. A control electrode of the eighth transistor M8 is coupled to the second node N2, a first electrode of the eighth transistor M8 is coupled to the second electrode of the seventh transistor M7, and a second electrode of the eighth transistor M8 is coupled to the first node N1.

[0080] For example, the eighth transistor M8 is turned on under the control of the active level of the signal of the second node N2 and turned off under the control of the inactive level of the signal of the second node N2. For example, the eighth transistor M8 is a P-type transistor, so the active level of the signal of the second node N2 is a low level and the inactive level is a high level. Alternatively, the eighth transistor M8 may be an N-type transistor, so the active level of the signal of the second node N2 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the eighth transistor can be determined according to the requirements of practical applications, which is not limited here.

[0081] It should be noted that the signal timing diagram corresponding to the Fig. 10 shown shift register unit, as shown in Fig. 5. In addition, the eighth transistor M8 is turned on under the control of the level of the second node N2 in the reset phase T3 and, in combination with the turned-on seventh transistor M7, supplies the second reference signal VREF2 at the high level to the first node N1. The eighth transistor M8 is turned off under the control of the level of the second node N2 in the input phase T1 and the output phase T2. In addition, the other working process of the Fig. 10 shown shift register unit in combination with the one in Fig. 5 may refer to the working process of the above shift register unit, which is not repeated here.

[0082] It should be noted that the arrangement of the eighth transistor M8 can reduce the influence of the leakage current of the first node N1 on the signal of the first node N1 and further improve the signal stability of the first node N1.

[0083] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 11, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be illustrated, and the similarities will not be repeated here.

[0084] In some embodiments of the present disclosure, as in Fig. As shown in Fig. 11, the shift register unit further includes: a second noise suppression circuit 70. The second noise suppression circuit 70 is configured to supply the first reference signal VREF1 to the first electrode of the eighth transistor M8 in response to the signal of the first node N1. The second noise suppression circuit 70 includes, for example: a ninth transistor M9. A control electrode of the ninth transistor M9 is coupled to the first node N1, a first electrode of the ninth transistor M9 is configured to receive the first reference signal VREF1, and a second electrode of the ninth transistor M9 is coupled to the first electrode of the eighth transistor M8.

[0085] For example, the ninth transistor M9 is turned on under the control of the active level of the signal of the first node N1 and turned off under the control of the inactive level of the signal of the first node N1. For example, the ninth transistor M9 is a P-type transistor, so the active level of the signal of the first node N1 is a low level and the inactive level is a high level. Alternatively, the ninth transistor M9 may be an N-type transistor, so the active level of the signal of the first node N1 is a high level and the inactive level is a low level. In practical applications, the specific embodiment of the ninth transistor can be determined according to the requirements of practical applications, which is not limited here.

[0086] In some embodiments of the present disclosure, when the shift register unit further comprises a second noise suppression circuit, the second noise suppression circuit may, in the input phase, provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node; and the second noise suppression circuit may, in the output phase, provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node.

[0087] It should be noted that the signal timing diagram corresponding to the Fig. 11 shown shift register unit, as shown in Fig. 5. In addition, the ninth transistor M9 is turned on under the control of the level of the first node N1 in the input phase T1 and the output phase T2 and supplies the first reference signal VREF1 at the low level to the first electrode of the eighth transistor M8. The ninth transistor M9 is turned off under the control of the level of the first node N1 in the reset phase T3. In addition, the other working process of the Fig. 11 shown shift register unit in combination with the in Fig. 5 may refer to the working process of the above shift register unit, which is not repeated here.

[0088] It should be noted that the arrangement of the ninth transistor M9 can further reduce the influence of the leakage current of the first node N1 on the signal of the first node N1 and further improve the signal stability of the first node N1.

[0089] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 12a, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be illustrated, and the similarities will not be repeated here.

[0090] In some embodiments of the present disclosure, as in Fig. As shown in Figure 12a, the first control circuit 30 is coupled to the first electrode of the third transistor M3, and a signal from the first electrode of the third transistor M3 is the first control signal CS1. Specifically, the control electrode of the first transistor M1 is coupled to the first electrode of the third transistor M3.

[0091] A signal timing diagram corresponding to the Fig. 12a shown shift register unit, is for example in Fig. 13, where m1 represents the signal of the control electrode of the first transistor M1. In addition, the other working process of the Fig. 12a shown shift register unit in combination with the in Fig. 13 may refer to the working process of the above shift register unit, which is not repeated here.

[0092] It should be noted that the first transistor M1 is turned on in both the input phase T1 and the output phase T2 under the control of the signal of the first electrode of the third transistor M3, and thus the second reference signal VREF2 at the high level can be supplied to the second node N2 in these two phases to avoid the second node N2 from floating in these two phases, so that the second node N2 can be stabilized in the output phase (e.g., at 7 V).

[0093] In some embodiments, it may not be necessary to arrange the second capacitor C2, since the second reference signal VREF2 is supplied at the high level to the second node N2 in both the input phase T1 and the output phase T2, as shown in Fig. 12b. Thus, the space occupied by the shift register unit can be further reduced. For example, if a second capacitor C2 is not arranged at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50 μm or 100 μm, that is, a stable output of the shift register unit can be realized.

[0094] An embodiment of the present disclosure provides a schematic diagram of further structures of the shift register unit as shown in Fig. 14a, which is modified from the embodiments in the above embodiments. In the following, only the differences between this embodiment and the above embodiments will be illustrated, and the similarities will not be repeated here.

[0095] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14a, the first control circuit 30 is coupled to the first node N1, and the signal of the first node N1 is the first control signal CS1. Specifically, a control electrode of the first transistor M1 is coupled to the first node N1.

[0096] A signal timing diagram corresponding to the Fig. 14a shown shift register unit, for example, in Fig. 15, where m1 represents the signal of the control electrode of the first transistor M1. In addition, the other working process of the Fig. 14a shown shift register unit in combination with the in Fig. 15 may refer to the working process of the above shift register unit, which is not repeated here.

[0097] It should be noted that the first transistor M1 is turned on in both the input phase T1 and the output phase T2 under the control of the signal of the first node N1, and thus the second reference signal VREF2 at the high level can be supplied to the second node N2 in these two phases to avoid the second node N2 from floating in these two phases, so that the second node N2 can be stabilized in the output phase (e.g., at 7 V).

[0098] In some embodiments, it may not be necessary to arrange the second capacitor C2 since the second reference signal VREF2 is supplied at the high level to the second node N2 in both the input phase T1 and the output phase T2, as shown in Fig. 14b. Thus, the space occupied by the shift register unit can be further reduced. For example, if a second capacitor C2 is not arranged at the control electrode of the sixth transistor M6, the width of the channel region of the sixth transistor M6 can be greater than 50 μm or 100 μm, that is, a stable output of the shift register unit can be realized.

[0099] An embodiment of the present disclosure further provides some driver control circuits. As in Fig. As shown in Figure 16, the driver control circuit includes a plurality of cascaded shift register units SR(1), SR(2), SR(3), ..., SR(N-1), and SR(N) (a total of N shift register units). An input signal GIP of the first-stage shift register unit SR(1) is provided through a frame trigger signal terminal STV; and for shift register units of two adjacent stages, an input signal GIP of a next-stage shift register unit is provided through the driver output terminal GSO of a previous-stage shift register unit.

[0100] The specific structure of each shift register unit in the above drive control circuit is the same in function and structure as the above shift register unit in the present disclosure, and repeated descriptions thereof are omitted here. The drive control circuit may be configured in a liquid crystal display panel or an electroluminescent display panel, which is not limited here.

[0101] In the above driver control circuit provided by an embodiment of the present disclosure, the first reference signal VREF1 of the shift register unit in each stage is provided through the same first DC signal terminal, and the second reference signal VREF2 of the shift register unit in each stage is provided through the same second DC signal terminal.

[0102] In the above driver control circuit provided by an embodiment of the present disclosure, as shown in Fig.As shown in Figure 16, the first clock signal CK1 of the shift register unit in the 3k-2nd stage, the second clock signal CK2 of the shift register unit in the 3k-1st stage, and the third clock signal CK3 of the shift register unit in the 3k-th stage are provided through the same clock terminal, i.e., the first clock terminal ck1. The second clock signal CK2 of the shift register unit in the 3k-2nd stage, the third clock signal CK3 of the shift register unit in the 3k-1st stage, and the first clock signal CK1 of the shift register unit in the 3k-th stage are provided through the same clock terminal, i.e., the second clock terminal ck2. The third clock signal CK3 of the shift register unit in the 3k-2nd stage, the first clock signal CK1 of the shift register unit in the 3k-1st stage, and the second clock signal CK2 of the shift register unit in the 3k-th stage are provided through the same clock terminal, ie, the third clock terminal ck3.Here k is a positive integer.

[0103] An embodiment of the present disclosure further provides a display device including the above drive control circuit provided by an embodiment of the present disclosure. The principle of the display device for solving the problem is similar to that of the above drive control circuit, so the embodiments of the display device can refer to the embodiments of the above drive control circuit, and the repeated description thereof is omitted here.

[0104] In a specific embodiment of the present disclosure, the display device may be a mobile phone, a tablet, a television, a display, a laptop, a digital photo frame, a navigation device, or any other product or component with display functions. One of ordinary skill in the art should understand that all other essential components of the display device are included, are not repeated here, and should not be considered limitations of the present disclosure.

[0105] In a specific embodiment, the display device may include a plurality of pixel units and a plurality of gate lines and data lines, wherein each pixel unit may include a plurality of subpixels, such as red subpixels, green subpixels, and blue subpixels. The above display device provided by an embodiment of the present disclosure may be an organic light-emitting display device or a liquid crystal display device, which is not limited here.

[0106] In one embodiment of the present disclosure, a driver control circuit is also correspondingly associated with the plurality of gate lines; and one gate line is coupled to the driver output terminal of the shift register unit in one stage in the driver control circuit. For example, when the above display device provided by one embodiment of the present disclosure is a liquid crystal display device, TFTs in the subpixels may be coupled to the gate lines, and the above driver control circuit may be used as a gate driver circuit coupled to the gate lines to supply the gate scanning signals to the TFTs in the subpixels. It should be noted that the TFTs in the subpixels may be N-type transistors or P-type transistors, which are not limited here.

[0107] In some embodiments of the present disclosure, when the above display device provided by an embodiment of the present disclosure is an organic light-emitting display device, the display device further comprises a plurality of light-emitting control signal lines; a driver control circuit is correspondingly associated with the plurality of light-emitting control signal lines; and one light-emitting control signal line is coupled to the driver output terminal of the shift register unit in a stage in the driver control circuit. Also, a driver control circuit is correspondingly associated with the plurality of gate lines; and one gate line is coupled to the driver output terminal of the shift register unit in a stage in the driver control circuit.For example, in the organic light-emitting display device, a plurality of organic light-emitting diodes and pixel circuits connected to each organic light-emitting diode are generally arranged. Generally, in the pixel circuit, a light-emitting control transistor for controlling the organic light-emitting diode to emit light and a scanning control transistor for controlling the input of data signals are arranged.

[0108] In a specific embodiment, the light-emitting control transistor may be coupled to the light-emitting control signal line, and the scan control transistor may be coupled to the gate line. The organic light-emitting display device may include any of the above driver control circuits provided by embodiments of the present disclosure, wherein the driver control circuit may be used as a light-emitting driver circuit, and the light-emitting driver circuit is coupled to the light-emitting control transistor and is used to provide a light-emitting control signal of the light-emitting control transistor. Alternatively, the driver control circuit may also be used as a gate driver circuit, and the gate driver circuit is coupled to the gate line and is used to provide a gate scan signal of the scan control transistor.

[0109] Of course, the organic light-emitting display device may also include two above driver control circuits provided by embodiments of the present disclosure, wherein one driver control circuit may be used as a light-emitting driver circuit coupled to the light-emitting control transistor and used to provide a light-emitting control signal of the light-emitting control transistor; and the other driver control circuit is used as a gate driver circuit coupled to the gate line and used to provide a gate scanning signal of the scanning control transistor, which is not limited here.

[0110] In the shift register unit, the drive control circuit, the display device, and the drive method provided by embodiments of the present disclosure, the duty cycle of the first control circuit can be increased by setting the active level duration of the first control signal to be longer than the active level duration of the signal of the drive output terminal, that is, the duration for which the second clock signal is supplied to the second node is increased to stabilize the level of the second node by the input signal. In this way, the level stability of the second node can be realized without additionally disposing a large capacitor, which not only improves the output stability but also reduces the occupied area.

[0111] Although preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they understand the basic inventive concepts. Therefore, the appended claims should be interpreted to encompass both the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0112] Of course, those skilled in the art may make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, if these modifications and variations of embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the disclosure is intended to encompass these modifications and variations.

Claims

[1] Shift register unit, comprising: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a driver output terminal in response to a signal from the first node and to provide a second reference signal to the driver output terminal in response to a signal from the second node; wherein a duration of an active level of the first control signal is greater than a duration of an active level of a signal of the driver output terminal. [2] The shift register unit of claim 1, wherein the duration of the active level of the first control signal is approximately equal to twice the duration of the active level of the signal of the driver output terminal. [3] The shift register unit of claim 1 or 2, wherein the first control circuit comprises a first transistor; wherein a control electrode of the first transistor is configured to receive the first control signal, wherein a first electrode of the first transistor is configured to receive the second clock signal, and wherein a second electrode of the first transistor is coupled to the second node. [4] The shift register unit of any of claims 1-3, wherein the input circuit comprises a second transistor; wherein a control electrode of the second transistor is configured to receive the first clock signal, wherein a first electrode of the second transistor is configured to receive the input signal, and wherein a second electrode of the second transistor is coupled to the first node. [5] The shift register unit of claim 4, wherein the input circuit further comprises a third transistor; wherein the second electrode of the second transistor is coupled to the first node via the third transistor; wherein a control electrode of the third transistor is configured to receive the first clock signal, wherein a first electrode of the third transistor is coupled to the second electrode of the second transistor, and wherein a second electrode of the third transistor is coupled to the first node. [6] A shift register unit according to claim 5, wherein the shift register unit further comprises: a first noise suppression circuit; wherein the first noise suppression circuit is configured to supply the third clock signal to the first electrode of the third transistor in response to the signal of the driver output terminal. [7] The shift register unit of claim 6, wherein the first noise suppression circuit comprises: a fourth transistor; wherein a control electrode of the fourth transistor is coupled to the driver output terminal, wherein a first electrode of the fourth transistor is configured to receive the third clock signal, and wherein a second electrode of the fourth transistor is coupled to the first electrode of the third transistor. [8] The shift register unit according to claim 6 or 7, wherein the first control circuit is coupled to the first electrode of the third transistor and a signal of the first electrode of the third transistor is the first control signal. [9] The shift register unit of any of claims 1-7, wherein the first control circuit is coupled to the first node and the signal of the first node is the first control signal. [10] A shift register unit according to any one of claims 1-9, wherein the output circuit comprises: a fifth transistor, a sixth transistor and a first capacitor; wherein a control electrode of the fifth transistor is coupled to the first node, wherein a first electrode of the fifth transistor is configured to receive the third clock signal, and wherein a second electrode of the fifth transistor is coupled to the driver output terminal; wherein a control electrode of the sixth transistor is coupled to the second node, wherein a first electrode of the sixth transistor is configured to receive the second reference signal, and wherein a second electrode of the sixth transistor is coupled to the driver output terminal; wherein a first electrode plate of the first capacitor is coupled to the first node, and wherein a second electrode plate of the first capacitor is coupled to the driver output terminal. [11] A shift register unit according to claim 10, wherein the output circuit further comprises: a second capacitor; wherein a first electrode plate of the second capacitor is coupled to the second node, and wherein a second electrode plate of the second capacitor is configured to receive the second reference signal. [12] The shift register unit of any of claims 1-11, wherein the shift register unit further comprises: a second control circuit; wherein the second control circuit is configured to provide the second reference signal to the first node in response to the signal of the second node. [13] A shift register unit according to claim 12, wherein the second control circuit comprises: a seventh transistor; wherein a control electrode of the seventh transistor is coupled to the second node, wherein a first electrode of the seventh transistor is configured to receive the second reference signal, and wherein a second electrode of the seventh transistor is coupled to the first node. [14] The shift register unit of claim 13, wherein the second control circuit further comprises: an eighth transistor; wherein the second electrode of the seventh transistor is coupled to the first node via the eighth transistor; wherein a control electrode of the eighth transistor is coupled to the second node, wherein a first electrode of the eighth transistor is coupled to the second electrode of the seventh transistor, and wherein a second electrode of the eighth transistor is coupled to the first node. [15] The shift register unit of claim 14, wherein the shift register unit further comprises: a second noise suppression circuit; wherein the second noise suppression circuit is configured to provide the first reference signal to the first electrode of the eighth transistor in response to the signal of the first node. [16] The shift register unit of claim 15, wherein the second noise suppression circuit comprises: a ninth transistor; wherein a control electrode of the ninth transistor is coupled to the first node, wherein a first electrode of the ninth transistor is configured to receive the first reference signal, and wherein a second electrode of the ninth transistor is coupled to the first electrode of the eighth transistor. [17] The shift register unit of any of claims 1-16, wherein the reset circuit comprises a tenth transistor; wherein a control electrode of the tenth transistor is configured to receive the second clock signal, wherein a first electrode of the tenth transistor is configured to receive the first reference signal, and wherein a second electrode of the tenth transistor is coupled to the second node. [18] A driver control circuit comprising a plurality of cascaded shift register units according to any one of claims 1-17; wherein an input signal of a first-stage shift register unit is provided by a frame trigger signal terminal; wherein, for shift register units of two adjacent stages, an input signal of a shift register unit of the next stage is provided by the driver output terminal of a shift register unit of the previous stage. [19] A display device comprising the driver control circuit according to claim 18. [20] A driving method for the shift register unit according to any one of claims 1-17, comprising: an input phase in which the input circuit provides the input signal to the first node in response to the first clock signal; the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal from the first node; an output phase in which the first control circuit provides the second clock signal to the second node in response to the first control signal; and the output circuit provides the third clock signal to the driver output terminal in response to the signal from the first node; a reset phase in which the reset circuit provides the first reference signal to the second node in response to the second clock signal; and the output circuit provides the second reference signal to the driver output terminal in response to the second node signal.

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