TECHNIQUES FOR COMPRESSING NEURAL NETWORKS

Abstract

Apparatus, systems, and techniques for compressing neural networks. In at least one embodiment, one or more first neural networks are used to cause one or more compressed neural networks to be selected based at least in part on the accuracy and performance of the one or more compressed neural networks.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates to processing resources used to perform and facilitate artificial intelligence. For example, at least one embodiment relates to processors or computing systems used to compress neural networks according to various novel techniques described herein. BACKGROUND

[0002] To achieve high accuracy, neural networks can consume significant memory, time, or computational resources when deployed on a processing unit. In many cases, compression of neural networks may be desirable to reduce their accuracy in exchange for better performance. Techniques used to compress neural networks can therefore be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a system for compressing a neural network according to at least one embodiment; Fig. 2 illustrates another example of a system for compressing a neural network according to at least one embodiment; Fig. 3 illustrates an example flowchart for a neural network compression process according to at least one embodiment; Fig. 4 illustrates another example of a flowchart for a process of compressing a neural network according to at least one embodiment; Fig. 5 illustrates an example of target performance and target accuracy for a compressed neural network according to at least one embodiment; Fig. 6 illustrates an example of initial performance and accuracy policies according to at least one embodiment; Fig. 7 illustrates an example of updated performance and accuracy policies according to at least one embodiment; Fig. 8A illustrates logic according to at least one embodiment; Fig. 8B illustrates logic according to at least one embodiment; Fig. 9 illustrates training and deployment of a neural network according to at least one embodiment; Fig. 10 illustrates an exemplary data center system according to at least one embodiment; Fig. 11A illustrates an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 11B illustrates an example of camera positions and fields of view for the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. Figure 11C is a block diagram illustrating an example system architecture for the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. 11D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 14 illustrates a computer system according to at least one embodiment; Fig. 15 illustrates a computer system according to at least one embodiment; Fig. 16A illustrates a computer system according to at least one embodiment; Fig. 16B illustrates a computer system according to at least one embodiment; Fig. 16C illustrates a computer system according to at least one embodiment; Fig. 16D illustrates a computer system according to at least one embodiment; Fig. 16E and Fig. 16F illustrate a shared programming model according to at least one embodiment; Fig. 17 illustrates example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 18A and Fig. 18B illustrate example integrated circuits and associated graphics processors according to at least one embodiment; Fig. 19A and Fig. 19B illustrate additional example graphics processor logic according to at least one embodiment; Fig. 20 illustrates a computer system according to at least one embodiment; Fig. 21A illustrates a parallel processor according to at least one embodiment; Fig. 21B illustrates a partition unit according to at least one embodiment; Fig. 21C illustrates a processing cluster according to at least one embodiment; Fig. 21D illustrates a graphics multiprocessor according to at least one embodiment; Fig. 22 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment; Fig. 23 illustrates a graphics processor according to at least one embodiment; Fig. 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 25 illustrates a deep learning application processor according to at least one embodiment; Fig. 26 is a block diagram illustrating an example neuromorphic processor according to at least one embodiment; Fig. 27 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 28 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 29 illustrates at least portions of a graphics processor according to one or more embodiments; Fig. 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 31 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 32A and Fig. 32B illustrate thread execution logic including an arrangement of processing elements of a graphics processor core, according to at least one embodiment; Fig. 33 illustrates a parallel processing unit ("PPU") according to at least one embodiment; Fig. 34 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. 35 illustrates a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment; Fig. 36 illustrates a streaming multiprocessor according to at least one embodiment. Fig. 37 is an example data flow diagram for an advanced compute pipeline according to at least one embodiment; Fig. 38 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced compute pipeline, according to at least one embodiment; Fig. 39 includes an exemplary illustration of an advanced compute pipeline 3810A for processing imaging data in accordance with at least one embodiment; Fig. 40A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 40B includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment; Fig. 41A illustrates a data flow diagram for a process for training a machine learning model according to at least one embodiment; and Fig. 41B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION

[0003] Fig. 1 illustrates an example of a neural network compression system 100 according to at least one embodiment. In at least one embodiment, the system 100 includes a neural network 102, a neural network compression system 104, a compressed neural network 106, and a processing unit 108. In at least one embodiment, the neural network compression system 104 receives a neural network 102 and determines a compressed neural network 106. In at least one embodiment, the compressed neural network 106 is deployed on a processing unit 108. In at least one embodiment, the neural network compression system 104 receives results of deploying the compressed neural network 106 on a processing unit 108 for further processing.In at least one embodiment, the neural network compression system 104 updates one or more compression configurations using metrics associated with deployment of the compressed neural network 106 on a processing device 108.

[0004] In at least one embodiment, a neural network 102 is a convolutional neural network (CNN). In at least one embodiment, a neural network 102 is one or more neural networks as part of one or more vehicle systems, medical imaging systems, satellite imaging systems, and / or variations thereof.In at least one embodiment, a neural network 102 is a neural network such as those of various neural network models, such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), and / or variations thereof. In at least one embodiment, a neural network 102 is implemented by one or more data objects and / or data structures that encode information of the neural network 102.In at least one embodiment, a neural network 102 is implemented by one or more data structures, such as one or more arrays, lists, and / or trees, that encode weights, biases, and structural connections (e.g., architecture(s) and / or configuration(s) of one or more neurons) of the neural network. In at least one embodiment, a neural network 102 is defined by a structure of neural network neurons and neural network weights.

[0005] In at least one embodiment, a neural network compression system 104 is a collection of one or more hardware and / or software computational resources having instructions that, when executed, compress one or more neural networks to achieve target performance and accuracy. In at least one embodiment, a neural network compression system 104 is a software program executing on computer hardware, an application executing on computer hardware, and / or variations thereof. In at least one embodiment, one or more processes of a neural network compression system 104 are executed by any suitable processing system or device (e.g.,Graphics processing unit (GPU), parallel processing unit (PPU), central processing unit (CPU)), and in any suitable manner, including sequential, parallel, and / or variations thereof. In at least one embodiment, a neural network compression system 104 includes one or more neural networks trained to compress neural networks.

[0006] In at least one embodiment, a neural network compression system 104 is a software module of one or more computing systems onboard one or more devices or systems, such as a vehicle (e.g., a manual vehicle, a semi-autonomous vehicle, an autonomous vehicle, or a drone), a robot, an edge device, or other system with neural network capabilities. In at least one embodiment, an edge device refers to a computing device such as a mobile phone, a tablet, a laptop, an Internet of Things (IoT) device (e.g., sensors, embedded devices), and / or variations thereof. In at least one embodiment, an edge device is a computing device with limited memory and / or limited processing capabilities.In at least one embodiment, one or more computing systems, such as a server or data center system, use a neural network compression system 104 to compress neural networks and deploy compressed neural networks to edge devices, where the edge devices perform various neural network functions using the compressed neural networks. In at least one embodiment, a computing system uses a neural network compression system 104 to compress a neural network 102 to determine a compressed neural network 106 and transmit the compressed neural network 106 to one or more edge devices so that the one or more edge devices can use the compressed neural network 106 to perform various neural network functions.

[0007] In at least one embodiment, a neural network compression system 104 corresponds to those used in connection with Fig. 2 are described.

[0008] In at least one embodiment, a compressed neural network 106 is a convolutional neural network (CNN). In at least one embodiment, the compressed neural network 106 is a series of compressed neural networks, each with different targeting accuracy and targeting performance. In at least one embodiment, a compressed neural network 106 is one or more neural networks as part of one or more vehicle systems, medical imaging systems, satellite imaging systems, and / or variations thereof.In at least one embodiment, a compressed neural network 106 is a neural network such as those of various neural network models, such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), a Boltzmann machine (BM), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a deep convolutional network (DCN), an extreme learning machine (ELM), a deep residual network (DRN), and / or variations thereof. In at least one embodiment, a compressed neural network 106 is implemented by one or more data objects and / or data structures that encode information of the compressed neural network 106.In at least one embodiment, a compressed neural network 106 is implemented by one or more data structures, such as one or more arrays, lists, and / or trees, that encode weights, biases, and structural connections (e.g., architecture(s) and / or configuration(s) of one or more neurons) of the neural network. In at least one embodiment, a compressed neural network 106 is defined by a structure of neural network neurons and neural network weights.

[0009] In at least one embodiment, a compressed neural network 106 is obtained by compressing a neural network 102 using a neural network compression system 104. In at least one embodiment, the compressed neural network 106 is reduced in size compared to the neural network 102. In at least one embodiment, the compressed neural network 106 has lower accuracy compared to the neural network 102. In at least one embodiment, the compressed neural network 106 has higher performance compared to the neural network 102.

[0010] In at least one embodiment, the compressed neural network 106 is deployed on a processing unit 108. The processing unit 108 is any suitable processing system or processing unit, such as a graphics processing unit (GPU), parallel processing unit (PPU), central processing unit (CPU), and in any suitable manner, including sequential, parallel, and / or variations thereof.

[0011] Fig. Figure 2 illustrates another example of a neural network compression system 200 according to at least one embodiment. In at least one embodiment, system 200 includes a neural network compression system 104. In at least one embodiment, neural network compression system 104 includes a reinforcement learning model 202. In at least one embodiment, reinforcement learning model 202 is a trainable neural network.

[0012] In at least one embodiment, reinforcement learning model 202 processes a performance policy 208 and an accuracy policy 210. In at least one embodiment, performance refers to the operational performance of a neural network on a processing unit, such as speed, power consumption, and / or variations thereof. In at least one embodiment, a policy specifies a plurality of layer metrics associated with compressing each of a plurality of layers within a neural network 102. In at least one embodiment, layer metrics include, but are not limited to, accuracy level, inference speed, power consumption, and / or variations thereof. In at least one embodiment, layer metrics may be expressed as a fraction and / or percentage of layer metrics in a corresponding uncompressed layer.In at least one embodiment, a performance policy 208 includes layer metrics associated with performance, and an accuracy policy 210 includes layer metrics associated with accuracy. In at least one embodiment, a policy includes compression configurations, such as sparsity ratio and / or data format. In at least one embodiment, a policy includes a processing unit for deploying an appropriate neural network, such as a specific type of GPU. For example, an entry of a performance policy 208 may be that compressing the #4 convolutional layer with 50% sparsity and FP16 data format can maintain the accuracy level of 0.997. In at least one embodiment, the performance policy 208 and the accuracy policy 210 correspond to those described in connection with. Fig. 6-7 are described.

[0013] In at least one embodiment, the performance simulator 204 initializes 211 a performance policy 208. In at least one embodiment, the accuracy simulator 206 initializes 211 an accuracy policy 210. In at least one embodiment, the performance simulator 204 and / or the accuracy simulator 206 is a neural network. In at least one embodiment, initializing 211 refers to estimating policies based on a prediction of the accuracy and performance of layers within a neural network 102 after compression. In at least one embodiment, initializing 211 may be performed based on historical data.

[0014] In at least one embodiment, reinforcement learning model 202 determines a combination strategy 212. In at least one embodiment, combination strategy 212 is a compression strategy of layers within neural network 102 determined based on performance policy 208 and accuracy policy 210. In at least one embodiment, combination strategy 212 includes a plurality of compression configurations corresponding to a plurality of layers within neural network 102. In at least one embodiment, each compression configuration within combination strategy 212 defines compression parameters of a corresponding layer. In at least one embodiment, compression parameters include, but are not limited to, sparsity ratio, data format, and / or variations thereof.In at least one embodiment, compression parameters are defined by layer metrics in the performance policy 208 and / or the accuracy policy 210. In at least one embodiment, the combination strategy 212 is a combination of compression configurations of each layer within a neural network 102 such that when each layer is compressed according to its corresponding compression configuration, the compressed neural network 106 achieves target performance and accuracy.

[0015] In at least one embodiment, the combination strategy 212 is determined based on a plurality of target metrics of the compressed neural network 106. In at least one embodiment, target metrics are predetermined accuracy and / or performance targets for the compressed neural network 106. In at least one embodiment, target metrics include both target accuracy metrics and target performance metrics of the compressed neural network 106. In at least one embodiment, target metrics are a list of different target accuracy and target performance of a plurality of compressed neural networks. In at least one embodiment, target metrics include, but are not limited to, accuracy level, inference speed, power consumption, and / or variations thereof.In at least one embodiment, target metrics include one or more processing units for deploying the compressed neural network 106 on, such as a specific type of GPU. For example, target metrics may include a compressed ResNet50 model with a 95% accuracy level, 150% inference speed, and 98% power consumption on the V100 GPU compared to the original compressed model. In at least one embodiment, target metrics correspond to those described in connection with [the text]. Fig. 5 are described.

[0016] In at least one embodiment, reinforcement learning model 202 processes deployment performance and accuracy metrics 214 to update 215 the performance policy 208 and the accuracy policy 210. In at least one embodiment, deployment performance and accuracy metrics 214 are obtained by deploying a compressed neural network 106 on a processing unit 108. In at least one embodiment, deployment performance and accuracy metrics 214 are actual accuracy and performance of the compressed neural network 106 on a processing unit 108. In at least one embodiment, reinforcement learning model 202 compares deployment performance and accuracy metrics 214 and target performance and accuracy metrics of the compressed neural network 106 and uses comparison results to update 215 the previously used performance policy 208 and the accuracy policy 210.In at least one embodiment, updating 215 refers to changing one or more layer metrics of one or more layers in the performance policy 208 and / or the accuracy policy 210 so that updated policies better reflect the actual impact on accuracy and / or performance of different compression configurations of each layer. In at least one embodiment, updated policies are used to determine an improved combining strategy 212. For example, one entry of a performance policy 208 is that compressing the #4 convolutional layer with 50% sparsity and FP16 data format can maintain the accuracy level of 0.997 on a V100 GPU, and the target accuracy level of the compressed neural network 106 is also set to 0.997, so for simplicity, the combining strategy 212 only compresses the #4 convolutional layer.4-convolutional layers with 50% sparsity and FP16 data format, and all other layers can be left as they are. After compressing the neural network 102 according to this strategy and deploying the compressed neural network 106 on the V100 GPU, deployment performance and accuracy metrics 214 are collected to indicate that the actual accuracy of the compressed neural network 106 is 0.9975, as opposed to the target accuracy of 0.997. As a result, the reinforcement learning model 202 can update 215 the performance policy 208 to show that compressing the No. 4 convolutional layer with 50% sparsity and FP16 data format can maintain the accuracy level of 0.9975 on a V100 GPU, and also update the combination strategy 212 because compressing only the No.4-convolutional layer with 50% sparsity and FP 16 data format and leaving all other layers as they are can no longer achieve a target accuracy level of 0.997.

[0017] In at least one embodiment, system 200 improves the overall accuracy and performance capability of compressed neural networks, such as Pareto optimality of compressed neural networks. In at least one embodiment, system 200 achieves both the desired performance and accuracy in a compressed neural network simultaneously without requiring additional steps. In at least one embodiment, system 200 can be applied to various GPU configurations, performance metrics, and model compression methods, thereby increasing the flexibility of neural network compression techniques. In at least one embodiment, system 200 improves compression efficiency through training by refining the compression strategy using outputs from the previous iteration.In at least one embodiment, the system 200 may generate a number of compressed neural networks with different accuracy and performance as candidates and easily compare them to determine which compressed model has the highest Pareto optimality, thereby making the selection of the compression strategy easier and more efficient.

[0018] Fig. 3 illustrates an example flowchart for a neural network compression process 300 according to at least one embodiment. In at least one embodiment, part or all of the process 300 (or any other processes described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that executes collectively on one or more processors by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors.In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable for performing process 300 are not stored exclusively using transient signals (e.g., propagating transient electrical or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transient signals. In at least one embodiment, process 300 is performed at least in part on a computer system such as those described elsewhere in this disclosure.In at least one embodiment, process 300 is performed by one or more systems such as those described in connection with. Fig. 1-2 are described.

[0019] In at least one embodiment, a system that performs at least a portion of process 300 includes executable code for inputting a neural network 302. In at least one embodiment, the neural network to be input is a compressed neural network. In at least one embodiment, the neural network is input to the neural network compression system 104 for further processing.

[0020] In at least one embodiment, a system that performs at least a portion of process 300 includes executable code for determining target performance and target accuracy 304. In at least one embodiment, the target performance and target accuracy are determined by Pareto optimality. In at least one embodiment, the target performance and target accuracy with the highest Pareto optimality are selected. In at least one embodiment, the target performance and target accuracy are target metrics according to those used in connection with Fig. 2. In at least one embodiment, determining the target performance and the target accuracy is used to select one or more compressed neural networks. In at least one embodiment, the target performance and the target accuracy are target metrics associated with one or more compressed neural networks selected by one or more users.

[0021] In at least one embodiment, a system that performs at least a portion of the process 300 includes executable code for obtaining the performance policy and the accuracy policy 306. In at least one embodiment, the performance policy and the accuracy policy correspond to those used in connection with Fig. 2. In at least one embodiment, the performance policy and the accuracy policy are initialized by simulators based on experience and / or historical data. In at least one embodiment, the performance policy and the accuracy policy are obtained by updating initialized policies based on actual accuracy and performance data.

[0022] In at least one embodiment, a system that performs at least a portion of the process 300 includes executable code for determining the combination strategy 308. In at least one embodiment, the combination strategy corresponds to those used in connection with Fig. 2. In at least one embodiment, the combination strategy is a combination of portions of the performance policy and the accuracy policy.

[0023] In at least one embodiment, a system that performs at least a portion of process 300 includes executable code for compressing neural network 310. In at least one embodiment, the neural network to be compressed is the neural network input to block 302. In at least one embodiment, the neural network is compressed using the combination strategy determined in block 308. In at least one embodiment, the compressed neural network is smaller in size compared to the input neural network. In at least one embodiment, the neural network is compressed using techniques including, but not limited to, pruning, quantization, low-rank approximation and sparsity, knowledge distillation, neural architecture search (NAS), and / or variations thereof.

[0024] In at least one embodiment, a system that performs at least a portion of process 300 includes executable code for deploying compressed neural network 312. In at least one embodiment, the compressed neural network is deployed on a processing unit 108, such as a GPU.

[0025] In at least one embodiment, a system that performs at least a portion of process 300 includes executable code for obtaining the deployment performance and deployment accuracy 314 of the compressed neural network. In at least one embodiment, the deployment performance and deployment accuracy correspond to deployment performance and accuracy metrics 214 according to those described in connection with Fig. 2. In at least one embodiment, the deployment performance and deployment accuracy indicate the actual performance and accuracy of the compressed neural network when deployed on a specific processing unit. In at least one embodiment, the deployment performance and deployment accuracy are compared to the target performance and target accuracy determined in block 304 for further processing.

[0026] Fig. 4 illustrates another example of a flowchart for a neural network compression process 400 according to at least one embodiment. In at least one embodiment, part or all of the process 400 (or any other processes described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that executes collectively on one or more processors by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors.In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable for performing process 400 are not stored exclusively using transient signals (e.g., propagating transient electrical or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transient signals. In at least one embodiment, process 300 is performed at least in part on a computer system such as those described elsewhere in this disclosure.In at least one embodiment, process 400 is performed by one or more systems such as those described in connection with. Fig. 1-2 are described.

[0027] In at least one embodiment, a system that performs at least a portion of process 400 includes executable code to initialize the performance policy and the accuracy policy 402. In at least one embodiment, the initialization of the performance policy and the accuracy policy corresponds to those described in connection with Fig. 2 are described.

[0028] In at least one embodiment, a system performing at least a portion of process 400 includes executable code for compressing the neural network based on the performance policy and the accuracy policy 404. In at least one embodiment, a combination strategy is determined from the performance policy and the accuracy policy, and the neural network is compressed using the combination strategy. In at least one embodiment, the performance policy and the accuracy policy include a list of layer metrics associated with each layer of the neural network that indicate the accuracy and performance of each layer under various compression configurations and / or processing units to be deployed.In at least one embodiment, the combination strategy includes a selection of compression configurations for one or more layers such that the overall performance and accuracy of the compressed neural network meet expectations.

[0029] In at least one embodiment, a system that performs at least a portion of process 400 includes executable code for testing the compressed neural network on a processing device 406. In at least one embodiment, testing consists of deploying the compressed neural network on a specific processing device and collecting metrics associated with its actual accuracy and performance.

[0030] In at least one embodiment, a system that performs at least a portion of process 400 includes executable code for detecting whether target performance and accuracy are met 408. In response to detecting that target performance and accuracy are not met, the process is performed in block 410. In response to detecting that target performance and accuracy are met, the process is performed in block 412. In at least one embodiment, process 400 iterates based on whether target performance and accuracy are met and stops iterating until target performance and accuracy are met. In at least one embodiment, it may be determined that target performance and accuracy are not achievable, and the iteration may therefore be terminated manually and / or automatically.In at least one embodiment, the maximum number of iterations may be preset, and the compressed neural network with the closest actual performance and / or accuracy to the target performance and / or accuracy may be obtained in the process in block 412.

[0031] In at least one embodiment, a system that performs at least a portion of process 400 includes executable code for updating the performance policy and the accuracy policy with collected deployment performance and accuracy metrics 410. Updating the performance policy and the accuracy policy corresponds to those described in Fig. 2. The collected performance and accuracy metrics correspond to those described in Fig. 3. In at least one embodiment, after completing the process in block 410, the process 400 returns to the process in block 404 to start the next iteration.

[0032] Fig. Figure 5 illustrates an example 500 of target performance and accuracy for compressed neural networks, according to at least one embodiment. The example 500 is based on a compressed ResNet50 model with accuracy level ACC and inference speed S_inf on the V100 GPU. A number of compressed ResNet50 models with different sparsity ratios and / or data formats may be required to meet different deployment criteria, as follows:

[0033] A compressed ResNet50 model with accuracy level: 0.95 * ACC, inference speed: 1.50 * S_inf and 98% power consumption on the V100 GPU;

[0034] A compressed ResNet50 model with accuracy level: 0.95 * ACC, inference speed: 1.75 * S_inf and 95% power consumption on the A100 GPU;

[0035] A compressed ResNet50 model with accuracy level: 0.95 * ACC, inference speed: 2.15 * S_inf and 90% power consumption on the H100 GPU;

[0036] A compressed ResNet50 model with accuracy level: 0.90 * ACC, inference speed: 1.60 * S_inf and 96% power consumption on the V100 GPU;

[0037] A compressed ResNet50 model with accuracy level: 0.90 * ACC, inference speed: 1.95 * S_inf and 93% power consumption on the A100 GPU;

[0038] A compressed ResNet50 model with accuracy level: 0.90 * ACC, inference speed: 2.30 * S_inf and 88% power consumption on the H100 GPU;

[0039] A compressed ResNet50 model with accuracy level: 0.85 * ACC, inference speed: 1.80 * S_inf and 94% power consumption on the V100 GPU;

[0040] A compressed ResNet50 model with accuracy level: 0.85 * ACC, inference speed: 2.20 * S_inf and 90% power consumption on the A100 GPU;

[0041] A compressed ResNet50 model with accuracy level: 0.85 * ACC, inference speed: 2.50 * S_inf, and 85% power consumption on the H100 GPU; and so on.

[0042] As in Fig. As shown in Figure 5, in each example entry of target performance and target accuracy, the accuracy level, inference speed, and power consumption of a corresponding compressed ResNet50 model are expressed as a fraction or percentage of that of the compressed ResNet50 model. The processing unit required to deploy the compressed ResNet50 model is also specified in each example entry. To achieve the target performance and target accuracy of an entire model, correct and accurate compression of each layer of the model is required. Information about the performance and accuracy impact of compressing each layer is provided in the accuracy policy and performance policy.

[0043] Fig. Figure 6 illustrates an example 600 of initial performance and accuracy policies according to at least one embodiment. Example 600 estimates the impact on accuracy and performance of various compression configurations of Layer 4 and Layer 5 as follows:

[0044] Compressing the No. 4 convolutional layer with 50% sparsity and FP16 data format can keep the accuracy level of 0.997, get inference speedup for one layer: 1.7X and consume 58% power for one layer on the V100 GPU;

[0045] Compressing the No. 4 convolutional layer without sparsity and INT8 data format can keep the accuracy level of 0.999, get inference speedup for one layer: 1.8X and consume 65% power for one layer on the V100 GPU;

[0046] Compressing the No. 5 convolutional layer with 50% sparsity and FP16 data format can keep the accuracy level of 0.995, get inference speedup for one layer: 1.6X and consume 60% power for one layer on the V100 GPU;

[0047] Compressing the No. 5 convolutional layer with 75% sparsity and INT8 data format can maintain the accuracy level of 0.998, obtain inference acceleration for one layer: 1.9X and consume 50% power for one layer on the V100 GPU; and so on.

[0048] As in Fig. As shown in Figure 6, in each example entry, the impact of an initial policy on the accuracy level of the entire model, the impact on the inference speed of the corresponding layer, and the power consumption of a corresponding layer are expressed as a fraction or percentage of that of the compressed ResNet50 model. Compression parameters, such as sparsity and data format, as well as a processing unit for deploying the compressed ResNet50 model, are also specified in each example entry. In at least one embodiment, the impact of compressing a layer on accuracy and performance can be expressed with respect to the entire model and can also be expressed with respect to the layer.For example, in Example 600, impacts on the accuracy level are expressed in terms of the ResNet50 model, while impacts on inference acceleration and power consumption are expressed in terms of a layer.

[0049] Fig. Figure 7 illustrates an example of updated performance and accuracy policies according to at least one embodiment. Example 700 illustrates updated impacts on accuracy and performance of various Layer 4 and Layer 5 compression configurations after actual deployment, as follows:

[0050] Compressing the No. 4 convolutional layer with 50% sparsity and FP16 data format can keep the accuracy level of 0.9975, get inference speedup for one layer: 1.45X and consume 65% power for one layer on the V100 GPU;

[0051] Compressing the No. 4 convolutional layer without sparsity and INT8 data format can keep the accuracy level of 0.9995, get inference speedup for one layer: 1.96X and consume 63% power for one layer on the V100 GPU;

[0052] Compressing the No. 5 convolutional layer with 50% sparsity and FP16 data format can keep the accuracy level of 0.9945, get inference speedup for one layer: 1.55X and consume 70% power for one layer on the V100 GPU;

[0053] Compressing the No. 5 convolutional layer with 75% sparsity and INT8 data format can maintain the accuracy level of 0.9985, obtain inference acceleration for one layer: 2.02X and consume 54% power for one layer on the V100 GPU; and so on.

[0054] As in Fig. 6 and Fig. For example, as shown in Figure 7, when compressing the No. 4 convolutional layer with 50% sparsity and FP16 data format, the expected impact on the accuracy level changes from 0.997 to 0.9975, indicating that initial policies overestimate the impact of compressing the No. 4 layer on accuracy using given configurations. LOGIC

[0055] Fig. 8A illustrates logic 815, which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein, according to at least one embodiment. In at least one embodiment, logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is inference and / or training logic. Details regarding logic 815 are described below in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, where logic, collectively or individually, may be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0056] In at least one embodiment, logic 815 may include, without limitation, code and / or data storage 801 for storing feedforward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 for storing graph code or other software for controlling timing and / or sequencing, into which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data of each neural network layer trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0057] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 801 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, a choice of whether code and / or data storage 801 is, for example, internal or external to a processor or comprises DRAM, SRAM, Flash, or another memory type may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inferencing functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0058] In at least one embodiment, logic 815 may include, without limitation, a code and / or data storage 805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 805 stores weight parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 805 for storing graph code or other software for controlling timing and / or sequencing, into which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0059] In at least one embodiment, code, such as graph code, causes weight or other parameter information to be loaded into processor ALUs based on a neural network architecture to which that code corresponds. In at least one embodiment, any portion of code and / or data memory 805 may be included with other on-chip or off-chip data memory, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data memory 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data memory 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, a choice of whether code and / or data storage 805 is, for example, internal or external to a processor or comprises DRAM, SRAM, Flash, or another memory type may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inferencing functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0060] In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be separate memory structures. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be a combined memory structure. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data memory 801 and code and / or data memory 805 may be included with other on-chip or off-chip data memory, including a processor's L1, L2, or L3 cache or system memory.

[0061] In at least one embodiment, logic 815 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 810, including integer and / or floating-point units, to perform logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g., graph code), a result of which may generate activations (e.g., output values ​​of layers or neurons within a neural network) stored in an activation memory 820 that are functions of input / output and / or weight parameter data stored in code and / or data memory 801 and / or code and / or data memory 805.In at least one embodiment, activations stored in activation memory 820 are generated according to linear algebraic and / or matrix-based mathematics performed by ALU(s) 810 in response to the execution of instructions or other code, wherein weight values ​​stored in code and / or data memory 805 and / or data memory 801 are used as operands along with other values, such as deviation values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 805 or code and / or data memory 801 or other on-chip or off-chip memory.

[0062] In at least one embodiment, ALU(s) 810 are included in one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 810 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, ALU(s) 810 may be included in the execution units of a processor or otherwise included in a bank of ALUs that are accessible by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed-function units, etc.).In at least one embodiment, code and / or data memory 801, code and / or data memory 805, and enable memory 820 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or a combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of enable memory 820 may be included with other on-chip or off-chip data memory, including a processor's L1, L2, or L3 cache or system memory.Furthermore, inference and / or training code may be stored with other code that is accessible by a processor or other hardware logic or circuitry and that is retrieved and / or processed using the fetch, decode, scheduling, execution, retirement, and / or other logic circuitry of a processor.

[0063] In at least one embodiment, activation memory 820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 820 may be entirely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, a choice of whether activation memory 820 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash, or another memory type, may depend on available on-chip versus off-chip memory, latency requirements of trained and / or inferencing functions being performed, batch size of data used in inference and / or training of a neural network, or a combination of these factors.

[0064] In at least one embodiment, the Fig. 8A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., “Lake Crest”) from Intel Corp. In at least one embodiment, the logic 815 illustrated in Fig. 8A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0065] Fig. 8B illustrates logic 815 according to at least one embodiment. In at least one embodiment, logic 815 is inference and / or training logic. In at least one embodiment, logic 815 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise used exclusively in connection with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic illustrated in Fig. 8B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., “Lake Crest”) from Intel Corp. In at least one embodiment, the logic 815 illustrated in Fig. 8B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 815 includes, without limitation, code and / or data storage 801 and code and / or data storage 805, which may be used to store code (e.g., graph code), weight values, and / or other information, including deviation values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, Fig. 8B, each of code and / or data memory 801 and code and / or data memory 805 is associated with a dedicated computing resource, such as computing hardware 802 and computing hardware 806, respectively. In at least one embodiment, each of computing hardware 802 and computing hardware 806 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data memory 801 and code and / or data memory 805, respectively, the result of which is stored in activation memory 820.

[0066] In at least one embodiment, each of code and / or data memory 801 and 805, or corresponding compute hardware 802 and 806, corresponds to different layers of a neural network, such that the resulting activation from one memory / compute pair 801 / 802 of code and / or data memory 801 and compute hardware 802 is provided as an input to a next memory / compute pair 805 / 806 of code and / or data memory 805 and compute hardware 806 to mirror a conceptual organization of a neural network. In at least one embodiment, each of memory / compute pairs 801 / 802 and 805 / 806 may correspond to more than one layer of a neural network. In at least one embodiment, additional memory / compute pairs (not shown) may be included after or in parallel with memory / compute pairs 801 / 802 and 805 / 806 in logic 815. TRAINING AND DEPLOYMENT OF NEURAL NETWORKS

[0067] Fig. 9 illustrates training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, the untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is a PyTorch framework, whereas in other embodiments, the training framework 904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or another training framework. In at least one embodiment, the training framework 904 trains an untrained neural network 906 and allows it to be trained using processing resources described herein to generate a trained neural network 908. In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be performed in either a supervised, semi-supervised, or unsupervised manner.

[0068] In at least one embodiment, the untrained neural network 906 is trained using supervised learning, where the training data set 902 includes an input paired with a desired output for an input, or where the training data set 902 includes an input with a known output and an output of the neural network 906 is manually ranked. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner and processes inputs from the training data set 902 and compares resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts weights that control the untrained neural network 906.In at least one embodiment, the training framework 904 includes tools to monitor how well the untrained neural network 906 converges on a model, such as the trained neural network 908, capable of generating correct answers, such as in the result 914, based on input data, such as a new dataset 912. In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting weights to refine an output of the untrained neural network 906 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 achieves a desired accuracy.In at least one embodiment, the trained neural network 908 may then be used to implement any number of machine learning operations.

[0069] In at least one embodiment, the untrained neural network 906 is trained using unsupervised learning, where the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 902 for unsupervised learning includes input data without associated output data or ground truth data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and can determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, the unsupervised training can be used to generate a self-organizing map in the trained neural network 908 capable of performing operations useful for reducing the dimensionality of the new dataset 912.In at least one embodiment, the unsupervised training may also be used to perform anomaly detection, which enables identification of data points in the new data set 912 that deviate from normal patterns of the new data set 912.

[0070] In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training dataset 902 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 904 may be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 908 to adapt to the new dataset 912 without forgetting knowledge embedded in the trained neural network 908 during initial training.

[0071] In at least one embodiment, the training framework 904 is a framework processed in conjunction with a software development toolkit, such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as those developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein.

[0072] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0073] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image inking, style transfer, action recognition, colorization, and / or variations thereof.

[0074] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various neural network operations, such as modifying inputs to a model (e.g., changing the size of inputs to a model), modifying a size of inputs of a model (e.g., modifying a batch size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as an integer), and / or variations thereof.

[0075] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or any suitable programming language library. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and produce one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.

[0076] In at least one embodiment, OpenVINO provides various capabilities for heterogeneously executing one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to execute a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA.In at least one embodiment, Open VINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0077] In at least one embodiment, OpenVINO includes various functionalities similar to functionalities associated with a CUDA programming model, such as various operations of neural network models associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more operations of CUDA programming models are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0078] Fig. 10 illustrates an example data center 1000 in which at least one embodiment may be used. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0079] In at least one embodiment, as in Fig. 10, the data center infrastructure layer 1010 may include a resource orchestrator 1012, clustered compute resources 1014, and node compute resources (“node CRs”) 1016(1)-1016(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more node CRs may be selected from the node CRs 1016(1)-1016(N) may be a server that has one or more of the computing resources listed above.

[0080] In at least one embodiment, the grouped computing resources 1014 may include separate groupings of node CRs housed in one or more racks (not shown) or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped computing resources 1014 may include grouped computing, networking, storage, or memory resources that may be configured or assigned to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped in one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0081] In at least one embodiment, resource orchestrator 1012 may configure or otherwise control one or more node CRs 1016(1)-1016(N) and / or clustered computing resources 1014. In at least one embodiment, resource orchestrator 1012 may include a software design infrastructure ("SDI") management entity for data center 1000. In at least one embodiment, resource orchestrator 1012 may include hardware, software, or a combination thereof.

[0082] In at least one embodiment, as in Fig. 10, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework to support software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or application(s) 1042 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be some type of free and open source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may use the distributed file system 1028 for large-scale data processing (e.g., "Big Data").In at least one embodiment, job scheduler 1022 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 1000. In at least one embodiment, configuration manager 1024 may be capable of configuring various layers, such as software layer 1030 and framework layer 1020, including Spark and distributed file system 1028, to support large-scale computing. In at least one embodiment, resource manager 1026 may be capable of managing clustered or grouped compute resources mapped to or allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, clustered or grouped compute resources may include grouped compute resources 1014 on data center infrastructure layer 1010.In at least one embodiment, the resource manager 1026 may coordinate with the resource orchestrator 1012 to manage these mapped or allocated compute resources.

[0083] In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least portions of the node CRs 1016(1)-1016(N), the clustered computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet website search software, email virus scanning software, database software, and streaming video content software.

[0084] In at least one embodiment, the application(s) 1042 included in the application layer 1040 may include one or more types of applications used by at least portions of the node CRs 1016(1)-1016(N), the clustered computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0085] In at least one embodiment, any of configuration manager 1024, resource manager 1026, and resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 1000 from making potentially poor configuration decisions and potentially avoid underutilized and / or poorly performing parts of a data center.

[0086] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 1000.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 1000 by using weighting parameters calculated by one or more training techniques described herein.

[0087] In at least one embodiment, the data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0088] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 10 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0089] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments. AUTONOMOUS VEHICLE

[0090] Fig. 11A illustrates an example of an autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1100 may be a tractor-trailer truck used to transport cargo. In at least one embodiment, the vehicle 1100 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0091] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of that standard). In at least one embodiment, the vehicle 1100 may be capable of operating according to one or more of Levels 1 through 5 of the autonomous driving levels. For example, in at least one embodiment, the vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0092] In at least one embodiment, vehicle 1100 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1100 may include, without limitation, a propulsion system 1150 such as an internal combustion engine, a hybrid electric power plant, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to a drivetrain of vehicle 1100, which may include, without limitation, a transmission, to enable propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving signals from throttle(s) 1152.

[0093] In at least one embodiment, a steering system 1154, which may include, without limitation, a steering wheel, is used to steer the vehicle 1100 (e.g., along a desired path or route) when the propulsion system 1150 is operating (e.g., when the vehicle 1100 is in motion). In at least one embodiment, the steering system 1154 may receive signals from steering actuator(s) 1156. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1146 may be used to apply vehicle brakes in response to receiving signals from brake actuator(s) 1148 and / or brake sensors.

[0094] In at least one embodiment, the controller(s) 1136, which may include, without limitation, one or more system-on-chips (“SoCs”) (in Fig. 11A not shown) and / or graphics processing unit(s) ("GPU(s)"), provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, the controller(s) 1136 may send signals to apply vehicle brakes via brake actuator(s) 1148, to actuate the steering system 1154 via steering actuator(s) 1156, to actuate the propulsion system 1150 via throttle / accelerator pedal(s) 1152. In at least one embodiment, the controller(s) 1136 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving the vehicle 1100.In at least one embodiment, the controller(s) 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0095] In at least one embodiment, the controller(s) 1136 provide signals to control one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be obtained, for example and without limitation, from Global Navigation Satellite System ("GNSS") sensor(s) 1158 (e.g., Global Positioning System sensor(s), RADAR sensor(s) 1160, Ultrasonic sensor(s) 1162, LIDAR sensor(s) 1164, Inertial Measurement Unit ("IMU") sensor(s) 1166 (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s) 1196, stereo camera(s) 1168, wide-view camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, Surround camera(s) 1174 (e.g.360-degree cameras), long-range cameras (not in . Fig. 11A), a medium-range camera(s) (not shown in Fig. 11A), (a) speed sensor(s) 1144 (e.g., for measuring the speed of the vehicle 1100), (a) vibration sensor(s) 1142, (a) steering sensor(s) 1140, (a) brake sensor(s) (e.g., as part of the brake sensor system 1146), and / or other types of sensors.

[0096] In at least one embodiment, one or more of the controller(s) 1136 may receive inputs (e.g., represented by input data) from an instrument cluster 1132 of the vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface ("HMI") display 1134, an audible annunciator, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, outputs may include information such as vehicle speed, velocity, time, map data (e.g., a high-resolution map (not shown) Fig. 11A), location data (e.g., location of vehicle 1100, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1136, etc. In at least one embodiment, HMI display 1134 may, for example, display information about the presence of one or more objects (e.g., a road sign, warning sign, traffic light change, etc.) and / or information about maneuvers the vehicle has performed, is performing, or will perform (e.g., change lanes now, take exit 34B in two miles, etc.).

[0097] In at least one embodiment, the vehicle 1100 further includes a network interface 1124 that may utilize wireless antenna(s) 1126 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1124 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the wireless antenna(s) 1126 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network(s), such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc.and / or low-power wide area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. protocols.

[0098] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 11A may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0099] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0100] Fig. Figure 11B illustrates an example of camera positions and fields of view for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at various positions on vehicle 1100.

[0101] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1100. In at least one embodiment, camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof.In at least one embodiment, the color filter array may include a Red Clear Clear Clear ("RCCC") color filter array, a Red Clear Clear Blue ("RCCB") color filter array, a Red Blue Green Clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer Sensors ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity.

[0102] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed to provide functions including lane departure warning, traffic sign support, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0103] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, to cut out stray light and reflections from within the vehicle 1100 (e.g., dashboard reflections reflected in windshield mirrors) that may impair camera image data collection capabilities. With reference to wing mirror mounting assemblies, in at least one embodiment, wing mirror assemblies may be custom 3D printed such that a camera mounting plate conforms to the shape of a wing mirror. In at least one embodiment, camera(s) may be integrated into wing mirrors. In at least one embodiment, camera(s) for side view cameras may also be integrated into four pillars at each corner of a cab.

[0104] In at least one embodiment, cameras with a field of view that includes portions of an environment in front of the vehicle 1100 (e.g., forward-facing cameras) may be used for surround vision to help identify forward paths and obstacles, as well as to help provide information critical to generating an occupancy grid and / or determining preferred vehicle paths using one or more controllers 1136 and / or control SoCs. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, but not limited to, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, but not limited to, lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0105] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform incorporating a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a far-view camera 1170 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 11B illustrates only one wide-view camera 1170, in other embodiments, there may be any number (including zero) of wide-view cameras on the vehicle 1100. In at least one embodiment, any number of long-range camera(s) 1198 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1198 may also be used for object detection and classification, as well as basic object tracking.

[0106] In at least one embodiment, any number of stereo cameras 1168 may also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 1168 may include an integrated control unit comprising a scalable processing unit that may provide a field-programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of the vehicle 1100, including a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo cameras 1168 may include, among other things, one or more compact stereo vision sensors, which may include, among other things, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance from the vehicle 1100 to the target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1168 may be used in addition to or alternatively to those described herein.

[0107] In at least one embodiment, cameras with a field of view that includes portions of the environment to the sides of the vehicle 1100 (e.g., side view cameras) may be used for surround vision, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, one or more surround cameras 1174 (e.g., four surround cameras, as in Fig. 11B) may be positioned on the vehicle 1100. In at least one embodiment, the surround view camera(s) 1174 may include, but are not limited to, any number and combination of wide view cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 may utilize three surround view cameras 1174 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround view camera.

[0108] In at least one embodiment, cameras with a field of view that includes portions of an environment behind the vehicle 1100 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 1198 and / or medium-range cameras 1176, stereo camera(s) 1168, infrared camera(s) 1172, etc.), as described herein.

[0109] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 11B may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0110] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0111] Fig. 11C is a block diagram illustrating an example system architecture for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1100 is Fig. 11C as connected via a bus 1102. In at least one embodiment, bus 1102 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1100 used to assist in controlling various features and functionality of vehicle 1100, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1102 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1102 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPMs"), button positions, and / or other vehicle status indicators.In at least one embodiment, bus 1102 may be a CAN bus that is ASIL B compliant.

[0112] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses that comprise bus 1102, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control.In at least one embodiment, each bus of bus 1102 may communicate with any of the components of vehicle 1100, and two or more buses of bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) ("SoC(s)") 1104 (such as SoC 1104(A) and SoC 1104(B)), each of controller(s) 1136, and / or each computer within the vehicle may have access to the same input data (e.g., inputs from sensors of vehicle 1100) and may be connected to a common bus, such as a CAN bus.

[0113] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136, such as those described herein with respect to Fig. 11A. In at least one embodiment, the controller(s) 1136 may be used for a variety of functions. In at least one embodiment, the controller(s) 1136 may be coupled to any of various other components and systems of the vehicle 1100 and may be used to control the vehicle 1100, artificial intelligence of the vehicle 1100, infotainment for the vehicle 1100, and / or other functions.

[0114] In at least one embodiment, vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of SoCs 1104 may include, without limitation, central processing units ("CPU(s)") 1106, graphics processing units ("GPU(s)") 1108, processor(s) 1110, cache(s) 1112, accelerator(s) 1114, data storage(s) 1116, and / or other unillustrated components and features. In at least one embodiment, SoC(s) 1104 may be used to control vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1104 in a system (e.g., system of vehicle 1100) may be combined with a high-definition (“HD”) map 1122 that may receive map updates and / or updates via network interface 1124 from one or more servers (not included in Fig. 11C).

[0115] In at least one embodiment, the CPU(s) 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 1106 may include multiple cores and / or level-two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1106 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1106 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1106 (e.g., CCPLEX) may be configured to support concurrent cluster operations, allowing any combination of clusters of CPU(s) 1106 to be active at any given time.

[0116] In at least one embodiment, one or more of the CPU(s) 1106 may implement power management capabilities including, without limitation, one or more of the following features: individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when such core is not actively executing due to the execution of wait-for-interrupt ("WFI") / wait-for-event ("WFE") instructions; each core may be independently clocked; each core cluster may be independently clocked when all cores are clocked or unclocked; and / or each core cluster may be independently clocked when all cores are clocked.In at least one embodiment, CPU(s) 1106 may further implement an improved performance state management algorithm, specifying allowed performance states and expected wake-up times, and hardware / microcode determining which best performance state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified performance state entry sequences in software with work offloaded to microcode.

[0117] In at least one embodiment, the GPU(s) 1108 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, the GPU(s) 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, the GPU(s) 1108 may use an enhanced tensor instruction set. In at least one embodiment, the GPU(s) 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-one ("L1") cache (e.g., an L1 cache with a memory capacity of at least 96 KB) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 1108 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1108 may use one or more computer application programming interfaces (APIs). In at least one embodiment, the GPU(s) 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0118] In at least one embodiment, one or more of the GPU(s) 1108 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1108 may be fabricated on a fin field-effect transistor ("FinFET") circuit. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block could include 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g.,Warp scheduler) or a sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0119] In at least one embodiment, one or more of the GPU(s) 1108 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as double data rate type five synchronous graphics random access memory ("GDDR5"), may be used in addition to or alternatively to the HBM memory.

[0120] In at least one embodiment, the GPU(s) 1108 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to enable the GPU(s) 1108 to directly access page tables of the CPU(s) 1106. In at least one embodiment, when a GPU of the memory management unit ("MMU") of the GPU(s) 1108 experiences a fault, an address translation request may be transmitted to the CPU(s) 1106. In response, two CPUs of the CPU(s) 1106, in at least one embodiment, may look in their page tables for a virtual-to-physical mapping for an address and transmit the translation back to the GPU(s) 1108.In at least one embodiment, the unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1106 and the GPU(s) 1108, thereby simplifying programming of the GPU(s) 1108 and porting applications to the GPU(s) 1108.

[0121] In at least one embodiment, the GPU(s) 1108 may include any number of access counters that may track the frequency of access by the GPU(s) 1108 to the memory of other processors. In at least one embodiment, the access counter(s) may help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving efficiency for memory shared between processors.

[0122] In at least one embodiment, one or more of the SoC(s) 1104 may include any number of cache(s) 1112, including those described herein. For example, in at least one embodiment, the cache(s) 1112 may include a level-three ("L3") cache available to both the CPU(s) 1106 and the GPU(s) 1108 (e.g., connected to the CPU(s) 1106 and the GPU(s) 1108). In at least one embodiment, the cache(s) 1112 may include a write-back cache that can track the states of lines, e.g., using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0123] In at least one embodiment, one or more of the SoC(s) 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1108 and offload some tasks from the GPU(s) 1108 (e.g., to free up more cycles of the GPU(s) 1108 to perform other tasks). In at least one embodiment, the accelerator(s) 1114 could be configured for targeted workloads (e.g.,Perception, convolutional neural networks (CNNs), recurrent neural networks (RNNs), etc.) that are robust enough to be amenable to acceleration may be used. In at least one embodiment, a CNN may include region-based or regional convolutional neural networks (RCNNs) and fast RCNNs (e.g., as used for object detection), or another type of CNN.

[0124] In at least one embodiment, the accelerator(s) 1114 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators (DLAs). In at least one embodiment, the DLA(s) may include, without limitation, one or more tensor processing units (TPUs), which may be configured to provide an additional tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may be further optimized for a specific set of neural network types and floating-point operations, as well as inference.In at least one embodiment, the design of the DLA(s) can provide more performance per millimeter than a typical general-purpose GPU and typically significantly exceeds the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, the DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for range estimation using data from camera sensors; a CNN for emergency vehicle detection and identification using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety and / or security-related events.

[0125] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 1108, and by using an inference accelerator, for example, a designer may target either the DLA(s) or the GPU(s) 1108 for any function. For example, in at least one embodiment, a designer may focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1108 and / or the accelerator(s) 1114.

[0126] In at least one embodiment, the accelerator(s) 1114 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for the advanced driver assistance system ("ADAS") 1138, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computing ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0127] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application-specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, RISC cores may include an instruction cache and / or tightly coupled RAM.

[0128] In at least one embodiment, DMA may enable components of the PVA to access system memory independently of the CPU(s) 1106. In at least one embodiment, DMA may support any number of features used to provide optimization for a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, a block width, a block height, a block depth, a horizontal block stride, a vertical block stride, and / or a depth stride.

[0129] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD") very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may improve throughput and speed.

[0130] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. Consequently, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image.In at least one embodiment, vector processors included in a particular PVA may concurrently execute different computer vision algorithms on an image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to improve overall system security.

[0131] In at least one embodiment, the accelerator(s) 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1114. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example, and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to the memory. In at least one embodiment, a backbone may include an on-chip computer vision network that connects a PVA and a DLA to the memory (e.g., using APB).

[0132] In at least one embodiment, an on-chip computer line of sight network may include an interface that determines that both a PVA and a DLA are ready and providing valid signals prior to transmitting any control signal / address / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0133] In at least one embodiment, one or more of the SoC(s) 1104 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model) to generate real-time visualization simulations for radar signal interpretation, sound propagation synthesis and / or analysis, simulation of sonar systems, general wave propagation simulation, comparison with lidar data for localization and / or other functions, and / or for other uses.

[0134] In at least one embodiment, the accelerator(s) 1114 may have a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are a good match for algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA performs well on semi-dense or dense regular computation, even on small datasets, which might require predictable, low-latency, and low-power runtimes. In at least one embodiment, such as in vehicle 1100, PVAs could be designed to execute classical computer vision algorithms because they can be efficient at object detection and operating on integer mathematics.

[0135] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, Level 3-5 autonomous driving applications use on-the-fly motion estimation / stereo matching (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0136] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw radar data (e.g., using a 4D fast Fourier transform) to provide processed radar data. In at least one embodiment, a PVA is used for runtime depth processing, for example, by processing raw runtime data to provide processed runtime data.

[0137] In at least one embodiment, a DLA may be used to execute any type of network to improve control and driving safety, including, for example, and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure allows a system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, a system may set a confidence threshold and consider only detections that exceed the threshold to be true positives.In an embodiment where an automatic emergency braking ("AEB") system is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered triggers for AEB. In at least one embodiment, a DLA may execute a neural network to reduce the confidence score. In at least one embodiment, the neural network may take as its input at least a subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), an output from one or more IMU sensors 1166 that correlates with the orientation of the vehicle 1100, a distance, 3D position estimates of an object obtained from the neural network, and / or other sensors (e.g.,LIDAR sensor(s) 1164 or RADAR sensor(s) 1160), among others.

[0138] In at least one embodiment, one or more of the SoC(s) 1104 may include one or more data stores 1116 (e.g., memory). In at least one embodiment, the data stores 1116 may be on-chip memory of the SoC(s) 1104 that may store neural networks to be executed on the GPU(s) 1108 and / or a DLA. In at least one embodiment, the data stores 1116 may be large enough in capacity to store multiple neural network instances for redundancy and security. In at least one embodiment, the data stores 1116 may include one or more L2 or L3 caches.

[0139] In at least one embodiment, one or more of the SoC(s) 1104 may include any number of processor(s) 1110 (e.g., embedded processors). In at least one embodiment, the processor(s) 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of the SoC(s) 1104 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance with system low-power state transitions, management of thermal and temperature sensors of the SoC(s) 1104, and / or management of power states of the SoC(s) 1104.In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC(s) 1104 may use ring oscillators to detect temperatures of the CPU(s) 1106, the GPU(s) 1108, and / or the accelerator(s) 1114. In at least one embodiment, if temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place the SoC(s) 1104 into a lower power state and / or place the vehicle 1100 into a chauffeur-driven safe stop mode (e.g., bring the vehicle 1100 to a safe stop).

[0140] In at least one embodiment, processor(s) 1110 may further include a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0141] In at least one embodiment, the processor(s) 1110 may further include an always-on processor engine that may provide necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic.

[0142] In at least one embodiment, the processor(s) 1110 may further include a security cluster engine, including, without limitation, a dedicated processor subsystem to handle security management for automotive applications. In at least one embodiment, a security cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a security mode, two or more cores, in at least one embodiment, may operate in a lockstep mode, functioning as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, processor(s) 1110 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1110 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0143] In at least one embodiment, processor(s) 1110 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a playback window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-view camera(s) 1170, the surround camera(s) 1174, and / or the in-cabin monitoring camera sensor(s). In at least one embodiment, the in-cabin monitoring camera sensor(s) is / are preferably monitored by a neural network running on another instance of SoC 1104 configured to identify and respond to in-cabin events.In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are otherwise disabled.

[0144] In at least one embodiment, a video image compositer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in a video, the noise reduction appropriately weights spatial information, thereby reducing weights of information provided by neighboring frames. In at least one embodiment, when an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image compositer may use information from a previous frame to reduce noise in a current frame.

[0145] In at least one embodiment, a video image compositer may also be configured to perform stereo rectification on input stereo lens images. In at least one embodiment, a video image compositer may further be used for user interface composition when using an operating system desktop, and the GPU(s) 1108 are not required to continuously render new surfaces. In at least one embodiment, when the GPU(s) 1108 are powered on and actively performing 3D rendering, a video image compositer may be used to offload the GPU(s) 1108 to improve performance and responsiveness.

[0146] In at least one embodiment, one or more of the SoC(s) 1104 may further include a Mobile Industrial Processor Interface ("MIPI") serial camera interface for receiving video and inputs from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of the SoC(s) 1104 may further include input / output controller(s) that may be controlled by software and may be used to receive I / O signals that are not committed to a specific role.

[0147] In at least one embodiment, one or more of SoC(s) 1104 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1104 may be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1164, RADAR sensor(s) 1160, etc., which may be connected via Ethernet channels), data from bus 1102 (e.g., speed of vehicle 1100, steering wheel position, etc.), data from GNSS sensor(s) 1158 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of SoC(s) 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free the CPU(s) 1106 from routine data management tasks.

[0148] In at least one embodiment, the SoC(s) 1104 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1104 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1114, when combined with the CPU(s) 1106, the GPU(s) 1108, and the memory(s) 1116, may provide a fast, efficient platform for Level 3-5 autonomous vehicles.

[0149] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to perform a wide variety of processing algorithms over a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many computer vision applications, such as those related to, for example, execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0150] Embodiments described herein enable multiple neural networks to be executed concurrently and / or sequentially and for results to be combined to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU(s) 1120) may include text and word recognition, enabling the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and providing a semantic understanding of a sign and passing that semantic understanding to path planning modules running on a CPU complex.

[0151] In at least one embodiment, multiple neural networks may be executed simultaneously, such as during Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions" along with an electrical light may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and text "flashing lights indicate icy conditions" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably executing on a CPU complex) that, when flashing lights are detected, icy conditions exist.In at least one embodiment, a flashing light may be identified by running a third deployed neural network across multiple images, informing a vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may be executed concurrently, such as within a DLA and / or on the GPU(s) 1108.

[0152] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify the presence of an authorized driver and / or owner of vehicle 1100. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, the SoC(s) 1104 provide security against theft and / or carjacking.

[0153] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 1104 use a CNN to classify ambient and urban noise, as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by the GNSS sensor(s) 1158.In at least one embodiment, if a CNN is operating in Europe, it will attempt to detect European sirens, and if it is operating in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slow a vehicle, pull to one side of a road, park a vehicle, and / or idle a vehicle using ultrasonic sensor(s) 1162 until emergency vehicles pass by.

[0154] In at least one embodiment, the vehicle 1100 may include CPU(s) 1118 (e.g., discrete CPU(s) or dCPU(s)) that may be coupled to the SoC(s) 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1118 may include, for example, an x86 processor. The CPU(s) 1118 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1104 and / or monitoring the status and integrity of the controller(s) 1136 and / or an infotainment system on a chip (“Infotainment SoC”) 1130. In at least one embodiment, the SoC(s) 1104 includes one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0155] In at least one embodiment, the vehicle 1100 may include GPU(s) 1120 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to the SoC(s) 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the GPU(s) 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of a vehicle 1100.

[0156] In at least one embodiment, the vehicle 1100 may further include a network interface 1124, which may include, without limitation, wireless antenna(s) 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1124 may be used to enable wireless connection to internet cloud services (e.g., to server(s) and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct connection may be established between the vehicle 110 and another vehicle and / or an indirect connection may be established (e.g., via networks and over the internet).In at least one embodiment, direct connections may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide information to vehicle 1100 about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, to one side of, and / or behind vehicle 1100). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1100.

[0157] In at least one embodiment, network interface 1124 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1136 to communicate over wireless networks. In at least one embodiment, network interface 1124 may include a radio frequency front end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible manner. For example, frequency conversions could be performed by well-known processes and / or using superheterodyne processes. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip.In at least one embodiment, network interfaces may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0158] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, but are not limited to, off-chip (e.g., off-SoC(s) 1104) memory. In at least one embodiment, the data stores 1128 may include, but are not limited to, one or more memory elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0159] In at least one embodiment, the vehicle 1100 may further include one or more GNSS sensors 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, sensing, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, and without limitation, a GPS using a USB connector with an Ethernet-to-serial (e.g., RS-232) bridge.

[0160] In at least one embodiment, vehicle 1100 may further include one or more radar sensors 1160. In at least one embodiment, the radar sensor(s) 1160 may be used by vehicle 1100 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, radar functional safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1160 may use a CAN bus and / or bus 1102 (e.g., to transmit data generated by the RADAR sensor(s) 1160 for control and to access object tracking data, with some examples accessing Ethernet channels to access raw data). In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and among other things, the RADAR sensor(s) 1160 may be suitable for front, rear, and side RADAR use.In at least one embodiment, one or more sensors of RADAR sensor(s) 1160 is / are a pulse Doppler RADAR sensor.

[0161] In at least one embodiment, the RADAR sensor(s) 1160 may include various configurations, such as long-range narrow field of view, short-range wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a wide field of view realized by two or more independent scans, such as within a range of 250 m (meters). In at least one embodiment, the RADAR sensor(s) 1160 may help distinguish between static and moving objects and may be used by the ADAS system 1138 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1160 included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and a high-speed CAN and FlexRay interface. In at least one embodiment, a central four-antenna array with six antennas may produce a focused beam pattern designed to record the surroundings of the vehicle 1100 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, making it possible to quickly detect vehicles entering or exiting a lane of the vehicle 1100.

[0162] For example, in at least one embodiment, medium-range RADAR systems may include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensors 1160 configured to be installed at either end of a rear bumper. When installed at either end of a rear bumper, in at least one embodiment, a RADAR sensor system may generate two beams that continuously monitor blind spots in a rearward direction and to the side of a vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system 1138 for blind spot detection and / or lane change assistance.

[0163] In at least one embodiment, the vehicle 1100 may further include one or more ultrasonic sensors 1162. In at least one embodiment, the ultrasonic sensor(s) 1162, which may be positioned at a front, rear, and / or side location of the vehicle 1100, may be used for parking and / or for creating and updating an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different sensing ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B.

[0164] In at least one embodiment, the vehicle 1100 may include one or more LIDAR sensors 1164. In at least one embodiment, the LIDAR sensor(s) 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1164 may operate at ASIL B functional safety level. In at least one embodiment, the vehicle 1100 may include multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0165] In at least one embodiment, the LIDAR sensor(s) 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1164 may have an advertised range of approximately 100 m with an accuracy of 2 cm to 3 cm and with support for a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1164 may include a small device that may be embedded in a front, rear, side, and / or corner location of the vehicle 1100.In at least one embodiment, the LIDAR sensor(s) 1164 in such an embodiment can provide up to a 120-degree horizontal field of view and a 35-degree vertical field of view with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the front-mounted LIDAR sensor(s) 1164 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0166] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1100 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receiver that records the laser pulse travel time and reflected light at each pixel, which in turn corresponds to a range from the vehicle 1100 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1100.In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a 5-nanosecond Class I (eye-safe) laser pulse per image and may collect reflected laser light as a 3D range point cloud and simultaneously registered intensity data. In at least one embodiment, the flash LIDAR device may use a 5-nanosecond Class I (eye-safe) laser pulse per image and may collect reflected laser light as a 3D range point cloud and.

[0167] In at least one embodiment, the vehicle 1100 may further include one or more IMU sensors 1166. In at least one embodiment, the IMU sensor(s) 1166 may be located at a center of a rear axle of the vehicle 1100. In at least one embodiment, the IMU sensor(s) 1166 may include, for example, and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1166 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1166 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0168] In at least one embodiment, the IMU sensor(s) 1166 may be implemented as a miniature, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1166 may enable the vehicle 1100 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to the IMU sensor(s) 1166. In at least one embodiment, the IMU sensor(s) 1166 and the GNSS sensor(s) 1158 may be combined into a single integrated unit.

[0169] In at least one embodiment, the vehicle 1100 may include one or more microphones 1196 placed in and / or around the vehicle 1100. In at least one embodiment, the microphone(s) 1196 may be used for, among other things, emergency vehicle detection and identification.

[0170] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including stereo camera(s) 1168, wide-view camera(s) 1170, infrared camera(s) 1172, surround camera(s) 1174, long-range camera(s) 1198, medium-range camera(s) 1176, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of the vehicle 1100. In at least one embodiment, the type of cameras used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around the vehicle 1100. In at least one embodiment, the number of cameras employed may vary depending on the embodiment.For example, in at least one embodiment, vehicle 1100 could include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera could be configured as previously described with respect to [ ]. Fig. 11A and Fig. 11B will be described in more detail.

[0171] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the vibration sensor(s) 1142 may measure vibrations of components of the vehicle 1100, such as axle(s). In at least one embodiment, the vibration sensor(s) 1142 may measure vibrations of components of the vehicle 1100, such as For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a driven axle and a free-spinning axle).

[0172] In at least one embodiment, vehicle 1100 may include ADAS system 1138. In at least one embodiment, ADAS system 1138 may include, among other things, an SoC in some examples. In at least one embodiment, ADAS system 1138 may include, among other things, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward collision warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic alert (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0173] In at least one embodiment, the ACC system may use one or more RADAR sensors 1160, one or more LIDAR sensors 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately ahead of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from the vehicles ahead. In at least one embodiment, a lateral ACC system performs follow-through and advises the vehicle 1100 to change lanes if necessary. In at least one embodiment, lateral ACC relates to other ADAS applications, such as LC and CW.

[0174] In at least one embodiment, a CACC system utilizes information from other vehicles, which may be received via network interface 1124 and / or one or more wireless antenna(s) 1126 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided through a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided through an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 1100), while I2V communication provides information about further ahead traffic.In at least one embodiment, a CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information from vehicles ahead of vehicle 1100 and has the potential to improve traffic flow smoothness and reduce congestion on the road.

[0175] In at least one embodiment, an FCW system is designed to warn a driver of a hazard so that such a driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or one or more RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, an FCW system can provide a warning, such as in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0176] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and may automatically apply braking if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, an AEB system may utilize one or more forward-facing cameras and / or one or more radar sensors 1160 coupled with a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, that AEB system may automatically apply braking to prevent or at least mitigate the impact of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or imminent collision braking.

[0177] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1100 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intended lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled with a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct the vehicle 1100 when the vehicle 1100 begins to depart from its lane.

[0178] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile's blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may utilize one or more rear-facing cameras and / or one or more radar sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0179] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside of a rear camera range when the vehicle 1100 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component.

[0180] In at least one embodiment, conventional ADAS systems may be prone to false positives, which may be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems warn a driver and allow that driver to decide whether a safety condition actually exists and act accordingly. In at least one embodiment, the vehicle 1100 itself decides, in the case of conflicting results, whether to consider the result from a primary computer or a secondary computer (e.g., a first controller or a second controller of the controllers 1136). For example, in at least one embodiment, the ADAS system 1138 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module.In at least one embodiment, a backup computer rationality monitor may execute redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, outputs from the ADAS system 1138 may be provided to a monitoring MCU. If outputs from a primary computer and outputs from a secondary computer conflict, a monitoring MCU, in at least one embodiment, determines how to reconcile the conflict to ensure safe operation.

[0181] In at least one embodiment, a primary computer may be configured to provide a monitoring MCU with a confidence value indicating the confidence of that primary computer in a chosen outcome. If that confidence value exceeds a threshold, in at least one embodiment, that monitoring MCU may follow the instruction of that primary computer regardless of whether that secondary computer provides a conflicting or inconsistent outcome. If a confidence value does not meet a threshold and if primary and secondary computers indicate different outcomes (e.g., a conflict), in at least one embodiment, a monitoring MCU may arbitrate between computers to determine an appropriate outcome.

[0182] In at least one embodiment, a monitoring MCU may be configured to execute neural network(s) trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) in a monitoring MCU may learn when the output of a secondary computer can be trusted and when it cannot. For example, if that secondary computer is a radar-based FCW system, neural network(s) in that monitoring MCU may learn when an FCW system identifies metallic objects that are not actually hazards, such as a drainage grate or manhole cover, that trigger an alarm.If a secondary computer is a camera-based LDW system, in at least one embodiment, a neural network in a monitoring MCU may learn to override LDW when cyclists or pedestrians are present and lane departure is actually the safest maneuver. In at least one embodiment, a monitoring MCU may include at least one of a DLA or a GPU capable of executing a neural network(s) with associated memory. In at least one embodiment, a monitoring MCU may include and / or be included as a component of SoC(s) 1104.

[0183] In at least one embodiment, ADAS system 1138 may include a secondary computer that performs ADAS functionality using conventional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision rules (if-then), and the presence of a neural network(s) in a supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementation and intended non-identity makes an overall system more fault-tolerant, particularly against errors caused by software (or software-hardware interface) functionality.For example, in at least one embodiment, if there is a software bug or a software error in software executing on a primary computer and non-identical software code executing on a secondary computer provides a consistent overall result, then a monitoring MCU may have greater confidence that an overall result is correct and a bug in software or hardware on that primary computer does not cause a material error.

[0184] In at least one embodiment, an output of the ADAS system 1138 may be fed into the perception block of a primary computer and / or the dynamic driving task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward collision warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own trained neural network, thus reducing the risk of false positives, as described herein.

[0185] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, among other things, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, among other things, a combination of hardware and software that may be used to provide the vehicle 1100 with audio (e.g., music, a personal digital assistant, navigation directions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g.,Navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door opening / closing, air filter information, etc.). For example, the infotainment SoC 1130 could include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car putters, in-vehicle entertainment, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 may be further used to provide information (e.g.,visual and / or audible), such as information from the ADAS system 1138, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0186] In at least one embodiment, the infotainment SoC 1130 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 may communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a supervisory MCU so that a GPU of an infotainment system can perform some self-driving functions in the event that the primary controller(s) 1136 (e.g., primary and / or backup computers of the vehicle 1100) fail. In at least one embodiment, the infotainment SoC 1130 may place the vehicle 1100 in a chauffeur-driven safe stop mode, as described herein.

[0187] In at least one embodiment, the vehicle 1100 may further include an instrument cluster 1132 (e.g., a digital instrument panel, an electronic instrument cluster, a digital dashboard, etc.). In at least one embodiment, the instrument cluster 1132 may include, among other things, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 1132 may include, among other things, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, gear shift position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between the infotainment SoC 1130 and the instrument cluster 1132. In at least one embodiment, the instrument cluster 1132 may be included as part of the infotainment SoC 1130, or vice versa.

[0188] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 11C may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0189] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0190] Fig. 11D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, the system may include, among other things, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, server(s) 1178 may include, among other things, a plurality of GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be connected to high-speed interconnects, such as, but not limited to, NVLink interfaces 1188 developed by NVIDIA and / or PCIe interconnects 1186.In at least one embodiment, GPUs 1184 are connected via an NVLink and / or NVSwitch SoC, and GPUs 1184 and PCIe switches 1182 are connected via PCIe connections. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1178 may include, among other things, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, the server(s) 1178 could each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0191] In at least one embodiment, the server(s) 1178 may receive, via one or more networks 1190 and from vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced roadwork. In at least one embodiment, the server(s) 1178 may transmit, via one or more networks 1190 and to vehicles, updated or otherwise updated neural networks 1192 and / or map information 1194, including, but not limited to, information related to traffic and road conditions. In at least one embodiment, updates to the map information 1194 may include, but not limited to, updates to the HD map 1122, such as information related to construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 1192 and / or map information 1194 may result from new training and / or experience represented in data received from any number of vehicles in an environment and / or may be based at least in part on training performed in a data center (e.g., using server(s) 1178 and / or other servers).

[0192] In at least one embodiment, the server(s) 1178 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles and / or may be generated in a simulation (e.g., using a gaming machine). In at least one embodiment, any amount of training data is labeled (e.g., if the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, any amount of training data is unlabeled and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g.,transmitted to vehicles via one or more networks 1190) and / or machine learning models may be used by the server(s) 1178 to remotely monitor vehicles.

[0193] In at least one embodiment, the server(s) 1178 may receive data from vehicles and apply the data to real-time neural networks for intelligent real-time inference. In at least one embodiment, the server(s) 1178 may include deep learning supercomputers and / or dedicated AI computers powered by the GPU(s) 1184, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1178 may include deep learning infrastructure using CPU-powered data centers.

[0194] In at least one embodiment, the deep learning infrastructure of server(s) 1178 may be capable of fast, real-time inference and may use this capability to evaluate and verify the integrity of processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1100, such as a sequence of images and / or objects that vehicle 1100 has been located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is malfunctioning, the server(s) 1178 may send a signal to the vehicle 1100 instructing a fail-safe computer of the vehicle 1100 to take over control, notify passengers, and complete a safe parking maneuver.

[0195] In at least one embodiment, the server(s) 1178 may include GPU(s) 1184 and one or more programmable inference accelerators (e.g., TensorRT 3 devices from NVIDIA). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, such as when performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware structure(s) 815 is / are used to perform one or more embodiments. Details regarding hardware structure(s) 815 are described herein in connection with Fig. 8A and / or Fig. 8B provided. COMPUTER SYSTEMS

[0196] Fig. 12 is a block diagram illustrating an example computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1200 may include, without limitation, a component such as a processor 1202 for employing execution units including logic for performing algorithms on process data according to the present disclosure, as in the embodiment described herein.In at least one embodiment, computer system 1200 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1200 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0197] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of performing one or more instructions according to at least one embodiment.

[0198] In at least one embodiment, computer system 1200 may include, without limitation, processor 1202, which may include, without limitation, one or more execution units 1208 to perform machine learning model training and / or inference according to techniques described herein. In at least one embodiment, computer system 1200 is a single-processor desktop or server system, but in another embodiment, computer system 1200 may be a multiprocessor system. In at least one embodiment, processor 1202 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computer ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor.In at least one embodiment, the processor 1202 may be coupled to a processor bus 1210 that may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0199] In at least one embodiment, processor 1202 may include, without limitation, an internal Level 1 ("L1") cache memory ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be located external to processor 1202. Other embodiments may also include a combination of both internal and external caches depending on a particular implementation and requirements. In at least one embodiment, a register file 1206 may store various types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0200] In at least one embodiment, execution unit 1208, including without limitation logic for performing integer and floating-point operations, is also located in processor 1202. In at least one embodiment, processor 1202 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1208 may include logic to handle a packed instruction set 1209. In at least one embodiment, by incorporating packed instruction set 1209 into an instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1202.In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor's data bus to perform operations on packed data, which may eliminate a need to transfer smaller units of data across that processor's data bus to perform one or more operations one data item at a time.

[0201] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, among other things, a memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 1220 may store instruction(s) 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0202] In at least one embodiment, a system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, a system logic chip may include, among other things, a memory control node ("MCH") 1216, and processor 1202 may communicate with MCH 1216 over processor bus 1210. In at least one embodiment, MCH 1216 may provide a high-bandwidth memory path 1218 to memory 1220 for instruction and data storage and for storing graphics commands, data, and textures. In at least one embodiment, MCH 1216 may route data signals between processor 1202, memory 1220, and other components in computer system 1200, and may bridge data signals between processor bus 1210, memory 1220, and a system I / O interface 1222. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller.In at least one embodiment, the MCH 1216 may be coupled to the memory 1220 via the high-bandwidth memory path 1218, and a graphics / video card 1212 may be coupled to the MCH 1216 via an accelerated graphics port ("AGP") connection 1214.

[0203] In at least one embodiment, computer system 1200 may use system I / O interface 1222 as a proprietary node interface bus to couple MCH 1216 to an I / O control node ("ICH") 1230. In at least one embodiment, ICH 1230 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1220, a chipset, and processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware node (“Flash BIOS”) 1228, a wireless transceiver 1226, a data store 1224, an alt I / O controller 1223 containing user input and keyboard interfaces 1225, a serial expansion port 1227, such as a Universal Serial Bus (“USB”) port, and a network controller 1234.In at least one embodiment, data storage 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0204] In at least one embodiment, Fig. 12 a system containing interconnected hardware devices or ‘chips’, whereas Fig. 12 may illustrate an exemplary SoC in other embodiments. In at least one embodiment, Fig. 12 may be connected using proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using Compute Express Link (CXL) interconnects.

[0205] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 12 be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0206] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0207] Fig. 13 is a block diagram illustrating an electronic device 1300 for using a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example and without limitation, a notebook, a master server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0208] In at least one embodiment, electronic device 1300 may include, without limitation, processor 1310 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as an I 2C-Bus, a System Management Bus (“SM-Bus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Fig. 13 a system containing interconnected hardware devices or ‘chips’, whereas Fig. 13 may illustrate an exemplary SoC in other embodiments. In at least one embodiment, Fig. 13 may be connected to proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 13 are connected using Compute Express Link (CXL) connections.

[0209] In at least one embodiment, Fig. 13 a display 1324, a touchscreen 1325, a touchpad 1330, a near-field communication unit (“NFC”) 1345, a sensor node 1340, a thermal sensor 1346, an Express Chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320, such as a solid-state disk (“SSD”) or a hard disk drive (“HDD”), a wireless local area network unit (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network unit (“WWAN”) 1356, a Global Positioning System (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354, such as a USB 3.0 camera, and / or a low double data rate ("LPDDR") ("LPDDR3") 1315 memory device, implemented, for example, in an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0210] In at least one embodiment, other components may be communicatively coupled to processor 1310 through components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor ("ALS") 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor node 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and the touchpad 1330 may be communicatively coupled to the EC 1335. In at least one embodiment, speakers 1363, headphones 1364, and a microphone ("mic") 1365 may be communicatively coupled to an audio unit ("audio codec and class-D amplifier") 1362, which in turn may be communicatively coupled to the DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352, as well as the WWAN unit 1356, may be implemented in a next-generation form factor ("NGFF").

[0211] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 13 be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0212] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0213] Fig. Figure 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement various processes and methods described in this disclosure.

[0214] In at least one embodiment, computer system 1400 includes, without limitation, at least one central processing unit ("CPU") 1402 connected to a communications bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communications protocol(s). In at least one embodiment, computer system 1400 includes, without limitation, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1404, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem (“Network Interface”) 1422 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1400.

[0215] In at least one embodiment, computer system 1400 includes, without limitation, input devices 1408, a parallel processing system 1412, and display devices 1406, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is received from input devices 1408, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be arranged on a single semiconductor platform to form a processing system.

[0216] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 14 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0217] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0218] Fig. 15 illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 includes, among other things, a computer 1510 and a USB flash drive 1520. In at least one embodiment, the computer 1510 may include, among other things, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1510 includes, among other things, a server, a cloud instance, a laptop, and a desktop computer.

[0219] In at least one embodiment, USB flash drive 1520 includes, among other things, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 may be any instruction execution system, instruction execution apparatus, or instruction execution device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, among other things, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 comprises an application-specific integrated circuit ("ASIC") optimized to perform any set and type of operations associated with machine learning.For example, in at least one embodiment, processing unit 1530 is a tensor processing unit (TPC) optimized to perform inference operations for machine learning. In at least one embodiment, processing unit 1530 is a vision processing unit (VPU) optimized to perform inference operations for machine vision and machine learning.

[0220] In at least one embodiment, USB interface 1540 may be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 may include any amount and type of logic that enables processing unit 1530 to interface with devices (e.g., computer 1510) via USB connector 1540.

[0221] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system Fig. 15 be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0222] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0223] Fig. 16A illustrates an example architecture in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed interconnects 1640(1)-1640(N) (e.g., buses, point-to-point links, etc.). In at least one embodiment, high-speed interconnects 1640(1)-1640(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1610(1)-1610(N) include one or more graphics cores (also referred to simply as “cores”) 1900, as shown in Fig. 19A and Fig. 19B. In at least one embodiment, one or more graphics cores 1900 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0224] Additionally, and in at least one embodiment, two or more of the GPUs 1610 are interconnected via high-speed interconnects 1629(1)-1629(2), which may be implemented using similar or different protocols / connections than those used for high-speed interconnects 1640(1)-1640(N). Likewise, two or more of the multi-core processors 1605 may be interconnected via a high-speed interconnect 1628, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between various system components implemented in Fig. 16A can be achieved using similar protocols / connections (e.g., via a common interconnect structure).

[0225] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to a processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(1)-1610(N) is communicatively coupled to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 may use similar or different memory access technologies. For example, and not by way of limitation, the processor memories 1601(1)-1601(M) and the GPU memories 1620 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memories (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of processor memory 1601 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0226] As described herein, various multi-core processors 1605 and GPUs 1610 may each be physically coupled to a particular memory 1601, 1620, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed across different physical memories. For example, processor memories 1601(1)-1601(M) may each comprise 64 GB of system memory address space, and GPU memories 1620(1)-1620(N) may each comprise 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0227] Fig. 16B illustrates additional details for a connection between a multi-core processor 1607 and a graphics acceleration module 1646 according to an example embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card coupled to the processor 1607 via a high-speed interconnect 1640 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1646 may be integrated on a package or die with the processor 1607.

[0228] In at least one embodiment, processor 1607 includes a plurality of cores 1660A-1660D (which may be referred to as "execution units"), each with a translation buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components for executing instructions and processing data, not illustrated. In at least one embodiment, caches 1662A-1662D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by sets of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1607 and graphics acceleration module 1646 are coupled to system memory 1614, which includes processor memories 1601(1)-1601(M) of FIG. Fig. 16A may include.

[0229] In at least one embodiment, coherency for data and instructions stored in various caches 1662A-1662D, 1656, and system memory 1614 is maintained via inter-core communication over a coherency bus 1664. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry associated with it to communicate over the coherency bus 1664 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over the coherency bus 1664 to snoop cache accesses.

[0230] In at least one embodiment, a proxy circuit 1625 communicatively couples the graphics acceleration module 1646 to the coherence bus 1664, enabling the graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of the cores 1660A-1660D. Specifically, in at least one embodiment, an interface 1635 provides a connection to the proxy circuit 1625 via the high-speed interconnect 1640, and an interface 1637 connects the graphics acceleration module 1646 to the high-speed interconnect 1640.

[0231] In at least one embodiment, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 includes one or more graphics cores 1900, as described in connection with Fig. 19A and Fig. 19B. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively comprise various types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1646 may be a GPU with a plurality of graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, line card, or die.

[0232] In at least one embodiment, accelerator integration circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1614. In at least one embodiment, MMU 1639 may also include a translation buffer (TLB) (not shown) for caching virtual / effective to physical / real translations. In at least one embodiment, a cache 1638 may store instructions and data for efficient access by graphics processing engines 1631(1)-1631(N).In at least one embodiment, data stored in cache 1638 and graphics memories 1633(1)-1633(M) is maintained coherently with core caches 1662A-1662D, 1656, and system memory 1614, possibly using a fetch unit 1644. As noted, this may be accomplished via proxy circuitry 1625 for cache 1638 and memories 1633(1)-1633(M) (e.g., sending updates to cache 1638 regarding modifications / accesses to cache lines on processor caches 1662A-1662D, 1656 and receiving updates from cache 1638).

[0233] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and a context management circuit 1648 manages thread contexts. For example, context management circuit 1648 may perform save and restore operations to save and restore contexts of different threads during context switches (e.g., when a first thread is saved and a second thread is saved so that a second thread can be executed by a graphics processing engine). For example, upon a context switch, context management circuit 1648 may save current register values ​​to a specific region in memory (e.g., identified by a context pointer). It may then restore register values ​​when returning to a context.In at least one embodiment, an interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0234] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1631 are translated by the MMU 1639 into real / physical addresses in system memory 1614. In at least one embodiment, the accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1646 may be dedicated to a single application executing on the processor 1607 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is depicted in which resources of the graphics processing engines 1631(1)-1631(N) are shared among multiple applications or virtual machines (VMs).In at least one embodiment, resources may be divided into "slices" that are assigned to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0235] In at least one embodiment, accelerator integration circuitry 1636 operates as a bridge to a system for graphics acceleration module 1646, providing address translation and system memory caching services. Additionally, in at least one embodiment, accelerator integration circuitry 1636 may provide virtualization facilities to a host processor to manage the virtualization of graphics processing engines 1631(1)-1631(N), interrupts, and memory management.

[0236] Because hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped to a real address space seen by host processor 1607, each host processor can directly address these resources using an effective address value. In at least one embodiment, a function of accelerator integration circuit 1636 is to physically separate graphics processing engines 1631(1)-1631(N) so that they appear to a system as independent entities.

[0237] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are each coupled to each of the graphics processing engines 1631(1)-1631(N), and N = M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store instructions and data processed by each of the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0238] To reduce data traffic over high-speed interconnect 1640, in at least one embodiment, biasing techniques may be used to ensure that data stored in graphics memories 1633(1)-1633(M) is data most frequently used by graphics processing engines 1631(1)-1631(N) and preferably not used by cores 1660A-1660D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by the cores (and preferably not by graphics processing engines 1631(1)-1631(N)) within caches 1662A-1662D, 1656, and system memory 1614.

[0239] Fig. 16C illustrates another exemplary embodiment in which accelerator integration circuitry 1636 is integrated within processor 1607. In this embodiment, graphics processing engines 1631(1)-1631(N) communicate directly over high-speed interconnect 1640 with accelerator integration circuitry 1636 via interface 1637 and interface 1635 (which may again be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1636 may perform similar operations to those described with respect to Fig. 16B, but possibly with higher throughput given their close proximity to the coherence bus 1664 and the caches 1662A-1662D, 1656. In at least one embodiment, an accelerator integration circuit supports various programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1636 and programming models controlled by the graphics acceleration module 1646.

[0240] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward other application requests to graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition.

[0241] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize the graphics processing engines 1631(1)-1631(N) to provide access by any operating system. In at least one embodiment, for single-partition systems without a hypervisor, the graphics processing engines 1631(1)-1631(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize the graphics processing engines 1631(1)-1631(N) to provide access to any process or application.

[0242] In at least one embodiment, the graphics acceleration module 1646 or an individual graphics processing engine 1631(1)-1631(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1614 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when its context is registered with the graphics processing engine 1631(1)-1631(N) (that is, system software is invoked to add a process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of a process handle may be an offset of a process element within a linked list of process elements.

[0243] Fig. 16D illustrates an exemplary accelerator integration slice 1690. In at least one embodiment, a "slice" comprises a specified portion of the processing resources of accelerator integration circuit 1636. In at least one embodiment, an application, which is an effective address space 1682 within system memory 1614, stores process elements 1683. In at least one embodiment, process elements 1683 are stored in response to GPU calls 1681 from applications 1680 executing on processor 1607. In at least one embodiment, a process element 1683 contains process state for the corresponding application 1680. In at least one embodiment, a work descriptor (WD) 1684 contained within process element 1683 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of an application.

[0244] In at least one embodiment, the graphics acceleration module 1646 and / or individual graphics processing engines 1631(1)-1631(N) may be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing process states and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment may be included.

[0245] In at least one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1646 or a single graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1636 for an ownership partition, and an operating system initializes the accelerator integration circuit 1636 for an ownership process when the graphics acceleration module 1646 is assigned.

[0246] In operation, in at least one embodiment, a WD fetch unit 1691 in the accelerator integration slice 1690 fetches the next WD 1684, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 may be stored in registers 1645 and used by the MMU 1639, the interrupt management circuitry 1647, and / or the context management circuitry 1648, as illustrated. For example, one embodiment of the MMU 1639 includes segment / page walkup circuitry for accessing segment / page tables 1686 within an OS virtual address space 1685. In at least one embodiment, the interrupt management circuitry 1647 may process interrupt events 1692 received from the graphics acceleration module 1646.In at least one embodiment, when performing graphics operations, an effective address 1693 generated by a graphics processing engine 1631(1)-1631(N) is translated into a real address by the MMU 1639.

[0247] In at least one embodiment, registers 1645 are duplicated for each graphics processing engine 1631(1)-1631(N) and / or each graphics acceleration module 1646 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1690. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor-initialized registers Register # Beschreibung 1 Scheibensteuerregister 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0248] Example registers that can be initialized by an operating system are shown in Table 2. Table 2 - Operating system initialized registers Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor

[0249] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engines 1631(1)-1631(N). In at least one embodiment, it contains all the information required by a graphics processing engine 1631(1)-1631(N) to perform work, or it may be a pointer to a memory location where an application has established a command queue for work to be performed.

[0250] Fig.16E illustrates additional details for an exemplary embodiment of a shared model. This embodiment includes a real hypervisor address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the real hypervisor address space 1698 is accessible via a hypervisor 1696 that virtualizes graphics acceleration engine engines for the operating system 1695.

[0251] In at least one embodiment, shared programming models enable all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1646. In at least one embodiment, there are two programming models where the graphics acceleration module 1646 is shared among multiple processes and partitions: shared time slices and shared graphics controllers.

[0252] In at least one embodiment, in this model, the system hypervisor 1696 owns the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, for a graphics acceleration module 1646 to support virtualization by the system hypervisor 1696, the graphics acceleration module 1646 may adhere to certain requirements, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1646 must provide a context save and restore mechanism, (2) an application's job request is guaranteed by the graphics acceleration module 1646 to complete in a certain amount of time, including any translation errors, or the graphics acceleration module 1646 provides an ability to preempt the processing of a job, and (3) the graphics acceleration module 1646 must be guaranteed fairness between processes when operating in a controlled shared programming model.

[0253] In at least one embodiment, application 1680 is required to make a system call to operating system 1695 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value.In at least one embodiment, the WD is specifically formatted for the graphics acceleration module 1646 and may be in the form of an instruction of the graphics acceleration module 1646, an effective address pointer to a user-defined structure, an effective address pointer to a queue of instructions, or any other data structure to describe the work to be performed by the graphics acceleration module 1646.

[0254] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuitry 1636 (not shown) and graphics acceleration module 1646 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1696 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1683.In at least one embodiment, CSRP is one of the registers 1645 that contains an effective address of a region in an application's effective address space 1682 for the graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional when no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be pinned system memory.

[0255] Upon receiving a system call, the operating system 1695 may verify that the application 1680 has been registered and granted permission to use the graphics acceleration module 1646. In at least one embodiment, the operating system 1695 then calls the hypervisor 1696 with the information shown in Table 3. Table 3 - OS-to-Hypervisor call parameters Parameters # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 A Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 A Logical Interrupt Service Number (LISN)

[0256] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1696 verifies that the operating system 1695 has been registered and authorized to use the graphics acceleration module 1646. In at least one embodiment, the hypervisor 1696 then places the process element 1683 in a linked list of process elements for a corresponding graphics acceleration module type 1646. In at least one embodiment, a process element may include information shown in Table 4. Table 4 - Process element information Item # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An Effective Address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TID) 5 Ein Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Eine Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table, abgeleitet von Hypervisor-Aufrufparametern 9 Ein State Register (SR)-Wert 10 Eine Logical Partition ID (LPID) 11 Ein Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0257] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1690 registers 1645.

[0258] As in Fig. 16F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1601(1)-1601(N) and GPU memories 1620(1)-1620(N). In this implementation, operations performed on GPUs 1610(1)-1610(N) use a same virtual / effective memory address space to access processor memories 1601(1)-1601(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is assigned to processor memory 1601(1), a second portion is assigned to second processor memory 1601(N), a third portion is assigned to GPU memory 1620(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1601 and GPU memories 1620, allowing any processor or GPU to access any physical memory with a virtual address associated with that memory.

[0259] In at least one embodiment, the bias / coherence management circuitry 1694A-1694E within one or more of the MMUs 1639A-1639E ensures cache coherence between caches of one or more host processors (e.g., 1605) and GPUs 1610 and implements biasing techniques that indicate physical memories in which certain data types should be stored. In at least one embodiment, while multiple instances of the bias / coherence management circuitry 1694A-1694E in Fig. 16F, the bias / coherence circuitry may be implemented within an MMU of one or more host processors 1605 and / or within the accelerator integration circuit 1636.

[0260] One embodiment enables GPU memory 1620 to be allocated as part of system memory and accessed using shared virtual memory (SVM) technology, but without incurring performance penalties associated with full system cache coherence. In at least one embodiment, a capability for GPU memory 1620 to be accessed as system memory without extensive cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement enables the software of host processor 1605 to set up operands and access the computation results without the overhead of traditional I / O DMA data copies.In at least one embodiment, such conventional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overheads may be critical to the execution time of an offloaded computation. In at least one embodiment, in cases with significant streaming write memory traffic, for example, the cache coherence overhead may significantly reduce an effective write bandwidth seen by a GPU 1610. In at least one embodiment, operand facility efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of GPU offloading.

[0261] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at a memory page granularity) including 1 or 2 bits per GPU-bound memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1620 with or without a bias cache in a GPU 1610 (e.g., to cache frequently / recently used bias table entries). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0262] In at least one embodiment, a bias table entry associated with each access to GPU-bound memory 1620 is accessed prior to the actual GPU memory access, causing the following operations. In at least one embodiment, local requests from a GPU 1610 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1620. In at least one embodiment, local requests from a GPU that find their page in the host bias are forwarded to the processor 1605 (e.g., over a high-speed interconnect, as described herein). In at least one embodiment, requests from the processor 1605 that find a requested page in the host processor bias complete a request like a normal memory read.Alternatively, requests for a GPU-biased page may be forwarded to a GPU 1610. In at least one embodiment, a GPU may then transition a page to host processor bias if it is not currently using a page. In at least one embodiment, a page's bias state may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0263] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn invokes a GPU's device driver, which in turn sends a message to a GPU (or queues a command descriptor) instructing it to change a bias state, and for some transitions, performs a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from host processor 1605 bias to GPU bias, but is not used for an opposite transition.

[0264] In at least one embodiment, cache coherence is maintained by temporarily uncaching GPU-biased pages by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by host processor 1605, and vice versa.

[0265] Hardware structure(s) 815 is / are used to perform one or more embodiments. Details regarding hardware structure(s) 815 may be described herein in connection with Fig. 8A and / or Fig. 8B are provided.

[0266] Fig. Figure 17 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0267] Fig. 17 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1700 that may be manufactured using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic, including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I 2 2S / I 22C controller 1740. In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1750 and a mobile industry processor interface (MIPI) display interface 1755. In at least one embodiment, memory may be provided by a flash memory subsystem 1760 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1770.

[0268] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in integrated circuit 1700 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0270] Fig. 18A- Fig. 18B illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0271] Fig. 18A- Fig. 18B are block diagrams illustrating example graphics processors for use within an SoC according to embodiments described herein. Fig. 18A illustrates an exemplary graphics processor 1810 of a system-on-chip integrated circuit that may be manufactured using one or more IP cores in accordance with at least one embodiment. Fig. 18B illustrates an additional exemplary graphics processor 1840 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 1810 is Fig. 18A is a low-performance graphics processor core. In at least one embodiment, the graphics processor 1840 is Fig. 18B, a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 may be variants of the graphics processor 1710 of Fig. be 17.

[0272] In at least one embodiment, graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1, and 1815N). In at least one embodiment, graphics processor 1810 may execute different shader programs via separate logic, such that vertex processor 1805 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processor(s) 1815A-1815N use primitive and vertex data generated by the vertex processor 1805 to generate a frame buffer displayed on a display device. In at least one embodiment, the fragment processor(s) 1815A-1815N are optimized to execute fragment shader programs, as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program, as provided in a Direct 3D API.

[0273] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, one or more MMU(s) 1820A-1820B provide virtual-to-physical address mapping for graphics processor 1810, including vertex processor 1805 and / or fragment processor(s) 1815A-1815N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more cache(s) 1825A-1825B. In at least one embodiment, one or more MMU(s) 1820A-1820B may be synchronized with other MMUs within a system, including one or more MMUs that are synchronized with one or more application processor(s) 1705, image processor(s) 1715, and / or video processor(s) 1720 of Fig. 17, so that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to connect to other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0274] In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F through 1855N-1 and 1855N), as shown in Fig. 18B, providing a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores may vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 acting as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N, and a tiling unit 1858 to accelerate tiling operations for tile-based rendering in which rendering operations for a scene are partitioned into image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0275] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in integrated circuit 18A and / or 18B may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0276] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0277] Fig. 19A- Fig. 19B illustrate additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, components described in Fig. 19A- Fig. 19B and described in connection therewith, are integrated into a single system, such as a graphics processing unit (GPU), an SoC, or other type of processor. Fig. 19A illustrates a graphics core 1900 included in at least one embodiment in the graphics processor 1710 of Fig. 17 and in at least one embodiment, a unified shader core 1855A -1855N as in Fig. 18B can be. Fig. 19B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1930, which in at least one embodiment is suitable for deployment on a multi-chip module. In at least one embodiment, the graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1700 includes the graphics core 1900, e.g., to form an integrated circuit and / or to form an SoC, such an integrated circuit and / or SoC performing operations described herein.

[0278] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 (e.g., including L1, L2, L3, a last-level cache, or other caches) that share execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A-1901N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to the graphics core 1900. In at least one embodiment, the slices 1901A-1901N have sub-slices that are part of a slice 1901A-1901N. In at least one embodiment, the disks 1901A-1901N are independent of other disks or dependent on other disks.In at least one embodiment, the slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N may include a set of additional functional units (AFUs 1912A-1912N), floating-point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address calculation units (ACUs 1913A-1913N), double-precision floating-point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, the MPUs 1917A-1917N are referred to as matrix engines.

[0279] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 1901A-1901N include 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, where vector engines and math units are exposed via matrix extensions. In at least one embodiment, a slice includes a specified portion of processing resources of a processing unit, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1900 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0280] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, a ray tracing unit computes ray tracing, triangle crossing, bounding box crossing, or other ray tracing operations.

[0281] In at least one embodiment, one or more slices 1901A-1901N include a media slice that encodes, decodes, and / or transcodes data; scales and / or format converts data; and / or performs video quality operations on video data.

[0282] In at least one embodiment, one or more slices 1901A-1901N are connected to L2 cache and memory fabric, interconnects, high bandwidth memory (HBM) (e.g., HBM2e, HDM3) stacks, and a media engine. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector machines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g.,instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in vector graphic format (e.g., shape) and converting it to a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 1901A-1901N includes a memory structure, e.g., an L2 cache.

[0283] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform 8-bit, 16-bit, and 32-bit variable-precision integer operations and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations.In at least one embodiment, the MPUs 1917-1917N may perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1912A-1912N may perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine). Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with. Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in graphics core 1900 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0284] In at least one embodiment, graphics core 1900 includes an interconnect and an interconnect fabric sublayer tied to a switch and a GPU-GPU bridge that enables multiple graphics processors 1900 (e.g., 8) to be connected without gluing together, with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0285] In at least one embodiment, graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected with an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1900 includes a compute tile, a memory tile (e.g., where a memory tile may be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, an interconnect tile, and an EMIB tile, all of which tiles are packaged together in graphics core 1900 as part of a GPU. In at least one embodiment, graphics core 1900 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 1900, an L1 cache; and a base tile may include a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, an 8-connect, 8-port interconnect tile with an embedded switch. In at least one embodiment, tiles are connected by face-to-face (F2F) chip-on-chip bonding through finely spaced 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, graphics core 1900 includes a memory structure that includes memory and is a tile accessible by multiple tiles. In at least one embodiment, graphics core 1900 stores, accesses, or loads its own hardware contexts in memory, where a hardware context is a set of data loaded from registers before a process continues, and where a hardware context may indicate a state of the hardware (e.g., the state of a GPU).

[0286] In at least one embodiment, graphics core 1900 includes a serializer / deserializer (SERDES) circuit that converts a serial data stream to a parallel data stream or converts a parallel data stream to a serial data stream.

[0287] In at least one embodiment, graphics core 1900 includes a coherent unified high-speed fabric (GPU-GPU), load / store units, bulk data transfer, and synchronization semantics, and connected GPUs through an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0288] In at least one embodiment, graphics core 1900 implements an API, where the API abstracts graphics core 1900 hardware and accesses libraries with instructions to perform mathematical operations (e.g., math core library), deep neural network operations (e.g., deep neural network library), vector operations, collective communications, thread building blocks, video processing, data analysis library, and / or ray tracing operations.

[0289] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0290] Fig. 19B illustrates a general-purpose processing unit (GPGPU) 1930 that may be configured to enable highly parallel computational operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1930 may be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable connection to a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 may be a vendor-specific communication interface or communication fabric.In at least one embodiment, GPGPU 1930 receives instructions from a host processor and uses a global scheduler 1934 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to dispatch execution threads associated with those instructions to a set of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H utilize a cache 1938. In at least one embodiment, cache 1938 may serve as a higher-level cache for caches within compute clusters 1936A-1936H. In at least one embodiment, GPGPU 1930 is part of an SoC, such as part of integrated circuit 1700 (. Fig. 17).

[0291] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR).

[0292] In at least one embodiment, compute clusters 1936A-1936H each include a set of graphics cores, such as the graphics core 1900 of Fig. 19A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0293] In at least one embodiment, multiple instances of GPGPU 1930 may be configured to operate as a compute cluster. In at least one embodiment, the communication used by compute clusters 1936A-1936H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU interconnect 1940 that enables direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU interconnect 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930.In at least one embodiment, GPU interconnect 1940 couples to a high-speed interconnect for transmitting and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate computing systems and communicate via a network device accessible via host interface 1932. In at least one embodiment, GPU interconnect 1940 may be configured to enable connection to a host processor in addition to, or alternatively to, host interface 1932.

[0294] In at least one embodiment, GPGPU 1930 may be configured to train neural networks. In at least one embodiment, GPGPU 1930 may be used within an inference platform. In at least one embodiment where GPGPU 1930 is used for inference, GPGPU 1930 may include fewer compute clusters 1936A-1936H compared to when GPGPU 1930 is used to train a neural network. In at least one embodiment, the memory technology associated with memory 1944A-1944B may differ between inference and training configurations, with higher-bandwidth memory technologies dedicated to training configurations. In at least one embodiment, an inference configuration of GPGPU 1930 may support the inference of specific instructions.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.

[0295] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in GPGPU 1930 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0296] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0297] Fig. 20 is a block diagram illustrating a computer system 2000 according to at least one embodiment. In at least one embodiment, computer system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 communicating via an interconnect path that may include a storage node 2005. In at least one embodiment, storage node 2005 may be a separate component within a chipset component or may be integrated with one or more processors 2002. In at least one embodiment, storage node 2005 couples to an I / O subsystem 2011 via a communications link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O node 2007 that may enable computer system 2000 to receive input from one or more input devices 2008.In at least one embodiment, I / O node 2007 may enable a display controller, which may be included in one or more processors 2002, to provide outputs to one or more display devices 2010A. In at least one embodiment, one or more display devices 2010A coupled to I / O node 2007 may include a local, internal, or embedded display device.

[0298] In at least one embodiment, processing subsystem 2001 includes one or more parallel processors 2012 coupled to storage node 2005 via a bus or other communication link 2013. In at least one embodiment, communication link 2013 may use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 2012 form a computationally focused parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as an integrated multiple core (MIC) processor.In at least one embodiment, some or all of the parallel processor(s) 2012 form a graphics processing subsystem that can output pixels to one or more display devices 2010A coupled via the I / O node 2007. In at least one embodiment, the parallel processor(s) 2012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2010B. In at least one embodiment, the parallel processor(s) 2012 include one or more cores, such as the graphics cores 1900 discussed herein.

[0299] In at least one embodiment, a system storage device 2014 may connect to the I / O node 2007 to provide a storage mechanism for the computing system 2000. In at least one embodiment, an I / O switch 2016 may be used to provide an interface mechanism to enable connections between the I / O node 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that may be integrated into the platform, and various other devices that may be added via one or more add-on devices 2020. In at least one embodiment, the network adapter 2018 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 2019 may include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

[0300] In at least one embodiment, the computing system 2000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I / O node 2007. In at least one embodiment, communication paths connecting various components in Fig. 20 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect or interconnect protocols.

[0301] In at least one embodiment, parallel processor(s) 2012 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and represent a graphics processing unit (GPU), e.g., parallel processor(s) 2012 include a graphics core 1900. In at least one embodiment, parallel processor(s) 2012 include circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 2012, memory node 2005, processor(s) 2002, and I / O node 2007 may be integrated into a system-on-chip (SoC) integrated circuit.In at least one embodiment, components of computing system 2000 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 2000 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0302] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in system FIG. 2000 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0303] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments. PROCESSOR

[0304] Fig. 21A illustrates a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2100 is a variant of one or more in Fig. 20, according to an exemplary embodiment. In at least one embodiment, a parallel processor 2100 includes one or more graphics cores 1900.

[0305] In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 may be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects to other devices using a node or switch interface, such as storage node 2105. In at least one embodiment, connections between storage node 2105 and I / O unit 2104 form a communication link 2113.In at least one embodiment, the I / O unit 2104 connects to a host interface 2106 and a memory crossbar 2116, where the host interface 2106 receives commands directed to performing processing operations and the memory crossbar 2116 receives commands directed to performing memory operations.

[0306] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 may direct work operations to a front end 2108 to perform those commands. In at least one embodiment, front end 2108 couples to a scheduler 2110 (which may be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is correctly configured and in a valid state before dispatching tasks to a cluster of processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2110 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 2112. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2112 via one of several graphics processing paths. In at least one embodiment, workloads may then be automatically distributed across the processing cluster array 2112 by the logic of the scheduler 2110 within a microcontroller that includes the scheduler 2110.

[0307] In at least one embodiment, the processing cluster array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B through cluster 2114N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may assign work to the clusters 2114A-2114N of the processing cluster array 2112 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred for each type of program or computation.In at least one embodiment, scheduling may be handled dynamically by scheduler 2110 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of processing cluster array 2112 may be assigned to process different types of programs or to perform different types of computations.

[0308] In at least one embodiment, processing cluster array 2112 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform parallel, multi-purpose computing operations. For example, in at least one embodiment, processing cluster array 2112 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0309] In at least one embodiment, processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tiling logic and other vertex processing logic. In at least one embodiment, processing cluster array 2112 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tile shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2102 may transfer data from system memory via I / O unit 2104 for processing.In at least one embodiment, data transferred during processing may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to system memory.

[0310] In at least one embodiment, when the parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 may be configured to divide a processing workload into approximately equally sized tasks to better facilitate the distribution of graphics processing operations across multiple clusters 2114A-2114N of the processing cluster array 2112. In at least one embodiment, portions of the processing cluster array 2112 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tile and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of the clusters 2114A-2114N may be stored in buffers to enable intermediate data to be transferred between the clusters 2114A-2114N for further processing.

[0311] In at least one embodiment, processing cluster array 2112 may receive processing tasks to be executed via scheduler 2110, which receives commands defining processing tasks from front-end 2108. In at least one embodiment, processing tasks may include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 2110 may be configured to retrieve indices corresponding to tasks or may receive indices from front-end 2108. In at least one embodiment, front-end 2108 may be configured to ensure that processing cluster array 2112 is configured to a valid state before executing a workload represented by incoming command buffers (e.g.,B. Stack buffer, Push buffer, etc.) is specified.

[0312] In at least one embodiment, each of one or more instances of parallel processing unit 2102 may couple to a parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 may be accessed via memory crossbar 2116, which may receive memory requests from processing cluster array 2112 as well as from I / O unit 2104. In at least one embodiment, memory crossbar 2116 may access parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, memory interface 2118 may include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which may couple to a portion (e.g., a memory unit) of parallel processor memory 2122.In at least one embodiment, a number of partition units 2120A-2120N is configured to be equal to a number of storage units, such that a first partition unit 2120A has a corresponding first storage unit 2124A, a second partition unit 2120B has a corresponding storage unit 2124B, and an Nth partition unit 2120N has a corresponding Nth storage unit 2124N. In at least one embodiment, a number of partition units 2120A-2120N may not be equal to a number of storage units.

[0313] In at least one embodiment, the memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including double data rate graphics memory (GDDR). In at least one embodiment, the memory units 2124A-2124N may also include stacked 3D memory, including, but not limited to, high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across the memory units 2124A-2124N, allowing the partition units 2120A-2120N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2122.In at least one embodiment, a local instance of parallel processor memory 2122 may be eliminated in favor of a unified memory design that uses system memory in conjunction with local cache memory.

[0314] In at least one embodiment, any of the clusters 2114A-2114N of the processing cluster array 2112 may process data written to any of the memory units 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 may be configured to transfer an output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N that may perform additional processing operations on an output. In at least one embodiment, each cluster 2114A-2114N may communicate with the memory interface 2118 via the memory crossbar 2116 to read from or write to various external memory devices.In at least one embodiment, memory crossbar 2116 includes a connection to memory interface 2118 to communicate with I / O unit 2104, as well as a connection to a local instance of parallel processor memory 2122, enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar 2116 may use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0315] In at least one embodiment, multiple instances of the parallel processing unit 2102 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2102 may be configured to interoperate, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.In at least one embodiment, the various instances of the parallel processing unit 2102 may be configured to cooperate with each other, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configurations. For example, in at least one embodiment, some instances of the parallel processing unit 2102 may include higher-precision floating-point units relative to other instances. In at least one embodiment, systems including one or more instances of the parallel processing unit 2102 or the parallel processor 2100 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld PCs, servers, workstations, gaming consoles, and / or embedded systems.

[0316] Fig. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is an instance of one of the partition units 2120A-2120N of Fig. 21A. In at least one embodiment, partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, L2 cache 2121 is a read / write cache configured to perform load and store operations received from memory crossbar 2116 and ROP 2126. In at least one embodiment, read misses and urgent write-back requests are issued by L2 cache 2121 to frame buffer interface 2125 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 2125 for processing. In at least one embodiment, frame buffer interface 2125 interfaces with one of the memory units in parallel processor memory, such as memory units 2124A-2124N of Fig. 21 (e.g. within the parallel processor memory 2122).

[0317] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP 2126 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to memory and for decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, a type of compression performed by ROP 2126 may vary based on statistical properties of data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0318] In at least one embodiment, the ROP 2126 is within each processing cluster (e.g., clusters 2114A-2114N of Fig. 21A) rather than within the partition unit 2120. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted across the memory crossbar 2116. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2010 of Fig. 20, for further processing by the processor(s) 2002 or for further processing by one of the processing entities within the parallel processor 2100 of Fig. 21A can be routed.

[0319] Fig. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2114A-2114N of Fig. 21A. In at least one embodiment, the processing cluster 2114 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction-multiple-data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction-multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters.

[0320] In at least one embodiment, the operation of the processing cluster 2114 may be controlled by a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 receives instructions from the scheduler 2110 of Fig. 21A and manages the execution of these instructions via a graphics multiprocessor 2134 and / or a texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2114. In at least one embodiment, one or more instances of the graphics multiprocessor 2134 may be included within a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and a data crossbar 2140 may be used to distribute processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2140.

[0321] In at least one embodiment, each graphics multiprocessor 2134 within the processing cluster 2114 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, in which new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be employed to perform different operations, and any combination of functional units may be present.

[0322] In at least one embodiment, instructions transferred to processing cluster 2114 represent a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within a graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within the graphics multiprocessor 2134.In at least one embodiment, when a thread group contains fewer threads than a number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is processing. In at least one embodiment, a thread group may also contain more threads than a number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group contains more threads than a number of processing engines within the graphics multiprocessor 2134, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2134.

[0323] In at least one embodiment, the graphics multiprocessor 2134 includes an internal cache to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2134 may forgo an internal cache and use a cache (e.g., L1 cache 2148) within the processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 also has access to L2 caches within partition units (e.g., partition units 2120A-2120N of Fig. 21A) that are shared by all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134 and can share common instructions and data that can be stored in L1 cache 2148.

[0324] In at least one embodiment, each processing cluster 2114 may include a memory management unit (MMU) 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside within the memory interface 2118 of Fig. 21A. In at least one embodiment, the MMU 2145 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, the MMU 2145 may include address translation buffers (TLBs) or caches that may be located within the graphics multiprocessor 2134 or the L1 cache 2148 or the processing cluster 2114. In at least one embodiment, a physical address is processed to distribute surface data access locally to enable efficient request interleaving between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0325] In at least one embodiment, a processing cluster 2114 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 for performing texture mapping operations, such as determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2134 issues processed tasks to the data crossbar 2140 to provide a processed task to another processing cluster 2114 for further processing or to store a processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2116.In at least one embodiment, a pre-ROP 2142 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2134 and pass data to ROP units that may be located with partition units as described herein (e.g., partition units 2120A-2120N of FIG. Fig. 21A). In at least one embodiment, the pre-ROP 2142 unit may perform optimizations for color mixing, organizing pixel color data, and performing address translations.

[0326] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in graphics processing cluster 2114 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0327] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0328] Fig. 21D illustrates a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to the pipeline manager 2132 of the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 includes an execution pipeline including, but not limited to, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general-purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166, where one or more load / store units 2166 may perform load / store operations to load / store instructions according to performing an operation.In at least one embodiment, GPGPU cores 2162 and load / store units 2166 are coupled to cache memory 2172 and shared memory 2170 via a memory and cache interconnect 2168. In at least one embodiment, GPGPU cores 2162 are part of an SoC, such as part of integrated circuit 1700 in FIG. Fig. 17.

[0329] In at least one embodiment, instruction cache 2152 receives a stream of instructions to be executed from pipeline manager 2132. In at least one embodiment, instructions are cached in instruction cache 2152 and dispatched for execution by an instruction unit 2154. In at least one embodiment, instruction unit 2154 may dispatch instructions as thread groups (e.g., warps, wavefronts, waves), where each thread of the thread group is assigned to a different execution unit within GPGPU cores 2162. In at least one embodiment, an instruction may access any of a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2156 may be used to translate addresses in a unified address space into a unique memory address that may be accessed by load / store units 2166.

[0330] In at least one embodiment, register file 2158 provides a set of registers for functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2162, load / store units 2166) of graphics multiprocessor 2134. In at least one embodiment, register file 2158 is partitioned between each of the functional units such that each functional unit is assigned a dedicated portion of register file 2158. In at least one embodiment, register file 2158 is partitioned between different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2134.

[0331] In at least one embodiment, the GPGPU cores 2162 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of the graphics multiprocessor 2134. In at least one embodiment, the GPGPU cores 2162 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of the GPGPU cores 2162 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs may implement floating-point arithmetic according to the IEEE 754-2008 standard or enable variable-precision floating-point arithmetic.In at least one embodiment, graphics multiprocessor 2134 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2162 may also include fixed-function or special-function logic.

[0332] In at least one embodiment, GPGPU cores 2162 include SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU cores 2162 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores may be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single-program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may execute from a single SIMD instruction.For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0333] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and to the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that enables the load / store unit 2166 to implement load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 may operate at the same frequency as the GPGPU cores 2162, so that data transfer between the GPGPU cores 2162 and the register file 2158 may have very low latency.In at least one embodiment, shared memory 2170 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2134. For example, in at least one embodiment, cache 2172 may be used as a data cache to cache texture data communicated between the functional units and texture unit 2136. In at least one embodiment, shared memory 2170 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2162 may programmatically store data within shared memory in addition to automatically cached data stored in cache 2172.

[0334] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on a package or chip as cores and communicatively coupled to cores via an internal processor bus / interconnect within a package or chip.In at least one embodiment, regardless of how a GPU is connected, processor cores of such a GPU may allocate work to such a GPU in the form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, this GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0335] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in graphics multiprocessor 2134 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0336] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0337] Fig. 22 illustrates a multi-GPU computer system 2200 according to at least one embodiment. In at least one embodiment, the multi-GPU computer system 2200 may include a processor 2202 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that couples the processor 2202 to a PCI Express bus over which the processor 2202 can communicate with GPGPUs 2206A-D. In at least one embodiment, GPGPUs 2206A-D may be interconnected via a set of high-speed, point-to-point GPU-to-GPU interconnects 2216. In at least one embodiment, the GPU-to-GPU connections 2216 connect to each of the GPGPUs 2206A-D via a dedicated GPU connection.In at least one embodiment, the P2P GPU connections 2216 enable direct communication between each of the GPGPUs 2206A-D without requiring communication over the host interface bus 2204 to which the processor 2202 is connected. In at least one embodiment, the host interface bus 2204 remains available with GPU-to-GPU traffic directed to the P2P GPU connections 2216 for system memory access or for communicating with other instances of the multi-GPU computing system 2200, for example, via one or more network devices. In at least one embodiment, GPGPUs 2206A-D are part of an SoC, such as part of the integrated circuit 1700 in FIG. Fig. 17, wherein GPGPUs 2206A-D perform operations described herein.

[0338] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in multi-GPU computing system 2200 may be used to infer or predict operations based at least in part on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0339] In at least one embodiment, multi-GPU computer system 2200 includes one or more graphics cores 1900.

[0340] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0341] Fig. 23 is a block diagram of a graphics processor 2300 according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated into a multi-core processing system. In at least one embodiment, graphics processor 2300 includes graphics core 1900.

[0342] In at least one embodiment, graphics processor 2300 receives batches of commands via ring interconnect 2302. In at least one embodiment, incoming commands are interpreted by a command streamer 2303 in pipeline front end 2304. In at least one embodiment, graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2380A-2380N. In at least one embodiment, command streamer 2303 provides commands to geometry pipeline 2336 for 3D geometry processing commands. In at least one embodiment, command streamer 2303 provides commands to a video front end 2334 coupled to media engine 2337 for at least some media processing commands.In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoder / decoder (MFX) 2333 engine to provide hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380.

[0343] In at least one embodiment, graphics processor 2300 includes scalable threaded execution resources with graphics cores 2380A-2380N (which may be modular and are sometimes referred to as core slices), each having a plurality of sub-cores 2350A-2360N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2300 may have any number of graphics cores 2380A. In at least one embodiment, graphics processor 2300 includes a graphics core 2380A with at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, graphics processor 2300 is a low-performance processor with a single sub-core (e.g., 2350A). In at least one embodiment, graphics processor 2300 includes a plurality of graphics cores 2380A-2380N, each including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N.In at least one embodiment, each subcore in the first subcores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each subcore in the second subcores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each subcore 2350A-2350N, 2360A-2360N utilizes a set of shared resources 2370A-2370N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic. In at least one embodiment, graphics processor 2300 includes load / store units in the pipeline front-end 2304.

[0344] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, logic 815 in graphics processor 2300 may be used to infer or predict operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0345] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0346] Fig. 24 is a block diagram illustrating a microarchitecture for a processor 2400 that may include logic circuitry for performing instructions, according to at least one embodiment. In at least one embodiment, the processor 2400 may execute instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), and so on. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point forms, may operate on packed data elements accompanying single-instruction, multiple-data ("SIMD"), and streaming SIMD extension ("SSE") instructions.In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond technology (commonly referred to as "SSEx") may hold such packed data operands. In at least one embodiment, processor 2400 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0347] In at least one embodiment, processor 2400 includes an in-order front-end ("front-end") 2401 to fetch instructions to be executed and prepare instructions to be used later in a processor pipeline. In at least one embodiment, front-end 2401 may include multiple units. In at least one embodiment, an instruction prefetcher 2426 fetches instructions from memory and passes instructions to an instruction decoder 2428, which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2428 decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also referred to as "micro-ops" or "uops" or "µ-ops"), that a machine may perform.In at least one embodiment, instruction decoder 2428 parses an instruction into an opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2430 can assemble decoded uops into program-ordered sequences or tracks in a uop queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, a microcode ROM 2432 provides uops needed to complete an operation.

[0348] In at least one embodiment, some instructions may be converted into a single micro-operation, while others may require multiple micro-ops to complete the full operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, instruction decoder 2428 may access microcode ROM 2432 to perform that instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2428. In at least one embodiment, an instruction may be stored within microcode ROM 2432 if a number of micro-ops are required to perform such an operation.In at least one embodiment, trace cache 2430 refers to a programmable entry point logic array ("PLA") for determining a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2432 according to at least one embodiment. In at least one embodiment, after microcode ROM 2432 finishes sequencing microops for an instruction, front-end 2401 of a machine may continue fetching microops from trace cache 2430.

[0349] In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 2403 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic includes a number of buffers to smooth and reorder the flow of instructions to optimize performance as they proceed down a pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2403 includes, without limitation, an arbiter / register renamer 2440, a memory uop queue 2442, an integer / floating point uop queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general floating point scheduler (“slow / general FP scheduler”) 2404, and a simple floating point scheduler (“simple FP scheduler”) 2406.In at least one embodiment, the fast scheduler 2402, the slow / general floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to herein as "uop schedulers 2402, 2404, 2406." In at least one embodiment, the arbiter / register renamer 2440 renames logical registers to entries in a register file. In at least one embodiment, the arbiter / register renamer 2440 also allocates an entry for each uop in one of two uop queues, the memory uop queue 2442 for memory operations and the integer / floating-point uop queue 2444 for non-memory operations, prior to the memory scheduler 2446 and the uop schedulers 2402, 2404, 2406.In at least one embodiment, the uop schedulers 2402, 2404, 2406 determine when a uop is ready for execution based on the readiness of their dependent input register operand sources and the availability of execution resources that the uop requires to complete its operation. In at least one embodiment, the fast scheduler 2402 can schedule on each half of a main clock cycle, while the slow / general floating-point scheduler 2404 and the simple floating-point scheduler 2406 can schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2402, 2404, 2406 arbitrate dispatch ports to schedule uops for execution.

[0350] In at least one embodiment, execution block 2411 includes, without limitation, an integer register file / bypass network 2408, a floating-point register file / bypass network (“FP register file / bypass network”) 2410, address generation units (“AGUs”) 2412 and 2414, fast arithmetic logic units (ALUs) (“Fast ALUs”) 2416 and 2418, a slow arithmetic logic unit (“Slow ALU”) 2420, a floating-point ALU (“FP”) 2422, and a floating-point move unit (“FP move”) 2424. In at least one embodiment, the AGUs 2412 and 2414, the fast ALUs 2416 and 2418, the slow ALU 2420, the floating-point ALU 2422, and the floating-point move unit 2424 also referred to herein as “execution units 2412, 2414, 2416, 2418, 2420, 2422 and 2424”.In at least one embodiment, execution block 2411 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0351] In at least one embodiment, register networks 2408, 2410 may be disposed between uop schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / bypass network 2408 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2410 performs floating-point operations. In at least one embodiment, each of register networks 2408, 2410 may include, without limitation, a bypass network that may bypass just-completed results that have not yet been written to a register file or forward them to new dependent uops. In at least one embodiment, register networks 2408, 2410 may communicate data with each other.In at least one embodiment, the integer register file / bypass network 2408 may include, without limitation, two separate register files, one register file for 32 low-order data bits and a second register file for 32 high-order data bits. In at least one embodiment, the floating-point register file / bypass network 2410 may include, without limitation, 128-bit wide entries, since floating-point instructions typically have operands 64 to 128 bits wide.

[0352] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, register networks 2408, 2410 store integer and floating-point data operand values ​​that microinstructions must execute. In at least one embodiment, processor 2400 may include, among other things, any number and combination of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 may execute floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2422 may include, among other things, a 64-bit by 64-bit floating point divider for performing divide, square root, and remainder micro-ops.In at least one embodiment, instructions involving a floating-point value may be handled with floating-point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2416, 2418. In at least one embodiment, the fast ALUs 2416, 2418 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations are passed to the slow ALU 2420, as the slow ALU 2420 may include, among other things, integer execution hardware for long-latency operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations may be performed by the ALUs 2412, 2414.In at least one embodiment, the fast ALU 2416, the fast ALU 2418, and the slow ALU 2420 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2416, the fast ALU 2418, and the slow ALU 2420 may be implemented to support a variety of data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2422 and the floating-point move unit 2424 may be implemented to support a range of operands with bits of different widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0353] In at least one embodiment, uop schedulers 2402, 2404, 2406 dispatch dependent operations before a parent load has completed execution. In at least one embodiment, because uops may be speculatively scheduled and executed in processor 2400, processor 2400 may also include logic to handle memory misses. In at least one embodiment, when a data load fails in a data cache, there may be dependent operations in flight in a pipeline that have exited a scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks instructions that use incorrect data and reexecutes them. In at least one embodiment, dependent operations may need to be replayed and independent operations may complete.In at least one embodiment, the schedulers and a replay mechanism of at least one embodiment of a processor may also be designed to detect instruction sequences for text string comparison operations. In at least one embodiment, the schedulers and a replay mechanism of at least one embodiment of a processor may also be designed to detect instruction sequences for text string comparison operations. In at least one embodiment.

[0354] In at least one embodiment, "registers" may refer to on-board processor memory locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside a processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, a register may store data, provide data, and perform functions described herein.In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0355] In at least one embodiment, the processor 2400 or each core of the processor 2400 includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g.,corresponding to operations or API calls), one or more micro-operation (µOP) caches for storing µOPs, one or more micro-operation (µOP) queues, an in-order execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shifter and / or pusher units, one or more fused multiply accumulate (FMA) units, one or more load and store units (“LSUs”) for performing the loading of memory operations corresponding to the load / store of data (e.g., instructions) to perform an operation (e.g.,Performing an API, an API call), one or more matrix multiply-accumulate (MMA) units, and / or one or more shuffle units for performing any function further described herein with respect to processor 2400. In at least one embodiment, processor 2400 may access, use, perform, or execute instructions corresponding to invoking an API.

[0356] In at least one embodiment, processor 2400 includes one or more ultrapath interconnects (UPIs), e.g., a point-to-point processor interconnect; one or more PCIe; one or more accelerators for accelerating computations or operations; and / or one or more memory controllers. In at least one embodiment, processor 2400 includes a shared last-level cache (LLC) coupled to one or more memory controllers that may enable shared memory access across processor cores.

[0357] In at least one embodiment, processor 2400 or a core of processor 2400 includes a mesh architecture in which processor cores, on-chip caches, memory controllers, and I / O controllers are organized into rows and columns, with wires and switches connecting them at each intersection to enable rotations. In at least one embodiment, processor 2400 includes one or more higher bandwidth memory blocks (HMBs, e.g., HMBe) for storing data or cache data, e.g., in double data rate 5 synchronous dynamic random access memory (DDR5 SDRAM). In at least one embodiment, one or more components of processor 2400 are interconnected using Compute Express Link (CXL) interconnects. In at least one embodiment, a memory controller uses a least recently used (LRU) approach to determine what is stored in a cache.In at least one embodiment, the processor 2400 includes one or more PCIe (e.g., PCIe 5.0).

[0358] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, portions or all of logic 815 may be included in execution block 2411 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more of the ALUs illustrated in execution block 2411. Furthermore, weighting parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of execution block 2411 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0359] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0360] Fig. 25 illustrates a deep learning application processor 2500 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2500 uses instructions that, when executed by the deep learning application processor 2500, cause the deep learning application processor 2500 to perform some or all of the processes and techniques described in this disclosure. In at least one embodiment, the deep learning application processor 2500 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2500 performs matrix multiplication operations either as a result of performing one or more instructions or both "hard-wired" in hardware.In at least one embodiment, the deep learning application processor 2500 includes, without limitation, processing clusters 2510(1)-2510(12), inter-chip interconnects (“ICLs”) 2520(1)-2520(12), inter-chip controllers (“ICCs”) 2530(1)-2530(2), second-generation high-bandwidth memory (“HBM2”) 2540(1)-2540(4), memory controllers (“Mem Ctrlrs”) 2542(1)-2542(4), high-bandwidth physical memory layer (“HBM PHY”) 2544(1)-2544(4), a management controller central processing unit (“Management Controller CPU”) 2550, a serial peripheral interface, an inter-integrated circuit, and a general-purpose input / output block (“SPI, I. 2 C, GPIO”) 2560, a Peripheral Component Interconnect Express Controller and Direct Memory Access Block (“PCIe Controller and DMA”) 2570 and a sixteen-lane Peripheral Component Interconnect Express Port (“PCI Express x 16”) 2580.

[0361] In at least one embodiment, processing clusters 2510 may perform deep learning operations, including inference or prediction operations based on weighting parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2510 may include, among other things, any number and type of processors. In at least one embodiment, deep learning application processor 2500 may include any number and type of processing clusters 2500. In at least one embodiment, inter-chip interconnects 2520 are bidirectional.In at least one embodiment, inter-chip interconnects 2520 and inter-chip controllers 2530 enable multiple deep learning application processors 2500 to exchange information, including activation information resulting from the execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2500 may include any number (including zero) and type of ICLs 2520 and ICCs 2530.

[0362] In at least one embodiment, the HBM2s 2540 provide a total of 32 gigabytes (GB) of memory. In at least one embodiment, the HBM2 2540(i) is associated with both the memory controller 2542(i) and the HBM PHY 2544(i), where "i" is any integer. In at least one embodiment, any number of HBM2s 2540 may provide any type and total amount of high-bandwidth memory and may be associated with any number (including zero) and type of memory controllers 2542 and HBM PHYs 2544. In at least one embodiment, SPI, I 2 C, GPIO 2560, PCIe control and DMA 2570 and / or PCIe 2580 can be replaced by any number and type of blocks enabling any number and type of communication standards in any technically possible way.

[0363] Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 815 are described herein in connection with Fig. 8A and / or Fig. 8B. In at least one embodiment, the deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2500. In at least one embodiment, the deep learning application processor 2500 is used to infer or predict information based on a trained machine learning model (e.g., neural network) trained by another processor or system or by the deep learning application processor 2500. In at least one embodiment, processor 2500 may be used to perform one or more neural network use cases described herein.

[0364] Embodiments of the above figure may include any of the Fig. 1- Fig. 7 described embodiments.

[0365] Fig. 26 is a block diagram of a neuromorphic processor 2600 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2600 may receive one or more inputs from sources external to the neuromorphic processor 2600. In at least one embodiment, these inputs may be communicated to one or more neurons 2602 within the neuromorphic processor 2600. In at least one embodiment, the neurons 2602 and components thereof may be implemented using circuitry or logic that includes one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2600 may include, among other things, thousands or millions of instances of neurons 2602, but any suitable number of neurons 2602 may be used. In at least one embodiment, each instance of neuron 2602 may include a neuron input 2604 and a neuron output 2606.In at least one embodiment, neurons 2602 may generate outputs that may be transmitted to inputs of other instances of neurons 2602. For example, in at least one embodiment, neuron inputs 2604 and neuron outputs 2606 may be connected to each other via synapses 2608.

[0366] In at least one embodiment, neurons 2602 and synapses 2608 may be interconnected such that neuromorphic processor 2600 operates to process or analyze information received by neuromorphic processor 2600. In at least one embodiment, neurons 2602 may transmit an output pulse (or "fire" or "spike") when inputs received through neuron input 2604 exceed a threshold. In at least one embodiment, neurons 2602 may sum or integrate signals received at neuron inputs 2604.For example, in at least one embodiment, neurons 2602 may be implemented as leaky-integrate-and-fire neurons, where when a sum (referred to as a "membrane potential") exceeds a threshold, neuron 2602 may generate an output (or "fire") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky-integrate-and-fire neuron may sum signals received at neuron inputs 2604 into a membrane potential and may also apply a decay factor (or leak) to decrease a membrane potential. In at least one embodiment, a leaky-integrate-and-fire neuron may fire when multiple input signals are received at neuron inputs 2604 quickly enough to exceed a threshold (i.e., before a membrane potential decays too low to fire).In at least one embodiment, neurons 2602 may be implemented using circuitry or logic that receives inputs, integrates inputs into a membrane potential, and decays a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neurons 2602 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron output 2606 when the result of applying a transfer function to neuron input 2604 exceeds a threshold. In at least one embodiment, once neuron 2602 fires, it may take previously received input information into account, for example, by resetting a membrane potential to 0 or another suitable default value.In at least one embodiment, once the membrane potential is reset to 0, the neuron 2602 may resume normal operation after a suitable period of time (or refractory period).

[0367] In at least one embodiment, neurons 2602 may be interconnected by synapses 2608. In at least one embodiment, synapses 2608 may operate to transmit signals from an output of a first neuron 2602 to an input of a second neuron 2602. In at least one embodiment, neurons 2602 may transmit information across more than one instance of synapse 2608. In at least one embodiment, one or more instances of neuron output 2606 may be connected across an instance of synapse 2608 to an instance of neuron input 2604 in the same neuron 2602. In at least one embodiment, an instance of neuron 2602 that generates an output to be transmitted across an instance of synapse 2608 may be referred to as a "presynaptic neuron" with respect to that instance of synapse 2608.In at least one embodiment, an instance of neuron 2602 that receives input transmitted across an instance of synapse 2608 may be referred to as a "postsynaptic neuron" with respect to that instance of synapse 2608. Because an instance of neuron 2602 may receive input from one or more instances of synapse 2608 and may also transmit outputs across one or more instances of synapse 2608, in at least one embodiment, a single instance of neuron 2602 may therefore be both a "presynaptic neuron" and a "postsynaptic neuron" with respect to different instances of synapses 2608.

[0368] In at least one embodiment, neurons 2602 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2602 may have a neuron output 2606 that may fan out through one or more synapses 2608 to one or more neuron inputs 2604. In at least one embodiment, neuron outputs 2606 from neurons 2602 in a first layer 2610 may be connected to neuron inputs 2604 from neurons 2602 in a second layer 2612. In at least one embodiment, each instance of neuron 2602 in an instance of the first layer 2610 may fan out to each instance of neuron 2602 in the second layer 2612. In at least one embodiment, each instance of neuron 2602 in an instance of second layer 2612 may fan out to fewer than all instances of neuron 2602 in a third layer 2614.In at least one embodiment, neurons 2602 in the second layer 2612 may fan out to neurons 2602 in multiple other layers, including neurons 2602 also in the second layer 2612. In at least one embodiment, the neuromorphic processor 2600 may include, among other things, any suitable combination of recurrent layers and feedforward layers, including, among other things, both sparsely connected feedforward layers and fully connected feedforward layers.

[0369] In at least one embodiment, the neuromorphic processor 2600 may include, among other things, a reconfigurable interconnect architecture or dedicated hard-wired interconnects to connect the synapse 2608 to the neurons 2602. In at least one embodiment, the neuromorphic processor 2600 may include, among other things, circuitry or logic that enables synapses to be assigned to different neurons 2602 as needed based on neural network topology and neuron fan-in / out. For example, in at least one embodiment, the synapses 2608 may be connected to the neurons 2602 using an interconnect structure, such as network-on-chip, or with dedicated interconnects. In at least one embodiment, synap...

Claims

[1] Processor comprising: one or more circuits for using one or more first neural networks to cause one or more compressed neural networks to be selected based at least in part on accuracy and performance of the one or more compressed neural networks. [2] The processor of claim 1, wherein selecting the one or more compressed neural networks comprises: Selecting one or more target metrics associated with the one or more compressed neural networks; Determining one or more compression strategies based at least in part on the one or more target metrics; and Obtaining the one or more compressed neural networks by compressing one or more second neural networks based at least in part on the one or more compression strategies. [3] The processor of claim 2, wherein the one or more target metrics include one or more target accuracy metrics and one or more target performance metrics of the one or more compressed neural networks on one or more processing units. [4] The processor of claim 2, wherein the one or more compression strategies comprise a plurality of compression configurations corresponding to a plurality of layers of the one or more second neural networks, each compression configuration determined at least in part based on one or more layer metrics associated with a corresponding layer of the one or more second neural networks. [5] The processor of claim 4, wherein the one or more layer metrics are initialized based on a prediction of the accuracy and performance of the one or more compressed neural networks after compressing the corresponding layer. [6] The processor of claim 1, wherein the one or more circuits are further to perform: Obtaining one or more performance metrics associated with the accuracy and performance of the one or more compressed neural networks on one or more processing units; and Using the one or more first neural networks to determine one or more compression strategies based at least in part on the one or more deployment metrics. [7] The processor of claim 6, wherein the one or more first neural networks are to determine the one or more compression strategies by updating one or more policies with the one or more deployment metrics. [8] A system comprising: one or more processors to use one or more first neural networks to cause one or more compressed neural networks to be selected based at least in part on accuracy and performance of the one or more compressed neural networks. [9] The system of claim 8, wherein selecting the one or more compressed neural networks comprises: Selecting one or more target metrics associated with the one or more compressed neural networks; Determining one or more compression strategies based at least in part on the one or more target metrics; and Obtaining the one or more compressed neural networks by compressing one or more second neural networks based at least in part on the one or more compression strategies. [10] The system of claim 9, wherein the one or more target metrics include one or more target accuracy metrics and one or more target performance metrics of the one or more compressed neural networks on one or more processing units. [11] The system of claim 9, wherein the one or more compression strategies comprise a plurality of compression configurations corresponding to a plurality of layers of the one or more second neural networks, each compression configuration determined at least in part based on one or more layer metrics associated with a corresponding layer of the one or more second neural networks. [12] The system of claim 11, wherein the one or more layer metrics are initialized based on a prediction of the accuracy and performance of the one or more compressed neural networks after compressing the corresponding layer. [13] The system of claim 8, wherein the one or more processors are further configured to: Obtaining one or more performance metrics associated with the accuracy and performance of the one or more compressed neural networks on one or more processing units; and Using the one or more first neural networks to determine one or more compression strategies based at least in part on the one or more deployment metrics. [14] The system of claim 13, wherein the one or more first neural networks are to determine the one or more compression strategies by updating one or more policies with the one or more deployment metrics. [15] A non-transitory machine-readable medium having stored thereon a set of instructions that, when executed by one or more processors, cause the one or more processors to do at least the following: Using one or more first neural networks to cause one or more compressed neural networks to be selected based at least in part on accuracy and performance of the one or more compressed neural networks. [16] The non-transitory machine-readable medium of claim 15, wherein selecting the one or more compressed neural networks comprises: Selecting one or more target metrics associated with the one or more compressed neural networks; Determining one or more compression strategies based at least in part on the one or more target metrics; and Obtaining the one or more compressed neural networks by compressing one or more second neural networks based at least in part on the one or more compression strategies. [17] The non-transitory machine-readable medium of claim 16, wherein the one or more target metrics include one or more target accuracy metrics and one or more target performance metrics of the one or more compressed neural networks on one or more processing units. [18] The non-transitory machine-readable medium of claim 16, wherein the one or more compression strategies comprise a plurality of compression configurations corresponding to a plurality of layers of the one or more second neural networks, each compression configuration determined at least in part based on one or more layer metrics associated with a corresponding layer of the one or more second neural networks. [19] The non-transitory machine-readable medium of claim 18, wherein the one or more layer metrics are initialized based on a prediction of the accuracy and performance of the one or more compressed neural networks after compressing the corresponding layer. [20] The non-transitory machine-readable medium of claim 15, wherein the set of instructions further causes the one or more processors to: Obtaining one or more performance metrics associated with the accuracy and performance of the one or more compressed neural networks on one or more processing units; and Using the one or more first neural networks to determine one or more compression strategies based at least in part on the one or more deployment metrics.

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