DISPLAY PANEL AND DISPLAY DEVICE

Abstract

A display panel and a display device are presented. A compensation module in a display panel is used to apply a first compensation voltage to the subpixels during the idle times of a first display image, and to supply a second compensation voltage to the subpixels during the idle times of a second display image. The polarity of the first compensation voltage corresponds to the polarity of the first data voltage, and the polarity of the second compensation voltage corresponds to the polarity of the second data voltage, wherein the first compensation voltage is non-zero, as is the second compensation voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology and, in particular, to a display panel and a display device. STATE OF THE ART

[0002] In conventional display panels, the polarity of the data voltages input to the sub-pixels is opposite in two continuously displayed images. Due to the current leakage in the source and drain electrodes of the switching transistors, the brightness of the sub-pixels gradually decreases after the scanning of the first display image is completed. After the transition to the second display image, due to the opposite polarity of the data voltages input to the sub-pixels, the voltage difference between the source and drain electrodes of the switching transistors increases. This accelerates the current leakage between the source and drain electrodes, causing the brightness of the sub-pixels to further decrease until the pixel brightness increases significantly after the next scan. Therefore, a significant brightness difference results between the two continuously displayed images in the display panel, which causes display flicker.US 2005 / 0 190 176 A1 discloses a flat display device. DISCLOSURE OF THE INVENTION OVERVIEW OF THE INVENTION

[0003] The present application presents a display panel and a display device for eliminating flickering of the display panel caused by a significant brightness difference between two continuously displayed images. On the one hand, the embodiments of the present application present a display panel in which an image displayed on the display panel comprises a first display image and a second display image that are continuously displayed. The display panel comprises: a plurality of sub-pixels, a plurality of scan lines, a plurality of data lines, and a compensation module. A plurality of said scan lines are arranged along a first direction and are respectively electrically connected to said plurality of sub-pixels; a plurality of said data lines are arranged along a second direction;the first and second directions are crossed, and a plurality of said data lines are each electrically connected to said plurality of sub-pixels; the polarity of the first data voltage to the sub-pixels during the display time of the first display image is opposite to the polarity of the second data voltage to the sub-pixels during the display time of the second display image; said compensation module is electrically connected to one end of a plurality of data lines and serves to apply the first compensation voltage to the sub-pixels during the idle times of the first display image and the second compensation voltage to the sub-pixels during the idle times of the second display image;The polarity of the first compensation voltage corresponds to the polarity of the first data voltage, and the polarity of the second compensation voltage corresponds to the polarity of the second data voltage. The first compensation voltage is non-zero, just like the second compensation voltage. According to a first proposal, the compensation module comprises a compensation voltage output, the compensation voltage output being electrically connected to one end of the plurality of data lines and serving to output the first compensation voltage and the second compensation voltage; the absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage.

[0004] According to a second proposal, the plurality of data lines includes a plurality of first data lines and a plurality of second data lines, wherein the plurality of first data lines and the plurality of second data lines are alternately arranged along the second direction. The first data voltage includes a first positive data voltage and a first negative data voltage; during the display time of the first display image, the data voltage input from the first data lines to the sub-pixels is the first positive data voltage, and the data voltage input from the second data lines to the sub-pixels is the first negative data voltage.The second data voltage includes a second positive data voltage and a second negative data voltage; during the display time of the second display image, the data voltage input from the first data lines to the sub-pixels is the second negative data voltage, and the data voltage input from the second data lines to the sub-pixels is the second positive data voltage.The compensation module comprises a first output of the compensation voltage and a second output of the compensation voltage, wherein the first output of the compensation voltage is electrically connected to the first data lines, wherein the first compensation voltage comprises a first positive compensation voltage and a first negative compensation voltage, wherein the magnitude of the first positive compensation voltage is less than or equal to the magnitude of the first positive data voltage, and the magnitude of the first negative compensation voltage is greater than or equal to the magnitude of the first negative data voltage.The second output of the compensation voltage is electrically connected to the second data lines, wherein the second compensation voltage comprises a second positive compensation voltage and a second negative compensation voltage, wherein the magnitude of the second positive compensation voltage is less than or equal to the magnitude of the second positive data voltage and the magnitude of the second negative compensation voltage is greater than or equal to the magnitude of the second negative data voltage. The compensation module comprises a plurality of first switching transistors and a plurality of second switching transistors, wherein the gate electrodes of the plurality of first switching transistors and the plurality of second switching transistors are electrically connected to a global control signal terminal.One of the source electrode and the drain electrode of the first switching transistors is electrically connected to the first output of the compensation voltage, and the other is electrically connected to one end of the first data lines; one of the source electrode and the drain electrode of the second switching transistors is electrically connected to the second output of the compensation voltage, and the other is electrically connected to one end of the second data lines. The first switching transistors and the second switching transistors are closed during the display time and open during the blank time, the blank time comprising a first blank time period and a second blank time period, the first blank time period being adjacent to the second blank time period.The first switching transistors and the second switching transistors are open during the first idle time period and closed during the second idle time period; or wherein the first switching transistors and the second switching transistors are open during the second idle time period and closed during the first idle time period.

[0005] On the other hand, in the embodiments of the present application, a display device is presented which comprises a frame and a display panel described herein. BENEFICIAL EFFECTS

[0006] In the embodiments of the present application, the compensation module is electrically connected to one end of a plurality of data lines and serves to apply the first compensation voltage to the sub-pixels during the idle times of the first display image in the continuously displayed first and second display images, and to apply the second compensation voltage to the sub-pixels during the idle times of the second display image, in order to reduce the voltage difference between the source and drain electrodes of the sub-pixels during the idle time, maintain the potential stability of the sub-pixels, and prevent current leakage. The problem of display flickering caused by a significant brightness difference between the two continuously displayed display images, orThe significant drop in brightness of the sub-pixels between the end of one scan and the beginning of the next scan, as well as the significant increase in brightness after a scan, caused by a power leak, is also mitigated by the aforementioned compensation module, thus improving the display quality. PRESENTATION OF THE INVENTION Fig. 1: a schematic representation of control of the display panel according to the first embodiment of this application; Fig. 2: the first timing diagram of driving the display panel according to the embodiment of this application; Fig. 3: the second timing diagram of driving the display panel according to the embodiment of this application; Fig. 4: a schematic representation of the display panel according to the first embodiment of this application; Fig. 5: the third timing diagram of driving the display panel according to the embodiment of this application; Fig. 6: the fourth timing diagram of driving the display panel according to the embodiment of this application; Fig. 7: the fifth timing diagram of driving the display panel according to the embodiment of this application; Fig. 8: a schematic representation of the display panel according to the third embodiment of this application; Fig. 9: the sixth timing diagram of driving the display panel according to the embodiment of this application; Fig. 10: the seventh timing diagram of driving the display panel according to the embodiment of this application; Fig. 11: a schematic representation of the display panel according to the fourth embodiment of this application. CONCRETE EMBODIMENTS

[0007] The technical solution is described below with reference to the accompanying drawings from the embodiments of the present application. The described embodiments serve solely to illustrate and explain the concept of the present application and should not be considered as limiting the scope of the application.

[0008] The present application offers various embodiments that are similar, and features in different embodiments are combined.

[0009] See Fig. 1.: In the embodiments of the present application, a display panel 100 is presented. In the display panel 100, an image displayed on the display panel includes a first display image and a second display image that are continuously displayed. The display panel 100 includes: a plurality of sub-pixels 10; a plurality of scan lines 20; a plurality of data lines 30; and a compensation module 40. A plurality of scan lines 20 are arranged along a first direction Y, and the plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10, respectively.A plurality of data lines 30 are arranged along a second direction X, wherein the first direction Y and the second direction X intersect; wherein a plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10, respectively, wherein the polarity of the first data voltage from the data lines 30 at the display time of the first display image to the sub-pixels 10 is opposite to the polarity of the second data voltage from the data lines 30 at the display time of the second display image to the sub-pixels 10.

[0010] The compensation module 40 is electrically connected to one end of the plurality of data lines 30 and is used to apply a first compensation voltage to the sub-pixels 10 during the idle times of the first display image and a second compensation voltage to the sub-pixels 10 during the idle times of the second display image; wherein the polarity of the first compensation voltage corresponds to the polarity of the first data voltage and the polarity of the second compensation voltage corresponds to the polarity of the second data voltage; wherein the first compensation voltage is not zero and the second compensation voltage is not zero.

[0011] By electrically connecting the compensation module 40 to one end of a plurality of data lines 30 and applying the first compensation voltage to the sub-pixels 10 during the idle time of the first display image in continuously displayed first and second display images, and applying the second compensation voltage to the sub-pixels 10 during the idle time of the second display image, the potential stability of the sub-pixels 10 in the display panel 100 is maintained, and the problem of display flicker caused by a significant brightness difference between the two continuously displayed display images, or a significant brightness drop of the sub-pixels 10 between the end of one scan and the start of the next scan due to a current leakage, and a significant increase in brightness after one scan of the sub-pixels 10, is also improved.

[0012] In the embodiments of the present application, the compensation module 40 includes a compensation voltage output V0 electrically connected to one end of the plurality of data lines 30 and serves to output the first compensation voltage and the second compensation voltage. The absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage.

[0013] If the first data voltage has a positive polarity, for example, if the first data voltage is 2 volts, the first compensation voltage is greater than 0 volts and less than or equal to 2 volts, for example, 1.5 volts. If the first data voltage has a negative polarity, for example, if the first data voltage is -2 volts, the first compensation voltage is less than 0 volts and greater than or equal to -2 volts, for example, -1.5 volts.

[0014] The absolute value of the first compensation voltage is equal to the absolute value of the second compensation voltage.

[0015] In the embodiments of the present application, the compensation module 40 includes a plurality of switching transistors T0, wherein the gate electrodes of the plurality of switching transistors T0 are electrically connected to a global control signal terminal GAS0. Either the source electrode or the drain electrode of the switching transistors T0 is electrically connected to the output of the compensation voltage V0, and the other is electrically connected to one end of the data lines 30.

[0016] In the embodiments of the present application, the display panel includes a gate electrode driver 50 and a source electrode driver 60; the gate electrode driver 50 is electrically connected to a plurality of scan lines 20 and serves to supply a scan signal to the sub-pixel 10. The source electrode driver 60 is electrically connected to one end of the plurality of data lines 30 and serves to supply data voltage to the sub-pixel 10.

[0017] In the embodiments of the present application, the turn-on time of the switching transistors T0 in the idle times is greater than or equal to the turn-off time.

[0018] See Fig. 1 and Fig. 2: During the display time t01, the global control signal terminal GAS0 is fed with a low electrical potential as the global control signal gas0. During the idle time t02, the global control signal terminal GAS0 is fed with a high electrical potential as the global control signal gas0. The switching transistors T0 remain open during the idle time t02.

[0019] See Fig. 1 and Fig. 3: During the display time t01, the global control signal terminal GAS0 is inputted with a low electric potential as the global control signal gas0. During a portion of the idle time t02, the global control signal terminal GAS0 is inputted with a high electric potential as the global control signal gas0. The switching transistors T0 are opened under the control of the high electric potential of the global control signal gas0. A portion of the idle time t02 includes any portion of the idle time t02.

[0020] See Fig. 4: In the embodiments of the present application, a display panel 200 is presented. The difference between the display panel 200 and the display panel 100 is that a plurality of data lines 30 comprise a plurality of first data lines 31 and a plurality of second data lines 32. The compensation module 40 comprises a first output of the compensation voltage V1, a second output of the compensation voltage V2, a plurality of first switching transistors T1, and a plurality of second switching transistors T2, wherein the first output of the compensation voltage V1 is electrically connected to the first switching transistors T1 and the first data lines 31, and the second output of the compensation voltage is electrically connected to the second switching transistors T2 and the second data lines 32.

[0021] In the display panel 200, an image displayed on the display panel includes a first display image and a second display image that are continuously displayed. The display panel 200 includes: a plurality of sub-pixels 10; a plurality of scan lines 20; a plurality of data lines 30; and a compensation module 40. A plurality of scan lines 20 are arranged along a first direction Y, and the plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10, respectively.A plurality of data lines 30 are arranged along a second direction X, wherein the first direction Y and the second direction X intersect; wherein a plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10, respectively, wherein the polarity of the first data voltage from the data lines 30 at the display time of the first display image to the sub-pixels 10 is opposite to the polarity of the second data voltage from the data lines 30 at the display time of the second display image to the sub-pixels 10.

[0022] A plurality of data lines 30 includes a plurality of first data lines 31 and a plurality of second data lines 32, wherein the plurality of first data lines 31 and the plurality of second data lines 32 are arranged alternately along the second direction. The first data voltage includes a first positive data voltage and a first negative data voltage; during the display time of the first display image, the data voltage input from the first data lines 31 to the sub-pixels 10 is the first positive data voltage, and the data voltage input from the second data lines 32 to the sub-pixels 10 is the first negative data voltage.The second data voltage includes a second positive data voltage and a second negative data voltage; during the display time of the second display image, the data voltage input from the first data lines 31 to the sub-pixels 10 is the second negative data voltage, and the data voltage input from the second data lines 32 to the sub-pixels 10 is the second positive data voltage.

[0023] In the embodiments of the present application, the compensation module 40 comprises a first output of the compensation voltage V1 and a second output of the compensation voltage V2, wherein the first output of the compensation voltage V1 is electrically connected to the first data lines 31, wherein the first compensation voltage comprises a first positive compensation voltage and a first negative compensation voltage, wherein the magnitude of the first positive compensation voltage is less than or equal to the magnitude of the first positive data voltage, and the magnitude of the first negative compensation voltage is greater than or equal to the magnitude of the first negative data voltage. For example, if the first data voltage is 2 volts, the first compensation voltage is greater than 0 volts and less than or equal to 2 volts, for example, 1.5 volts.If the first data voltage is -2 volts, the first compensation voltage is less than 0 volts and greater than or equal to -2 volts, for example -1.5 volts.

[0024] The second output of the compensation voltage V2 is electrically connected to the second data lines 32, wherein the second compensation voltage comprises a second positive compensation voltage and a second negative compensation voltage, wherein the magnitude of the second positive compensation voltage is less than or equal to the magnitude of the second positive data voltage and the magnitude of the second negative compensation voltage is greater than or equal to the magnitude of the second negative data voltage.

[0025] For example, if the second data voltage is 2 volts, the second compensation voltage is greater than 0 volts and less than or equal to 2 volts, for example, 1 volt. If the second data voltage is -2 volts, the second compensation voltage is less than 0 volts and greater than or equal to -2 volts, for example, -1 volt.

[0026] In the embodiments of the present application, the compensation module 40 comprises a plurality of first switching transistors T1 and a plurality of second switching transistors T2, wherein the gate electrodes of the plurality of first switching transistors T1 and the plurality of second switching transistors T2 are electrically connected to a global control signal terminal GAS0. One of the source electrodes and the drain electrodes of the first switching transistors T1 is electrically connected to the first output of the compensation voltage V1, and the other is electrically connected to one end of the data lines 31. One of the source electrodes and the drain electrodes of the second switching transistors T2 is electrically connected to the second output of the compensation voltage V2, and the other is electrically connected to one end of the data lines 32.

[0027] In the embodiments of the present application, the first switching transistors T1 and the second switching transistors T2 are closed during the display time and open during the idle time.

[0028] See Fig. 5: During the display time t01, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0, with the first switching transistors T1 and the second switching transistors T2 being closed. The idle time t02 comprises a first idle time period t001 and a second idle time period t002, with the first idle time period t001 adjacent to the second idle time period t002, and the duration of the first idle time period t001 is equal to the duration of the second idle time period t002. During the first idle time period t001, the global control signal terminal GAS0 is supplied with a high electrical potential as the global control signal gas0, with the first switching transistors T1 and the second switching transistors T2 being open during the first idle time period t001.During the second idle time period t002, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0, wherein the first switching transistors T1 and the second switching transistors T2 are closed during the second idle time period t002.

[0029] See Fig. 6: During the display time t01, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0, and the first switching transistors T1 and the second switching transistors T2 are closed. The idle time t02 comprises a first idle time period t001 and a second idle time period t002, wherein the first idle time period t001 is adjacent to the second idle time period t002, and the duration of the first idle time period t001 is equal to the duration of the second idle time period t002. During the first idle time period t001, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0, and the first switching transistors T1 and the second switching transistors T2 are closed during the first idle time period t001.During the second idle time period t002, the global control signal terminal GAS0 is supplied with a high electric potential as the global control signal gas0, wherein the first switching transistors T1 and the second switching transistors T2 are open during the second idle time period t002.

[0030] See Fig. 7: During idle times t02, the on-time of the first switching transistors T1 and the second switching transistors T2 is longer than the off-time. This ensures that the subpixels located on the data lines electrically connected to the first switching transistors T1 have a sufficiently long duration to receive the compensation voltage, thus improving the potential stability of the subpixels. Likewise, this ensures that the subpixels located on the data lines electrically connected to the second switching transistors T2 have a sufficiently long duration to receive the compensation voltage, thus improving the potential stability of the subpixels.

[0031] The idle time t02 comprises a first idle time period t001 and a second idle time period t002, wherein the first idle time period t001 is adjacent to the second idle time period t002, and the duration of the first idle time period t001 is longer than the duration of the second idle time period t002.

[0032] In the embodiments of the present application, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0 during the display time t01, wherein the first switching transistors T1 and the second switching transistors T2 are closed. The idle time comprises a first idle time period t001 and a second idle time period t002, wherein the first idle time period t001 is adjacent to the second idle time period t002. During the first idle time period t001, the global control signal terminal GAS0 is supplied with a high electrical potential as the global control signal gas0, wherein the first switching transistors T1 and the second switching transistors T2 are open during the first idle time period t001.During the second idle time period t002, the global control signal terminal GAS0 is supplied with a low electrical potential as the global control signal gas0, wherein the first switching transistors T1 and the second switching transistors T2 are closed during the second idle time period t002.

[0033] Alternatively, the duration of the second idle time period t002 is longer than the duration of the first idle time period t001, wherein the first switching transistors T1 and the second switching transistors T2 are open during the second idle time period t002 and closed during the first idle time period t001.

[0034] See Fig. 8: In the embodiments of the present application, a display panel 300 is presented. The difference between the display panel 300 and the display panel 200 is that the gate electrode of a plurality of first switching transistors T1 is electrically connected to the first control signal terminal GAS1, and the gate electrode of a plurality of second switching transistors T2 is electrically connected to the second control signal terminal GAS2.

[0035] In particular, the compensation module 40 comprises a plurality of first switching transistors T1 and a plurality of second switching transistors T2, wherein the gate electrodes of the plurality of first switching transistors T1 are electrically connected to a first control signal terminal GAS1, and the gate electrodes of the plurality of second switching transistors T2 are electrically connected to a second control signal terminal GAS2. One of the source electrodes and the drain electrodes of the first switching transistors T1 is electrically connected to the first output of the compensation voltage V1, and the other is electrically connected to one end of the data lines 31. One of the source electrodes and the drain electrodes of the second switching transistors T2 is electrically connected to the second output of the compensation voltage V2, and the other is electrically connected to one end of the data lines 32.

[0036] The remaining components of the display panel 300 are identical to the remaining components of the display panel 200.

[0037] See Fig. 8: Types of the first switching transistors T1 are identical to types of the second switching transistors T2, namely N-channel transistors (N-type).

[0038] See Fig. 9: The idle time comprises a plurality of first idle time periods t001 and a plurality of second idle time periods t002, wherein the first idle time periods t001 and the second idle time periods t002 alternate. The first switching transistors T1 are open during a plurality of first idle time periods t001, and the second switching transistors T2 are open during a plurality of second idle time periods t002.

[0039] During the display time, the first control signal terminal GAS1 is supplied with a low electrical potential as the global control signal gas1, with the first switching transistors T1 being closed. During the display time, the second control signal terminal GAS2 is supplied with a low electrical potential as the global control signal gas2, with the second switching transistors T2 being closed. During a plurality of first idle time periods t001, the first control signal terminal GAS1 is supplied with a high electrical potential as the global control signal gas1, with the first switching transistors T1 being open during a plurality of first idle time periods t001. During a plurality of second idle time periods t002, the first control signal terminal GAS1 is supplied with a low electrical potential as the global control signal gas1, with the first switching transistors T1 being closed during a plurality of second idle time periods t002.During a plurality of second idle time periods t002, the second control signal terminal GAS2 is supplied with a high electrical potential as the global control signal gas2, wherein the second switching transistors T2 are open during a plurality of second idle time periods t002. During a plurality of first idle time periods t001, the second control signal terminal GAS2 is supplied with a low electrical potential as the global control signal gas2, wherein the second switching transistors T2 are closed during a plurality of first idle time periods t001.

[0040] See Fig. 10: The idle time includes a first idle time period t001, a second idle time period t002, and a third idle time period t003, wherein the second idle time period t002 lies between the first idle time period t001 and the third idle time period t003. The first switching transistors T1 are open during the first idle time period t001 and the second idle time period t002, and the second switching transistors T2 are open during the second idle time period t002 and the third idle time period t003.

[0041] During the display time, the first control signal terminal GAS1 is supplied with a low electrical potential as the first control signal gas1, and during the display time, the second control signal terminal GAS2 is supplied with a low electrical potential as the second control signal gas2, with the first switching transistors T1 and T2 closed. During the first idle time period t001 and the second idle time period t002, the first control signal terminal GAS1 is supplied with a high electrical potential as the first control signal gas1, with the first switching transistors T1 open. During the third idle time period t003, the first control signal terminal GAS1 is supplied with a low electrical potential as the first control signal gas1, with the first switching transistors T1 closed.During the first idle time period t001, the second control signal terminal GAS2 is supplied with a low electrical potential as the second control signal gas2, with the second switching transistors T2 being closed. During the second idle time period t002 and the third idle time period t003, the second control signal terminal GAS2 is supplied with a high electrical potential as the first control signal gas2, with the second switching transistors T2 being open.

[0042] See Fig.11: In the exemplary embodiments, a display panel 400 is presented. The difference between the display panel 400 and the display panel 300 is that one of the first switching transistor T1 and the second switching transistor T2 is an N-channel transistor (N-type), while the other is a P-channel transistor (P-type). To realize the versatility of the circuit arrangement in the compensation module 40, for example, the first switching transistor T1 and the second switching transistor T2 can be electrically connected to the first control signal terminal GAS1 and the second control signal terminal GAS2, respectively, or alternatively to the same control signal terminal, which contributes to reducing the space requirement of the compensation module 40 and the number of signal connections.

[0043] The remaining components of the display panel 400 are identical to the remaining components of the display panel 300.

[0044] In the embodiments of the present application, a display device is presented which comprises a display panel and a frame, wherein the display panel is arranged within the frame.

[0045] A display panel and a display device are described in detail by the above-mentioned embodiments of the present application. The specific embodiments cited in this application are merely intended to help understand the basic concept of the present application and should not be considered as limiting the scope of the present application.

Claims

[1] A display panel (100, 200, 300, 400), wherein an image displayed on the display panel (100, 200, 300, 400) comprises a first display image and a second display image which are continuously displayed, the display panel (100, 200, 300, 400) comprising: several subpixels (10); a plurality of scan lines (20), wherein the plurality of scan lines (20) are arranged along a first direction, and the plurality of scan lines (20) are each electrically connected to the plurality of sub-pixels (10); a plurality of data lines (30), wherein the plurality of data lines (30) are arranged along a second direction, the first direction and the second direction intersecting each other, and the plurality of data lines (30) are each electrically connected to the plurality of sub-pixels (10), the polarity of the first data voltage in the display time of the first display image to the sub-pixels (10) being opposite to the polarity of the second data voltage in the display time of the second display image to the sub-pixels (10); a compensation module electrically connected to one end of the plurality of data lines (30) and configured to apply a first compensation voltage to the sub-pixels (10) during idle times of the first display image and a second compensation voltage to the sub-pixels (10) during idle times of the second display image, the polarity of the first compensation voltage corresponding to the polarity of the first data voltage and the polarity of the second compensation voltage corresponding to the polarity of the second data voltage; wherein the first compensation voltage is not zero, and the second compensation voltage is not zero, wherein the compensation module (40) includes a compensation voltage output, the compensation voltage output being electrically connected to one end of the plurality of data lines (30) and serving to output the first compensation voltage and the second compensation voltage; the absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage. [2] A display panel (100, 200, 300, 400), wherein an image displayed on the display panel (100, 200, 300, 400) comprises a first display image and a second display image which are continuously displayed, the display panel (100, 200, 300, 400) comprising: several subpixels (10); a plurality of scan lines (20), wherein the plurality of scan lines (20) are arranged along a first direction, and the plurality of scan lines (20) are each electrically connected to the plurality of sub-pixels (10); a plurality of data lines (30), wherein the plurality of data lines (30) are arranged along a second direction, the first direction and the second direction intersecting each other, and the plurality of data lines (30) are each electrically connected to the plurality of sub-pixels (10), the polarity of the first data voltage in the display time of the first display image to the sub-pixels (10) being opposite to the polarity of the second data voltage in the display time of the second display image to the sub-pixels (10); a compensation module electrically connected to one end of the plurality of data lines (30) and configured to apply a first compensation voltage to the sub-pixels (10) during idle times of the first display image and a second compensation voltage to the sub-pixels (10) during idle times of the second display image, the polarity of the first compensation voltage corresponding to the polarity of the first data voltage and the polarity of the second compensation voltage corresponding to the polarity of the second data voltage; where the first compensation voltage is not zero, and the second compensation voltage is not zero, wherein the plurality of data lines (30) comprise a plurality of first data lines (30, 31) and a plurality of second data lines (30), wherein the plurality of first data lines (30, 31) and the plurality of second data lines (30, 32) are arranged alternately along the second direction; the first data voltage comprises a first positive data voltage and a first negative data voltage; during the display time of the first display image, the data voltage input from the first data lines (30, 31) to the sub-pixels (10) is the first positive data voltage, and the data voltage input from the second data lines (30) to the sub-pixels (10) is the first negative data voltage; the second data voltage comprises a second positive data voltage and a second negative data voltage; during the display time of the second display image, the data voltage input from the first data lines (30, 31) to the sub-pixels (10) is the second negative data voltage, and the data voltage input from the second data lines (30) to the sub-pixels (10) is the second positive data voltage, wherein the compensation module (40) comprises a first output of the compensation voltage and a second output of the compensation voltage, wherein the first output of the compensation voltage is electrically connected to the first data lines (30, 31), wherein the first compensation voltage comprises a first positive compensation voltage and a first negative compensation voltage, wherein the magnitude of the first positive compensation voltage is less than or equal to the magnitude of the first positive data voltage, and the magnitude of the first negative compensation voltage is greater than or equal to the magnitude of the first negative data voltage; the second output of the compensation voltage is electrically connected to the second data lines (30), wherein the second compensation voltage comprises a second positive compensation voltage and a second negative compensation voltage, wherein the magnitude of the second positive compensation voltage is less than or equal to the magnitude of the second positive data voltage and the magnitude of the second negative compensation voltage is greater than or equal to the magnitude of the second negative data voltage, wherein the compensation module (40) comprises a plurality of first switching transistors (T1) and a plurality of second switching transistors (T2), wherein the gate electrodes of the plurality of first switching transistors (T1) and the plurality of second switching transistors (T2) are electrically connected to a global control signal terminal (GASO); either the source electrode or the drain electrode of the first switching transistors (T1) is electrically connected to the first output of the compensation voltage, and the other is electrically connected to one end of the first data lines (30, 31); either the source electrode or the drain electrode of the second switching transistors (T2) is electrically connected to the second output of the compensation voltage, and the other is electrically connected to one end of the second data lines (30), wherein the first switching transistors (T1) and the second switching transistors (T2) are closed during the display time and open during the idle time, wherein the idle time comprises a first idle time period and a second idle time period, the first idle time period being adjacent to the second idle time period; wherein the first switching transistors (T1) and the second switching transistors (T2) are open during the first idle time period and are closed during the second idle time period; or wherein the first switching transistors (T1) and the second switching transistors (T2) are open during the second idle time period and are closed during the first idle time period. [3] The display panel (100, 200, 300, 400) according to claim 2, wherein the compensation module (40) includes an output of the compensation voltage, the output of the compensation voltage being electrically connected to one end of the plurality of data lines (30) and serving to output the first compensation voltage and the second compensation voltage; the absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage. [4] The display panel (100, 200, 300, 400) according to claim 1 or 3, wherein the compensation module (40) includes a plurality of switching transistors (T1, T2), the gate electrodes of the plurality of switching transistors (T1, T2) being electrically connected to a global control signal terminal (GASO); one of the source electrode and the drain electrode of the switching transistors (T1, T2) being electrically connected to the output of the compensation voltage, and the other being electrically connected to one end of the data lines (30). [5] Display panel (100, 200, 300, 400) according to claim 4, wherein the switch-on time of the switching transistors (T1, T2) in the idle times is greater than or equal to the switch-off time. [6] The display panel (100, 200, 300, 400) according to claim 1, wherein the plurality of data lines (30, 31, 32) comprise a plurality of first data lines (30, 31) and a plurality of second data lines (30, 32), the plurality of first data lines (30, 31) and the plurality of second data lines (30, 32) being arranged alternately along the second direction; the first data voltage comprises a first positive data voltage and a first negative data voltage; during the display time of the first display image, the data voltage input from the first data lines (30, 31) to the sub-pixels (10) is the first positive data voltage, and the data voltage input from the second data lines (30, 32) to the sub-pixels (10) is the first negative data voltage; the second data voltage comprises a second positive data voltage and a second negative data voltage; during the display time of the second display image, the data voltage input from the first data lines (30, 31) to the sub-pixels (10) is the second negative data voltage, and the data voltage input from the second data lines (30, 32) to the sub-pixels (10) is the second positive data voltage. [7] The display panel (100, 200, 300, 400) of claim 6, wherein the compensation module (40) comprises a first output of the compensation voltage and a second output of the compensation voltage, the first output of the compensation voltage being electrically connected to the first data lines (30, 31), the first compensation voltage comprising a first positive compensation voltage and a first negative compensation voltage, the magnitude of the first positive compensation voltage being less than or equal to the magnitude of the first positive data voltage, and the magnitude of the first negative compensation voltage being greater than or equal to the magnitude of the first negative data voltage;the second output of the compensation voltage is electrically connected to the second data lines (30), wherein the second compensation voltage comprises a second positive compensation voltage and a second negative compensation voltage, wherein the magnitude of the second positive compensation voltage is less than or equal to the magnitude of the second positive data voltage and the magnitude of the second negative compensation voltage is greater than or equal to the magnitude of the second negative data voltage; [8] The display panel (100, 200, 300, 400) according to claim 7, wherein the compensation module (40) comprises a plurality of first switching transistors (T1) and a plurality of second switching transistors (T2), the gate electrodes of the plurality of first switching transistors (T1) and the plurality of second switching transistors (T2) being electrically connected to a global control signal terminal (GASO); either the source electrode or the drain electrode of the first switching transistors (T1) is electrically connected to the first output of the compensation voltage, and the other is electrically connected to one end of the first data lines (30, 31); either the source electrode or the drain electrode of the second switching transistors (T2) is electrically connected to the second output of the compensation voltage, and the other is electrically connected to one end of the second data lines (30, 32). [9] Display panel (100, 200, 300, 400) according to claim 8, wherein the first switching transistors (T1) and the second switching transistors (T2) are closed during the display time and open during the idle time. [10] The display panel (100, 200, 300, 400) of claim 9, wherein the idle time comprises a first idle time period and a second idle time period, the first idle time period being adjacent to the second idle time period; wherein the first switching transistors (T1) and the second switching transistors (T2) are open during the first idle time period and are closed during the second idle time period; or wherein the first switching transistors (T1) and the second switching transistors (T2) are open during the second idle time period and are closed during the first idle time period. [11] The display panel (100, 200, 300, 400) according to claim 2 or 7, wherein the compensation module (40) comprises a plurality of first switching transistors (T1) and a plurality of second switching transistors (T2), wherein the gate electrodes of the plurality of first switching transistors (T1) are electrically connected to a first control signal terminal (GAS1), and the gate electrodes of the plurality of second switching transistors (T2) are electrically connected to the second control signal terminal (GAS2); either the source electrode or the drain electrode of the first switching transistors (T1) is electrically connected to the first output of the compensation voltage, and the other is electrically connected to one end of the first data lines (30, 31); either the source electrode or the drain electrode of the second switching transistors (T2) is electrically connected to the second output of the compensation voltage, and the other is electrically connected to one end of the second data lines (30, 32). [12] The display panel (100, 200, 300, 400) according to claim 11, wherein the idle time comprises a first idle time period, a second idle time period, and a third idle time period, the second idle time period being between the first idle time period and the third idle time period; wherein the first switching transistors (T1) are open during the first idle time period and the second idle time period, and the first switching transistors (T1) are closed during the third idle time period, and the second switching transistors (T2) are open during the second idle time period and the third idle time period, and the second switching transistors (T2) are closed during the first idle time period. [13] The display panel (100, 200, 300, 400) of claim 11, wherein the idle time comprises a plurality of first idle time periods and a plurality of second idle time periods, the first idle time period alternating with the second idle time period; wherein the first switching transistors (T1) are open during the plurality of first idle time periods, and the first switching transistors (T1) are closed during the plurality of second idle time periods, and the second switching transistors (T2) are open during the plurality of second idle time periods, and the second switching transistors are closed during the plurality of first idle time periods. [14] Display panel (100, 200, 300, 400) according to claim 2 or 10, wherein the turn-on time of the first switching transistors (T1) and the second switching transistors (T2) in the idle times is longer than the turn-off time. [15] A display device, the display device comprising a frame and a display panel (100, 200, 300, 400) according to any one of claims 1 to 14.

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