ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE ELECTRONIC DEVICE

Abstract

An electronic device comprises a first electronic component having a nickel-based electrode and a second electronic component connected to the nickel-based electrode via a tin-based solder. A (Cu, Ni, Pd)6Sn5 compound layer exists at a solder interface between the nickel-based electrode and the tin-based solder, and the Pd content existing as a (Pd, Ni)Sn4 compound in an initial phase of the tin-based solder after connection is less than or zero than the Pd content existing in the (Cu, Ni, Pd)6Sn5 compound layer.

Description

Technical area

[0001] The present invention relates to an electronic device and a method for manufacturing the electronic device. Technical background

[0002] Because the use of lead wires included in electronic control devices mounted on motor vehicles is regulated by the RoHS and ELV directives, lead-free solder composed mainly of Sn-3Ag-0.5Cu (wt%) has been preferred so far. A power module used in an inverter must have high power density to achieve miniaturization and weight reduction, and for example, the following two points are required. First, the upper and lower surfaces of a power semiconductor must be soldered to allow heat dissipation from the upper and lower surfaces of the power module. Second, the guaranteed temperature of a power semiconductor solder joint must be increased to allow high current flow.

[0003] A Ni-based electrode for solder connection is used as an electrode of a semiconductor element, and the exposed layer of the electrode is metallized with Au or Ag to ensure easy wetting by the solder. However, depending on the heating or storage environment in a chip manufacturing process, Ni may diffuse on the surface of a thin Au or Ag metallization with many defects, generating Ni oxide on the outermost surface of the exposed layer, thereby impairing the solder connection ability. Therefore, to prevent Ni oxide from forming on the exposed layer, a Pd layer is provided on the Ni-based electrode, and Au or Ag metallization is deposited on the Pd layer. PTL 1 discloses an alloy for lead-free solder balls consisting of 3 to 6% Ag, 1 to 4% Cu, 0.01 to 2% Co, and the remaining Sn, by atomic %. Citation listPatent literature

[0004] PTL 1: Japanese Patent No. 3724486 Summary of the inventionTechnical problem

[0005] In the invention described in PTL 1, there is room for investigating countermeasures against voids. Solution to the problem

[0006] An electronic device according to a first aspect of the present invention comprises: a first electronic component having a Ni-based electrode; and a second electronic component connected to the Ni-based electrode via an Sn-based solder. A (Cu, Ni, Pd)6Sn5 compound layer exists at a solder joint interface between the Ni-based electrode and the Sn-based solder, and the content of Pd existing as a (Pd, Ni)Sn4 compound in an initial phase of the Sn-based solder after joining is smaller than the content of Pd existing in the (Cu, Ni, Pd)6Sn5 compound layer, or is zero.

[0007] A method for manufacturing an electronic device according to a second aspect of the present invention is a method for manufacturing an electronic device including a first electronic component having a Ni-based electrode and a second electronic component connected to the Ni-based electrode via an Sn-based solder. The method includes: a disposing step of, in the first electronic component in which a Pd layer is formed on an outer periphery of the Ni-based electrode, disposing the Sn-based solder containing Cu beyond the eutectic composition on a surface of the Pd layer. In the electronic device, a (Cu, Ni, Pd)6Sn5 compound layer is formed at a solder joint interface between the Ni-based electrode and the Sn-based solder. Advantageous effects of the invention

[0008] According to the present invention, the formation of voids can be suppressed. Brief description of the drawings

[0009] They show: Fig. 1 a diagram showing an example of blowholes, Fig. 2 a diagram showing the behavior of the solder during cooling, Fig. 3 is a diagram illustrating a first configuration of an electronic component, Fig. 4 is a diagram showing a configuration using a general plumb line, Fig. 5 is a diagram illustrating a second configuration of the electronic component, Fig. 6 is a diagram illustrating a method of manufacturing a semiconductor device, Fig. 7 a diagram showing examples 1 to 6, Fig. 8 is a diagram showing comparative examples 1 and 2, Fig. 9 is a diagram illustrating a method of manufacturing the semiconductor device, Fig. 10 is a diagram showing examples 7 to 9, and Fig. 11 is a diagram showing comparative examples 3 and 4. Description of embodiments-First embodiment-

[0010] Hereinafter, a semiconductor device as an electronic component according to a first embodiment will be described with reference to the Fig. 1 to 11. When using a chip in which a palladium (Pd) layer is provided on a nickel (Ni)-based electrode, there is a known problem that voids are easily generated in a solder joint compared to a case in which a chip with a Pd layer is used.

[0011] Fig. 1 is a diagram showing an example of voids. In Fig. 1, a solder joint 3 is formed between a semiconductor element 1 and an emitter-side lead 2 of a power module. Cavities 101 shown in black are formed in a region of the solder joint 3 located near the emitter-side lead 2. It should be noted that in the Fig. 1, more heat was dissipated from the semiconductor element 1 side than from the emitter-side lead 2 side. When voids are formed, a heat dissipation path for dissipating the heat generated by excitation of the semiconductor element is reduced, and reliability is difficult to ensure. Therefore, if voids are formed, a defective product is determined during quality control after assembly. It is believed that the voids are generated because the liquidus temperature of lead-free Sn(tin)-based solder rises when Pd formed at the Ni-based electrode of the semiconductor element diffuses into the molten lead-free Sn(tin)-based solder during soldering.

[0012] Examples of the Ni-based electrode according to the present embodiment include only nickel, nickel and phosphorus, nickel and vanadium, and the like. In this case, the ratio of nickel to phosphorus is, for example, about 100:1 to 15. In this case, the ratio of nickel to vanadium is, for example, about 100:1 to 15.

[0013] Fig. Figure 2 is a graph showing the behavior of the solder during cooling. The left side of Fig. 2 shows a case where the temperature difference between the beginning and the end of the solidification of the solder is small, and the right side of Fig. Figure 2 shows a case where the temperature difference between the beginning and the end of the solder solidification is large. Fig. 2, time runs from the top to the bottom of the drawing. In addition, the Fig. 2, a large amount of heat is dissipated from the side of the semiconductor element 1. If the temperature difference between the beginning and the end of the solidification of the solder is small, as on the left side of Fig. 2, the entire solder joint 3 undergoes a total contraction under the influence of the volume contraction accompanying the solidification. On the other hand, if the temperature difference between the beginning and end of the solder solidification is large, the solder will be compressed as shown on the right side of Fig. 2, gradually solidifies from the cooled side, and the final solidification portion undergoes volume contraction during solidification, so that voids 101 are easily formed. Note that the voids 101 are formed on the semiconductor element 1 side if more heat is dissipated from the emitter-side lead 2 side than from the semiconductor element 1 side.

[0014] Fig. 3 is a diagram showing a first configuration of a semiconductor device 100, which is an electronic component according to the present embodiment. The left side in the drawing shows a state before bonding, and the right side in the drawing shows a state after bonding. A Ni-based electrode 8, a Pd layer 7, and a metal film 6 are provided on the surface of the semiconductor element 1. The metal film 6 is plated with Au (gold) or Ag (silver). A Ni plating 5 is provided on the surface of the emitter-side lead 2. According to the present embodiment, a copper-added solder 24 is interposed between the metal film 6 and the Ni plating 5 and bonded thereto. The copper-added solder 24 is an Sn-based solder to which Cu (copper) has been added beyond the eutectic composition.In particular, the weight fraction of Cu in the copper-added solder 24 is at least 0.9%, preferably at least 3% and less than 6%, and the weight fraction of Sn is at least 80%.

[0015] The copper-added solder 24, which contains Cu in addition to the eutectic composition, contains a large proportion of a Cu6Sn5 compound, indicated by reference numeral 25. By joining using the Cu6Sn5 compound, Pd is incorporated into the Cu6Sn5 compound supplied by the solder, and a (Cu, Ni, Pd)6Sn5 compound can be formed at a solder joint interface 26. The solder joint has the solder joint interface 26 located above and below in the drawing and a central solder layer 27.

[0016] At this time, the Cu content in the solder and the thickness L of the solder joint are controlled according to the Pd thickness of the semiconductor element 1, so that Pd can be substantially incorporated into the (Cu, Ni, Pd)6Sn5 compound formed at the solder joint interface 26. Here, the thickness of the Pd layer 7 is represented by a symbol d, the thickness of the Pd layer is represented by the symbol d, the thickness of the upper solder joint interface 26 is represented by a symbol y1, the thickness of the lower solder joint interface 26 is represented by a symbol y2, the density of Pd is represented by a symbol D1, and the density D2 of (Cu, Ni, Pd)6Sn5 is represented by a symbol D2. Since the content of Pd in ​​(Cu, Ni, Pd)6Sn5 is 3.6 wt%, the following expression 1 can be derived in terms of the weight of Pd. The left side of Expression 1 describes Pd before joining, and the right side describes Pd after joining.Note that “×” in Expression 1 is an operation symbol meaning a product. d×D1=(y1+y2)×D2×0.036

[0017] Here the Pd density D1 is 12.03 g / cm 3 and the (Cu, Ni, Pd)6Sn5 density D2 is 8.33 g / cm 3 , so that the following expression 2 is obtained by rearranging expression 1: y=y1+y2=40.1×d

[0018] That is, Expression 2 shows that the sum of the thickness of the upper solder joint interface 26 and the thickness of the lower solder joint interface 26 is approximately 40 times the thickness of the Pd layer 7 before joining. Note that if the desired solder thickness L is fixed, the required Cu content of the solder can be calculated based on the thickness y of the solder joint interface 26.

[0019] If all of the Pd can be incorporated into the solder joint interface 26, hardly any of the (Pd, Ni)Sn4 compound exists in the central solder layer 27, and an increase in the liquidus temperature can be suppressed, so that voids can be suppressed. A high void suppression effect is obtained when the content of Pd existing as the (Pd, Ni)Sn4 compound in the initial phase of the Sn-based solder after joining is smaller than the content of Pd existing in the (Cu, Ni, Pd)6Sn5 compound layer as described above, or is zero. Note that the Ni content in the (Cu, Ni, Pd)6Sn5 compound layer is at most 5 wt%.

[0020] Fig. Figure 4 is a diagram showing a configuration using a general solder for comparison. The left side of the drawing shows a state before joining, and the right side of the drawing shows a state after joining. The left side of Fig. 4 differs from the left side of Fig. 3 by using the general solder 4 instead of the copper-added solder 24 in Fig. 3 is used. The Ni-based electrode 8, the Pd layer 7 and the metal film 6 are located on the surface of the semiconductor element 1, and the Ni coating 5 is located on the surface of the emitter-side lead 2, which is Fig. 3. For example, general solder 4 is a lead-free Sn-based solder such as Sn-3Ag-0.5Cu.

[0021] In this case, the Pd contained in the Pd layer 7 is divided into a portion that is incorporated into the (Ni, Cu, Pd)3Sn4 compound formed at the solder joint interface by reacting with the solder, and a portion that exists in the form of a floating island as a (Pd, Ni)Sn4 compound within the solder joint. If the solder joint is considered to be divided into an intermetallic compound at the solder joint interface and the solder portion separate from it, the intermetallic compound formed at the solder joint interface is not related to the liquidus temperature of the solder, but the liquidus temperature of the solder portion separate from it affects the probability of void formation. The more of the (Pd, Ni)Sn4 compound 23 formed, the higher the liquidus temperature of the solder and the more likely void formation is.

[0022] Fig. Figure 5 is a diagram showing a second configuration of the semiconductor device 100 according to the present embodiment. In the semiconductor element 1 of the power module type, both surfaces on the emitter side and the collector side can be soldered, as shown in Fig. 5. In particular, the Fig. 5 is sandwiched between a collector-side lead 12 on the lower side in the drawing and an emitter-side lead 2 on the upper side in the drawing. In this case, because the semiconductor element 1 is cooled by the collector-side lead 12 on the lower side in the drawing, the collector-side solder joint designated by reference numeral 13, which is located on the lower side of the semiconductor element 1, cools faster, and the emitter-side solder joint designated by reference numeral 3 cools slower. Because voids are more likely to occur when the cooling rate is lower, voids are more likely to form at the emitter-side solder joint.Therefore, at least at the emitter-side solder joint, the formation of voids can be suppressed by bonding the semiconductor element in which Pd is present on the Ni-based electrode to the Sn-based solder to which Cu has been added beyond the eutectic composition. (Examples 1 to 6)

[0023] Examples 1 to 6 are presented with reference to the Fig. 6 and Fig. 7. A process for producing a Fig. The semiconductor device 100A shown in Figure 6 proceeds as follows. First, collector-side solder 24-2 is supplied to a solder application position of a collector-side Cu lead 32 with a roughened Ni coating. The semiconductor element 1, in which a Pd layer with a thickness of 600 nm is formed on the Ni-based electrodes on both surfaces, is deposited thereon. Further, the emitter-side solder 24-1 is deposited on the electrode on the upper surface of the mounted semiconductor element 1, and an emitter-side lead 31 made of copper with a roughened Ni coating is laminated thereon and bonded thereto. Accordingly, the Pd supplied from the semiconductor element can be incorporated into the (Cu, Ni, Pd)6Sn5 compound at the solder joint interface in a state where there is almost no (Pd, Ni)Sn4 compound within the emitter-side solder joint where voids are likely to form.Subsequently, sealing with resin 33 is carried out by pressure molding and the semiconductor device 100A is completed.

[0024] The compositions of the emitter-side solder 24-1 and the collector-side solder 24-2 for the respective examples are shown in the columns “substrate top-side solder” and “substrate bottom-side solder” in Fig. 10. For example, in Example 1, both the collector-side solder 24-2 and the emitter-side solder 24-1 contain Sn as the main component and at least 3 wt% and less than 6 wt% Cu. In Example 2, both the collector-side solder 24-2 and the emitter-side solder 24-1 contain Sn as the main component and 4 wt% Ag and at least 3 wt% and less than 6 wt% Cu.

[0025] For each of the examples, 100 semiconductor devices 100A were manufactured, and the presence of voids 101 was evaluated. The evaluation of voids 101 resulted in a pass in the case where no voids 101 exceeding 5% of the solder joint area were observed in any of the 100 semiconductor devices, and a fail in the case where voids 101 exceeding 5% were observed in at least one semiconductor device. All of Examples 1 to 6 were determined to be passed. (Comparison examples 1 and 2)

[0026] Comparative Examples 1 and 2 are compared with reference to the Fig. 6 and Fig. 8. Comparative Examples 1 and 2 differ from Examples 1 to 6 only in the composition of the emitter-side solder 24-1 and the collector-side solder 24-2, and the semiconductor device was manufactured and evaluated in the same manner. The evaluation result was that all Comparative Examples 1 and 2 were found to be "failed." (Examples 7 to 9)

[0027] Examples 7 to 9 are presented with reference to the Fig. 9 and Fig. 10. A process for producing a Fig. The semiconductor device 100B shown in Figure 9 proceeds as follows. First, a layer of the under-substrate solder 24-4 is deposited on a heat dissipation base 45, and a ceramic insulating substrate 34 is laminated thereon. The emitter-side lead 2 is disposed on top of the ceramic insulating substrate 43 in the drawing. Next, the over-substrate solder 24-3 is deposited on the emitter-side lead 2, the semiconductor element 1 is installed, and then heated to perform bonding. Further, after the solder joint is formed, an aluminum wire 42 and a terminal 41 are connected, and then a package 47 is attached. Finally, the interior of the package 47 is sealed with gel 46 to complete the semiconductor device 100B.

[0028] The compositions of the substrate top solder 24-3 and the substrate bottom solder 24-4 for the respective examples are shown in the columns “substrate top solder” and “substrate bottom solder” in Fig. 10. For each of the examples, 100 semiconductor devices 100B were manufactured, and the presence of voids 101 was assessed. The assessment of voids 101 resulted in a pass in a case where voids 101 exceeding 5% of the solder joint area were not observed in any of the 100 semiconductor devices, and a fail in a case where voids 101 exceeding 5% were observed in at least one semiconductor device. "Pass" was determined in all examples 7 to 9, as shown in Fig. 10 is shown. (Comparison examples 3 and 4)

[0029] Comparative Examples 3 and 4 are compared with reference to the Fig. 9 and Fig. 11. These examples differ from Examples 7 to 9 only in the compositions of the substrate-top solder 24-3 and the substrate-bottom solder 24-4. In Comparative Examples 3 and 4, a semiconductor device was manufactured and evaluated in the same manner. The compositions of the substrate-top solder 24-3 and the substrate-bottom solder 24-4 from Comparative Examples 3 and 4 are shown in the columns "Substrate-top solder" and "Substrate-bottom solder" in Fig. 11. The result of the assessment was that all comparative examples 1 and 2 were found to be "failed".

[0030] According to the first embodiment described above, the following operational effects can be obtained. (1) The semiconductor device 100 as an electronic device includes the semiconductor element 1 having a Ni-based electrode, and the emitter-side lead 2 connected to the Ni-based electrode by Sn-based solder. A (Cu, Ni, Pd)6Sn5 compound layer exists at the solder joint interface 26 between the Ni-based electrode and the Sn-based solder, and the content of Pd existing as a (Pd, Ni)Sn4 compound in the initial phase of the Sn-based solder after joining is smaller than the content of Pd existing in the (Cu, Ni, Pd)6Sn5 compound layer, or zero. Therefore, the formation of the voids 101 is suppressed.

[0031] (2) The semiconductor element 1 has a plurality of Ni-based electrodes, and the (Cu, Ni, Pd)6Sn5 compound layer exists at least at a solder joint interface between the Ni-based electrode, at which heat dissipation takes the longest among the plurality of Ni-based electrodes, and the Sn-based solder. For example, in the Fig. 6, heat is dissipated from the collector-side lead 32 side on the underside of the drawing, it is less likely that voids 101 will form in the collector-side solder 24-2, which cools earlier, so that the need for countermeasures is low. On the side that requires time for cooling, ie, on the emitter side in the example of Fig. 6, however, there is a possibility that voids 101 may form if no countermeasures are taken. Therefore, the formation of voids 101 is suppressed by using the solder having the above-described composition.

[0032] (3) In the semiconductor device 100, the (Cu, Ni, Pd)6Sn5 compound layer has a Ni content of at most 5 wt%.

[0033] (4) A method for manufacturing the semiconductor device 100 comprising the semiconductor element 1 having a Ni-based electrode and the emitter-side lead 2 connected to the Ni-based electrode by Sn-based solder includes a disposition step of disposing, in the semiconductor element 1 in which a Pd layer is formed on an outer periphery of the Ni-based electrode, the copper-added solder 24 containing Cu beyond the eutectic composition on a surface of the Pd layer. In the semiconductor device 100, a (Cu, Ni, Pd)6Sn5 compound layer is formed at a solder joint interface between the Ni-based electrode and the Sn-based solder.

[0034] (5) The semiconductor element 1 has a plurality of Ni-based electrodes. In the assembling step, the copper-added solder 24 containing Cu beyond the eutectic composition is plated at least between the Ni-based electrode on the top side in Fig. 6, at which time is required for heat dissipation, and the emitter-side supply line 31.

[0035] (6) The composition of the copper-added solder 24 containing Cu beyond the eutectic composition contains 3 to 6 wt% Cu.

[0036] (7) As explained with reference to Fig. 3, a (Cu, Ni, Pd)6Sn5 compound layer with a thickness L that is 40 times the thickness d of the Pd layer on the Ni electrode of the semiconductor element 1 is formed at the solder joint interface. (First modification)

[0037] In the first embodiment described above, the composition of the solder for suppressing the formation of voids 101 in the solder joint of the power module, which is the semiconductor element, was described. However, since the formation of voids 101 can become a problem in any electronic component situation, the application scope of the present invention is not limited to power modules but can be applied to various semiconductor elements. Furthermore, the present invention is not limited to semiconductors and can be applied to electronic devices having various electrodes.

[0038] The embodiment and modification described above can be combined with each other. Although various embodiments and modifications have been described above, the present invention is not limited to these contents. Other embodiments considered to be within the scope of the technical spirit of the present invention are also included within the scope of the present invention. List of reference symbols 1 semiconductor element 7 Pd layer 8 Ni-based electrode 12 collector-side supply line 24 copper-plated solder 24-1 emitter-side solder 24-2 collector-side solder 24-3 substrate top solder 24-4 substrate underside solder 31 emitter-side supply line 32 collector-side supply line 100, 100A, 100B semiconductor device 101 blowholes QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 3724486

[0004]

Claims

[1] Electronic device comprising: a first electronic component having a Ni-based electrode, and a second electronic component connected to the Ni-based electrode via a Sn-based solder, wherein a (Cu, Ni, Pd)6Sn5 compound layer exists at a solder joint interface between the Ni-based electrode and the Sn-based solder, and the content of Pd existing as a (Pd, Ni)Sn4 compound in an initial phase of the Sn-based solder after joining is smaller than the content of Pd existing in the (Cu, Ni, Pd)6Sn5 compound layer or zero. [2] The electronic device according to claim 1, wherein the first electronic component is a semiconductor element. [3] Electronic device according to claim 1, wherein the first electronic component is a semiconductor element having a plurality of Ni-based electrodes and the (Cu, Ni, Pd)6Sn5 compound layer exists at least at a solder joint interface between the Ni-based electrode, at which heat dissipation takes the longest among the plurality of Ni-based electrodes, and the Sn-based solder. [4] The electronic device according to claim 1, wherein the (Cu, Ni, Pd)6Sn5 compound layer has a Ni content of at most 5 wt%. [5] A method of manufacturing an electronic device comprising a first electronic component having a Ni-based electrode and a second electronic component connected to the Ni-based electrode via a Sn-based solder, the method comprising: an arranging step of arranging, in the first electronic component in which a Pd layer is formed on an outer edge of the Ni-based electrode, the Sn-based solder containing Cu beyond the eutectic composition is arranged on a surface of the Pd layer, wherein in the electronic device, a (Cu, Ni, Pd)6Sn5 compound layer is formed at a solder joint interface between the Ni-based electrode and the Sn-based solder. [6] A method of manufacturing an electronic device according to claim 5, wherein the first electronic component is a semiconductor element. [7] A method of manufacturing an electronic device according to claim 5, wherein the first electronic component is a semiconductor element having a plurality of Ni-based electrodes and in the arranging step, the Sn-based solder containing Cu beyond the eutectic composition is arranged at least between the Ni-based electrode which requires the longest time for heat dissipation among the plurality of Ni-based electrodes and the second electronic component. [8] A method for manufacturing an electronic device according to claim 5, wherein the composition of the Sn-based solder containing Cu in excess of the eutectic composition contains 3 to 6 wt% of Cu. [9] A method of manufacturing an electronic device according to claim 5, wherein a (Cu, Ni, Pd)6Sn5 compound layer having a thickness 40 times as large as the thickness of the Pd layer on the Ni electrode of the first electronic component is formed at the solder joint interface.

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