REDUCTION OF THE LIMIT CYCLE CAUSED BY DCO FREQUENCY OVERLAP IN HYBRID AND DIGITAL PLLS

Abstract

One method includes: observing that a digitally controlled oscillator (DCO) frequency lies at a boundary of a DCO frequency overlap region; and bypassing at least one section of the DCO frequency overlap region.

Description

PRIORITY CLAIM

[0001] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 371,105, filed August 11, 2022, for MITIGATE DCO OVERLAP INDUCED LIMIT CYCLE IN HYBRID AND DIGITAL PLLS, the contents and disclosure of which are incorporated herein by this reference in their entirety. AREA

[0002] One or more examples generally relate to clock tracking circuits for tracking an output clock against a reference clock. One or more examples relate to reducing the undesirable effects of frequency redundancy in a digitally controlled oscillator of a clock tracking circuit. BACKGROUND

[0003] Clock tracking circuits, such as phase-locked loops and delay-locked loops, are circuits used to track clocks and other oscillating signals. The output signal of a clock tracking circuit is locked to the phase and frequency of a reference signal. Clock tracking circuits are used in numerous operating contexts, including when two signals with known relationships are used to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To easily identify the discussion of a specified element or particular action, the main numeral(s) in a reference number refer to the figure number in which that element is first introduced. Fig. Figure 1A is a graph showing a curve representing a change in a DCO control code over time and another curve representing a phase error signal generated by a PLL exhibiting interference. Fig. Figure 1B is a graph showing a curve representing a change in a DCO control code over time and another curve representing a phase error signal generated by a PLL that exhibits less or no interference (compared to Fig. 1A), according to one or more examples. Fig. 2 is a block diagram illustrating an integral path section for bypassing DCO frequency overlap regions in a PLL according to one or more examples. Fig. 3 is a block diagram illustrating an apparatus for generating an adjustment signal according to one or more examples. Fig. 4 is a block diagram illustrating an apparatus for bypassing DCO control codes corresponding to a DCO frequency overlap region, according to one or more examples. Fig. 5 is a block diagram illustrating an apparatus for bypassing DCO control codes corresponding to a DCO frequency overlap region, according to one or more examples. Fig. 6 is a flowchart illustrating a process for bypassing DCO frequency overlap regions in a PLL, according to one or more examples. Fig. 7 is a flowchart illustrating a process for observing that a DCO frequency is at a boundary of a DCO frequency overlap region, according to one or more examples. Fig. 8 is a flowchart illustrating a process for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples. Fig. 9 is a flowchart illustrating a process for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples. Fig. 10 is a flowchart illustrating a process for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples. Fig. 11 is a block diagram illustrating a device for tracking a clock (may also be referred to herein as a “clock tracking circuit”), according to one or more examples. Fig. 12 is a block diagram of circuitry that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration specific examples of examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and procedural changes may be made without departing from the scope of the disclosure.

[0006] The illustrations presented herein are not intended to be actual views of any particular method or system, device, or structure, but are merely idealized representations used to describe the examples of the present disclosure. The drawings presented herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to practice the disclosed examples. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of any example of this disclosure to the specified components, steps, features, functions, or the like.

[0008] It will be readily appreciated that the components of the examples generally described herein and illustrated in the drawings may be arranged and configured in a variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between various blocks are exemplary of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art would understand that information and signals may be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein.A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer is configured to execute computational instructions (e.g., software code) related to examples of the present disclosure.

[0012] The examples may be described with respect to a process represented as a flowchart, a flowchart, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or dispatched as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0013] Any reference herein to an element using a label such as "first," "second," etc., does not limit the quantity or order of those elements unless such a limitation is expressly stated. Rather, these labels may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element in any way. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to an extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the specified parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90% satisfied, at least 95% satisfied, or even at least 99% satisfied.

[0015] As used herein, relational terms such as "over," "under," "upon," "underlying," "above," "beneath" are used without limitation for clarity and convenience in understanding the disclosure and the accompanying drawings and are not associated with or dependent upon any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0016] In this specification, the term "coupled" and derivatives thereof may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. Conversely, when an element is described as "directly coupled" to another element, no intervening elements or layers are present.

[0017] The term "connected" may be used interchangeably with the term "coupled" in this specification and has the same meaning unless expressly stated otherwise or the context would indicate otherwise to a person of ordinary skill in the art.

[0018] A clock signal, or simply a "clock," is a signal that oscillates between a high and a low state in a reliably predictable manner. A circuit can operate in response to the edges of a clock to coordinate its actions.

[0019] A phase-locked loop (PLL) produces an output signal exhibiting a phase or frequency that has a predetermined relationship to a phase or frequency of a reference signal. The process of establishing and maintaining such a predetermined relationship between the phase or frequency of an output signal and a reference signal is referred to herein as "tracking." The predetermined relationship may be such that the frequency of the output signal is the same as, or a multiple of, a frequency of the reference signal. As a non-limiting example, the frequency of the output signal may be 1 / 200, 1 / 10, 10, or 200 times the frequency of the reference signal. When a PLL reliably tracks an output signal to a reference signal, it is said to be "locked" or in a "locked state."When the phase or frequency of a reference signal changes in the locked state, a PLL adjusts the phase or frequency of the output signal accordingly to maintain the predetermined relationship.

[0020] A typical PLL includes an electronic oscillator that the PLL controls to produce an output signal that tracks a reference signal. An electronic oscillator may include one or more banks of control elements (e.g., capacitors, inductors, delay circuits, without limitation) that are voltage-controlled, current-controlled, digitally controlled, or a combination or subcombination thereof. By enabling and disabling the respective control elements, the capacitance, inductance, or delay of the electronic oscillator is varied in a predictable manner, thereby changing the output frequency of the electronic oscillator in a predictable manner. As a non-limiting example, an increase in the capacitance, inductance, or delay of an electronic oscillator causes its output frequency to decrease.A decrease in the capacitance, inductance or delay of an electronic oscillator causes its output frequency to increase.

[0021] An electronic oscillator may include multiple inputs for controlling (enabling / disabling) various sets of control elements and, accordingly, regulating the phase and frequency of an output signal. Non-limiting examples of electronic oscillators include a voltage-controlled oscillator (VCO), which generates an output signal exhibiting a phase or frequency controlled by the voltage of a control signal; a current-controlled oscillator (CCO), which generates an output signal exhibiting a phase or frequency controlled by the current of a control signal; a digitally controlled oscillator (DCO), which generates an output signal exhibiting a phase or frequency controlled at least in part by the value of a control code; and combinations / subcombinations thereof.

[0022] A PLL may include one or more control paths for controlling the electronic oscillator via one or more control inputs of the electronic oscillator. Non-limiting examples of control paths include a proportional control path for temporarily correcting phase differences between a feedback signal and a reference signal, and an integral control path for driving an average frequency of the electronic oscillator toward a target frequency. Such control paths may include analog circuitry, digital circuitry, or combinations thereof. A PLL that includes exclusively analog control paths is called an "analog PLL." A PLL that includes exclusively digital control paths is called a "digital PLL." A PLL that includes a combination of analog and digital control paths is sometimes referred to as a "hybrid PLL" or "mixed-mode PLL."

[0023] Digital and hybrid PLLs use digital control codes to control the PLL output when a DCO is used. A control code, via a digital control input (or simply "digital input") of the DCO, sets the number of control elements in the DCO, so adjusting the value of a control code sets the number of control elements in the DCO and thus the frequency of the DCO ("DCO frequency"). A typical convention is to configure the PLL so that an increase in the value of a control code increases the DCO frequency (i.e., by increasing the value of a control code, the number of adjusted control elements decreases, thereby increasing the DCO frequency) and a decrease in the value of a control code decreases the DCO frequency (i.e., by increasing the number of adjusted control elements, thereby decreasing the DCO frequency). Other conventions may be employed without exceeding the scope of this disclosure.

[0024] In a digital PLL, specific values ​​of control codes are associated with specific frequency subranges of the DCO. Generally, a DCO should provide a continuous frequency within a predefined frequency range. Discontinuities (also called "gaps") in a frequency range of the DCO cause jitter, which is generally undesirable. Discontinuities are specific frequencies or subranges within the predefined frequency range of the DCO that are skipped when the value of the control code monotonically increases or decreases. Gaps in the frequency domain can occur, for example, due to process voltage temperature (PVT) fluctuations and mismatches during the manufacturing of a DCO or a PLL in general.

[0025] Frequency redundancy is sometimes implemented in a DCO to ensure frequency domain continuity. The DCO is intentionally configured to exhibit overlapping frequency subranges (each such overlap is referred to herein as a "DCO frequency overlap region") for ranges of control code values ​​to ensure continuous frequency coverage (i.e., no frequency gaps) even when subject to PVT fluctuations. Frequency overlap involves overlapping portions of frequency subranges for DCO codes.

[0026] During operation, when the PLL ramps the control code from one set of values ​​to another set of values ​​representing a first frequency subrange to a second frequency subrange, the DCO frequency ramps back and sweeps through the portion of the DCO frequency range for the set of values ​​corresponding to the DCO frequency overlap region. Exceeding a DCO frequency overlap region can disrupt a PLL's phase error, and the disruption can be exhibited as a limit cycle in the control code. In the context of a PLL, a limit cycle is a recurring pattern or oscillation in the behavior of the PLL control code or state variables that occurs when the PLL is unable to achieve a steady state and instead adopts periodic or repetitive behavior. Limit cycles degrade jitter performance.Therefore, frequency redundancy can compensate for degraded jitter performance.

[0027] When a DCO frequency overlap region is exceeded, the DCO frequency decreases and then increases or decreases again with the monotonically increasing or decreasing control code. The DCO frequency backtracks a portion of a previous DCO frequency sub-range, and this portion represents the DCO frequency overlap region between the previous DCO frequency sub-range and the current DCO frequency sub-range. Reducing the amount of DCO frequency overlap experienced by the PLL reduces the limit cycles due to DCO frequency backtracking. The amount of the DCO frequency overlap region is reduced by increasing or decreasing the value of the control code by an adjustment amount, thereby skipping some or all of the control code values ​​associated with the DCO frequency overlap region while still avoiding gaps in the DCO frequency range.

[0028] One or more examples generally relate to reducing limit cycles due to the DCO frequency overlap region in a clock tracking circuit, and to methods and apparatus including the same.

[0029] One or more examples generally relate to a method including detecting that a limit of DCO overlap has been reached, determining a direction of an integral control path, determining an amount of DCO overlap at the detected limit, and adjusting an integral control signal, at least temporarily, based at least in part on the determined amount of DCO overlap at the detected limit.

[0030] Fig. Figure 1A is a graph illustrating a curve representing a change in a DCO control code over time and another curve representing a phase error signal generated by a PLL having an output signal controlled at least in part by the DCO control codes. The phase error signal generated by the PLL exhibits a disturbance, as explained below.

[0031] Curve 102 represents a relationship between the values ​​of the DCO control codes and time (or the DCO control codes over a period of time). The y-axis is the values ​​of the DCO control codes, increasing from the bottom of the axis to the top of the axis. The x-axis is time, increasing from left to right.

[0032] Curve 104 represents a phase error signal generated by a PLL with an output signal controlled at least in part by the DCO control codes represented in curve 102. The y-axis is the magnitude of the delay (where one of the positive or negative signs represents a leading delay and the other of the positive or negative signs represents a lagging delay). The x-axis is time, increasing from left to right.

[0033] At approximately time T 0 the curve 102 shows a change from a first value to a second value, and then, after time T 0 , the curve 102 rises gradually over a period of time T 0 are 1from the second value to a third value and then beyond. The third value lies between the first value and the second value. The range of DCO control codes between the second value and the third value corresponds to a DCO frequency overlap region for a DCO controlled by these DCO control codes.

[0034] Before time T 0 the curve 104 is generally horizontal, representing a generally stable phase error. At approximately time T 0 the curve 104 shows a disturbance 106: a shift to a higher phase error (ie a larger delay), and then the curve 104 lets the time period from time T 0 are 1 to the same phase error before time T 0 The disturbance 106 corresponds to a DCO frequency overlap region corresponding to the range of values ​​between the second value and the third value.

[0035] Fig. 1B is a graph illustrating a curve representing a change in a DCO control code over time and another curve representing a phase error signal generated by a PLL having an output signal controlled at least in part by the DCO control codes, according to one or more examples. The Fig. 1B shows the phase error signal (compared to the one in Fig. 1A) shows less or no interference.

[0036] Curve 108 represents a relationship between DCO control code values ​​and time (or DCO control code values ​​over a specific period of time). The y-axis is the DCO control code values, increasing from the bottom of the axis to the top of the axis. The x-axis is time, increasing from left to right.

[0037] Curve 110 represents a phase error signal generated by a PLL with an output signal controlled at least in part by the DCO control codes represented in curve 108. The y-axis is the magnitude of the delay (where one of the positive or negative signs represents a leading delay and the other of the positive or negative signs represents a lagging delay). The x-axis is time, increasing from left to right.

[0038] At approximately time T 0 the curve 108 shows a change from a first value to an adjusted value (also referred to herein as “changed value”), and after time T 0 the curve 108 rises from the fitted value. Also shown (as a useful reference) is a second value corresponding to the second value in Fig. 1A. The fitted value lies between the first value and the second value. Most importantly, curve 108 never shows the second value. At time T 0 the curve 108 changes from the first value to the adjusted value and never corresponds to the range of values ​​corresponding to a DCO frequency overlap region, i.e. second value ≤ DCO control code < adjusted value. Thus, the curve 110, the phase error signal, shows, in comparison to the curve 104 in Fig. 1A no interference (e.g. interference 106) due to DCO frequency overlap.

[0039] Fig. 2 is a block diagram illustrating an integral path section 200 for bypassing DCO frequency overlap regions in a PLL according to one or more examples.

[0040] The integral path section 200 includes a digital integrator 202 and a logic circuit 212. The digital integrator 202 includes a register 206.

[0041] The integral path section 200 is a section of an integral control path of a PLL. The integral path section 200 processes digital phase error signals to produce frequency error signals. More specifically, the integral path section 200 integrates frequency information and filters out fast phase error information. Therefore, a change in a frequency error signal produced by the integral path section 200 is slower than a change in an error signal used for proportional control of the PLL, which responds more quickly to a phase error but detects little or no frequency information from the error signal. A frequency error signal produced by the integral path section 200 can be used as a DCO control code (here, DCO control code 210) that can be applied to an integral input of a DCO of the PLL.Thus, a frequency error signal / DCO control code produced by the integral path section 200 represents the PLL's attempt to correct a gradual frequency drift.

[0042] Digital integrator 202 receives digital phase error signal 208 and generates DCO control code 210. Digital integrator 202 may be, by way of non-limiting example, a digital signal processor (DSP) or other logic circuitry. Digital phase error signal 208 is a binary representation of a phase error signal representing the phase difference between two clock signals. DCO control code 210 represents the frequency error information (i.e., a frequency error signal) of digital phase error signal 208.

[0043] The digital integrator 202 accumulates a digital input signal (e.g., a discrete-time signal or discrete samples of a continuous-time signal, without limitation) over time and produces an output signal corresponding to the integrated value 216 stored in register 206. When the digital input signal is the digital phase error signal 208, the integrated value 216 represents the frequency error information in the digital phase error signal 208. As explained above, in a digital PLL, the bits (i.e., the register bits) of the integrated value 216 can be used as control code provided to an integral input of a DCO. Thus, the bits of the integrated value 216 can be used to control (i.e., adjust) the DCO frequency.

[0044] Because DCO control code 210 can be used to adjust the DCO frequency, and DCO control code 210 is based on the bits of integrated value 216, integrated value 216 can be adjusted to bypass at least a portion of a DCO frequency overlap region. As a non-limiting example, integrated value 216 can monotonically increase or decrease without external influences, depending on whether the PLL is increasing or decreasing the DCO frequency. If DCO control code 210 matches a DCO control code value associated with a boundary of a DCO frequency overlap region, integrated value 216 can be adjusted by a certain amount (an "adjustment amount") to bypass (or, in other words, "skip") at least a portion (i.e., some or all) of those DCO control code values ​​associated with the DCO frequency overlap region.DCO control code value(s) associated with a DCO frequency overlap region is / are a value or range of values ​​of the DCO control code 210 that corresponds to a DCO frequency overlap region. Bypassing at least some of these DCO control code values ​​may, as a non-limiting example, reduce the boundary cycles and associated jitter.

[0045] Logic circuit 212 receives DCO control code 210 and generates an adjustment signal 214 to adjust the integrated value 216 stored in register 206 of digital integrator 202. Logic circuit 212 may, as a non-limiting example, be a digital logic circuit. Adjustment signal 214 is a signal used by integral path portion 200, and in particular by logic circuit 212, to adjust the integrated value 216. Adjustment signal 214 may, as non-limiting examples, represent an amount by which the integrated value 216 should increase or decrease, or a new value to which the integrated value 216 should be set. The amount of increase or decrease in the integrated value 216 caused by adjustment signal 214 is proportional to the value / magnitude of adjustment signal 214.

[0046] In one or more examples, logic circuitry 212 generates adjustment signal 214 at least in part in response to observing that a value of DCO control code 210 is associated with a boundary of a DCO frequency overlap region. As a non-limiting example, the value of a DCO control code 210 may correspond to a frequency that is at or near a boundary of a DCO frequency overlap region. In one or more examples, the values ​​of the DCO control codes associated with the boundaries of the DCO frequency overlap region may be predetermined and stored in logic circuitry 212.Upon observing that a DCO control code 210 corresponds to a boundary, logic circuit 212 determines a new value for the integrated value 216 or an amount by which the integrated value 216 stored in register 206 should increase or decrease to avoid the DCO frequency overlap region (an "adjustment amount"), and generates an adjustment signal 214 proportional to the determined adjustment amount. In one or more examples, logic circuit 212 may determine a new value by determining an adjustment amount and adding or subtracting it from a current value of DCO control code 210. In one or more examples, predetermined adjustment amounts or new values ​​may be stored in logic circuit 212 and used by logic circuit 212.

[0047] Any suitable technique can be used to adjust the integrated value 216 stored in register 206 via the adjustment signal 214. In one or more examples, amplification of the digital integrator 202 can be variable amplification, expressed according to an amplification function. Such an amplification function can be at least partially based on one or more amplification-defining parameters of the digital integrator 202. In one or more examples, the adjustment signal 214 can change the amplification of the digital integrator 202, which affects the integrated value 216 stored in register 206. By changing the amplification, the integration process can be controlled so that adjustments of the integrated value 216 are possible.

[0048] The gain of the digital integrator 202 can be adjusted via one or more gain-defining parameters of the digital integrator 202. The specific gain-defining parameters depend on the specific implementation of the digital integrator 202. Non-limiting examples include: an accumulator register that accumulates phase errors or phase error samples over time; or a numerical integration algorithm for discrete-time calculations to calculate an integral value and update the integrated value 216 accordingly.

[0049] In the case of an accumulation register, non-limiting examples of gain-defining parameters include: an accumulation step size, an accumulation time, or a gain factor applied to an accumulator output. The accumulation step size is the step size or increment value used in an accumulation register to determine how much each input value contributes to an accumulated value stored in the accumulation register (the accumulated value corresponds to the integrated value 216). Adjusting the step size controls the gain of the digital integrator 202. Increasing the step size increases the gain of the digital integrator 202 (resulting in higher gain), and decreasing the step size decreases the gain of the digital integrator 202 (resulting in lower gain).The accumulation time is the rate at which the accumulated value stored in register 206 is updated (the "update rate"), which affects the gain of digital integrator 202. As a non-limiting example, the accumulation time can be controlled by the rate of a clock signal applied to digital integrator 202. By changing the time interval between updates, the effective gain of digital integrator 202 is controlled. Increasing the update rate increases the effective gain of digital integrator 202 (resulting in a higher gain), and decreasing the update rate decreases the effective gain of digital integrator 202 (resulting in a lower gain). A scaling factor is a function or value applied to values ​​provided to or received from an accumulation register.Such a scaling factor can be a fixed value or dynamically adjusted. A scaling factor multiplies or divides an accumulated value and thus controls the gain of the digital integrator 202.

[0050] Register 206 receives and stores the integrated value 216, and DCO control code 210 is based on at least some of the bits of register 206 used to represent the accumulated integrated value 216. For a given number of register bits N of register 206, 2^ N Steps are applied to a DCO input for integral control of the DCO frequency. The respective steps correspond to incremental changes in the DCO frequency.

[0051] Fig. 3 is a block diagram illustrating a device 300 for generating an adjustment signal according to one or more examples. The device 300 is a non-limiting example of the logic circuit 212 of Fig. 2.

[0052] The device 300 includes a boundary detector 302 and a look-up table (LUT) 306. The look-up table 306 includes boundary codes 308 and adjustment values ​​310. The boundary detector 302 includes boundary codes 304.

[0053] The edge detector 302 detects the presence of one or more signals of interest (here: edge codes 304) in an input signal (here: DCO control code 210) and generates an edge detector output signal (here: edge detection signal 312) to indicate the presence or absence of the one or more signals of interest. The edge detector 302 receives DCO control codes 210 and generates an edge detection signal 312 to indicate the detection of the presence of edge codes 304 in the DCO control code 210. The edge detector 302 can be, by way of non-limiting example, a logic circuit that detects signals or performs pattern comparisons. Edge codes 304 represent values of DCO control codes that are pre-determined such that they are associated with frequencies that define the upper and lower limits of the frequency range in DCO frequency overlap regions.

[0054] Boundary detector 302 compares the values ​​of DCO control code 210 to boundary codes 304 and, at least in part, in response to the comparison, generates a boundary detection signal 312. Boundary detection signal 312 indicates whether or not a boundary of a DCO frequency overlap region has been detected. In one or more examples, boundary detector 302 generates a boundary detection signal 312 having a first value in response to determining that a DCO control code 210 matches one of boundary codes 304 and generates a boundary detection signal 312 having a second, different value in response to determining that none of boundary codes 304 matches DCO control code 210.

[0055] In one or more examples, the specific boundary codes 304 that boundary detector 302 detects are based at least in part on a state of the DCO frequency (rising or falling). Boundary detector 302 may detect the presence of a first subset of boundary codes 304 when the DCO frequency is increasing and detect the presence of a second, different subset of boundary codes 304 when the DCO frequency is decreasing. In one or more examples, boundary detector 302 may use any suitable technique to detect the state of the DCO frequency (rising or falling).

[0056] In one or more examples, boundary detector 302 may derive a rising DCO frequency in response to a rising DCO control code 210 and a falling DCO frequency in response to a falling DCO control code 210. In one or more examples, boundary detector 302 may use any suitable technique to determine whether DCO control code 210 is rising or falling.

[0057] As a non-limiting example, boundary detector 302 may monitor an average change in digital phase error signal 208 and determine directional information based at least in part on the average change. Additionally or alternatively, boundary detector 302 may monitor an average change in the value of the DCO control codes and determine the directional information based at least in part on the average change.

[0058] As another non-limiting example, the boundary detector 302 may determine a rising or falling DCO frequency based on the directional information in the digital phase error signal 208 (reception of the digital phase error signal 208 is described in Fig. 3 and should be understood as optional). If the digital phase error signal 208 is generated by a bang-bang phase detector, the increment and decrement signals generated by the bang-bang phase detector may be decoded to determine directional information about the digital phase error signal 208 and thus the DCO frequency. As a non-limiting example, the limit detector 302 should detect when the digital integrator 202 increments more on average (e.g., increments the integrated value 216 and thus the DCO control code 210) as the DCO control code 210 approaches a value corresponding to an upper limit of a DCO frequency overlap region. If the digital integrator 202 decrements more on average (e.g.,the integrated value 216 and thus decrements the DCO control code 210), then the limit detector 302 should detect when the DCO control code 210 approaches a value corresponding to a lower limit of a DCO frequency overlap region.

[0059] In one or more examples, boundary detector 302 may maintain (e.g., store in memory, without limitation) historical DCO control codes and determine that the DCO control codes are increasing or decreasing based on a difference between a previous DCO control code and a current DCO control code.

[0060] The lookup table 306 associates input values ​​(here, values ​​of the DCO control code 210) with output values ​​(here, adjustment values ​​310). In one or more examples, the lookup table 306 associates input values ​​by using input values ​​(or values ​​derived from the input values) as addresses that map to memory locations in a memory or memory array of the lookup table 306 (memory not shown) in which the output values ​​are stored. The lookup table 306 retrieves the output values ​​from memory using the input values ​​as addresses.

[0061] The lookup table 306 receives the DCO control code 210 at an input and the limit detection signal 312 at an enable input and, at least in part in response thereto, provides the adjustment signal 214. A direct mapping between limit codes 308 and adjustment values ​​310 is provided in the lookup table 306. When the limit detection signal 312 is asserted, the lookup table 306 is activated and attempts to determine an adjustment value associated with the DCO control code 210.

[0062] Adjustment values ​​310 represent amounts by which the integrated value 216 should increase or decrease, or a new value to which the integrated value 216 should be set equal to in order to bypass DCO control code values ​​predetermined to correspond to a DCO frequency overlap region. Respective adjustment values ​​310 may be predetermined. As a non-limiting example, the adjustment values ​​310 may be predetermined and stored during calibration of a DCO or PLL.

[0063] In one or more examples, the stored adjustment values ​​310 may be signed (positive or negative) such that the adjustment signal 214 may also be signed (positive or negative). The respective adjustment values ​​310 and the adjustment signal 214 are signed to represent whether an offset represented by the adjustment values ​​310 or the adjustment signal 214 should be applied from the lower end of a range or from the upper end of a range of DCO code values ​​associated with a DCO frequency overlap region to bypass the DCO control corresponding to a DCO frequency overlap region. When approaching an upper limit code, the offset amount is applied from the lower end of the range and therefore has a positive sign. When approaching a lower limit code, the offset amount is applied from the upper end of the range and thus has a negative sign.

[0064] Fig. 4 is a block diagram illustrating a device 400 for bypassing DCO control codes corresponding to a DCO frequency overlap region, according to one or more examples. The device 400 includes a counter 402 and a detector 404. The device 400 is a non-limiting example of an integral path section 200.

[0065] The counter 402 receives the direction signal 406, the clock signal 408 (clk signal 408), and the reset signal 410. The direction signal 406 indicates whether the DCO control codes are increasing or decreasing. To determine the direction information indicated by the direction signal 406, any suitable technique can be used, such as using the average change in the value of the phase error signal or the DCO control code, without limitation. In one or more examples, the direction signal 406 can be generated by another logic circuit located outside the counter 402, or by a logic circuit of the counter 402 (e.g., the counter 402 is a count value logic circuit that receives signals indicating a phase error or a DCO control code and determines direction information based thereon).

[0066] The clock signal 408 may be a local clock, a system clock, a reference clock of a PLL, a feedback clock of a PLL, or derived from any of the foregoing (e.g., a frequency-divided version, without limitation).

[0067] In one or more examples, counter 402 operates as follows: When direction signal 406 indicates that digital phase error signal 208 is decreasing, counter 402 decrements the value of a count 418 by a predetermined amount each clock cycle. When the direction signal indicates that digital phase error signal 208 is increasing, counter 402 increments the value of count 418 by a predetermined amount each clock cycle.

[0068] Counter 402 resets a value of count 418 in response to an activation of reset signal 410. In response to reset signal 410 being activated and direction signal 406 indicating that digital phase error signal 208 is decreasing, counter 402 resets the value of count 418 to the upper end of the DCO control code range less a predetermined adjustment amount to avoid values ​​corresponding to the DCO frequency overlap region. In response to reset signal 410 being activated and direction signal 406 indicating that digital phase error signal 208 is increasing, counter 402 resets the value of count 418 to the lower end of the DCO control code range plus a predetermined adjustment amount to avoid values ​​corresponding to the DCO frequency overlap region. DCO tax code 210 may be based at least in part on count value 418.

[0069] Detector 404 (which may also be referred to herein as "threshold detector 404") detects when count value 418 exceeds a value of threshold signal 412. The value of threshold signal 412 may change or be adjusted by circuitry not shown. As the value of count value 418 increases (and thus the DCO control codes increase), detector 404 detects a crossover from below to above the value of threshold signal 412. As the value of count value 418 decreases (and thus the DCO control codes decrease), detector 404 detects a crossover from above to below the value of threshold signal 412. Detector 404 asserts reset signal 410 at least in part in response to detecting an crossover of the value of threshold signal 412.

[0070] In this example, the adjustment signal 214 is the reset signal 410, in response to which the counter 402 sets the counter value 418 equal to the reset values.

[0071] Fig. 5 is a block diagram illustrating a device 500 for bypassing DCO control codes corresponding to a DCO frequency overlap region, according to one or more examples. The device 500 is a non-limiting example of an integral path section 200.

[0072] The device 500 includes a counter 504, a detector 506, and a multiplexer 502. The multiplexer 502 selects one of the step size signals 508 as the selected step size signal 518 in response to a selection signal 522 generated by the detector 506. The step size signals 508 include at least two step sizes representing different magnitudes.

[0073] Counter 504 receives the selected step size signal 518 output from multiplexer 502, the direction signal 520, and the clock signal 512 (clk signal 512). The value of the selected step size signal 518 represents an amount by which counter 504 increments or decrements a value of count 516 each clock cycle. Direction signal 520 indicates whether counter 504 increments or decrements the value of count 516 each clock cycle. Any suitable technique may be employed to determine the direction information indicated by direction signal 520. As a non-limiting example, the direction information indicated by direction signal 520 may be determined based on an average change in value of a phase error signal. The direction signal 520 may be generated by another logic circuit located outside the counter 504 or by a logic circuit of the counter 504 (e.g.Counter 504 is a count logic circuit that receives signals indicating a phase error and determines the direction information based thereon.

[0074] In one or more examples, counter 504 operates as follows: When direction signal 520 indicates that the value of count 516 is decreasing (and thus, when the DCO control codes are decreasing), counter 504 decrements a value of count 516 by a selected step size signal 518 per clock cycle. When direction signal 520 indicates that the value of count 516 is increasing (and thus, when the DCO control codes are increasing), counter 504 increments the value of count 516 by the selected step size signal 518 every clock cycle.

[0075] Detector 506 (which may also be referred to herein as "threshold detector 506") observes when a count value 516 exceeds a value of a threshold signal 510 and sets selection signal 522 based on the type of crossing it observes. The value of threshold signal 510 may be adjusted by circuitry not shown. In response to observing that the value of count value 516 is increasing, detector 506 detects a crossing from below to above the value of threshold signal 510 (a first type of crossing). In response to observing that a count value 516 is decreasing, detector 506 detects a crossing from above to below the value of threshold signal 510 (a second type of crossing, different from the first type of crossing).The detector 506 sets the selection signal 522 at least in part in response to observing an exceedance of the threshold and the nature of the observed exceedance.

[0076] In one or more examples, the values ​​to which detector 506 can set selection signal 522 are pre-linked to specific inputs of multiplexer 502 and the respective step size signals 508 received at the respective inputs of multiplexer 502. In one or more examples, detector 506 drives selected step size signal 518 via selection signal 522 and multiplexer 502 to a value sufficient to bypass a range of values ​​of count 516 associated with a DCO frequency overlap region, and then, in a subsequent clock cycle, drives selected step size signal 518 via selection signal 522 and multiplexer 502 to a value associated with the DCO step size or the normal step size.

[0077] The DCO control code 210 may be based on the count value 516. In this example, the adjustment signal 214 is the selected step size signal 518, which is used by the counter 504 to increment or decrement the value of the count value 516.

[0078] Fig. 6 is a flowchart illustrating a process 600 for bypassing DCO frequency overlap regions in a PLL, according to one or more examples. Some or all of the operations of process 600 may be performed, as a non-limiting example, by the integral path portion 200 of Fig. 2, the establishment of 300 of Fig. 3, the establishment of 400 of Fig. 4, the establishment of 500 of Fig. 5 or a PLL including the same.

[0079] While the example process 600 depicts a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 600. In other examples, different components of an example device or system implementing the process 600 may perform functions at substantially the same time or in a particular sequence.

[0080] In one or more examples, process 600 includes observing that a DCO frequency is at a boundary of a DCO frequency overlap region at operation 602. In one or more examples, process 600 may include inferring that the DCO frequency is at a boundary of a DCO frequency overlap region in response to observing that a DCO control code has exceeded a threshold set at or near a control code associated with the boundary of the DCO frequency overlap region.

[0081] In one or more examples, process 600 includes bypassing at least a portion of the DCO frequency overlap region at operation 604. Process 600 may bypass at least the portion of the DCO frequency overlap region in response to observing that the DCO frequency is at a boundary of the DCO frequency overlap region at operation 602.

[0082] Fig. 7 is a flowchart illustrating a process 700 for observing that a DCO frequency is at a boundary of a DCO frequency overlap region, according to one or more examples.

[0083] While the example process 700 depicts a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 700. In other examples, different components of an example device or system implementing the process 700 may perform functions at substantially the same time or in a particular sequence.

[0084] In one or more examples, process 700 includes receiving a current control code for an integral input of a DCO at operation 702. The current control code may be bits of an accumulated value that is used as a control code output by a digital integrator.

[0085] In one or more examples, process 700 includes determining a direction of the current control code at least partially based on a difference between the current control code and a previous control code at operation 704.

[0086] In one or more examples, process 700 includes selecting a set of control codes predetermined to correspond to the boundaries of DCO frequency overlap regions based at least in part on the determined direction of the current control code at operation 706. In one or more examples, the respective control codes of the set may exactly correspond to a boundary or be within a certain distance of a boundary to allow time to establish the adjustment value. In other words, in some examples, boundary codes may be predetermined to detect approaching boundaries of the respective DCO frequency overlap regions.

[0087] In one or more examples, process 700 includes comparing the current tax code to the selected set of tax codes at operation 708.

[0088] In one or more examples, process 700 includes observing that the DCO frequency is at least partially at the boundary of the DCO frequency overlap region, including responding to the comparison at operation 710.

[0089] In one or more examples, process 700 optionally includes, if the current control code is observed to correspond to a boundary of the DCO frequency overlap region, then indicating that the DCO frequency is at a boundary of a DCO frequency overlap region at operation 712.

[0090] In one or more examples, process 700 optionally includes, if it is observed that the current control code does not correspond to a boundary of the DCO frequency overlap region, then indicating that the DCO frequency is at a boundary of a DCO frequency overlap region at operation 714.

[0091] Fig. 8 is a flowchart illustrating a process 800 for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples. Some or all of the operations of process 800 may be performed, as non-limiting examples, by the integral path portion 200 of Fig. 2 or the establishment 300 of Fig. 3, the facility 400 of Fig. 4 or the establishment 500 of Fig. 5 be carried out.

[0092] While the example process 800 depicts a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 800. In other examples, different components of an example device or system implementing the process 800 may perform functions at substantially the same time or in a particular sequence.

[0093] In one or more examples, process 800 includes obtaining an adjustment value associated with a control code indicated by a received boundary detection signal at operation 802. The received boundary detection signal is generated in response to observing a boundary of a DCO frequency overlap region, for example, as shown in Fig. 7 described.

[0094] In one or more examples, process 800 includes generating an adjustment signal proportional to the adjustment value at operation 804.

[0095] In one or more examples, process 800 includes providing the adjustment signal to a digital integrator that provides control codes for an integral input of a DCO at operation 806.

[0096] Fig. 9 is a flowchart illustrating a process for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples.

[0097] While the example process 900 depicts a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 900. In other examples, different components of an example device or system implementing the process 900 may perform functions at substantially the same time or in a particular sequence.

[0098] According to one or more examples, process 900 includes incrementing or decrementing a count value by a predetermined step size signal at operation 902.

[0099] According to one or more examples, process 900 includes observing that the count value exceeds a value of a threshold signal at operation 904.

[0100] According to one or more examples, process 900 includes setting the count value to a predetermined value at least in part in response to observing the exceedance at operation 906.

[0101] Fig. 10 is a flowchart illustrating a process for bypassing at least a portion of the DCO frequency overlap region, according to one or more examples.

[0102] Although the example illustrates a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not substantially affect the functionality of the sequence. In other examples, different components of an example device or system implementing the operation may perform functions at substantially the same time or in a particular sequence.

[0103] According to one or more examples, process 1000 includes incrementing or decrementing a count value by a step size signal at operation 1002.

[0104] According to one or more examples, process 1000 includes observing that the count value exceeds a threshold signal at operation 1004.

[0105] According to one or more examples, process 1000 includes adjusting the step size signal at least in part in response to observing the overshoot at operation 1006. In one or more examples, the step size signal is adjusted to a different, larger value in response to observing the overshoot at operation 1006.

[0106] Fig. 11 is a block diagram illustrating a device 1100 for tracking a clock (may also be referred to herein as a "clock tracking circuit 1100") according to one or more examples. In one or more examples, the clock tracking circuit 1100 may be a hybrid PLL or a digital PLL.

[0107] Clock tracking circuit 1100 generally operates to generate an output clock signal 1108 that is phase-locked and frequency-locked to a reference clock signal 1114. Clock tracking circuit 1100 includes an error detector 1102, a controller 1104, and a digitally controlled oscillator 1106. Controller 1104 includes a DCO frequency overlap region bypass circuit 1118.

[0108] Error detector 1102 receives reference clock signal 1114 and feedback clock signal 1116 and, at least in part, in response thereto, generates error signal 1112. More specifically, error detector 1102 generates an error signal proportional to the phase and frequency difference between the two input signals. More specifically, the magnitude and direction of the error signal are proportional to the phase and frequency difference between the input signals. When the phase and frequency of the two input signals are substantially the same, the magnitude and direction of error signal 1112 are zero, indicating that the phase and frequency of the two signals are the same. When there is a phase or frequency difference between the two input signals, the magnitude and direction of error signal 1112 are non-zero and proportional to the difference between the phase (and indirectly the frequency) of the two input signals.

[0109] In a case where the error detector 1102 is a binary phase detector that generates a binary signal, the error detector 1102 may generate the error signal 1112 as a binary signal with two separate and distinct component signals, an UP signal and a DOWN signal. The error detector 1102 generates the UP signal and the DOWN signal as a series of pulses, with the pulses at respective ones of the UP signal and the DOWN signal indicating the magnitude and direction of the error signal 1112. An UP pulse indicates that the phase or frequency of one of the input signals is leading the other, and a DOWN pulse indicates that the phase or frequency of one of the input signals is lagging the other. The magnitude of the error signal 1112 is represented by the number of pulses generated in the UP or DOWN signal in a given period of time.A larger number of pulses indicates a larger phase or frequency difference between the two input signals, a smaller number of pulses indicates a smaller phase or frequency difference.

[0110] The reference clock signal 1114 may be generated from any suitable clock source for a particular operational context. The feedback clock signal 1116 may be the same as the output clock signal 1108 generated by the clock tracking circuit 1100 (e.g., the output clock signal 1108 is provided directly to an input of the error detector 1102, without limitation), or it may be a clock signal indicative of the phase and frequency of the output clock signal 1108. For example, the phase and frequency of the feedback clock signal 1116 may be the same or different than the output clock signal 1108, but in either case, they are traceable to the phase and frequency of the output clock signal 1108. In one or more examples, the feedback clock signal 1116 may be a frequency-divided version of the output clock signal 1108 (e.g., via a frequency divider or buffer, without limitation).In one or more cases, the error detector 1102 may be any suitable error detector for producing a digital signal representing the phase error between the reference clock signal 1114 and the feedback clock signal 1116, including, as a non-limiting example, a bang-bang phase detector, without limitation.

[0111] Digitally controlled oscillator 1106 is an electronic oscillator for generating output clock signal 1108 at least partially in response to control signal 1110, wherein control signal 1110 is a digital control signal or a digital control code. Control signal 1110 is provided to an input of digitally controlled oscillator 1106.

[0112] The controller 1104 provides the control signal 1110 to the digitally controlled oscillator 1106 to adjust the output clock signal 1108. In one or more examples, the controller 1104 may include circuitry (analog circuitry, digital circuitry, or both) to provide a proportional control path and an integral control path for controlling the digitally controlled oscillator 1106. The integral control path may include an integral path portion 200 implementing a DCO frequency overlap region bypass circuit 1118. Because the controller 1104 places the control signal 1110 over the DCO frequency overlap region bypass circuit 1118, the clock tracking circuit 1100 may exhibit reduced DCO frequency overlap-induced limit cycles.

[0113] It will be understood by those skilled in the art that functional elements of examples disclosed herein (e.g., functions, operations, actions, processes, and / or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof. Fig. 12 illustrates non-limiting examples of implementations of functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware specifically dedicated to executing the functional elements.

[0114] It will be understood by those skilled in the art that functional elements of examples disclosed herein (e.g., functions, operations, actions, processes, and / or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof. Fig. 12 illustrates non-limiting examples of implementations of functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware specifically dedicated to executing the functional elements.

[0115] Fig.12 is a block diagram of a device 1200 (also referred to herein as "circuitry 1200" or "circuitry logic 1200") that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. The circuitry 1200 includes one or more processors 1202 (sometimes referred to herein as "processors 1202") operatively coupled to one or more data storage devices 1206 (sometimes referred to herein as "storage 1206"). The memory 1206 includes machine-executable code 1208 stored thereon, and the processors 1202 include the logic circuitry 1204. The machine-executable code 1208 includes information describing functional elements that may be implemented (e.g., performed) by the logic circuitry 1204.Logic circuitry 1204 is adapted to implement (e.g., perform) the functional elements described by machine-executable code 1208. Circuitry 1200, when executing the functional elements described by machine-executable code 1208, should be considered special-purpose hardware configured to execute functional elements disclosed herein. In some examples, processors 1202 may perform the functional elements described by machine-executable code 1208 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0116] When implemented by logic circuitry 1204 of processors 1202, machine-executable code 1208 adapts processors 1202 to perform operations of examples disclosed herein. As a non-limiting example, machine-executable code 1208 adapts processors 1202 to perform some or all of the operations related to reducing the limit cycles caused by DCO frequency overlap in the hybrid and digital PLLs discussed herein. As a further non-limiting example, machine-executable code 1208 adapts processors 1202 to perform some or all of the operations related to one or more of the following processes: process 600, process 700, process 800, process 900, or process 1000.

[0117] As a non-limiting example, machine-executable code 1208 may adapt processors 1202 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following devices: device 100, device 200, device 300, device 400, device 500, or system 1100.

[0118] Processors 1202 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer while the general-purpose computer executes or is configured to execute functional elements according to the machine-executable code 1208 (e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, processors 802 may include any conventional processor, controller, microcontroller, or state machine. Processors 1202 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0119] In some examples, memory 1206 includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, erasable programmable read-only memory (EPROM), without limitation). In some examples, processors 1202 and memory 1206 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), but not limited thereto). In some examples, processors 1202 and memory 1206 may be implemented in separate devices.

[0120] In some examples, machine-executable code 1208 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 1206, which is directly accessible by processors 1202, and executed by processors 1202 using at least logic circuitry 1204. Also as a non-limiting example, the computer-readable instructions may be stored on memory 1206, transferred to a storage device (not shown) for execution, and executed by processors 1202 using at least logic circuitry 1204. Accordingly, in some examples, logic circuitry 1204 includes electrically configurable logic circuitry 1204.

[0121] In some examples, machine-executable code 1208 may describe hardware (e.g., circuit logic) to be implemented in logic circuitry 1204 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), may be used. As non-limiting examples, VERILOG®, SystemVerilog™, or a very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0122] HDL descriptions can be converted at will into descriptions at any of numerous other levels of abstraction. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g.,The operations to be performed on logic circuitry 1204 (e.g., gates, flip-flops, registers, without limitation) may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, machine-executable code 1208 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0123] In examples where machine-executable code 1208 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1206) may implement the hardware description described by machine-executable code 1208. As a non-limiting example, processors 1202 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1204 may be electrically controlled to implement circuitry corresponding to the hardware description in logic circuitry 1204. Also as a non-limiting example, logic circuitry 1204 may include hard-wired logic manufactured by a manufacturing system (not shown, but including storage 1206) according to the hardware description of machine-executable code 1208.

[0124] Regardless of whether the machine-executable code 1208 includes computer-readable instructions or a hardware description, the logic circuit 1204 is adapted to perform the functional elements described by the machine-executable code 1208 when implementing the functional elements of the machine-executable code 1208. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0125] As used in this disclosure, the terms "module" or "component" may refer to specific hardware implementations for performing the actions of the module or component and / or to software objects or software routines that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In some examples, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are contemplated.

[0126] As used in the present disclosure, the term "combination" with respect to a plurality of elements may include a combination of all of the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0127] Terms used in the present disclosure, and particularly in the appended claims (e.g., without limitation, the body of the appended claims), are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but not limited to"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0128] Furthermore, if a specific number of introduced claim statements are intended, that intention will be expressly stated in the claim, and in the absence of such reciting, no such intention exists. As an aid to understanding, for example, the following accompanying claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that the introduction of a claim statement by the indefinite articles "a" or "an" limits a particular claim containing such introduced claim statement to examples containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g.,"a" and / or "an" shall be interpreted to mean "at least one" or "one or more", without limitation); the same applies to the use of certain articles used to introduce claim particulars.

[0129] Additionally, even if a particular number of an introduced claim statement is explicitly stated, one of ordinary skill in the art will recognize that such a statement should be interpreted to mean at least the stated number (e.g., simply stating "two statements" without other modifiers means at least two statements, or two or more statements, without limitation). Furthermore, where a convention analogous to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without limitation.

[0130] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including either term, one term or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0131] Other non-limiting examples include: Example 1: A device comprising: a digital integrator for generating a frequency error signal based at least in part on a digital phase error signal; and a logic circuit for adjusting an integrated value of the digital phase error signal stored in a register of the digital integrator. Example 2: The device according to example 1, wherein, to adjust the integrated value of the digital phase error signal stored in the register of the digital integrator, the logic circuit is adapted to: adjust a gain of the digital integrator. Example 3: Device according to one of examples 1 and 2, wherein, in order to adjust the gain of the digital integrator, the logic circuit is adapted to: set a parameter that controls the integration of the digital phase error signal at the digital integrator. Example 4: The device of any one of examples 1 to 3, wherein the parameter comprises: an accumulation step size, an accumulation time, or a scaling factor. Example 5: The device of any one of examples 1 to 4, wherein the logic circuit comprises: a boundary detector; and a look-up table (LUT) responsive to the boundary detector, the LUT associating adjustment values ​​with boundary codes. Example 6: The device of any one of examples 1 to 5, wherein the logic circuit for adjusting the integrated value is based at least in part on a respective adjustment value. Example 7: The device of any one of examples 1 to 6, wherein according to one of the digital integrator includes a counter for incrementing and decrementing a count value, and wherein the logic circuit includes a threshold detector for setting the counter to a predetermined value at least in part in response to the count value and a threshold value. Example 8: The device of any one of examples 1 to 7, wherein the logic circuit includes a detector for setting a selection signal in response to a count value and a threshold value, and a multiplexer for receiving one of the step size signals and outputting a selected step size signal in response to the selection signal, and wherein the digital integrator includes a counter for incrementing or decrementing the count value by an amount corresponding to the selected step size signal. Example 9: A method comprising: observing that a DCO frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region. Example 10: The method of Example 9, wherein observing that the DCO frequency is at the boundary of the DCO frequency overlap region comprises: receiving a current control code for an integral input of a DCO; determining a direction of the current control code based at least in part on a difference between the current control code and a previous control code; comparing the current control code to a set of control codes; and observing that the DCO frequency is at the boundary of the DCO frequency overlap region at least in part in response to the comparison. Example 11: The method of any one of examples 9 and 10, comprising: indicating that the DCO frequency is at the boundary of the DCO frequency overlap region in response to observing that the current control code corresponds to the boundary of the DCO frequency overlap region. Example 12: The method of any one of examples 9 to 11, comprising: indicating that the DCO frequency is not at the boundary of the DCO frequency overlap region in response to observing that the current control code does not correspond to the boundary of the DCO frequency overlap region. Example 13: The method of any one of examples 9 to 12, comprising: selecting a set of control codes predetermined to correspond to the boundaries of DCO frequency overlap regions based at least in part on the determined direction of the current control code. Example 14: The method of any one of examples 9 to 13, wherein bypassing at least a portion of the DCO frequency overlap region comprises: obtaining an adjustment value associated with a control code identified by a boundary detection signal; generating an adjustment signal proportional to the adjustment value; and providing the adjustment signal to a digital integrator that provides control codes for an integral input of a DCO. Example 15: The method of any one of examples 9 to 14, comprising: incrementing or decrementing a count value by a signal at a predetermined step size; observing that the count value is at a value of a threshold signal; and setting the count value to a predetermined value at least in part in response to observing the exceedance. Example 16: A method according to any one of Examples 9 to 15, comprising: incrementing or decrementing a count value by a step size signal; observing that the count value exceeds a threshold signal; and setting the step size signal to a larger value at least partially in response to observing that the count value exceeds the threshold signal. Example 17: An apparatus comprising: a digitally controlled oscillator (DCO) of a hybrid or digital clock tracking circuit, the DCO including an input for integral control of the DCO; and a controller for generating a control code for the input for integral control of the digitally controlled oscillator, the controller using control codes to reduce boundary cycles induced by DCO frequency overlaps. Example 18: The device of example 17, comprising: an error detector for generating an error signal representing a difference between an output of the DCO and a reference signal, wherein the control for generating the control code for reducing the difference is represented by the error detector. Example 19: The apparatus of any one of examples 17 and 18, wherein the controller sets the value of the control code to bypass a DCO frequency overlap region of the DCO. Example 20: The apparatus of any one of examples 17 to 19, wherein the controller sets control code bypass values ​​corresponding to DCO frequencies within a DCO frequency overlap region.

[0132] Although the present disclosure has been described herein with reference to certain illustrated examples, those of ordinary skill in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 371,105

[0001]

Claims

[1] Facility comprising: a digital integrator for generating a frequency error signal based at least in part on a digital phase error signal; and a logic circuit for setting an integrated value of the digital phase error signal stored in a register of the digital integrator. [2] The device of claim 1, wherein, for adjusting the integrated value of the digital phase error signal stored in the register of the digital integrator, the logic circuit is adapted to: Adjusting a gain of the digital integrator. [3] Device according to claim 2, wherein for adjusting the gain of the digital integrator the logic circuit is adapted to: Setting a parameter that controls the integration of the digital phase error signal on the digital integrator. [4] The device of claim 3, wherein the parameter comprises: an accumulation step size, an accumulation time, or a scaling factor. [5] The device of claim 1, wherein the logic circuit comprises: a boundary detector; and a lookup table (LUT) in response to boundary detector, where the LUT links adjustment values ​​to boundary codes. [6] The device of claim 5, wherein the logic circuit for adjusting the integrated value is based at least in part on a respective adjustment value. [7] The apparatus of claim 1, wherein the digital integrator includes a counter for incrementing and decrementing a count value, and wherein the logic circuit includes a threshold detector for setting the counter to a predetermined value at least in part in response to the count value and a threshold value. [8] The device of claim 1, wherein the logic circuit includes a detector for setting a selection signal in response to a count value and a threshold value, and a multiplexer for receiving step size signals and outputting a selected step size signal in response to the selection signal, and wherein the digital integrator includes a counter for incrementing or decrementing the count value by an amount corresponding to the selected step size signal. [9] Method comprising: Observing that a DCO frequency lies at a boundary of a DCO frequency overlap region; and Bypass at least a portion of the DCO frequency overlap region. [10] The method of claim 9, wherein observing that the DCO frequency is at the boundary of the DCO frequency overlap region comprises: Receiving a current control code for an integral input of a DCO; determining a direction of the current control code based at least in part on a difference between the current control code and a previous control code; Comparing the current tax code with a set of tax codes; and Observe that the DCO frequency is at least partly in response to the comparison at the boundary of the DCO frequency overlap region. [11] A method according to claim 10, comprising: Indicating that the DCO frequency is at the boundary of the DCO frequency overlap region in response to observing that the current control code corresponds to the boundary of the DCO frequency overlap region. [12] Method according to claim 10 comprising: Indicating that the DCO frequency is not at the boundary of the DCO frequency overlap region in response to observing that the current control code does not correspond to the boundary of the DCO frequency overlap region. [13] A method according to claim 10, comprising: Selecting a set of control codes predetermined to correspond to the boundaries of DCO frequency overlap regions, based at least in part on the particular direction of the current control code. [14] The method of claim 9, wherein bypassing at least a portion of the DCO frequency overlap region comprises: Obtaining an adjustment value associated with a control code identified by a limit detection signal; Generating an adjustment signal proportional to the adjustment value and Providing the adjustment signal for a digital integrator that provides control codes for an integral input of a DCO. [15] A method according to claim 9, comprising: Incrementing or decrementing a count value by a predetermined step size signal; Observe that the count value is at a value of a threshold signal; and Setting the count value to a predetermined value at least in part in response to observing the exceedance. [16] A method according to claim 9, comprising: Incrementing or decrementing a count value by a step size signal; Observe that the count value exceeds a threshold signal; and Setting the step size signal to a larger value at least in part in response to observing that the counter reading exceeds the threshold signal. [17] Facility comprising: a digitally controlled oscillator (DCO) of a hybrid or digital clock tracking circuit, the DCO including an input for integral control of the DCO; and a controller for generating a control code for the integral control input of the digitally controlled oscillator, the controller using control codes to reduce limit cycles induced by DCO frequency overlaps. [18] Device according to claim 17, comprising: an error detector for generating an error signal representing a difference between an output of the DCO and a reference signal, where the control for generating the control code for reducing the difference is represented by the error detector. [19] The apparatus of claim 18, wherein the controller sets the value of the control code to bypass a DCO frequency overlap region of the DCO. [20] The apparatus of claim 17, wherein the controller sets bypass values ​​of the control code corresponding to DCO frequencies within a DCO frequency overlap region.

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