DATA STORAGE DEVICE AND METHOD FOR DYNAMIC CONTROLLER MEMORY BUFFER ALLOCATION

Abstract

A data storage device and method for dynamic controller memory buffer allocation are disclosed. In one embodiment, a data storage device is provided that includes a memory and a controller having a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; to receive a request from the host to change the size of the controller memory buffer during operation of the data storage device; and to determine whether to grant the request to change the size of the controller memory buffer. Other embodiments are possible, and each of the embodiments may be used alone or in combination with one another.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of the entire contents of U.S. Non-Provisional Application No. 18 / 223,144, entitled "Data Storage Device and Method for Dynamic Controller Memory Buffer Allocation," filed in the U.S. Patent and Trademark Office on July 18, 2023, and claims priority to U.S. Provisional Application No. 63 / 437,171, filed on January 5, 2023, and is hereby incorporated by reference for all purposes. BACKGROUND

[0002] A host can store and read data from a memory of a data storage device. The data storage device may include a controller that facilitates read and write operations to the memory. The controller may include a volatile memory called a controller memory buffer. The size of the controller memory buffer is set by the data storage device at boot time and remains constant during operation of the data storage device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a block diagram of a data storage device of one embodiment. Fig. 1B is a block diagram illustrating a storage module of one embodiment. Fig. Figure 1C is a block diagram illustrating a hierarchical storage system of one embodiment. Fig. Figure 2A is a block diagram showing components of the controller of the Fig. 1A according to one embodiment. Fig. Figure 2B is a block diagram showing components of the Fig. 1A, according to one embodiment. Fig. 3 is a block diagram of a host and a data storage device of one embodiment. Fig. 4 is a block diagram of a host and a controller of one embodiment. Fig. 5 is a flowchart of a method of one embodiment for dynamic controller memory buffer allocation by a host. Fig. 6 is a flowchart of one embodiment method for dynamic controller memory buffer allocation by a data storage device. DETAILED DESCRIPTIONOverview

[0003] By way of introduction, the following embodiments relate to a data storage device and method for dynamic controller memory buffer allocation. In one embodiment, a data storage device is provided that includes non-volatile memory and a controller having a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; to receive a request from the host to change the size of the controller memory buffer during operation of the data storage device; and to determine whether to grant the request to change the size of the controller memory buffer.

[0004] In some embodiments, the controller is further configured to utilize excess memory space in the controller memory buffer that is not used by the host.

[0005] In some embodiments, the controller is further configured to consider the workload when deciding whether to grant the request.

[0006] In some embodiments, the request comprises a dedicated command.

[0007] In some embodiments, the controller and the host each include respective controller memory buffer allocation modules.

[0008] In some embodiments, the controller is further configured to reject the request if the request attempts to increase the size of the controller memory buffer beyond its maximum size.

[0009] In some embodiments, the controller is further configured to page out data in the controller memory buffer to satisfy the request.

[0010] In some embodiments, the controller is further configured to prioritize data in the controller memory buffer for paging.

[0011] In some embodiments, the controller is further configured to send an acknowledgment to the host upon approval of the request.

[0012] In some embodiments, the non-volatile memory comprises a three-dimensional memory.

[0013] In another embodiment, a method is provided that executes in a host in communication with a data storage device that includes a controller having a controller memory buffer. The method includes: instructing the data storage device to configure a size of the controller memory buffer; receiving a request from the data storage device to change the size of the controller memory buffer; and determining whether to grant the request from the data storage device to change the size of the controller memory buffer.

[0014] In some embodiments, the data storage device is configured to utilize excess memory space in the controller memory buffer that is not used by the host.

[0015] In some embodiments, the workload is taken into account when determining whether to grant the request.

[0016] In some embodiments, the request comprises a dedicated command.

[0017] In some embodiments, the controller and the host each include respective controller memory buffer allocation modules.

[0018] In some embodiments, the method further comprises determining to reject the request if the request attempts to increase the size of the controller memory buffer beyond its maximum size.

[0019] In some embodiments, the method further comprises causing data to be swapped out of the controller memory buffer to satisfy the request.

[0020] In some embodiments, the method further comprises prioritizing data for offloading.

[0021] In some embodiments, the method further comprises sending an acknowledgment to the data storage device after the request is approved.

[0022] In another embodiment, a data storage device is provided, comprising: a non-volatile memory; a controller configured to communicate with the non-volatile memory and comprising a controller memory buffer; and means for changing a size of the controller memory buffer from an initial size to a changed size during operation of the data storage device.

[0023] Other embodiments are possible, and each of the embodiments may be used alone or in combination with each other. Accordingly, various embodiments will now be described with reference to the accompanying drawings. Embodiments

[0024] The following embodiments relate to a data storage device (DSD). As used herein, "data storage device" refers to a device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below.

[0025] Data storage devices suitable for use in implementing aspects of these embodiments are described in the Fig. 1A to 1C. Fig. 1A is a block diagram illustrating a data storage device 100 according to an embodiment of the subject matter described herein. Referring to Fig. 1A, the data storage device 100 includes a controller 102 and a non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to the collection of non-volatile memory cells and associated circuitry for managing the physical operation of these non-volatile memory cells formed on a single semiconductor substrate. The controller 102 is connected to a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory die 104.

[0026] The controller 102 (which may be a non-volatile memory controller (e.g., a flash memory, resistive random access memory (ReRAM), phase change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may take the form of, for example, processing circuitry, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. The controller 102 may be configured with hardware and / or firmware to perform the various functions described below and illustrated in the flowcharts.Additionally, some of the components shown as internal to the controller may be stored external to the controller, and other components may be used. Furthermore, the term "operatively associated with" may mean a direct connection to, or an indirect (wired or wireless) connection to, one or more components that may or may not be shown or described herein.

[0027] As used herein, a non-volatile memory controller is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory controller may have various functions in addition to the specific functions described here. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory functions properly, locate faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to store firmware to operate the non-volatile memory controller and implement other functions.During operation, when a host needs to read or write data to non-volatile memory, it can communicate with the non-volatile memory controller. If the host provides a logical address to which data should be read / written, the non-volatile memory controller can convert the logical address received from the host into a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address.) The non-volatile memory controller can also perform various memory management functions, such as wear-leveling (spreading out writes to avoid wearing out certain memory blocks that would otherwise be repeatedly written to) and automatic garbage collection (when a block is full, only the valid data pages are moved to a new block, allowing the full block to be erased and reused).

[0028] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may be in the form of solid-state memory cells (e.g., flash memory cells) and may be programmable once, multiple times, or many times. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or utilize technologies with other memory cell levels now known or later developed. In addition, the memory cells may be fabricated two-dimensionally or three-dimensionally.

[0029] The interface between controller 102 and non-volatile memory die 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, data storage device 100 may be a solid-state drive. In an alternative embodiment, data storage device 100 may be part of an embedded data storage device.

[0030] Although in the Fig. 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Fig. 1B and Fig. 1C), depending on the controller functions, there may be two, four, eight, or more memory channels between the controller and the memory device. In all embodiments described herein, there may be more than a single channel between the controller and the memory die, even though only a single channel is shown in the drawings.

[0031] Fig. 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. As such, the storage module 200 may include a storage controller 202 connected to a host and to the data storage device 204, which includes a plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, or a Double Data Rate (DDR) interface. The storage module 200, in one embodiment, may be a solid-state drive (SSD) or a non-volatile dual in-line storage module (NVDIMM) such as those found in server PCs or portable computing devices such as laptops and tablet computers.

[0032] Fig. 1C is a block diagram illustrating a hierarchical storage system. A hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. Host systems 252 may access storage within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) interface or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the Fig. The system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as might be found in a data center or other location where mass storage is required.

[0033] Fig. Figure 2A is a block diagram illustrating the components of controller 102 in more detail. Controller 102 includes a front-end module 108 connected to a host, a back-end module 110 connected to one or more non-volatile memory dies 104, and various other modules that perform functions that will now be described in detail. A module may take the form of a bundled functional hardware unit designed for use with other components, a piece of program code (e.g., software or firmware) that can be executed by a (micro)processor or processing logic that typically performs a specific function of related functions, or a self-contained hardware or software component that is connected, for example, to a larger system.In addition, "means" for performing a function may be implemented with at least one of the structures specified herein for the controller and may be pure hardware or a combination of hardware and computer readable program code.

[0034] Referring again to the modules of controller 102, a buffer manager / bus controller 114 manages buffers in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102. A read-only memory (ROM) 118 stores the system startup code. Although in Fig. 2A as being located separately from the controller 102, in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located both within the controller 102 and external to the controller.

[0035] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122, which provide the electrical interface with the host or the next-level storage controller. The choice of host interface 120 type may depend on the storage type used. Examples of host interfaces 120 include, but are not limited to, Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0036] The back-end module 110 includes an error-correcting code (ECC) engine 124, which encodes the data bytes received from the host and decodes and corrects errors from the data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, to be transmitted to the non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of corrupted data. RAID parity can be used as an additional level of integrity protection for the data written to the storage device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides the command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104.In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of back-end module 110.

[0037] The data storage device 100 also includes other separate components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may be connected to the controller 102. In alternative embodiments, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that are not required in the controller 102.

[0038] Fig. Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes the non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 further includes a data cache 156 that temporarily stores data. The peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102.

[0039] With reference again to Fig. 2A, the flash control layer 132 (referred to herein as the flash translation layer (FTL) or more generally as the "media management layer" because the memory may not be flash) handles flash errors and communicates with the host. In particular, the FTL, which may be an algorithm in the firmware, is responsible for the internal operations of memory management and translates writes from the host into writes to memory 104. The FTL may be necessary because memory 104 may have a limited lifetime, can only be written to in multiples of pages, and / or cannot be written to unless erased as a block. The FTL understands these potential limitations of memory 104, which may not be visible to the host. Accordingly, the FTL attempts to translate the writes from the host into writes to memory 104.

[0040] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses ("LBAs") from the host into physical addresses in memory 104. The FTL may include other features, such as, but not limited to, power-off recovery (so that the FTL's data structures can be recovered in the event of a sudden loss of power) and wear-leveling (so that wear is even across memory blocks to prevent certain blocks from becoming excessively worn, which would lead to a greater likelihood of failure).

[0041] Referring again to the drawings, Fig. 3 is a block diagram of a host 300 and a data storage device 100 of one embodiment. The host 300 may take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc. The host 300 in this embodiment (herein, a computing device) includes a processor 330 and a memory 340. In one embodiment, computer-readable program code stored in the host memory 340 configures the host processor 330 to perform the actions described herein. Therefore, actions performed by the host 300 are sometimes considered herein to be performed by an application (computer-readable program code) executing on the host 300.For example, host 300 may be configured to send data (e.g., initially stored in host memory 340) to data storage device 100 for storage in memory 104 of the data storage device.

[0042] With further reference to Fig. 2A, in this embodiment, the controller 102 also includes a volatile memory (e.g., DRAM), referred to herein as a controller memory buffer (CMB) 103. In one embodiment, the CMB 103 is a general-purpose read / write memory that can be used by the data storage device 100 and / or the host 300 for any suitable purpose, such as, but not limited to, caching a portion of a logical-to-physical address mapping stored in the non-volatile memory 104, storing commit and / or completion queues, storing control or other data, etc.

[0043] The following paragraphs provide details of an implementation of the CMB 103 according to the NVMe specification. It is understood that these details are provided merely as an example, and that the details discussed herein (relating to the NVMe specification or otherwise) should not be read into the claims unless expressly recited therein.

[0044] In one embodiment, controller 102 indicates support for CMB 103 by setting CAP.CMBS to "1." Once this bit is set to "1," controller 102 indicates the properties of CMB 103 via the CMBLOC and CMBSZ properties. Host 300 indicates the intent to use CMB 102 by setting CMBMSC.CRE to "1." As mentioned above, CMB 103 can be used for a variety of purposes, and controller 102 can indicate which purposes CMB 103 can be used for by setting support flags in the CMBSZ property. The CMB's PCI Express address range can be used for external memory read and write requests to CMB 103. The PCI Express base address of the CMB 103 can be defined by the PCI Base Address Register (BAR), specified by CMBLOC.BIR, and the offset can be specified by CMBLOC.OFST. The size of the CMB 103 can be specified by CMBSZ.SZ.Controller 102 may use the CMB's controller address range to point to CMB 103 using addresses provided by host 300. The PCI Express address range and the CMB 103's controller address range may be different, but both ranges may be the same size and equivalent offsets within each range may have a one-to-one correspondence.

[0045] Host 300 can configure the controller address range via the CMBMSC property. Host 300 can enable the CMB's controller memory space via the CMBMSC.CMSE bit. When controller memory space is enabled and host 300 provides an address that points to the CMB's controller address range, controller 102 can forward memory read or write requests for that address to CMB 103. CMB 103 can be used by host 300 to store submission queues, allowing controller 102 to read the addresses directly from CMB 103 when the read command is issued. Completion queues in CMB 103 can be used for peer-to-peer or other applications. When writing small amounts of data, it may be advantageous for the host 300 to write the data and / or metadata to the CMB 103 rather than having the controller 102 retrieve it from the host memory 340.

[0046] Controller 102 may support Physical Region Pages (PRPs) and Scatter Gather Lists (SGLs) in CMB 103. When the CMBLOC.CDPMLS bit is set to "0," for a given PRP list or SGL associated with a single instruction, all memory associated with the PRP list or SGL may be located either entirely within CMB 103 or entirely outside CMB 103. Controller 102 may support data and metadata in CMB 103. When the CMBLOC.CDMMMS bit is set to "0," all data and metadata, if any, associated with a given instruction may be located either entirely within CMB 103 or entirely outside CMB 103. The address range allocated for CMB 103 may be aligned to 4 KiB. Controller 102 may allocate CMB 103 on an 8 KiB boundary. The controller 102 can support burst transactions up to the maximum payload size, support byte activations, and support arbitrary byte alignment.

[0047] The size of the CMB 103 can be specified by the CMBSZ.SZ field from the NVMe specification. This configuration is determined during the boot process of the data storage device 100. The size of the CMB 103 is constant during operation of the data storage device 100, and the space reserved for the CMB 103 can remain empty when the host 300 is not using it.

[0048] The following embodiments can be used to change the size of the CMB 103 during operation of the data storage device 100. These embodiments can improve the flexibility of the CMB implementation and the utilization of DRAM, resulting in faster operation of the high-end storage controller. In one embodiment, the host 300 can change the CMB size according to its current requirements and conditions, and the data storage device 100 can use the excess storage space in the CMB 103 when the host 300 does not need it (and coordinate operation with the host 300 to better utilize the controller's RAM). In one embodiment, a modified interface between the host 300 and the data storage device 100 can be used, and the host 300 can use a dedicated command that specifies the CMB size it needs for its operations (e.g.,larger or smaller than the currently used CMB size). For this purpose, the host 300 may have a host CMB allocation module 55, and the controller 102 in the data storage device 100 may have a storage controller CMB allocation module 455 (see . Fig. 4). The storage controller CMB allocation module 455, which may be computer-readable program code executing on a processor in the controller 102, may control the CMB size according to a host command or other triggering event (e.g., to dynamically change the host-controlled addresses). The host CMB allocation module 55, which may be computer-readable program code executing on the processor 330 in the host 300, may issue and receive commands related to the CMB size change.

[0049] The allocation modules 55, 455 can take the current workload into account to change the CMB size according to the expected load. For example, for a low-intensity, short-data-length workload, the data storage device 100 may decide to use the CMB 103 to store user data because it is relatively small and the associated overhead would not be significant. For a high-intensity, long-sequential workload, the CMB transfer and retrieval may incur additional unnecessary overhead that the host 300 can avoid, while allowing the host 300 to use the CMB 103 for its own purposes.

[0050] Fig. 5 is a flowchart 500 of a method of one embodiment for dynamic controller memory buffer allocation by the host 300. As in Fig. 5, the host 300 first sets an initial CMB size (and / or purpose) (action 510). Then, following a workload change or other trigger (e.g., a change in environment, a change in workload location, power instability, an increase in bit error rate (BER), etc.), the host CMB allocation module 55 issues a CMB size (and / or purpose) change command (action 520). The controller CMB allocation module 455 then analyzes the current CMB usage and responds to the host 300 by either acknowledging or denying the request (action 530). For example, if the host 300 requests to increase the CMB 103 beyond its maximum size, the controller CMB allocation module 455 may deny the request (action 540). However, if the controller's CMB allocation module 455 can satisfy the request, the controller's CMB allocation module 455 changes the CMB size as requested (action 550).This may include swapping out some controller data currently residing in DRAM to free up memory space. The controller's CMB allocation module 455 may prioritize which data can be swapped out with minimal impact to the controller's performance. After the corresponding memory space requested by the host 300 has been freed, the controller's CMB allocation module 455 may return an acknowledgment message to the host 300 (action 560).

[0051] Fig. 6 is a flowchart 600 of one embodiment method for dynamic controller memory buffer allocation by data storage device 100. In this embodiment, controller 102 may issue a request to change the CMB size. The request may be in the form of an asynchronous event and may be triggered by a controller's need to use DRAM (e.g., a critical management operation, the detection of an unusually low hit rate for controller metadata cached in DRAM, or the detection that host 300 is not fully utilizing the allocated memory space for a long period of time). As shown in Fig.6, the host 300 first establishes an initial CMB size (and / or purpose) (action 610). Then, following a critical management operation or other trigger, the controller's CMB allocation module 455 issues an asynchronous event to the host 300 to change the CMB size (action 620). The host CMB allocation module 55 then responds to the controller command (action 630). For example, if the controller 102 requests to increase the CMB 103 beyond its maximum size, the host CMB allocation module 55 may deny the request (action 640). However, if the host CMB allocation module 55 is able to grant the request, the host CMB allocation module 55 changes the CMB size as requested (action 650). The controller's CMB allocation module 455 then issues an asynchronous event to the host 300 to use the changed CMB size (action 660).

[0052] Several advantages are associated with these embodiments. For example, when the CMB is used in certain NVMe data storage devices to support high-throughput use cases, these embodiments can be used to enable better integration of the CMB with those data storage devices. This can improve the utilization of their CMB / DRAM and, as a result, reduce power consumption and improve performance under certain workloads.

[0053] Finally, as mentioned above, any suitable memory type may be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM"), non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each memory device type can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0054] The memory devices may be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element, such as an antifuse, a phase-change material, etc., and optionally a steering element, such as a diode, etc. As another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0055] Multiple memory elements can be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, flash memory devices in a NAND (NAND memory) configuration typically include memory elements connected in series. A NAND memory array can be configured so that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bitline and are accessed as a group. Alternatively, memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured differently.

[0056] The semiconductor memory elements located within and / or above a substrate may be arranged in two or three dimensions, for example as a two-dimensional memory structure or as a three-dimensional memory structure.

[0057] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., a plane in the xz direction) that is substantially parallel to a major surface of a substrate supporting the memory elements. The substrate may be a wafer over or within which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0058] The memory elements may be arranged in an ordered array, such as in a plurality of rows and / or columns, within the single memory device level. However, the memory elements may be arranged in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0059] A three-dimensional memory array is arranged so that memory elements occupy multiple levels or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the y direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate).

[0060] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As a further non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements in each column. The columns may be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions may also form a three-dimensional memory array.

[0061] As a non-limiting example, in a three-dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xz) memory device plane. Alternatively, the memory elements may be coupled together to form a vertical NAND string spanning multiple horizontal memory device planes. Other three-dimensional configurations are envisioned, where some NAND strings contain memory elements in a single memory plane, while other strings contain memory elements spanning multiple memory planes. Three-dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

[0062] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also include one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers forming each memory device level of the array are typically formed on top of the layers of the array's underlying memory device levels. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or may have intermediate layers between the memory device levels.

[0063] On the other hand, two-dimensional arrays can be formed separately and then stacked together to form a non-monolithic memory device with multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory planes on separate substrates and then stacking the memory planes on top of each other. The substrates can be thinned or removed from the memory device planes before stacking, but because the memory device planes are first formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then bundled to form a stacked-chip memory device.

[0064] Operating and communicating with the memory elements typically requires associated circuitry. As non-limiting examples, memory devices may include circuitry used to control and drive memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0065] Those skilled in the art will recognize that this invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures within the spirit and scope of the invention as described herein and understood by those skilled in the art.

[0066] The foregoing detailed description is intended to illustrate selected forms the invention may take, and not as a definition of the invention. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it is to be understood that any aspect of any embodiment described herein may be used alone or in combination with one another. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 223,144

[0001] US 63 / 437,171

[0001]

Claims

[1] Data storage device comprising: a non-volatile memory and a controller comprising a controller memory buffer, the controller configured to communicate with the non-volatile memory and further configured to: to configure a controller memory buffer size; for receiving a request from the host to change the size of the controller memory buffer during operation of the data storage device; and to determine whether to grant the request to resize the controller memory buffer. [2] The data storage device of claim 1, wherein the controller is further configured to utilize excess memory space in the controller memory buffer that is not used by the host. [3] The data storage device of claim 1, wherein the controller is further configured to consider the workload when deciding whether to grant the request. [4] The data storage device of claim 1, wherein the request comprises a dedicated command. [5] The data storage device of claim 1, wherein the controller and the host each comprise corresponding controller memory buffer allocation modules. [6] The data storage device of claim 1, wherein the controller is further configured to reject the request if the request attempts to increase the size of the controller memory buffer beyond its maximum size. [7] The data storage device of claim 1, wherein the controller is further configured to page out data in the controller memory buffer to satisfy the request. [8] The data storage device of claim 7, wherein the controller is further configured to prioritize data in the controller memory buffer for eviction. [9] The data storage device of claim 1, wherein the controller is further configured to send an acknowledgment to the host upon approval of the request. [10] The data storage device of claim 1, wherein the non-volatile memory comprises a three-dimensional memory. [11] A method comprising: Executing in a host in communication with a data storage device comprising a controller having a controller memory buffer: instructing the data storage device to configure a controller memory buffer size; Receiving a request from the data storage device to change the size of the controller memory buffer; and Determine whether to grant the data storage device's request to change the size of the controller memory buffer. [12] The method of claim 11, wherein the data storage device is configured to use excess memory space in the controller memory buffer that is not used by the host. [13] The method of claim 11, wherein the workload is taken into account in determining whether to grant the request. [14] The method of claim 11, wherein the request comprises a dedicated command. [15] The method of claim 11, wherein the controller and the host each comprise respective controller memory buffer allocation modules. [16] The method of claim 11, further comprising determining to reject the request if the request attempts to increase the size of the controller memory buffer beyond its maximum size. [17] The method of claim 11, further comprising causing a swap of data from the controller memory buffer to satisfy the request. [18] The method of claim 17, further comprising prioritizing the data for offloading. [19] The method of claim 11, further comprising sending an acknowledgment to the data storage device upon approval of the request. [20] Data storage device comprising: a non-volatile memory a controller configured to communicate with the non-volatile memory and including a controller memory buffer; and Means for changing a size of the controller memory buffer from an initial size to a changed size during operation of the data storage device.

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