Low-voltage cascode current mirror

Abstract

Methods and apparatus for a low-headroom cascode current mirror are presented. In one aspect, a gate voltage for a cascode transistor of an input branch of the current mirror is provided by a feedback block operating on a mirrored current output from an output branch of the current mirror. The feedback block includes a feedback current mirror outputting a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage for the cascode transistor of the input branch. In another aspect, the cascode current mirror includes a start-up circuit coupled between an input of the input branch and a gate of the cascode transistor of the input branch, the start-up circuit generating a start-up voltage during a transient mode of operation of the cascode current mirror.According to one aspect, a transistor is used as a starting circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Non-Provisional Application No. 18 / 048,729 for "LOW VOLTAGE CASCODE CURRENT MIRROR," filed October 21, 2022, the contents of which are incorporated herein by reference in their entirety. AREA

[0002] The present disclosure relates to electronic circuits and, more particularly, to cascode current mirrors with low headroom (voltage) requirements. BACKGROUND

[0003] With the advent of nanometer-scale technologies (i.e., < 90 nm), electronic circuits may need to operate at low voltages (e.g., < 1.2 volts) due to the lower breakdown voltages of transistors fabricated using such nanometer-scale technologies. Accordingly, analog signal processing may benefit from current-based rather than voltage-based approaches, as the low operating voltages allow for less headroom. Current mirrors are therefore expected to play a more important role in current-mode signal processing.

[0004] However, transistors manufactured using nanometer technologies can have lower output resistances. When used in a current mirror (e.g., in an output branch), a transistor with a lower output resistance can degrade the current mirror's performance and deviate from operation as an ideal current source (one with infinite output / internal resistance). This, in turn, may require a designer to increase the current mirror's output resistance by using a cascode current mirror configuration, examples of which are shown in the Fig. 1A-1D are shown.

[0005] The Fig. The prior art cascode current mirror (100a) shown in Figure 1A comprises an input branch (120a1) which supplies an input current I IN from an input current source (also known as I IN designated), and an output branch (120a2) which supplies a corresponding (sink) output current I OUTEach of the input and output branches (120a1) and (120a2) contains a respective cascode transistor stack, also referred to as a cascode stack of transistors, (Mn1, Mnc1) and (Mn2, Mnc2), with the respective transistors Mn1 and Mn2 forming the main transistors (also called mirror transistors) within the current mirror that establishes the relationship between the input current and the output current, and the respective cascode transistors Mnc1 and Mnc2, wherein the respective main transistors are connected in series with the respective cascode transistors. The transistors (Mn1, Mnc1) of the input branch (120a1) are connected as diodes and configured to bias themselves to detect the input current I IN through these transistors. In other words, since the respective drains and gates of transistors Mn1 and Mnc1 are connected to each other, the respective gate voltages VG N and VG NCfor conducting the input current I IN This in turn establishes gate bias voltages for the transistors (Mn2, Mnc2) of the output branch (120a2) to control the output current I OUT Through a ratiometric relationship between the transistors of the output branch (120a2) and the transistors of the input branch (120a1), a corresponding ratiometric relationship is established between the magnitude of the output current I OUT and the size of the input current I INA ratiometric relationship between the transistors can be established by size ratios (e.g., width, length, width-to-length ratio) of the transistors. Although the cascode current mirror (100a) can benefit from a higher output resistance (i.e., output resistance at the drain of the cascode transistor Mnc2), it requires a headroom voltage equal to the sum of the gate-source voltages (Vgs) of the transistors Mn1 and Mnc1 of the input branch (120a1). In other words, the operation of the cascode current mirror (100a) according to the state of the art requires a level of the supply voltage V DD , which is higher than the sum of the gate-source voltages (Vgs) of the transistors Mn1 and Mnc1 of the input branch (120a1). Since the Vgs of a transistor can be close to about 0.6 volts, a headroom of two Vgs can cover a significant part of the available supply voltage V DD turn off.

[0006] The Fig. The prior art cascode current mirror (100b) shown in Figure 1B attempts to reduce the required (high) headroom voltage of the configuration (100a) by reducing the gate voltage VG NC of the cascode transistor Mnc1 via an additional current source I' IN which is conducted through a diode-connected transistor Mn3, which is in a ratiometric relationship with the cascode transistor Mnc1. Accordingly, the generation of each of the gate voltages VG N and VG NC and thus the operation of the cascode current mirror (100b) with a headroom voltage that is limited to a single Vgs drop from the supply voltage V DD is reduced. The requirement of the additional current source I' IN and potential problems in maintaining an appropriate level of gate voltage VG NC under varying conditions of the input current I INHowever, the use of the configuration (100b) of Fig. 1B impractical.

[0007] The Fig. 1C or Fig. The prior art cascode current mirrors (100c) and (100d) shown in Figure 1D also attempt to reduce the required (high) headroom voltage of the configuration (100a) by reducing the gate voltage VG NC by a differential voltage between the gate voltages VG N and VG NC This differential voltage is provided by a voltage drop that may be less than the gate-source voltage of the transistor Vgs and is provided by one or more elements connected in series between the input current source I IN and the input branch (120a1) of the current mirror. In the configuration (100c) of Fig. 1C, the voltage drop is provided by a resistor R, for example, and in the configuration (100d) of Fig. 1D, the voltage drop is provided by a drain-source voltage (Vds) of a transistor Mn31, which is part of a transistor stack (120a3) including the transistor Mn31 coupled to a diode-connected transistor Mn32. In such configurations (100c) and (100d), the elements (e.g., R, Mn31, Mn32) can be selected to provide a voltage drop that is less than a gate-source voltage of the transistor, Vgs, while simultaneously controlling the input current I IN and therefore allow the operation of the cascode current mirrors (100c) and (100d) with a headroom voltage equal to the Vgs of the transistor Mn1 plus the (non-zero) voltage drop. Although the configuration (100d) of Fig. 1D compared to the configuration (100c) of Fig. 1C has the advantage of minimizing process, voltage and temperature (PVT) variations in the generated (cascode) gate voltage VG NCTo reduce the overall voltage drop, it has a higher total voltage drop due to the drain-source drop Vds of the diode-connected transistor Mn32.

[0008] Since the supply voltage V DD can be a battery voltage with a voltage level that can vary from about 3.3 volts down to about 1.5 volts or less, any headroom voltage required to operate a cascode current mirror (an input branch) can be a significant part of the supply voltage V DD, particularly at a lower range of the supply voltage. Furthermore, for the more practical of the above-mentioned prior art current mirrors (e.g., 100a, 100c, 100d), a corresponding headroom voltage may increase with the additional number of cascode transistors required for even higher output resistances of the current mirrors, so that such prior art current mirrors are simply not feasible for operation at lower voltages, as the required headroom voltage may be greater than the available supply voltage. Regardless of the need to operate at lower voltages, any reduction in headroom voltage can directly translate into power savings and thus prolong the operation of portable / handheld devices using such current mirrors.It follows that providing a practical and scalable cascode current mirror with a reduced headroom voltage is a motivation for the teachings according to the present disclosure. SUMMARY

[0009] According to a first aspect of the present disclosure, a cascode current mirror circuit is presented, comprising: an input branch comprising a first cascode stack of transistors; an intermediate output branch comprising a second cascode stack of transistors; and a feedback block comprising a feedback current mirror, wherein the feedback block is coupled to the intermediate output branch, wherein the feedback block is configured to generate a gate voltage for a cascode transistor of the input branch based on an intermediate current output from the intermediate output branch.

[0010] According to a second aspect of the present disclosure, a cascode current mirror circuit is presented, comprising: a main cascode current mirror with start-up circuit configured to receive an input current and generate a corresponding mirrored current therefrom; a feedback cascode current mirror with start-up circuit that is the dual of the main cascode current mirror with start-up circuit, wherein the feedback cascode current mirror with start-up circuit is configured to receive the mirrored current and generate a feedback current therefrom, which is used to generate a gate voltage for a cascode transistor of the main cascode current mirror with start-up circuit.

[0011] According to a third aspect of the present disclosure, a method for operating a cascode current mirror with low headroom voltage is presented, the method comprising: i) providing a cascode current mirror comprising an input branch and an intermediate output branch; ii) coupling an input current to the input branch to a gate of a main transistor of the input branch; iii) coupling a start-up aid circuit between the gate of the main transistor and a gate of a cascode transistor of the input branch; and iv) based on steps ii) and iii), generating a gate voltage at the gate of the cascode transistor of the input branch during a transient mode of operation immediately following the start of the cascode current mirror. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in this specification, illustrate one or more embodiments of the present disclosure and, together with the description of embodiments, serve to explain the principles and implementations of the disclosure. Fig. 1A, Fig. 1B, Fig. 1C and Fig. 1D show various state-of-the-art cascode current mirrors. Fig. 2A shows a simplified schematic diagram of a cascode current mirror according to an embodiment of the present disclosure, including a feedback block for generating a cascode gate voltage. Fig. Figure 2B shows details of a circuit for generating the gate voltage of the cascode of Fig. 2A based on a current generated by the feedback block. Fig. Figure 3 shows details of a feedback block used in the cascode current mirror of Fig. 2A may be used according to an embodiment of the present disclosure. Fig. 4 shows a simplified schematic diagram of another cascode current mirror according to an embodiment of the present disclosure. Fig. Figure 5A shows a simplified schematic representation of a cascode current mirror based on the current mirror of Fig. 2B, with the height of the cascode stack increased. Fig. Figure 5B shows details of a feedback block used in the cascode current mirror of Fig. 5A can be used. Fig. Figure 5C shows details of another feedback block used in the cascode current mirror of Fig. 5A can be used. Fig. 6 shows alternative circuits according to embodiments of the present disclosure for generating gate cascode voltages of the cascode current mirror of Fig. 4. Fig. Figure 7 shows details of an output stage of the cascode current mirror of Fig. 3. Fig. 8 is a process diagram illustrating various steps of a method for operating a low headroom voltage cascode current mirror according to the present disclosure.

[0013] Like reference numbers and designations in the different drawings indicate like elements. DETAILED DESCRIPTION

[0014] As in Fig. 2A, teachings according to the present disclosure further reduce the required headroom voltage for the operation of a cascode current mirror (200a) by using a feedback block (250, circuit) to generate the gate voltage VG NC for the cascode transistor Mnc1 of the input branch (220a1). As in Fig. 2A, the feedback block (250) according to the present teachings may provide a (mirrored) current I OUT1which is generated by mirroring the input current I IN which is conducted in the input branch (220a1) via an intermediate output branch (220a2). In other words: In contrast to the prior art cascode current mirrors described above, the gate voltage VG NC not (directly) via the input current I IN generated, but via a mirrored current I OUT1 , which is passed through another branch (e.g. 220a2) containing a cascode transistor stack (Mn2, Mnc2). The feedback block (250) in turn receives the current I OUT1 as input to set the gate voltage VG NC for the cascode transistor Mnc1. On the other hand, the gate voltage VG N for the (main) transistor Mn1 via a direct coupling / connection of the gate of the transistor Mn1 to the input current source I IN or, in other words, with the drain of the cascode transistor Mnc1.

[0015] With continued reference to Fig. 2A, according to one embodiment of the present disclosure, the transistors Mn2 and Mnc2 of the intermediate output branch (220a2) may be designed to conduct the same current as the transistors Mn1 and Mnc1 of the input branch (220a1). In other words, considering a steady-state operating mode of the cascode current mirror (200a) characterized by steady-state levels of the gate voltages (e.g., VG N , VG NC ) at the various Fig. 2A shown branches, a magnitude of the current, I OUT1 , equal to a magnitude of the current I IN According to other embodiments of the present disclosure, the transistors Mn2 and Mnc2 of the intermediate output branch (220a2) may be designed to conduct a current I during the steady-state operating mode of the cascode current mirror (200a). OUT1 which differs from the input current I INAs described later, a ratiometric relationship between the sizes of transistors (Mn1, Mnc1) and (Mn2, Mnc2) can be used to design transistors used in the feedback block (250) to control the gate voltage VG NC to generate.

[0016] With further reference to Fig. 2A, the cascode current mirror (200a) according to the present teaching may include an output branch (280n) comprising a cascode transistor stack (Mn OUT , Mnc OUT ) which is controlled by the gate voltages (VG N , VG NC ) is biased to provide an output current (sink current) I OUT_SK based on the input current I IN Based on the ratiometric assignment of transistors of the output branch (280n) to transistors of the input branch (220a1), a corresponding ratiometric relationship can be established between (a value of) the output current I OUT_SK and (a value of) the input current IIN As will be explained later with reference to e.g. Fig. 3, the cascode current mirror according to the present teaching can have a complementary output branch (e.g. 280p in Fig. 3) which contains an output current (source) (e.g. I OUT_SC in Fig. 3) which is based on the input current I IN based.

[0017] According to one embodiment of the present disclosure, the block (250) of Fig. 2A the (output) voltage VG NC . It is understood that the gate voltage VG NCis equal to the gate-source voltage Vgs of the cascode transistor Mnc1 plus the drain-source voltage Vds of the main transistor Mn1. Accordingly, the voltage generated by the feedback block (250) can be reduced by reducing the drain-source voltage Vds of the main transistor Mn1 (e.g., via design parameters of the transistor). Accordingly, the headroom voltage required for the operation of the output branch (280n), which is determined by the gate voltage VG NC can be defined by reducing the drain-source voltage Vds of the main transistor Mn1. On the other hand, the required headroom voltage for the operation of the input branch (Mn1, Mnc1) can be equal to the gate-source voltage Vgs of the main transistor Mn1, which is determined by the gate voltage VG NIn other words, the input branch (the - stage) of the cascode current mirror (200a) according to the present teaching can operate with a headroom voltage similar (i.e., a gate-source voltage Vgs) to that defined by the circuit described above with reference to Fig. 1B is provided according to the prior art, but without an additional current source (e.g. I' IN from Fig. 1B).

[0018] When commissioning the cascode current mirror (200a) of Fig. 2A, the gate voltages VG N and VG NC be at a voltage level of zero (e.g. because the supply voltage V DD may be off / deactivated), and therefore no current can flow through the cascode transistor Mnc1. Changing the gate voltage VG Non the main transistor Mn1 cannot change the conduction state of the cascode transistor Mnc1, and therefore no current can flow through the input branch (220a1) or the intermediate output branch (220a2). It follows that, according to an exemplary embodiment of the present disclosure, a kick-start circuit block (220a3) is inserted between the input current source I IN and the gate of the cascode transistor Mnc1 can be coupled (connected) to ensure / enable (start-up) conduction of the cascode transistor Mnc1.

[0019] With continued reference to Fig. 2A, the circuit block (220a3) according to an embodiment of the present disclosure may be configured to generate a varying level of the gate voltage VG NCduring a transient operating mode of the cascode current mirror (200a), wherein the transient operating mode is based on a time required for the cascode current mirror (200a) to reach its steady-state operating mode, which is defined by the gate voltage VG NC (and the gate voltage VG N ) are at their stationary level.

[0020] When commissioning the cascode current mirror (200a) of Fig. 2A and during operation according to the transient operating mode, the gate voltage VG N increase so that the input current I IN through the main transistor Mn1. Since the gate voltage VG N is coupled to an input of the circuit block (220a3), such an increase in the gate voltage VG N in turn cause an output of the circuit block (220a3) coupled to the gate of the cascode transistor Mnc1 to set the gate voltage VG NCincreased, allowing current to flow through transistors Mnc1 and Mn1. Such an increase in the gate voltage VG N and thus the gate voltage VG NC can continue until the cascode stack (220a1) is biased to supply the input current I IN (exactly) conducts, or in other words, until operation occurs in stationary mode.

[0021] With continued reference to Fig. 2A, according to an embodiment of the present disclosure, the gate voltage VG NC during the steady-state operating mode exclusively by the feedback block (250) on the basis of the (mirrored) current I OUT1 In other words, during the steady-state operation mode, the circuit block (220a3) cannot influence the gate voltage VG NC On the other hand, the gate voltage VG NCat least during a part of the transition mode immediately after commissioning, be generated exclusively by the circuit block (220a3), and during a further part of the transition mode up to the steady state, the gate voltage VG NC by a combined function of the circuit block (220a3) and the feedback block (250). In some embodiments, the circuit block (220a3) can be used to stabilize the gate voltage VG NC In some embodiments, the circuit block (220a3) may contribute to a value of the gate voltage VG NC to maintain if an interruption and / or disruption of V DD occurs.

[0022] With continued reference to Fig. 2A, the circuit block (220a3) according to an embodiment of the present disclosure may include a (start-up) transistor Mnst comprising a first (control) terminal (e.g., gate) connected / coupled to the output (e.g., drain of Mnc1) of the cascode stack (220a1), a second (output) terminal (e.g., source) connected / coupled to the gate of the transistor Mnc1, and a third (bias) terminal (e.g., drain) connected to the supply voltage V DD connected / coupled. During commissioning, the gate voltage (VG N ) of the cascode transistor must be higher than the source voltage (VG NC ) to the transistor, and therefore the transistor Mnst conducts to maintain the cascode gate voltage VG NC When the cascode gate voltage VG NC rises to its steady-state level, i.e. to a level higher than the gate voltage VG N, the gate-source voltage Vgs of the transistor Mnst decreases until the transistor stops conducting and is therefore (effectively) decoupled from the gate of the cascode transistor Mnc1. It should be noted that the Fig. 2A, the cascode current mirror (200a) comprises n-type input and output branches (220a1, 220a2) containing n-type FET transistors (NMOS) (Mn1, Mn2, Mnc1, Mnc2), the branches (220a1, 220a2) being configured to act as “sinks” for the respective currents I IN and I OUT1 Accordingly, the circuit block (220a3) may include an NMOS-FET transistor of the same polarity (i.e., n-type) Mnst. The teachings according to the present disclosure may also apply to a dual / complementary cascode current mirror configuration including p-type transistors (e.g., PMOS-FETs) for providing input and output branches configured to serve as "sources" for the respective currents (e.g., Fig. 4, described later).

[0023] Fig. Figure 2B shows details of a circuit block (250b) for generating the gate voltage of the cascode VG NC based on a current I OFB which is generated by a circuit block (250a) within the feedback block (250). In other words, according to an embodiment of the present disclosure, the circuit block (250a) that is part of the feedback block (250) can generate a (source) current I OFB based on the input (sink) current I OUT1 generate, where the current I OFB the circuit block (250b), which is part of the feedback block (250), is provided to determine the cascode gate voltage VG NC According to one embodiment of the present disclosure and as described in Fig. 2B, the circuit block (250b) may include a diode-connected transistor Mncg that biases itself to prevent the conduction of current IOFB between its drain / gate and source terminals (coupled to the reference ground). The self-bias of the transistor Mncg connected as a diode can in turn determine the gate voltage VG NC the cascode generate.

[0024] With continued reference to Fig. 2B and with reference to Fig. 3, the generated gate voltage VG NC to conduct the input current I IN by the cascode transistor Mnc1 of the input branch (220a1) by switching the transistors Mnc1 and Mncg and thus the currents I IN , I OUT1 and I OFB According to one embodiment of the present disclosure, a ratiometric assignment of the currents I OUT1 and I OFB by a (feedback) current mirror (e.g. 250a1, 250a2 of Fig. 3) included in the circuit block (250a) of the feedback block (250), such a current mirror being configured to measure the current I OUT1 as input to a corresponding input branch (e.g. 250a1 of Fig. 3) and measure the current I OFB through a corresponding output branch (e.g. 250a2 of Fig. 3). It should be noted that, although in the foregoing such a feedback current mirror is described as a cascode current mirror, which in some cases can be considered as the dual / complement of the (main) cascode current mirror (e.g., 220a1, 220a2, 220a3), the teachings according to the present disclosure may equally apply to the use of a feedback current mirror that is not necessarily of the cascode type (e.g., a single transistor per branch) to output the current I OFB to generate.

[0025] Fig. Figure 3 shows details of a feedback block (250a, 250b) used in the cascode current mirror (200a) of Fig. 2A / 2B can be used. In particular, Fig. 3 Details of the Fig. 2B according to an embodiment of the present disclosure. As described above with reference to Fig. 2B, the circuit block (250a) may include a (feedback) cascode current mirror (250a1, 250a2) having an input branch (250a1) comprising transistors (Mp1, Mpc1), wherein the input branch (250a1) is connected between the supply voltage V DD and the intermediate output branch (220a2) is coupled to the current I OUT1 as input. Furthermore, the cascode current mirror (250a1, 250a2) may comprise an output branch (250a2) with transistors (Mp2, Mpc2), wherein the output branch (250a2) is connected between the supply voltage V DDand the circuit block (250b, e.g. transistor Mncg connected as a diode), is configured to control the current I OUT1 of the input branch (Mp1, Mpc1) in order to determine the output current I OFB to generate.

[0026] It should be noted that for operation according to a current mirror and as in Fig. 3 (and other figures of the present disclosure), the respective gates of the transistors of the input branch (e.g., Mp1, Mpc1) are biased with the same voltages (e.g., VG P , VG PC ) as the respective gates of the transistors of the output branch (e.g. Mp2, Mpc2). Accordingly, the operation of the feedback block (250), including the blocks (250a, 250b) for generating the gate voltage VG NC , via a headroom voltage equal to the gate voltage VG NCplus the drain-source voltages Vds of the transistors Mp2 and Mpc2. As already mentioned, such drain-source voltages can be small (e.g., down to 50 mV or less) due to the design of the transistors, and therefore the voltage required to generate the gate voltage VG NC headroom voltage required by the feedback block (250) is substantially equal to a gate-source voltage Vgs.

[0027] With continued reference to Fig. 3, the input branch (250a1) of the feedback current mirror (250a1, 250a2) may include a startup state (e.g., gate of cascode transistor Mpc2 high during startup) that produces similar effects to those described above with reference to the input branch (220a1). It follows that, according to one embodiment of the present disclosure, the feedback block (250a) may further include a kick-start circuit block (250a3) coupled (connected) between an input (e.g., drain of transistor Mpc1) of the input branch (250a1) and a gate of the cascode transistor Mpc1 to provide / activate a (start-up) conduction of the cascode transistor Mpc1. Further details of the operation of the circuit block (250a3), also based on a corresponding transistor Mpst, can be taken from the above description of the circuit block (220a3) and the corresponding transistor Mnst, where the opposite polarities (e.g.n-type vs. p-type) of such transistors and their different starting states (e.g. low vs. high starting gate voltages) must be taken into account.

[0028] With further reference to Fig. 3, according to an embodiment of the present disclosure, the gate voltage VG PC for the cascode transistor Mpc1 of the input branch (250a1) of the feedback current mirror (250a1, 250a2) via a circuit (e.g. 220a4, 220b) which corresponds to the circuit described above (e.g. 250a2, 250b) for generating the gate voltage VG NC for the cascode transistor Mnc1, where the opposite polarities (e.g., n-type vs. p-type) are taken into account by the transistors used in the two current mirrors (220a1, 220a2) and (250a1, 250a2) and therefore by their respective output currents (e.g., I OUT1 a sink output current for the output branch 220a2, and I OFBis a source output current for the output branch 250a2).

[0029] According to an exemplary embodiment of the present disclosure and as described in Fig. 3, the gate voltage VG PC by conducting a current I OUT2 generated by a transistor Mpcg connected as a diode, where the current I OUT2 and the transistor Mpcg each in a ratiometric relationship to the current I OUT1 (and thus I OFB ) and the transistor Mpc1. According to one embodiment of the present disclosure, the current I OUT2 with a cascode transistor stack (Mn3, Mnc3), which can be considered as an additional intermediate output branch (220a4) of the input branch (220a1). This is possible because all Fig. 3 can be in a ratiometric relationship to each other, based on the (known) ratiometric relationship of the (transistors of) the various Fig. 3 branches shown.

[0030] With further reference to Fig. 3, the circuit block (250a) can be described as containing a feedback current mirror with start-up aid circuit (250a1, 250a2, 250a3), which is the dual / complementary circuit of a (main) cascode current mirror with start-up aid circuit (220a1, 220a2, 220a3). In other words, the transistors used in the dual circuit (250a1, 250a2, 250a3) can be of opposite polarity (e.g., p-type) to the transistors used in the main circuit (220a1, 220a2, 220a3). As shown in Fig. 3, an output / mirror current (e.g. I OUT1) of the main circuit (220a1, 220a2, 220a3) can be an input current of the dual circuit (250a1, 250a2, 250a3). In addition, the (cascode) gate voltage VG NC , to the main circuit (220a1, 220a2, 220a3) by conducting a current (e.g. I OFB ) which is a mirrored current of the input current (e.g., I OUT1 ) flows through a diode-connected transistor (e.g., Mncg) with the same polarity (e.g., n-type) as the transistors of the main circuit (220a1, 220a2, 220a3) into the double circuit (250a1, 250a2, 250a3). Likewise, the (cascode) gate voltage VG PC , for dual switching (250a1, 250a2, 250a3) by conducting a current (e.g. I OUT2 ) which is a mirrored current of the input current (e.g., I IN) to the main circuit (220a1, 220a2, 220a3) by a diode-connected transistor (e.g. Mpcg) having the same polarity (e.g. p-type) as the polarity of the transistors of the dual circuit (250a1, 250a2, 250a3).

[0031] With continued reference to Fig. 3, the main circuit (220a1, 220a2, 220a3) according to the present disclosure can be referred to as an n-type cascode current mirror with start-up aid circuit, and the double circuit (250a1, 250a2, 250a3) can be referred to as a p-type cascode current mirror with start-up aid circuit. Since the current mirror branches (220a1, 220a2) are connected to a low-impedance reference voltage (i.e., reference ground) and the current mirror branches (250a1, 250a2) are connected to a high-impedance supply voltage (i.e., V DD), the main circuit (220a1, 220a2, 220a3) can be referred to as a low-side (n-type) cascode current mirror with start-up aid circuit, and the double circuit (250a1, 250a2, 250a3) can be referred to as a high-side (p-type) cascode current mirror with start-up aid circuit.

[0032] As in Fig. 3, complementary output branches (280n) and (280p), which are formed by mirroring the input currents (e.g. I IN and I OUT1 ) provided by the input branches (e.g. 220a1 and 250a1) of the low-side and high-side cascode current mirrors (220a1, 220a2, 220a3 and 250a1, 250a2, 250a3), output sink and source currents I OUT_SK and I OUT_SC By ratiometrically relating transistors (Mnout, Mncout) of the (low-side) output branch (280n) to transistors of the (low-side) input branch (220a1), a corresponding ratiometric relationship can be established between (a value of) the output sink current IOUT_SK and (a value of) the input current, I IN , can be produced. Likewise, by ratiometrically relating transistors (Mpout, Mpcout) of the (high-side) output branch (280p) to transistors of the (high-side) input branch (250a1), a corresponding ratiometric relationship between (a value of) the output source current I OUT_SC and (a value of) the input current I OUT1 and thus the input current I IN be provided.

[0033] Teachings according to the present disclosure are not limited to a (main) cascode current mirror (e.g. 220a1, 220a2, 220a3 of Fig. 3) with an input branch (e.g. 220a1 of Fig. 3) which is configured to accept an input current (e.g. I IN from Fig. 3) to reduce. As in Fig. 4, a dual / complementary configuration of the Fig. 3 shown configuration for receiving an input current I INSuch a dual configuration can be obtained by, as in Fig. 4, considers a main circuit (250a1, 250a2, 250a3) which may be a high-side cascode current mirror (p-type) with a start-up aid circuit similar to that described above with reference to Fig. 3, but for receiving the input current I IN , and a corresponding double circuit (220a1, 220a2, 220a3), which may be a low-side cascode current mirror (n-type) with a start-up aid circuit, similar to that described above with reference to Fig. 3 described circuit, but for receiving the output current I OUT1 . Details on other aspects of the Fig. 4 can be found in the above description with reference to Fig. 3, including details related to the generation of the cascode gate voltages VG PC (comparable to VG NC from Fig. 3) and VG NC (comparable to VG PC from Fig. 3). The performance in relation to the power required for the operation of the cascode current mirror in Fig. 4 required open circuit voltage is similar to Fig. 3 (e.g. open circuit voltage of about 1 Vgs).

[0034] Fig. 5A shows a simplified schematic representation of a cascode current mirror (500a) according to an embodiment of the present disclosure, which is based on the device described above with reference to Fig. 2B, with an increased cascode stack height. In other words, a number of cascode transistors in the different branches (e.g., 220a1, 220a2, 22a3) of the cascode current mirror (500a) may be greater than one, such as two (as in Fig. 5A), or even more than two, while maintaining performance in terms of the required headroom voltage. According to an embodiment of the present disclosure, as described in Fig. 5A, the kick-start circuit block (220a3) may be configured to provide different levels of the (cascode) gate voltages VG during a transient operating mode of the cascode current mirror (500a). NCa and VG NCb wherein the transient operating mode is based on a time that the cascode current mirror (500a) may need to reach its steady-state operating mode, which is defined by the gate voltages VG NCa and VG NCb (and the gate voltage VG N ) are at their respective steady state levels.

[0035] According to an embodiment of the present disclosure, the circuit block (220a3) as shown in Fig. 5A, a respective (start-up) transistor (e.g., Mnsta, Mnstb) for providing the (transition / start-up) gate voltage for each of the cascode transistors (e.g., Mnc1a, Mnc1b). The operation of each of these transistors can be seen from the above description with reference to the transistor Mnst in Fig. 2A / 2B. Similarly, as in Fig. 5A shows the generation of the gate voltages VG NCa and VG NCb by conducting the respective currents I OFB and I' OFB through the respective transistors Mncga and Mncgb connected as diodes, whereby the respective currents I OFB and I' OFB can be generated by the circuit block (250a) in a similar manner as described above with reference to Fig. 2A for the generation of current I OFB It should be noted that the currents I OFB and I' OFBcan be the same or different, as long as the ratiometric relationships between transistors and currents are maintained. Further aspects of generating the gate voltages VG NCa and VG NCb can be found in the above description with reference to Fig. 2B.

[0036] Fig. Figure 5B shows details of elements of a feedback block (250a, 250b) used in the cascade current mirror (500a) of Fig. 5A can be used. In particular, Fig. 5B according to an embodiment of the present disclosure details of the Fig. 5A. It should be noted that such details are based on the above description of the Fig. 2A / 2B / 3 are easy to understand. Accordingly, the circuit block (250a) can be Fig. 5B, a (feedback) cascode current mirror (250a1, 250a2) with an input branch (Mp1, Mpc1) connected between the supply voltage V DD and the intermediate output branch (220a2) is coupled to the current I OUT1 as input. In addition, the cascode current mirror (250a1, 250a2) may comprise respective output branches (Mp2, Mpc2) and (M'p2, M'pc2) connected between the supply voltage V DD and the circuit block (250b, e.g. transistors Mncgb and Mncga connected as a diode), which are configured to measure the current I OUT1 of the input branch (Mp1, Mpc1) in order to determine the respective output currents I OFB and I' OFB Furthermore, as explained above with reference to Fig. 3, which in Fig. Gate voltage VG shown in Figure 5B PC by conducting a current I OUT2generated by a transistor Mpcg connected as a diode, where the current I OUT2 and the transistor Mpcg each in a ratiometric relationship to the current I OUT1 and the transistor Mpc1. As shown in Fig. As shown in Figure 5B, the current I OUT2 generated by an additional (low-side) output branch (220a4) containing the transistors Mn3, Mnc3a and Mnc3b.

[0037] The example configuration of the circuit block (250a) according to the Fig. 5B uses high-side (p-type) (feedback) current mirror input / output branches that include two transistors (i.e., a cascode transistor). As previously described, the teachings of the present disclosure may use a feedback current mirror that is not necessarily of the cascode type (e.g., a single transistor per branch) to measure the current I OFB In addition, as described in Fig. 5B, the stack height of the high-side current mirror does not necessarily match that of the low-side current mirror. Increasing the stack height of the high-side current mirror may require a corresponding increase in the number of start-up transistors used in the circuit block (250a3) and a corresponding increase in the number of circuits (or circuit elements) for generating the cascode gate voltages. This is shown in Fig. 5C for a case where the high-side current mirror input / output branches (e.g., 250a1, 250a2) have the same stack height as the low-side current mirror input / output branches (e.g., 220a1, 220a2 of Fig. 5A).

[0038] With reference to Fig. 5C, the circuit block (250a3) may include start-up transistors (Mpsta, Mpstb) that are each operatively connected to cascode transistors (Mpc1a, Mpc1b) for generating respective gate voltages during the transient mode of operation in a manner consistent with the embodiments described above with reference to Fig. 5A described transistors (Mnsta, Mnstb). Likewise, the generation of each of the cascode gate voltages (VG PCa , VG PCb ) for operation during the steady-state mode of operation with the generation of the cascode gate voltage VG PC compared with those described above with reference to Fig. 5B was described.

[0039] It should be noted that the use of different stack heights for the main and feedback current mirrors (cascode) or in other words for the low-side and high-side current mirrors (cascode), as described above with reference to the Fig. 3 / 4 / 5, affect the stack height of the low-side and high-side output branches (280n, 280p), since each of the low-side or high-side branches can have the same stack height. It should also be noted that the use of a particular stack height may be based on an expected high voltage coupled to the stack (e.g., at an output node of the stack) and the respective (low) withstand voltage of the individual transistors of the stack, so that the high voltage is distributed across the individual transistors in such a way that each of these transistors is subjected to a voltage lower than its respective withstand voltage.

[0040] Fig. Figure 6 shows alternative circuits according to embodiments of the present disclosure for generating cascode gate voltages (e.g., VG NCa , VG NCb ) of the Fig. 4. In particular, a configuration (a) of Fig. 6, which in Fig. 4, two similar circuits for generating each of the cascode gate voltages VG NCa and VG NCb where each of these circuits contains an output branch of a current mirror (e.g., Mp2, Mpc2a, Mpc2b or M'p2, M'pc2a, M'pc2b) to measure a current (e.g., I OFB or I' OFB ) which is conducted through a (self-biasing) diode-connected transistor (e.g., Mncgb or Mncga). On the other hand, according to an embodiment of the present disclosure, a configuration (b) as shown in Fig. 6, a single (common) output branch (Mp2, Mpc2a, Mpc2b) can be used to generate a single (common) current I OFB which is passed through two series-connected transistors (Mncga, Mncgb). Mncga is configured to generate VG NCa to produce, and the combination of Mncga and Mncgb produces VG NCb. The transistor Mncgb is configured to generate a voltage at its drain to source that meets the voltage requirements for VG NCb The gate of Mncgb is biased with a voltage V B coupled, where V B an internal bias voltage within the current mirror 500a or V DD or an external bias voltage suitable to produce the required voltage drop across the drain from Mncgb to the source when I OFB flows through Mncgb. Thus, VG NCb to make the voltage drop at Mncgb greater than VG NCa

[0041] Fig. Figure 7 shows details of an output stage (280n, 280p) of the cascode current mirror according to the present teaching. As in Fig. 7, the output stage (280n, 280p) may comprise (complementary) low-side and high-side output stages (280n) and (280p), each of which may comprise one or more (parallel) output (mirror) branches. As shown in Fig. 7, the low-side output stage (280n) may, for example, include a number m of parallel (low-side) output branches (e.g., transistors for each branch indexed from 1 to m) to provide corresponding (sink) currents (I OUT_SK1 , I OUT_SK2 ,...,I OUT_SKm ). Likewise, the high-side stage (280p) can have a number k of parallel (high-side) output branches (e.g. transistors of each branch, indexed from 1 to k) for outputting corresponding (source) currents (I OUT_SC1 , I OUT_SC2 ,...,I OUT_SCk). It should be noted that the low-side and high-side output stages (280n, 280p) may have respective stack heights corresponding to the respective stack heights of the low-side and high-side current mirrors used (e.g. main current mirrors 220a1, 220a2 and dual current mirrors 250a1, 250a2 in Fig. 3), and therefore do not have to be limited to an equal and constant stack height.

[0042] Fig.8 is a process diagram (800) illustrating various steps of a method according to the present disclosure for operating a cascode current mirror with low headroom voltage. As can be seen from the process diagram (800), such steps include: providing a cascode current mirror having an input branch and an intermediate output branch according to step (810); coupling an input current to the input branch to a gate of a main transistor of the input branch according to step (820); coupling a start-up aid circuit between the gate of the main transistor and a gate of a cascode transistor of the input branch according to step (830); based on steps (820) and (830), generating a gate voltage to the gate of the cascode transistor of the input branch during a transient mode of operation immediately following startup of the cascode current mirror according to step (840).

[0043] The term "MOSFET" as used in this disclosure encompasses any field-effect transistor (FET) with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" encompass at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" encompasses at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" encompasses at least one semiconductor material.

[0044] For the purposes of this publication, the term "radio frequency" (RF) refers to an oscillation rate in the range of approximately 3 kHz to approximately 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency can be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0045] Various embodiments of the invention can be implemented to meet a variety of specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention can be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments can be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, high-resistance bulk CMOS, silicon-on-insulator (SOL), and silicon-on-sapphire (SOS). Unless otherwise stated above, embodiments of the invention can also be employed in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz). Monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least distributed evenly across all devices so that they can be compensated).

[0046] Depending on the specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS transistors, enhancement-mode or depletion-mode transistors), the voltage levels may be adjusted and / or the voltage and / or logic signal polarities may be reversed. The voltage, current, and energy handling capabilities of the components can be adjusted as needed, e.g., by adjusting the size of the devices, serially stacking components (especially FETs) to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional features without significantly altering the functionality of the disclosed circuits.

[0047] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be housed in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of the present invention are often used in modules in which one or more such ICs are combined with other circuits (e.g., filters, amplifiers, passive components, and possibly additional ICs) in a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of a final product such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless.

[0048] A number of embodiments of the invention have been described. It should be understood that various changes may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence independent and may therefore be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the above methods may be performed repeatedly, serially, and / or in parallel.

[0049] It is to be understood that the foregoing description is illustrative and not limiting, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes all possible combinations of one or more of the methods, machines, manufacturing processes, or compositions of matter recited in the following claims. (It should be noted that the parentheses surrounding claim elements are provided to facilitate reference to these elements and do not, in themselves, indicate any particular required order or enumeration of elements; further, these terms may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting sequence of terms.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 048,729

[0001]

Claims

[1] Cascode current mirror circuit comprising: an input branch with a first cascode stack of transistors, an intermediate output branch comprising a second cascode stack of transistors, and a feedback block comprising a feedback current mirror, the feedback block being connected to the intermediate output branch, wherein the feedback block is configured to generate a gate voltage for a cascode transistor of the input branch based on an intermediate current output from the intermediate output branch. [2] A cascode current mirror circuit according to claim 1, wherein: the feedback block further comprises a diode-connected transistor connected to a gate of the cascode transistor, and the feedback current mirror is configured to generate a mirrored intermediate current for conduction through the diode-connected transistor. [3] Cascode current mirror circuit according to claim 2, wherein: the diode-connected transistor is configured to generate a self-biased gate voltage for conducting the mirrored intermediate current, where the self-biased gate voltage is coupled to the gate of the cascode transistor. [4] A cascode current mirror circuit according to claim 1, further comprising: an output current stage with an output branch that mirrors an input current to the input branch. [5] The cascode current mirror circuit of claim 1, further comprising a start-up circuit selectively connected between an input of the input branch and a gate of the cascode transistor of the input branch. [6] A cascode current mirror circuit according to claim 1, further comprising: a start-up circuit connected between an input of the input branch and a gate of the cascode transistor of the input branch at least during a part of a transient operating mode of the cascode current mirror circuit immediately following a start-up of the cascode current mirror, where the start-up circuit is configured to supply the gate voltage to the cascode transistor during said portion of the transient operating mode. [7] Cascode current mirror circuit according to claim 6, wherein: the start-up circuit is configured to decouple from the gate of the cascode transistor of the input branch during a steady-state operating mode of the cascode current mirror circuit following the transient operating mode. [8] Cascode current mirror circuit according to claim 6, wherein: the start-up circuit comprises a start-up transistor having a gate coupled to the input of the input branch, a source coupled to the gate of the cascode transistor of the input branch, and a drain coupled either to the supply voltage or to a reference ground. [9] Cascode current mirror circuit according to claim 8, wherein: the input branch is configured to receive an input current at the input of the input branch, and the input of the input branch is coupled to a gate of a main transistor of the input branch. [10] Cascode current mirror circuit according to claim 8, wherein: the input of the input branch is a drain of the cascode transistor of the input branch. [11] Cascode current mirror circuit according to claim 8, wherein: the input of the input branch is a drain of another cascode transistor of the input branch. [12] A cascode current mirror circuit according to claim 1, wherein: the input branch is configured to receive an input current at an input of the input branch, and the input of the input branch is coupled to a gate of a main transistor of the input branch. [13] A cascode current mirror circuit according to claim 12, wherein: a voltage at the input of the input branch is equal to a gate-source voltage of the main transistor of the input branch. [14] A cascode current mirror circuit according to claim 12, wherein: a headroom voltage for the operation of the input branch, which is defined by a minimum voltage at the input of the input branch, is equal to a gate-source voltage of the main transistor of the input branch. [15] A cascode current mirror circuit according to claim 14, wherein: the headroom voltage is about 0.6 volts. [16] A cascode current mirror circuit according to claim 12, wherein: the input of the input branch is a drain of the cascode transistor of the input branch. [17] A cascode current mirror circuit according to claim 12, wherein: the input of the input branch is a drain of an additional cascode transistor of the input branch. [18] A cascode current mirror circuit according to claim 17, wherein: the feedback block is further configured to generate an additional gate voltage for the additional cascode transistor of the input branch based on the intermediate current. [19] A cascode current mirror circuit according to claim 18, wherein: the feedback block further comprises an additional diode-connected transistor connected to a gate of the additional cascode transistor, and the feedback current mirror is configured to generate an additional mirrored intermediate current for conduction through the additional transistor connected as a diode. [20] A cascode current mirror circuit according to claim 18, wherein: the feedback block further comprises an additional transistor connected to a gate of the additional cascode transistor, and the additional transistor is connected in series with the transistor connected as a diode to conduct the mirrored intermediate current. [21] A cascode current mirror circuit according to claim 17, further comprising: a starting circuit connected between an input of the input branch and respective gates of the cascode and additional cascode transistors of the input branch are connected at least during a portion of a transient operating mode of the cascode current mirror circuit immediately following a start-up of the cascode current mirror, wherein the start-up circuit is configured to supply the gate voltage and the additional gate voltage to the cascode transistors during said portion of the transient operating mode. [22] A cascode current mirror circuit according to claim 21, wherein: the start-up circuit is configured to decouple from the respective gates of the cascode transistors of the input branch during a steady-state operating mode of the cascode current mirror circuit following the transient operating mode. [23] Cascode current mirror circuit according to claim 2, wherein: the feedback current mirror comprises a feedback input branch configured to receive the intermediate current and a feedback output branch configured to generate the mirrored intermediate branch, and a polarity of the feedback current mirror, as defined by a polarity of transistors of the feedback input branch and the feedback output branch, is opposite to a polarity of the cascode current mirror circuit, as defined by a polarity of transistors of the input branch and the intermediate output branch. [24] A cascode current mirror circuit according to claim 23, wherein: a stack height of the first and second cascode stacks of transistors is the same as a stack height of the respective cascode stacks of transistors of the feedback input and output branches. [25] A cascode current mirror circuit according to claim 23, wherein: a stack height of the first and second cascode stacks of transistors differs from a stack height of the respective cascode stacks of transistors of the feedback input and output branches. [26] A cascode current mirror circuit according to claim 23, wherein: the feedback input branch and the feedback output branch each consist of a single transistor. [27] A cascode current mirror circuit according to claim 23, further comprising: a starting circuit connected between an input of the input branch and respective gates of cascode transistors of the input branch, including the cascode transistor, are switched on at least during a part of a transient operating mode of the cascode current mirror circuit immediately following a start-up of the cascode current mirror, and an additional start-up circuit connected between an input of the feedback input branch and respective gates of cascode transistors of the feedback input branch at least during a part of the transient operating mode, wherein the start-up circuit is configured to supply appropriate gate voltages to the cascode transistors of the input branch during said portion of the transition operating mode, and the additional start-up circuit is configured to supply corresponding gate voltages to the cascode transistors of the feedback input branch during said portion of the transient operating mode. [28] A cascode current mirror circuit according to claim 23, further comprising: an output current stage with complementary output branches for outputting a sink and a source current, where a first output branch of the complementary output branches mirrors an input current onto the input branch and a second output branch of the complementary output branches mirrors an input current onto the feedback input branch. [29] Cascode current mirror circuit, comprising: a main cascode current mirror with start-up assistance circuitry configured to receive an input current and generate a corresponding mirrored current therefrom, a feedback cascode current mirror with start-up aid circuit that is the dual of the main cascode current mirror with start-up aid circuit, the feedback cascode current mirror with start-up aid circuit configured to receive the mirrored current and generate therefrom a feedback current that is used to generate a gate voltage for a cascode transistor of the main cascode current mirror with start-up aid circuit. [30] A method of operating a cascode current mirror with low headroom voltage, the method comprising: i) providing a cascode current mirror with an input branch and an intermediate output branch, ii) coupling an input current to the input branch to a gate of a main transistor of the input branch, iii) coupling a start-up aid circuit between the gate of the main transistor and a gate of a cascode transistor of the input branch, and iv) on the basis of steps ii) and iii), generating a gate voltage for the gate of the cascode transistor of the input branch during a transient mode of operation immediately following the switching on of the cascode current mirror. [31] The method of claim 30, further comprising: v) based on steps ii) and iv), conducting a current through the input branch and mirroring a corresponding current through the intermediate branch, thereby generating a mirrored intermediate current, and vi) generating a gate voltage at the gate of the cascode transistor of the input branch via the mirrored intermediate current during a steady-state operating mode following the transient operating mode.

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