Rear contacts for stacked field-effect transistors

Abstract

Embodiments of a semiconductor device and a method of fabrication are disclosed. The device includes a first gate having an upper FET disposed over a lower FET and in electrical contact with an upper source / drain epitaxial (S / D-Epi) layer and a back-end-of-line (BEOL) interconnect. The device also includes the lower FET. The lower FET is in electrical contact with a lower S / D-Epi layer. Furthermore, a shallow backside contact is in electrical contact with the lower S / D-Epi layer. Furthermore, the device includes a deep via in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the lower S / D-Epi layer.

Description

BACKGROUND

[0001] The present disclosure relates to backside contacts, in particular backside contacts for stacked field effect transistor (FET) semiconductor devices.

[0002] Semiconductor devices (devices) can be used in computer processors, computer memories, and the like. These devices include transistors, for example, field-effect transistors (FETs), which enable the processing and data storage of a computer processor and memory by controlling the current flow from source to drain. The FET controls the current flow using an electric field. Some semiconductor devices include stacked FETs, i.e., two layers, each layer having metal wiring and contacts to the front and back of the device.

[0003] The term "front" refers to the back-end-of-line (BEOL) connection, which includes signal wiring for the semiconductor device. The signal wiring may include the logic circuitry for the device. With respect to the back, the term specifically refers to the back connection, which may include the wiring for the device's power supply (i.e., Vss / Vdd).

[0004] Semiconductor devices are manufactured on wafers. Accordingly, when explaining the manufacture of wafers with semiconductor devices, it may be useful to describe the position of elements of the wafer using reference points. In particular, reference points are provided on the back and front sides to describe the relative positions of certain elements of the wafer. For example, the back side is located "below" the front side. Additionally, the wafers include a middle of line (MOL) that has wiring and contacts. In these descriptions, the BEOL (front side) connection is located above the top layer of FETs, which is located above the MOL, which is located above the bottom layer of FETs, which is located above the back side connection. When references to relative positions in this description (e.g.However, the terms used (e.g., above, below, underneath, to the left of, etc.) are merely examples and do not represent a limitation with regard to any particular arrangement described.

[0005] As mentioned earlier, FETs can be stacked in upper and lower layers. Accordingly, the upper layer of stacked FETs is arranged between the BEOL and the lower source / drain (S / D), which is the S / D of the FET in the lower layer. As such, the upper FET layer blocks the potential path for wiring between the lower S / D and the BEOL. Furthermore, using a back-side contact for wiring may result in a short circuit to the back-side Vss / Vdd. Therefore, routing wiring between the lower S / D and the BEOL's signal wiring can be difficult. SUMMARY

[0006] Embodiments for a semiconductor device are disclosed. The device includes a first gate stack having an upper FET disposed over a lower FET and in electrical contact with an upper source / drain epitaxial (S / D-Epi) layer and a back-end-of-line (BEOL) interconnect. The device further includes the lower FET. The lower FET is in electrical contact with a lower S / D-Epi layer. Furthermore, a shallow backside contact is in electrical contact with the lower S / D-Epi layer. Furthermore, the device includes a deep via in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the lower S / D-Epi layer.

[0007] Embodiments of a method for manufacturing a semiconductor device are disclosed. The method includes forming a first backside contact placeholder by forming a first recess below a first lower source / drain epitaxial (S / D-Epi) region of a first gate stack having a first upper S / D-Epi layer disposed above the first lower S / D-Epi layer. The method further includes depositing a sacrificial dielectric material in the first recess. Furthermore, the method includes forming a first gate cutout between the first gate stack and a second gate stack. Furthermore, the method includes filling the first gate cutout with a two-layer dielectric fill.The method additionally comprises forming a first deep via through an inner dielectric of the two-layer dielectric fill, the first deep via in contact with the back contact placeholder. The method further comprises removing the first back contact placeholder. Furthermore, the method comprises forming a shallow back contact by creating a first deep back contact by filling an area previously occupied by the removed back contact placeholder with a conductive metal in electrical contact with the first deep via and the first lower S / D, recessing the first deep back contact, and forming a back-end-of-line (BEOL) connection in electrical contact with the first deep via.The flat backside contact does not short to a backside power rail (BSPR).

[0008] Further aspects of the present disclosure relate to computer program products having functionality similar to the functionality discussed above with respect to the methods implemented on a computer. This summary is not intended to illustrate every aspect of every implementation and / or every embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings included in this application are incorporated in and constitute a part of the specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings are intended only to illustrate certain embodiments and are not limitative of the disclosure. Fig. 1 shows a block diagram of an example computing environment according to some embodiments of the present disclosure. Fig. 2A shows a top view of an exemplary semiconductor device according to some embodiments of the present disclosure. Fig. 2B shows vertical cross-sectional views of the exemplary semiconductor device according to some embodiments of the present disclosure. Fig. 3A and Fig. 3B illustrate portions of a process flow diagram of a method of manufacturing an exemplary semiconductor device according to some embodiments of the present disclosure. Fig. 4 shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D illustrate example manufacturing states of an example semiconductor device during manufacture according to some embodiments of the present disclosure. Fig. 5E shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5F illustrates an exemplary manufacturing state of an exemplary semiconductor device during manufacture in accordance with some embodiments of the present disclosure. Fig. 5G shows a block diagram of a top view of an example semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5H illustrates an exemplary manufacturing state of an exemplary semiconductor device during manufacture in accordance with some embodiments of the present disclosure. Fig. 5I shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5J illustrates an exemplary manufacturing state of an exemplary semiconductor device during manufacture in accordance with some embodiments of the present disclosure. Fig. 5K shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5L illustrates an exemplary manufacturing state of an exemplary semiconductor device during manufacture in accordance with some embodiments of the present disclosure. Fig. 5M shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5N, Fig. 50, Fig. 5P, Fig. 5Q, Fig. 5R, Fig. 5S illustrate example manufacturing states of an example semiconductor device during manufacture according to some embodiments of the present disclosure. Fig. 5T shows a block diagram of a top view of an exemplary semiconductor device during manufacturing according to some embodiments of the present disclosure. Fig. 5U, Fig. 5V, Fig. 5W illustrate example manufacturing states of an example semiconductor device during manufacture in accordance with some embodiments of the present disclosure.

[0010] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail. It should be understood, however, that the present disclosure is not intended to limit the present disclosure to the described embodiments. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. DETAILED DESCRIPTION

[0011] As previously mentioned, wiring overload of a stacked FET device can be reduced with an embedded power rail (BPR) and a backside power distribution network (BSPDN) in the backside interconnect. However, wiring connections between the bottom S / D of stacked FETs and the signal wiring in the BEOL can be difficult.

[0012] Accordingly, some embodiments of the present disclosure may fabricate a stacked FET semiconductor device having wiring between the bottom S / D epitaxies (Epis) and the signal wiring of the BEOL. Such embodiments may include gate cutout regions filled with bilayer dielectrics located between top and bottom stacked FET cells. Furthermore, such embodiments may include at least one deep via formed through an internal dielectric fill. This deep via is connected to a shallow backside contact wired to a bottom S / D. Furthermore, the reduced depth of the shallow backside contact may prevent shorting to the backside power rail.Furthermore, such embodiments include a backside contact with a greater height compared to a flat backside contact that connects a lower S / D-Epi layer to a BPR. Furthermore, such embodiments may include a deep via connecting an upper S / D-Epi layer to the BPR. Thus, such embodiments may provide a stacked FET semiconductor device having interconnection between the lower S / D-Epi layer and the BEOL, as well as between the upper S / D-Epi layer and the backside.

[0013] Fig. 1 shows a block diagram of an exemplary computing environment 100 according to some embodiments of the present disclosure. Various aspects of the present disclosure are described by descriptive text, flowcharts, computer system block diagrams, and / or machine logic block diagrams included in computer program product (CPP) embodiments. With respect to flowcharts, depending on the technology used, operations may be performed in a different order than that presented in a particular flowchart. For example, again depending on the technology used, two operations presented in consecutive blocks of a flowchart may be performed in reverse order, as a single integrated step, concurrently, or in a manner that at least partially overlaps in time.

[0014] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in the present disclosure to describe any set of one or more storage media (also called "media") collectively included in a set of one or more storage units, collectively comprising machine-readable code corresponding to instructions and / or data for performing computer operations specified in a particular claim for a CPP. A "storage unit" is any physical device capable of retaining and storing instructions for use by a computer processor.Without limitation, the computer-readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some common types of storage devices that comprise these media include: floppy disk (floppy disk), hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), DVD (digital versatile disc), memory stick, floppy disk, mechanically encoded devices (e.g., punched cards or pits / ridges formed in a major surface of a disc), or any suitable combination of the foregoing.A computer-readable storage medium, as used in the present disclosure, is not intended to be understood as storage in the form of transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses traversing an optical fiber cable, electrical signals transmitted through a wire, and / or other transmission media. As one skilled in the art will understand, data is typically moved at certain times during the normal operation of a storage device, for example, during access, defragmentation, or garbage collection, but this does not render the storage device transient because the data is non-volatile while stored.

[0015] The computing environment 100 includes an example of an environment for executing at least a portion of the computer code required to perform the inventive methods, for example, the semiconductor device manufacturing management 150. Furthermore, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remotely located server 104, a public cloud 105, and a private cloud 106.In this embodiment, the computer 101 comprises a processor set 110 (including, among other things, a processing circuit 120 and a cache 121), a data transmission fabric 111, a volatile memory 112, a persistent memory 113 (including, among other things, an operating system 122 and a semiconductor device manufacturing management 150, as identified above), a set of peripheral devices 114 (including, among other things, a set of user interface (UI) devices 123, a memory 124, and a set of Internet of Things (IoT) sensors 125), and a network module 115. The remote server 104 comprises a remote database 130. The public cloud 105 comprises a gateway 140, a cloud orchestration module 141, a set of physical host machines 142, a set of virtual machines 143, and a set of containers 144.

[0016] The COMPUTER 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or developed in the future that can execute a program, access a network, or submit a search query to a database, for example, to the remotely located database 130. As is well known in the art of computer technology, the performance of a method implemented on a computer may be distributed across multiple computers and / or multiple locations, depending on the technology. In this illustration of the computing environment 100, the focus of the detailed explanation is on a single computer, in particular computer 101, in order to keep the illustration as simple as possible. Computer 101 may be located in a cloud, even if it is in Fig. 1 is not shown in a cloud. On the other hand, it is not necessary for the computer 101 to be in a cloud unless explicitly indicated.

[0017] Processor set 110 includes one or more computer processors of any type currently known or developed in the future. Processing circuitry 120 may be distributed across multiple packages, for example, multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores executing on processor set 110. Cache memories are typically organized into multiple levels depending on their relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor set may be located off-chip.In some computing environments, the processor set 110 may be configured to work with qubits and perform computing with a quantum computer.

[0018] Computer-readable program instructions are typically loaded onto computer 101 to cause a series of functional steps to be executed by processor set 110 of computer 101, thereby effecting a computer-implemented method, such that the so-executed instructions instantiate the methods specified in flowcharts and / or narrative descriptions of computer-implemented methods included in this document (collectively, "the inventive methods"). These computer-readable program instructions are stored in various types of computer-readable storage media, for example, in cache 121 and the other storage media discussed below. Processor set 110 accesses the program instructions and associated data to control and regulate the execution of the inventive methods.In the data processing environment 100, at least some of the instructions for performing the inventive methods in the semiconductor device manufacturing management 150 may be stored in the persistent storage 113.

[0019] The data transmission structure 111 is the signal transmission path over which the various components of the computer 101 can exchange data with each other. Typically, this data transmission structure consists of switching units and electrically conductive paths, for example, the switching units and electrically conductive paths that make up buses, bridges, physical input / output ports, and the like. Other types of signal transmission paths may also be used, for example, fiber optic data transmission paths and / or wireless data transmission paths.

[0020] Volatile memory 112 is any type of volatile memory now known or developed in the future. Examples include dynamic random access memory (RAM) or static random access memory. Typically, volatile memory 112 is characterized as random access, but this is not required unless explicitly stated. In computer 101, volatile memory 112 is located in a single housing and is integrated with computer 101, but alternatively or additionally, volatile memory may be distributed across multiple housings and / or external to computer 101.

[0021] Persistent storage 113 is any form of non-volatile computer memory currently known or developed in the future. The non-volatility of this memory means that the stored data is retained regardless of whether power is directly applied to the computer 101 and / or persistent storage 113. Persistent storage 113 may be read-only memory (ROM), but typically at least a portion of the persistent storage allows data to be written, erased, and rewritten. Known forms of persistent storage include magnetic disks and solid-state media. Operating system 122 may take various forms, including various well-known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that utilize a kernel.The code contained in block 150 typically comprises at least a portion of the computer code required to carry out the methods of the invention.

[0022] The set of peripheral units 114 includes the set of peripheral units of the computer 101. Data transmission connections between the peripheral units and the other components of the computer 101 can be implemented in various ways, for example, as Bluetooth connections, near-field communication (NFC) connections, wired connections (e.g., Universal Serial Bus (USB) cables), plug-in connections (e.g., Secure Digital (SD) cards), connections via local area networks, and even connections via wide area networks such as the Internet. In various embodiments, the set of UI interface units 123 can include components such as a display, a speaker, a microphone, wearable units (e.g., glasses and smartwatches), a keyboard, a mouse, a printer, a touchpad, game controllers, and haptic units.The memory 124 is external storage, for example, an external hard drive, or insertable storage, for example, an SD card. Memory 124 may be persistent and / or volatile. In some embodiments, the memory 124 may take the form of a quantum computer memory unit for storing data in the form of qubits. In embodiments where the computer 101 requires a large amount of storage space (for example, when the computer 101 locally stores and manages a large database), this storage space may be provided by peripheral storage units designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The set of IoT sensors 125 consists of sensors that can be used in Internet of Things applications.For example, one sensor may be a thermometer and another may be a motion detector.

[0023] The network module 115 is a collection of computer software, computer hardware, and computer firmware that enables the computer 101 to communicate with other computers over a wide area network 102. The network module 115 may include hardware, such as modems or Wi-Fi signal transmitters and receivers, software for packetizing and / or depacketizing data for transmission over a data transmission network, and / or web browser software for exchanging data over the Internet. In some embodiments, network control functions and network forwarding functions of the network module 115 are executed on the same physical hardware device.In other embodiments (e.g., embodiments using Software-Defined Networking (SDN)), the control functions and forwarding functions of network module 115 are executed on physically separate units, such that the control functions manage multiple different network hardware units. Computer-readable program instructions for performing the inventive methods can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0024] WAN 102 is a wide area network (e.g., the Internet) that can exchange computer data over non-local distances using any computer data exchange technology now known or yet to be developed. In some embodiments, WAN 102 may be replaced and / or supplemented by local area networks (LANs) that are used to exchange data between devices located within a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, fiber optic transmission lines, wireless transmissions, routers, firewalls, switching devices, gateway computers, and edge servers.

[0025] The end user device (EUD) 103 is a computer system used and controlled by an end user (for example, a customer of a company operating the computer 101) and may be in any of the forms discussed above in connection with the computer 101. The EUD 103 typically receives helpful and useful data from the operations of the computer 101. For example, in a hypothetical case where the computer 101 is configured to provide a recommendation to an end user, that recommendation would typically be transmitted from the network module 115 of the computer 101 to the EUD 103 over the WAN 102. In this way, the EUD 103 can display or otherwise present the recommendation to an end user. In some embodiments, the EUD 103 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, and so on.

[0026] The remote server 104 is a computer system that provides at least some data and / or functionality to the computer 101. The remote server 104 may be controlled and used by the same entity that operates the computer 101. The remote server 104 represents the machine(s) that collect and store helpful and useful data for use by other computers, such as the computer 101. For example, in a hypothetical case where the computer 101 is configured and programmed to provide a recommendation based on historical data, this historical data could be provided to the computer 101 from the remote database 130 of the remote server 104.

[0027] The PUBLIC CLOUD 105 is a computer system available for use by multiple entities, providing on-demand availability of computer system resources and / or other computer functions, particularly data storage (cloud storage) and computing power, without direct, active management by the user. Cloud computing typically utilizes shared resource use to achieve consistency and economies of scale. The direct and active management of the computing resources of the public cloud 105 is performed by the computer hardware and / or software of the cloud orchestration module 141.The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that comprise the computers of the set of physical host machines 142, which represents and / or is available to the public cloud 105. The virtual computing environments (VCEs) typically take the form of virtual machines from the set of virtual machines 143 and / or containers from the set of containers 144. It is understood that these VCEs can be stored as images and transferred between each other and between the various physical machine hosts, either as images or after the VCE has been instantiated.The cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. The gateway 140 is a collection of computer software, hardware, and firmware that enables the public cloud 105 to exchange data over the WAN 102.

[0028] Some further explanation of virtualized computing environments (VCEs) is now provided. VCEs can be stored as "images." A new active instance of the VCE can be instantiated from the image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of the operating system where the kernel allows the existence of multiple isolated user-space instances, called containers. These isolated user-space instances typically behave like real computers from the perspective of the programs running within them. A computer program running on an ordinary operating system can use all of that computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware features.However, programs running inside a container can only use the contents of the container and the units assigned to the container, a feature known as containerization.

[0029] The PRIVATE CLOUD 106 is similar to the PUBLIC CLOUD 105, except that the computing resources are available to only a single enterprise. While the private cloud 106 is illustrated as communicating with the WAN 102, in other embodiments, a private cloud may be completely disconnected from the internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private cloud, community cloud, or public cloud), often implemented by different vendors. Each of these multiple clouds remains a separate and distinct entity, but the larger hybrid cloud architecture is interconnected by standardized or proprietary technology that enables orchestration, management, and / or data / application portability between the multiple constituent clouds.In this embodiment, the public cloud 105 and the private cloud 106 are both part of a larger hybrid cloud.

[0030] Fig. 2A shows a top view 250 of an exemplary semiconductor device 200 according to some embodiments of the present disclosure. The top view 250A includes four device regions 252-1, 252-2, 252-3, 252-4 (collectively referred to as device regions 252) and three gate regions 254-1, 254-2, 254-3 (collectively referred to as gate regions 254). The device regions 252 represent the positions of the channels and S / D epis of the exemplary semiconductor device 200. The gate regions 254 include a portion of the intersecting device regions 252 that include a stacked FET. Furthermore, the top view 250A includes section lines X, Y1, and Y2, which correspond to cross-sectional views (described below) of the exemplary semiconductor device 200.

[0031] Fig. 2B shows vertical cross-sectional views of the exemplary semiconductor device 200 according to some embodiments of the present disclosure. As shown, the X-section line corresponds to view X, which illustrates a cross-section of the device region 252-1 across the gate regions 254-1, 254-2, 254-3. Furthermore, view Y1 illustrates a cross-section of the gate region 254-1 across the device regions 252-1, 252-2, and view Y2 illustrates a cross-section of the space between the gate regions 254-2, 254-3 (i.e., along the device regions 252-1, 252-2, 252-3, 252-4).

[0032] Furthermore, the views have features that are similar in all views. For example, views X, Y1, and Y2 include, on the front side, a carrier wafer 202, the BEOL 204, and the ILD 206; and a backside ILD layer 216, the BSPR 222, and the BSPDN 224. The carrier wafer 202 may represent a silicon (Si) wafer layer. Furthermore, the BEOL 204 may consist of multiple layers of metal lines (including signal wiring and power rails) and vias (e.g., copper (Cu)-based interconnects). Regarding the backside, the backside ILD layer 216 may be made of materials such as SiO2, SiOC, SiN, low-k oxide, etc. The backside ILD layer 216 isolates the backside contacts from each other and isolates the device layer from the BSPR 222. The BSPR 222 includes the source and drain power rails on the backside.The backside ILD layer 216 is a backside interlayer dielectric (ILD) deposited from the backside of the wafer. Accordingly, the BSPR 222 and the BSPDN 224 can power the example semiconductor device 200 when connected to a power source. The BSPDN 224 includes insulators (e.g., backside ILD) and backside interconnects (e.g., backside metal wires and backside metal vias).

[0033] Since view X depicts device region 252-1 across three gate regions 254, view X includes three stacks of stacked FETs 212 (e.g., gate stacks), the two stacks of S / D epis 214 between these three gate stacks, contacts, and vias. The gate stacks include, from top to bottom, the upper FET 212-T and the lower FET 212-B (collectively, stacked FETs 212). The ILD 206 may be formed of dielectric materials such as SiO2, SiN, SiBCN, SiOCN, SiOC, SiC, and the like. With respect to the gate stacks, the upper and lower FETs are separated from each other by a middle dielectric isolation (MDI) layer 212-0M. Similarly, the bottom FET 212-B is separated from the backside ILD layer 216 by a bottom dielectric isolation (BDI) layer 212-0B.

[0034] Furthermore, the stacked FETs 212 may represent transistors that include spacers 212-1, nanosheet channels 212-2, internal spacers 212-3, high-k metal gates (HK / MG) 212-4, and an MDI layer 212-0M and a BDI layer 212-0B. The spacers 212-1 may include layers of dielectric material deposited and etched back to provide a distance between the HK / MGs 212-4 and the contacts 208-A. Furthermore, the nanosheet channels 212-2 may include nanosheets of a semiconductor material that may be conductive in an "on" state or highly resistive in an "off" state. The conductivity of the nanosheet channels 212-2 can be controlled by the HK / MGs 212-4. Furthermore, the inner spacers 212-3 can be a dielectric material that provides a distance between the HK / MGs 212-4 and the S / D epis 214.In addition, the HK / MGs 212-4 may include a transistor gate electrode and a gate dielectric made of a high-k material (e.g., k = 7 or more). The materials for the HK / MGs 212-4 may vary depending on the type of device being built (e.g., N-type or P-type FET).

[0035] Furthermore, view X includes two stacks of S / D-Epi 214 (upper S / D-Epi layer 214-T and lower S / D-Epi layer 214-B). The S / D-Epi 214 may be heavily doped epitaxial layers, for example, boron-doped SiGe for p-type field-effect transistors (PFETs) or phosphorus-doped Si for n-type FETs (NFETs). Furthermore, the S / D-Epi stacks include, from top to bottom, contact 208-A, the upper S / D-Epi layer 214-T, the ILD 206 (which isolates the upper and lower S / D-Epi layers from each other), and the lower S / D-Epi layer 214-B. Furthermore, the S / D epi stacks below the lower S / D epi layer 214-B differ from each other. In particular, the left S / D epi stack (between gate regions 254-1 and 254-2) also includes a flat backside contact 208-S, which is part of an interconnect (not shown) between the lower S / D epi layer 214-B and the BEOL 204.According to some embodiments of the present disclosure, the shallow backside contact 208-S allows the exemplary semiconductor device 200 to be connected to this interconnect without risk of shorting to the BSPR 222. In contrast, the right S / D-Epi stack (between the gate regions 254-2 and 254-3), the lower S / D-Epi layer 214-B, is connected to the BSPR 222 via a deep backside contact 208-D.

[0036] As previously mentioned, view Y1 represents a cross-section of the gate region 254-1 across the device regions 252-1, 252-2. Thus, view Y1 represents the four FETs (i.e., two gate stacks) as well as the contacts and vias on and between these device regions. The Y1 view structure includes (from top to bottom) a contact 208-B, the HK / MG 212-4, the nanosheet channels 212-2, and an MDI 212-0M at the bottom of the upper FET 212-T, and a BDI layer 212-0B at the bottom of the lower FET 212-B. Furthermore, the Y1 view structure includes an STI layer 218. Each of the gate stacks is located above and isolated from a BSPR 222-VSS.

[0037] Between the gate stacks, view Y1 includes the backside ILD layer 216 on either side of a deep via 210. The deep via 210 provides a conductive path (shown in view Y2) between an upper S / D epi layer 214-T and the BSPR 222-VDD. Furthermore, the backside ILD layer 216 isolates the deep via 210 from the gate stacks.

[0038] As previously stated, view Y2 illustrates a cross-section of the exemplary semiconductor device 200 of the device regions 252-1, 252-2, 252-3, 252-4 in the space located between the gate regions 254-2, 254-3. In particular, view Y2 includes the S / D Epis 214, contacts, and vias between the gates (i.e., the stacked FETs) at these gate regions. Accordingly, view Y2 illustrates a S / D Epi cross-sectional view of the four S / D Epi stacks (i.e., the top and bottom S / D Epis), contacts, and vias located between the 16 stacked FETs 212 (eight stacks, four along each of the gate regions 254-2, 254-3). The S / D epi stacks of view Y2 are similar to the S / D epi stacks of views X and Y1.From left to right, the S / D epi stacks represent the S / D epis in device regions 252-1, 252-2, 252-3, and 252-4 and include a deep back contact 208-D, a shallow back contact 208-S, a deep back contact 208-D, and a deep front contact 208-DF. The deep front contact 208-DF shorts the lower S / D epi layer 214-B and the upper S / D epi layer 214-T.

[0039] Furthermore, view Y2 between the S / D epi stacks in device regions 252-1 and 252-2 includes a pillar of a first dielectric material 217-1 and a second dielectric material 217-2, an STI layer 218, and a backside ILD layer 216. Furthermore, view Y2 between the S / D epi stacks in device regions 252-2 and 252-3 includes a deep via 210 in contact with the BEOL 204 and the flat backside contact 208-S. Furthermore, the backside ILD layer 216 on both sides of the deep via 210 isolates the deep via 210 from the adjacent S / D epis 214. The backside ILD layer 216 also contacts the STI layer 218. In this way, the exemplary semiconductor device 200 provides a conductive path between the signal wiring in the BEOL 204 and the lower S / D epi layer for a lower FET in a stacked FET device.

[0040] Furthermore, view Y2 includes a deep via 210 between the S / D-Epi stacks in device regions 252-3 and 252-4, which contacts contact 208-A at the top of the S / D-Epi stack and the BSPR 222-VDD. Furthermore, the backside ILD layer 216 on both sides of the deep via 210 isolates the deep via 210 from the adjacent S / D-Epi stacks. In this way, the deep via 210 provides a conductive path from the top S / D-Epi layer 214T to the BSPR 222-VDD.

[0041] Fig. 3 (the Fig. 3A and Fig. 3B) shows a process flow diagram of a method 300 for manufacturing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, an exemplary semiconductor device manufacturing management, for example, the one described with respect to Fig. 1, perform the method 300. In this method, the semiconductor unit manufacturing management 150 may manufacture a semiconductor unit such as the one described with respect to Fig. 2. For clarity, the method 300 is described with respect to Fig. 4 and 5A to 5W, in which views of an exemplary semiconductor device being manufactured are provided after each operation of the method 300. Furthermore, the Fig. 4 and Fig. The views illustrated in Figures 5A through 5W are merely examples of views that method 300 may generate. However, some practices of method 300 may generate other views.

[0042] At operation 302, semiconductor device manufacturing management 150 may instruct a manufacturing tool to form dummy gates. Forming dummy gates may include depositing sacrificial layers that serve as placeholders for gates. In particular, semiconductor device manufacturing management 150 may instruct a manufacturing tool to form a patterned nanosheet stack over an insulating layer. Patterning nanosheets may include forming a patterned nanosheet stack over an underlying layer. In particular, the manufacturing tool may alternately deposit nanosheet layers of sacrificial nanosheet layers and nanosheet channel layers. The sacrificial nanosheet layers may be made of silicon germanium (e.g., SiGe). Furthermore, the channel layers may be made of Si.Furthermore, forming the dummy gate may include depositing material that forms the dummy gate and the gate hard mask over the patterned nanosheet stack. For clarity, operation 302 is described with reference to FIG. Fig. 4 and Fig. 5A.

[0043] Fig. 4 shows a block diagram of a top view 450 of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. In the top view 450, the exemplary semiconductor device 400 includes the device regions 452-1, 452-2, 452-3, 452-4 (collectively referred to as device regions 452) and the gate regions 454-1, 454-2, 454-3 (collectively referred to as gate regions 454). The device regions 452 represent the positions of the channels and S / D epis to be manufactured. Similarly, the gate regions 454 indicate the positions of the gates to be manufactured, particularly at the interface between the device region 452 and the gate region 454. The top view 450 is similar to the top view 250A described with respect to FIG. Fig. 2A. Accordingly, the top view 450 includes the section lines X, Y1, and Y2, which correspond to the cross-sectional views described below with respect to Fig. 5A to 5D.

[0044] As described below, Fig. 5A to 5W illustrate manufacturing states of an exemplary semiconductor device during manufacture. Specifically, these figures include several elements, each labeled for explanatory purposes. However, due to the number of elements, providing reference numbers for each element would make the figure cluttered and difficult to understand. Therefore, the following steps are taken to limit the reuse of reference numbers in the figures. For example, these figures include multiple views of the same device. Therefore, the views share some common elements. Therefore, to limit reference numbers, a reference number is placed only in the leftmost view of the element. As such, like elements (without reference numbers) are indicated by: the same vertical position (as shown) and the same diamond pattern (or lack thereof). Furthermore, an element added to a figure will have a reference number.However, subsequent figures may not contain the reference number, even if the element is still present. For example, elements contained in . Fig. 5A and are therefore marked, in Fig. 5B may not be labeled. While these steps are useful for making the figures easier to understand, there are some exceptions to the labeling described above in the interest of clarity.

[0045] Fig. 5A shows an exemplary manufacturing state 500A of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The exemplary manufacturing state 500A may represent the state of the semiconductor device after the operation 302. The exemplary manufacturing state 500A includes views X, Y1, and Y2, which illustrate the Fig. 4 described intersection lines X, Y1, and Y2. Similar to the section with respect to Fig. 2B, the views of the example manufacturing stage 500A have features that are similar across all views. For example, views X, Y1, and Y2 each include a substrate 402-S (e.g., silicon (Si)), an etch stop layer 404, a silicon layer 402-1, and a patterned nanosheet stack 406. Furthermore, the nanosheet stack 406 includes the sacrificial layers 406-1, 406-2, which may be made of SiGe60 and SiGe30, respectively. Furthermore, the nanosheet stack 406 includes the nanosheet channels 406-3, which may be made of a semiconductor material such as Si.

[0046] Furthermore, views X and Y1 each include a dummy gate 407-DG and a gate hardmask 407-HM. The dummy gate may serve as a placeholder for the actual gate, which is manufactured in a different manufacturing state. The gate hardmask 407-HM may be a cap that facilitates the patterning of nanosheet stacks. The dummy gates 407-DG of view X may represent the positions of the gate regions 454-1, 454-2, 454-3 (from left to right, as shown) that are arranged with respect to Fig. 4 are described.

[0047] Furthermore, view Y1 includes two nanosheet stacks 406 representing device regions 452-1 and 452-2 along section line Y1. Furthermore, view Y1 includes an STI layer 408 in trenches between and on both sides of the two nanosheet stacks 406. STI layer 408 may be similar to STI layer 218, which may be Fig. 2 was described.

[0048] Furthermore, view Y2 includes four nanosheet stacks 406 representing device regions 452-1, 452-2, 452-3, 452-4 along section line Y2. Similar to view Y1, view Y2 includes STI layer 408 between and on both sides of nanosheet stacks 406. In this way, example manufacturing state 500A may represent a state of the semiconductor device under manufacture after performing operation 302.

[0049] With reference to Fig. 3A, at operation 304, semiconductor device manufacturing management 150 may instruct a manufacturing tool to perform the removal of the sacrificial layers; to form spacers, BDI, MDI, and internal spacers. The manufacturing tool removes the sacrificial layers 406-1, which may be comprised of a SiGe material such as SiGe60. Removing the SiGe60 layers may include etching the sacrificial layers 406-1 selectively to the Si nanosheet channels 406-3 and other surrounding materials.

[0050] Furthermore, forming the spacers may include conformal deposition of a dielectric and anisotropic reactive-ion etching (RIE) to remove the spacer material from horizontal surfaces. The spacers may be made of a dielectric material (e.g., SiN, SiBCN, SiOCN, SiOC, and the like). Furthermore, forming the BDI includes depositing a dielectric material in a region previously occupied by a sacrificial layer removed from the bottom of the nanosheet stack 406. Similarly, forming the MDI includes depositing a dielectric material in a region previously occupied by a sacrificial layer removed from the center of the nanosheet stack 406.

[0051] Furthermore, forming the inner spacers may include performing nanosheet deepening, SiGe notching, and forming inner spacers. In particular, performing nanosheet deepening may include etching back the nanosheet stacks (e.g., the sacrificial layer 406-2 and the nanosheet channels 406-3). Furthermore, the SiGe notching may include a mechanical process to remove portions of the sacrificial layer 406-2 to provide sufficient space for depositing material to form the inner spacers 412-2. Furthermore, the formation of inner spacers may include depositing dielectric material in the spaces created by the SiGe notching. For clarity, operation 304 will be described with respect to Fig. 5B.

[0052] Fig. 5B illustrates an exemplary manufacturing stage 500B of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500A, view X of the exemplary manufacturing stage 500B includes two trenches between the dummy gates 407-DG, thereby forming three nanosheet stacks 406. Furthermore, view X includes the BDI layer 406-0B and the MDI layer 406-0M in the areas previously occupied by the sacrificial layers 406-1, which have been removed. Furthermore, view X includes the spacers 412-1 on both sides of the dummy gates 407-DG and the gate hard masks 407-HM. Similar to view X, view Y1 includes BDI layer 406-0B and MDI layer 406-0M in the areas previously occupied by sacrificial layers 406-1, which were removed.In this way, the example manufacturing state 500B may represent a state of the semiconductor device under manufacture after performing operation 304.

[0053] With reference to Fig. 3A, at operation 306, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform patterning of placeholders. Performing patterning of placeholders may include applying the mask material (e.g., an organic planarization layer (OPL)) followed by conventional lithographic patterning. Furthermore, patterning of placeholders includes creating trenches that pass through the OPL and extend into the silicon layer 402-1 and the STI layer 408. For clarity, operation 306 is described with respect to Fig. 5C.

[0054] Fig. 5C illustrates an exemplary manufacturing state 500C of an exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500B, view X of the exemplary manufacturing state 500C further includes the trenches 414 and the OPL 416. As previously mentioned, the trenches pass through the OPL 416 and enter the silicon layer 402-1. In this way, the exemplary manufacturing state 500C may represent a state of the semiconductor device under manufacture after performing operation 306.

[0055] With reference to Fig. 3A, at operation 308, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to form the placeholders, perform S / D epi growth, form the ILD layer, remove the dummy gates and the sacrificial layer, and form the replacement HK / MGs. Forming the placeholder includes depositing a sacrificial material in the trenches 414 and deepening it to be flush with the BDI layer 406-0B, or forming a sacrificial placeholder 418 through a bottom-up deposition process, e.g., selective epitaxial growth. Furthermore, performing S / D epi growth includes growing semiconductor S / D epitaxy from exposed semiconductor surfaces (e.g., the nanosheet channels 406-3). Furthermore, forming the ILD layer includes performing an interlayer dielectric (ILD) deposition on the STI layer 408 and the grown S / D epis.Furthermore, forming the ILD layer includes performing chemical mechanical planarization (CMP), wherein material (e.g., material of the gate hard mask 407-HM, ILD layer 422) is removed to form a flat surface. To remove dummy gates, the manufacturing tool may selectively remove the dummy gates 407-DG with respect to the surrounding materials (e.g., ILD). Furthermore, removing the sacrificial layer 406-2 includes dissolving SiGe. To dissolving SiGe, the manufacturing tool may etch the sacrificial layers 406-2 (e.g., SiGe30) selectively with respect to the Si of the nanosheet channels 406-3 and other surrounding materials. Furthermore, forming the replacement gates includes depositing high-k metal gate material in the gaps created by removing the dummy gates 407-DG and the sacrificial layers 406-2. For clarity, operation 308 is described with reference to FIG. Fig. 5D described.

[0056] Fig. 5D illustrates an exemplary manufacturing stage 500D of an exemplary semiconductor device 400 during manufacturing in accordance with some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500C, views X and Y1 of the exemplary manufacturing stage 500D do not include the dummy gate 407-DG, the gate hard mask 407-HM, or the sacrificial layer 406-2. Furthermore, compared to the exemplary manufacturing stage 500C, view X includes three gate stacks and two intermediate S / D epi stacks. The gate stacks include the bottom FET 406-B, which includes (from bottom to top) the BDI layer 406-0B, the inner spacers 412-2, and alternating layers of the HK / MG 424 and the nanosheet channels 406-3. The upper FET 406-T includes the MDI layer 406-0M, the inner spacers 412-2, and alternating layers of the HK / MG 424 and the nanosheet channels 406-3.In addition, the S / D-Epi stacks (from bottom to top) include sacrificial placeholders 418, lower S / D-Epi layer 420-B, ILD layer 422, upper S / D-Epi layer 420-T, and ILD layer 422. In contrast to the three gate stacks of View X, View Y1 includes two gate stacks. These gate stacks include the elements of an upper FET 406-T and a lower FET 406-B. View Y2 includes four S / D-Epi stacks similar to the S / D-Epi stacks described with respect to View X. However, the second S / D-Epi stack from the left includes a placeholder that extends beyond the right edge of the overlying S / D-Epis. In this way, the sacrificial placeholder 418 enables the creation of a via that reaches a contact to be created instead of the sacrificial placeholder 418. Furthermore, the rightmost S / D epi stack does not include a sacrificial placeholder 418. In this way, . Fig. 5D illustrate a state of the semiconductor device under manufacture after operation 308.

[0057] With reference to Fig. 3A, at operation 310, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform ILD deposition and gate cutout patterning. Performing the ILD deposition includes depositing ILD material onto the semiconductor device to be manufactured. Furthermore, performing the gate cutout patterning includes overfilling the deposited ILD with a sacrificial material and removing the sacrificial material and the deposited ILD to create gate cutouts down to the STI layer 408 and between the device regions 452. For clarity, operation 310 is described with respect to Fig. 5E and Fig. 5F described in more detail.

[0058] Fig. 5E shows a block diagram of a top view 450E of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450E is similar to the top view 450 and further includes the gate cutouts 456-1, 456-2, 456-3 (collectively referred to as gate cutouts 456) between the device regions 454.

[0059] Fig. 5E shows a block diagram of an exemplary manufacturing state 500F of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500D, views X, Y1, and Y2 of the exemplary manufacturing state 500F further include additional ILD in the ILD layer 422 and the OPL 426. Furthermore, view Y1 further includes the gate cutout 456-1. Similarly, view Y2 further includes the gate cutouts 456-1, 456-2, 456-3. In this way, Fig. 5F illustrate a state of the semiconductor device under manufacture after operation 310.

[0060] With reference to Fig. 3A, at operation 312, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform a two-layer gate cutout fill. When performing the two-layer gate cutout fill, the OPL 426 is removed. Furthermore, performing the two-layer gate cutout fill includes lining the gate cutouts 456 with a first dielectric material and filling the lined gate cutouts with a second dielectric material that is different from the first dielectric material. For example, the first dielectric material may be silicon nitride (SiN) and the second dielectric material may be silicon oxide (SiO2). For clarity, operation 312 will be described with respect to Fig. 5G and Fig. 5H is described in more detail.

[0061] Fig. 5G shows a block diagram of a top view 450G of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450G is similar to the top view 450E, with the gate cutouts 456 further including the first dielectric material 430 and the second dielectric material 432.

[0062] Fig. 5H shows a block diagram of an exemplary manufacturing state 500H of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500F, views X, Y1, and Y2 of the exemplary manufacturing state 500H no longer include the OPL 426. Furthermore, views Y1 and Y2 include the first dielectric material 430 lining the gate cutouts 456 and the second dielectric material filling the gate cutouts 456. In this way, Fig. 5H illustrates the semiconductor device being manufactured after operation 312.

[0063] With reference to Fig. 3A, at operation 314, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform self-aligned patterning of deep vias. Performing self-aligned patterning of deep vias includes overfilling with a sacrificial material and creating deep trenches through the OPL 426, the second dielectric material 432, the STI layer 408, and either into the silicon layer 402-1 or to expose a sacrificial placeholder 418. For clarity, operation 314 is described with respect to Fig. 5I and Fig. 5J described in more detail.

[0064] Fig. 5I shows a block diagram of a top view 450I of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450I is similar to the top view 450G and further includes the deep trenches 458-1, 458-2, 458-3, 458-4 (collectively referred to as deep trenches 458).

[0065] Fig. 5J shows a block diagram of an exemplary manufacturing stage 500J of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500H, views X, Y1, and Y2 of the exemplary manufacturing stage 500J include the OPL 426 above the ILD layer 422. Furthermore, view Y1 includes the deep trench 458-1 located between two gate stacks. Furthermore, view Y2 of the exemplary manufacturing stage 500G includes a deep trench 458-3 (exposing the sacrificial placeholder 418) located between two gate stacks and a deep trench 458-4 (reaching down to the silicon layer 402-1) located between two S / D epi stacks. In this way, Fig. 5J illustrates the semiconductor device under manufacture after operation 314.

[0066] With reference to Fig. 3A, at operation 316, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform contact patterning. Performing contact patterning includes removing the OPL 426 and material from the ILD layer 422 to expose the upper S / D epis 420-T, HK / MGs 424, a lower S / D epi layer 420-B in the device region 452-3, and to create openings for deep vias. For clarity, operation 316 is described with respect to Fig. 5K and Fig. 5L is described in more detail.

[0067] Fig. 5K shows a block diagram of a top view 500K of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450K is similar to the top view 450I and further includes the front-side contact openings 434-OA, 434-OB (individually also referred to as S / D-Epi openings 434-OA and gate openings 434-OB).

[0068] Fig. 5L shows a block diagram of an exemplary manufacturing stage 500L of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500J, views X, Y1, and Y2 of the exemplary manufacturing stage 500L no longer include the OPL 426. Furthermore, view X includes the S / D contact openings 434-OA to the upper S / D epis 420-T. View Y1 further includes the gate openings 434-OB to the HK / MGs 424 of the upper FETs 406-T. In addition, view Y2 includes three S / D openings 434-OA to the tops of the respective upper S / D epis 420-T and a fourth S / D opening 434-OA to one side of both an upper S / D epi layer 420-T and a lower S / D epi layer 420-B in the device area 452-4.View Y2 also includes three 428-DO deep via openings: one is located near the center of view Y2; the second is located near the center of view Y2 and exposes sacrificial dummy 418; and the third is located to the right of the second deep via in view Y2. In this way, . Fig. 5L illustrates the semiconductor device under manufacture after operation 316.

[0069] With reference to Fig. 3A, the operation 316 shows a flow to a placeholder A. The placeholder A does not represent an operation of the method, but serves to Fig. 3A with the other operations of method 300 that are related to Fig. 3B are described in more detail.

[0070] Fig. Figure 3B shows a process flow diagram of operations 318 to 334 of method 300 according to some embodiments of the present disclosure. For clarity, these operations are described with respect to Fig. 5M to 5W described.

[0071] The process flow chart in Fig. 3B shows a flow from placeholder A to operation 318. As already mentioned, placeholder A does not represent an operation of method 300, but serves to Fig. 3A with operations 318-334 described below.

[0072] At operation 318, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform middle-of-line (MOL) metallization, form the BEOL, and perform carrier wafer bonding. Performing MOL metallization includes filling the front-side contact openings 434-OA, 434-OB with a conductive metal to create front-side contacts. Furthermore, performing the BEOL interconnect formation may include fabricating the elements of the BEOL interconnect 436, for example, multiple layers of Cu-based metallic lines and vias. Furthermore, the carrier wafer bonding may include bonding the carrier wafer 402-2 to the BEOL interconnect 436. For clarity, operation 318 will be described with respect to Fig. 5M and Fig. 5N is described in more detail.

[0073] Fig. 5M shows a block diagram of a top view 450M of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450M is similar to the top view 450K and further includes the front-side contacts 434-A, 434-B instead of the corresponding front-side contact openings 434-OA, 434-OB. For clarity, not all front-side contacts are labeled. Rather, the boxes indicating the front-side contacts 434-A, 434-B also represent similar contacts in similarly sized boxes. Here, the front-side contacts 434-A, 434-B are individually referred to as S / D contacts 434-A and gate contacts 434-B.

[0074] Fig. 5N shows a block diagram of an exemplary manufacturing stage 500N of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500L, views X, Y1, and Y2 of the exemplary manufacturing stage 500N further include a carrier wafer 402-2 and a BEOL connection 436. Furthermore, view X includes the S / D contacts 434-A on the upper S / D epis 420-T. View Y1 further includes the gate contacts 434-B to the HK / MGs 424. Furthermore, view Y1 includes a deep via 440-D into the silicon layer 402-1. View Y2 further includes three S / D contacts 434-A to the top of the respective upper S / D epis 420-T and a fourth S / D contact 434-A to both a side of an upper S / D epi layer 420-T and a lower S / D epi layer 420-B.Furthermore, view Y2 includes two deep vias 440-D between the device regions 452-2, 452-3, extending to the sacrificial placeholder 418. The second deep via 440-D extends downward to the silicon layer 402-1. In this way, . Fig. 5N represent the semiconductor device under manufacture after operation 318.

[0075] With reference to Fig. 3A, at operation 320, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform a wafer flip and a substrate removal. Performing the wafer flip may include reversing the vertical orientation of the semiconductor device being manufactured. By flipping the wafer, the substrate 402-S may thus be exposed for removal. Performing the substrate removal includes an etching process in which the substrate material is removed from the exposed surface down to the etch stop layer 404. For clarity, operation 320 is described with respect to Fig. 5O described in more detail.

[0076] Fig. 5O shows a block diagram of an exemplary manufacturing state 500O of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500N, views X, Y1, and Y2 of the exemplary manufacturing state 500O no longer include the substrate 402-S. In this way, Fig. 5O illustrates the semiconductor device being manufactured after operation 320.

[0077] With reference to Fig. 3A, at operation 322, semiconductor device manufacturing management 150 may instruct a manufacturing tool to remove etch stop layer 404 and the remaining silicon layer 402-1. Removing etch stop layer 404 and silicon layer 402-1 exposes the underlying sacrificial placeholders, BDI layer 406-0B, STI layer 408, and deep vias 440-D. For clarity, operation 322 is described with respect to Fig. 5P described in more detail.

[0078] Fig. 5P shows a block diagram of an exemplary manufacturing stage 500P of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500O, views X, Y1, and Y2 of the exemplary manufacturing stage 500P include neither the silicon layer 402-1 nor the etch stop layer 404. In view X1, removing these layers exposes the sacrificial placeholders 418 below the lower S / D epis 420-B. In view Y1, removing these layers exposes the STI layer 408, the BDI layer 406-0B, and the deep via 440-D. In view Y2, removing these layers exposes three sacrificial placeholders 418, the rightmost deep via 440-D, and the rightmost BDI layer 406-0B. In this way, Fig. 5P represents the semiconductor device being manufactured after operation 322.

[0079] With reference to Fig. 3A, at operation 324, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform a backside ILD deposition and a CMP. Performing the backside ILD deposition includes depositing ILD material on the surfaces exposed by removing the silicon layer and the etch stop layer. Performing the CMP includes creating a planar surface on the deposited ILD. For clarity, operation 324 is described with respect to Fig. 5Q is described in more detail.

[0080] Fig. 5Q shows a block diagram of an exemplary manufacturing state 500Q of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500P, views X, Y1, and Y2 of the exemplary manufacturing state 500Q further include the ILD layer 438. In this way, Fig. 5Q represents the semiconductor device being manufactured after operation 324.

[0081] With reference to Fig. 3A, at operation 326, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to remove the sacrificial placeholders 418. Removing the sacrificial placeholders 418 may include selective dry etching or wet etching processes. For clarity, operation 326 is described with respect to Fig. 5R is described in more detail.

[0082] Fig. 5R shows a block diagram of an exemplary manufacturing state 500R of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500Q, views X, Y1, and Y2 no longer include the sacrificial placeholders 418. In the remaining areas, the backside contact openings 442-O remain. In this way, Fig. 5R illustrates the semiconductor device being manufactured after operation 326.

[0083] With reference to Fig. 3A, at operation 328, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform backside contact metallization. Backside contact metallization may include depositing conductive metal material in the backside contact openings 442-O. In this way, some embodiments of the present disclosure may provide backside contact interconnects: the lower S / D epis 420-B and one of the deep vias 440-D to a backside interconnect, which will be described in more detail below. For clarity, operation 328 will be described with respect to Fig. 5S is described in more detail.

[0084] Fig. 5S shows a block diagram of an exemplary manufacturing state 500S of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500R, views X and Y2 of the exemplary manufacturing state 500S include deep backside contacts (BSCA) 442-D instead of the removed sacrificial placeholders 418. Furthermore, in views X and Y2, the deep backside contacts 442-D extend to the lower S / D epis 420-B. However, view Y1 remains unchanged. In this way, Fig. 5S represents the semiconductor device under manufacture after operation 328.

[0085] With reference to Fig. 3A, at operation 330, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to perform selective backside contact recessing. Selective backside contact recessing includes performing overfilling with a sacrificial material to form an OPL 426 and removing portions of the OPL 426. Furthermore, the selective backside contact recessing includes removing the metal from predetermined backside contacts 442-D to reduce the thickness. In this way, selective backside contact recessing may be useful to form shallow backside contacts, for example, the shallow backside contacts 208-S described with respect to Fig. 2. For clarity, operation 330 is described in relation to Fig. 5T and Fig. 5U is described in more detail.

[0086] Fig. 5T shows a block diagram of a top view 450T of the exemplary semiconductor device 400 during manufacturing according to some embodiments of the present disclosure. The top view 450T is similar to the top view 450M and further includes deep backside contacts 442-D and shallow backside contacts 442-S (collectively, backside contacts 442). For clarity, not all backside contacts are labeled. Rather, the boxes indicating the backside contacts 442 also represent similar backside contacts in similarly sized boxes.

[0087] Fig. 5U shows a block diagram of an exemplary manufacturing stage 500U of a semiconductor device according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500S, views X, Y1, and Y2 of the exemplary manufacturing stage 500U each include an OPL 426 with missing portions below the flat back contacts 442-S. Accordingly, view X further includes a flat back contact 442-S below the lower S / D epi layer 420-B, located between the gate regions 454-1 and 454-2. In contrast, view Y1 does not include any further changes. However, view Y2 further includes a flat back contact 442-S for the lower S / D epi layer 420-B of the device region 452-2. In this way, Fig. 5U represents the semiconductor device under manufacture after operation 330.

[0088] With reference to Fig. 3A, at operation 332, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to refill the backside ILD and perform a CMP. Refilling the backside ILD and the CMP include removing the remaining OPL 426, depositing an ILD layer, and performing a CMP on the deposited ILD layer. For clarity, operation 332 is described with respect to Fig. 5V described in more detail.

[0089] Fig. 5V shows a block diagram of an exemplary manufacturing state 500V of a semiconductor device according to some embodiments of the present disclosure. Compared to the exemplary manufacturing state 500U, views X, Y1, and Y2 of the exemplary manufacturing state 500V further include the ILD layer 438. In this way, Fig. 5V represents the semiconductor device under manufacture after operation 332.

[0090] At operation 334, the semiconductor device manufacturing manager 150 may instruct a manufacturing tool to form the backside power rail and the BSPDN. Forming the backside power rail may include fabricating the power rails in the ILD layer 438. Furthermore, forming the BSPDN includes fabricating the backside interconnect elements, such as metal lines and ILD material. For clarity, operation 334 is described with respect to Fig. 5W described in more detail.

[0091] Fig. 5W shows a block diagram of an exemplary manufacturing stage 500W of a semiconductor device according to some embodiments of the present disclosure. Compared to the exemplary manufacturing stage 500V, views X, Y1, and Y2 of the exemplary manufacturing stage 500W further include the BSPDN 446. Furthermore, view X includes a BSPR 444-VSS contacting the lower S / D epi layer 420-B located between the gate regions 454-2 and 454-3. Furthermore, view Y1 includes three BSPR 444s (two BSPR 444-VSS and one BSPR 444-VDD). The BSPR 444-VDD is in contact with the deep via 440-D between the gate stacks. In addition, view Y2 includes seven BSPR 444s that alternate between BSPR 444-VSS and 444-VDD. The BSPR 444-VSSs in device areas 452-1 and 452-3 are in contact with the corresponding deep backside contacts 442-D.Furthermore, the BSPR 444-VDD in the device region 452-3 is in contact with the deep via 440-D, which is in contact with the front-side contact 434-A to the upper S / D epi layer 420-T. In this way, . Fig. 5W represents the semiconductor unit under manufacture after operation 334.

[0092] For the purposes of this description, certain aspects, advantages, and novel features of the embodiments of this disclosure are described herein. The disclosed methods and systems are not intended to be limiting in any way. Instead, this disclosure refers to all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and subcombinations with each other. The methods and systems are not limited to any particular aspects or features, or combinations thereof, nor do the disclosed embodiments require one or more specific advantages to be present or problems to be solved.

[0093] Although the operations of some of the disclosed embodiments are described in a particular sequential order for convenience of illustration, it should be understood that this type of description also encompasses rearrangement unless a particular order is required by specific language defined below. For example, operations described sequentially may, in some cases, be rearranged or performed concurrently. Also, for simplicity, the accompanying figures may not illustrate the various ways in which the disclosed methods may be used in conjunction with other methods. In addition, the description occasionally uses terms such as "providing" or "achieving" to describe the disclosed methods. These terms are highly abstract representations of the actual operations performed.The actual operations corresponding to these terms may vary depending on the particular implementation and will be readily apparent to one skilled in the art.

[0094] As used in this application and the claims, the singular forms "a," "an," "another," and "the" include the plural forms unless the context clearly indicates otherwise. Furthermore, the term "comprises" means "comprising."

[0095] The descriptions of the various embodiments of the present disclosure have been presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen for the purpose of explaining the principles of the embodiments, practical application, or technical improvement over current technologies, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0096] A non-limiting list of examples is provided below to illustrate some aspects of the present disclosure.

[0097] Example 1 is a semiconductor device. The device includes a first stacked FET having: an upper FET disposed over a lower FET and in electrical contact with an upper source / drain epitaxy (S / D-Epi) and a back-end-of-line (BEOL) interconnect; and the lower FET, wherein the lower FET is in electrical contact with a lower S / D-Epi layer; a shallow backside contact in electrical contact with the lower S / D-Epi layer; and a first deep via in electrical contact with the BEOL interconnect and the shallow backside contact, wherein the first deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the lower S / D-Epi layer.

[0098] Example 2 includes the device of Example 1, with or without optional features. In this example, the device includes a second deep via in electrical contact with a top source / drain contact and a backside power rail (BSPR). Optionally, the device includes a frontside contact between the first top FET and the BEOL connection.

[0099] Example 3 includes the device of any of Examples 1-2, with or without optional features. In this example, a depth of the shallow backside contact prevents a short to a backside power rail (BSPR). Optionally, the device includes a third deep via in electrical contact with the BEOL connection and the BSPR, wherein a first dielectric element insulates the third deep via from: a first gate; and a second gate. Optionally, the device includes a deep backside contact, the deep backside contact in electrical contact with the second bottom FET and the BSPR. Optionally, the device includes a gate cutout region disposed between the first gate and a third gate, the gate cutout region filled with bilayer dielectrics.

[0100] Example 4 is a method of manufacturing a semiconductor device, the method comprising forming a first backside contact placeholder by: forming a first recess under a first lower source / drain epitaxial (S / D-Epi) region, wherein a first upper S / D-Epi layer is disposed over the first lower S / D-Epi layer; and depositing a sacrificial dielectric material in the first recess; forming a first gate cutout between a first gate and a second gate surrounding the first lower S / D-Epi layer and the first upper S / D-Epi layer; filling the first gate cutout with a bi-layer dielectric fill; forming a first deep via through an inner dielectric of the bi-layer dielectric fill, wherein the first deep via is in electrical contact with the first backside contact placeholder;removing the first backside contact placeholder; forming a shallow backside contact by: creating a first deep backside contact by filling an area previously occupied by the first backside contact placeholder that was removed with a conductive metal that is in electrical contact with the first deep via and the first lower S / D epi layer; and recessing the first deep backside contact; and forming a back-end-of-line (BEOL) connection that is in electrical contact with the first deep via, and wherein a depth of the shallow backside contact prevents a short circuit to a backside power rail (BSPR);

[0101] Example 5 includes the method of Example 4, with or without optional features. In this example, the bilayer dielectric fill comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the inner dielectric.

[0102] Example 6 includes the method of any of Examples 4 to 5, with or without optional features. In this example, forming the first deep via includes removing the inner dielectric of the dual-layer dielectric fill to expose the backside contact placeholder.

[0103] Example 7 includes the method of any of Examples 4 to 6, with or without optional features. In this example, the method includes forming a second gate cutout between the second gate and a third gate, the second gate cutout exposing a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cutout with the bi-layer dielectric fill; forming a second deep via through the inner dielectric of the bi-layer dielectric fill, the second deep via in contact with a silicon layer disposed beneath the STI layer; performing contact patterning to expose a second upper S / D epi layer of the second gate;forming a front-side contact in electrical contact with the second upper S / D-Epi layer and the second deep via, wherein the formed BEOL connection is in electrical contact with the front-side contact; and forming the BSPR, wherein the BSPR is in electrical contact with the second deep via. Optionally, the method comprises forming a third gate cutout between the first gate and a fourth gate, wherein the third gate cutout exposes an STI layer between the first gate and the fourth gate; and filling the third gate cutout with the two-layer dielectric fill. Optionally, the method comprises forming a fourth gate cutout between the fourth gate and a fifth gate, wherein the fourth gate cutout exposes an STI layer between the fourth gate and the fifth gate;filling the fourth gate cutout with the two-layer dielectric fill; and forming a third deep via through the inner dielectric of the two-layer dielectric fill, the third deep via in contact with the silicon layer disposed beneath the STI layer between the fourth gate and the fifth gate, the third deep via in electrical contact with the formed BEOL interconnect and the formed BSPR. Optionally, the method comprises forming a second backside contact placeholder by: forming a second recess below a region for a second lower S / D-Epi layer of the second gate, the second lower S / D-Epi layer disposed beneath the second upper S / D-Epi layer; and depositing the sacrificial dielectric material in the second recess; removing the second backside contact placeholder;forming a second deep backside contact by filling an area previously occupied by the second backside contact placeholder, which was removed, with the conductive metal such that the conductive metal is in electrical contact with the second lower S / D epi layer, and wherein the formed BSPR is in electrical contact with the second deep backside contact;

[0104] Example 8 is a computer program product having program instructions stored on a computer-readable storage medium. The computer-readable medium includes instructions instructing the processor to form a first backside contact placeholder by: forming a first recess under a first lower source / drain epitaxial (S / D-Epi) region, with a first upper S / D-Epi layer disposed over the first lower S / D-Epi layer; and depositing a sacrificial dielectric material in the first recess; forming a first gate cutout between a first gate and a second gate surrounding the first lower S / D-Epi layer and the first upper S / D-Epi layer; filling the first gate cutout with a two-layer dielectric fill;forming a first deep via through an inner dielectric of the two-layer dielectric fill, wherein the first deep via is in electrical contact with the first backside contact placeholder; removing the first backside contact placeholder; forming a shallow backside contact by: creating a first deep backside contact by filling an area previously occupied by the first backside contact placeholder that was removed with a conductive metal that is in electrical contact with the first deep via and the first lower S / D epi layer; and recessing the first deep backside contact; and forming a back-end-of-line (BEOL) connection that is in electrical contact with the first deep via, and wherein a depth of the shallow backside contact prevents a short to a backside power rail (BSPR);

[0105] Example 9 includes the computer-readable medium of Example 8, with or without optional features. In this example, the bilayer dielectric fill comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the inner dielectric.

[0106] Example 10 includes the computer-readable medium of any of Examples 8 to 9, with or without optional features. In this example, forming the first deep via comprises removing the inner dielectric of the two-layer dielectric fill to expose the backside contact placeholder.

[0107] Example 11 includes the computer-readable medium of any of Examples 8 to 10, with or without optional features. In this example, the computer-readable medium includes forming a second gate cutout between the second gate and a third gate, the second gate cutout exposing a shallow trench isolation (STI) layer disposed between the second gate and the third gate; filling the second gate cutout with the bi-layer dielectric fill; forming a second deep via through the inner dielectric of the bi-layer dielectric fill, the second deep via in contact with a silicon layer disposed beneath the STI layer; performing contact patterning to expose a second upper S / D-Epi layer of the second gate;forming a front-side contact in electrical contact with the second upper S / D-Epi layer and the second deep via, wherein the formed BEOL connection is in electrical contact with the front-side contact; and forming the BSPR, wherein the BSPR is in electrical contact with the second deep via. Optionally, the computer-readable medium comprises forming a third gate cutout between the first gate and a fourth gate, wherein the third gate cutout exposes an STI layer between the first gate and the fourth gate; and filling the third gate cutout with the bi-layer dielectric fill. Optionally, the computer-readable medium comprises forming a fourth gate cutout between the fourth gate and a fifth gate, wherein the fourth gate cutout exposes an STI layer between the fourth gate and the fifth gate;filling the fourth gate cutout with the two-layer dielectric fill; and forming a third deep via through the inner dielectric of the two-layer dielectric fill, the third deep via in contact with the silicon layer disposed beneath the STI layer between the fourth gate and the fifth gate, the third deep via in electrical contact with the formed BEOL interconnect and the formed BSPR.

Claims

[1] Semiconductor device comprising: a first stacked FET comprising: an upper FET disposed over a lower FET and in electrical contact with an upper source / drain epitaxial layer, S / D-Epi layer, and a back-end-of-line connection, BEOL connection; and the lower FET, wherein the lower FET is in electrical contact with a lower S / D epi layer; a flat back contact in electrical contact with the lower S / D epi layer; and a first deep via in electrical contact with the BEOL interconnect and the shallow back contact, wherein the first deep via and the shallow back contact provide a conductive path between the BEOL interconnect and the lower S / D epi layer. [2] The semiconductor device of claim 1, further comprising a second deep via in electrical contact with a top source / drain contact and a backside power rail (BSPR). [3] The semiconductor device of claim 2, further comprising a front side contact between the first upper FET and the BEOL connection. [4] The semiconductor device of claim 1, wherein a depth of the shallow back contact prevents a short circuit to a back power rail, BSPR. [5] The semiconductor device of claim 4, further comprising a deep back contact, the deep back contact being in electrical contact with the second lower FET and the BSPR. [6] The semiconductor device of claim 5, further comprising a gate cutout region disposed between the first gate and a third gate, the gate cutout region being filled with two-layer dielectrics. [7] The semiconductor device of claim 6, further comprising a deep front side contact shorting a second lower S / D epi layer and a second upper S / D epi layer. [8] A method of manufacturing a semiconductor device, the method comprising: Forming a first back contact placeholder by: Forming a first recess under a region for a first lower source / drain epitaxial layer, S / D epi layer, wherein a first upper S / D epi layer is disposed over the first lower S / D epi layer; and Applying a dielectric sacrificial material in the first recess; Forming a first gate cutout between a first gate and a second gate surrounding the first lower S / D epi layer and the first upper S / D epi layer; Filling the first gate cutout with a two-layer dielectric filling; Forming a first deep via through an inner dielectric of the two-layer dielectric fill, the first deep via being in electrical contact with the first backside contact placeholder; Removing the first back contact placeholder; Forming a flat back contact by: Creating a first deep backside contact by filling an area previously occupied by the first backside contact placeholder, which was removed, with a conductive metal that is in electrical contact with the first deep via and the first lower S / D epi layer; and Deepening the first deep back contact; and Forming a back-end-of-line connection, BEOL layer, in electrical contact with the first deep via, and wherein a depth of the shallow back contact prevents a short circuit to a back power rail, BSPR. [9] The method of claim 8, wherein the two-layer dielectric filling comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the inner dielectric. [10] The method of claim 8, wherein forming the first deep via comprises removing the inner dielectric of the two-layer dielectric fill to expose the backside contact placeholder. [11] The method of claim 8, further comprising: forming a second gate cutout between the second gate and a third gate, the second gate cutout exposing a layer of shallow trench isolation, STI, disposed between the second gate and the third gate; Filling the second gate cutout with the two-layer dielectric filling; Forming a second deep via through the inner dielectric of the two-layer dielectric fill, the second deep via in contact with a silicon layer disposed beneath the STI layer; performing contact patterning to expose a second upper S / D epi layer of the second gate; Forming a front-side contact in electrical contact with the second upper S / D epi layer and the second deep via, wherein the formed BEOL connection is in electrical contact with the front-side contact; and Forming the BSPR, wherein the BSPR is in electrical contact with the second deep via. [12] The method of claim 11, further comprising: Forming a third gate cutout between the first gate and a fourth gate, the third gate cutout exposing an STI layer between the first gate and the fourth gate; and Filling the third gate cutout with the two-layer dielectric filling. [13] The method of claim 12, further comprising: Forming a fourth gate cutout between the fourth gate and a fifth gate, the fourth gate cutout exposing an STI layer between the fourth gate and the fifth gate; Filling the fourth gate cutout with the two-layer dielectric filling, and Forming a third deep via through the inner dielectric of the two-layer dielectric fill, the third deep via in contact with the silicon layer disposed beneath the STI layer between the fourth gate and the fifth gate, the third deep via in electrical contact with the formed BEOL interconnect and the formed BSPR. [14] The method of claim 13, further comprising: Forming a second back contact placeholder by: Forming a second recess under a region for a second lower S / D epi layer of the second gate, wherein the second lower S / D epi layer is arranged below the second upper S / D epi layer; and Applying the dielectric sacrificial material in the second recess; Removing the second rear contact placeholder; Forming a second deep back contact by filling an area previously occupied by the second back contact placeholder that was removed with the conductive metal such that the conductive metal is in electrical contact with the second lower S / D epi layer, and wherein the formed BSPR is in electrical contact with the second deep back contact. [15] A computer program product comprising program instructions stored on a computer-readable storage medium, the program instructions being executable by a processor to cause the processor to perform a method on a wafer, the method comprising: Forming a first back contact placeholder by: Forming a first recess under a region for a first lower source / drain epitaxial layer, S / D epi layer, wherein a first upper S / D epi layer is disposed over the first lower S / D epi layer; and Applying a dielectric sacrificial material in the first recess; Forming a first gate cutout between a first gate and a second gate surrounding the first lower S / D epi layer and the first upper S / D epi layer; Filling the first gate cutout with a two-layer dielectric filling; Forming a first deep via through an inner dielectric of the two-layer dielectric fill, the first deep via being in electrical contact with the first backside contact placeholder; Removing the first back contact placeholder; Forming a flat back contact by: Creating a first deep backside contact by filling an area previously occupied by the first backside contact placeholder, which was removed, with a conductive metal that is in electrical contact with the first deep via and the first lower S / D epi layer; and Deepening the first deep back contact; and Forming a back-end-of-line (BEOL) connection in electrical contact with the first deep via, and wherein a depth of the shallow back contact prevents a short circuit to a back power rail (BSPR). [16] The computer program product of claim 15, wherein the two-layer dielectric filling comprises a first dielectric and a second dielectric, wherein the first dielectric is different from the second dielectric, and wherein the second dielectric comprises the inner dielectric. [17] The computer program product of claim 15, wherein forming the first deep via comprises removing the inner dielectric of the two-layer dielectric fill to expose the backside contact placeholder. [18] The computer program product of claim 15, wherein the method further comprises: forming a second gate cutout between the second gate and a third gate, the second gate cutout exposing a layer of shallow trench isolation, STI, disposed between the second gate and the third gate; Filling the second gate cutout with the two-layer dielectric filling; Forming a second deep via through the inner dielectric of the two-layer dielectric fill, the second deep via in contact with a silicon layer disposed beneath the STI layer; performing contact patterning to expose a second upper S / D epi layer of the second gate; Forming a front-side contact in electrical contact with the second upper S / D epi layer and the second deep via, wherein the formed BEOL connection is in electrical contact with the front-side contact; and Forming the BSPR, wherein the BSPR is in electrical contact with the second deep via. [19] The computer program product of claim 18, wherein the method further comprises: Forming a third gate cutout between the first gate and a fourth gate, the third gate cutout exposing an STI layer between the first gate and the fourth gate; and Filling the third gate cutout with the two-layer dielectric filling. [20] The computer program product of claim 19, wherein the method further comprises: Forming a fourth gate cutout between the fourth gate and a fifth gate, the fourth gate cutout exposing an STI layer between the fourth gate and the fifth gate; Filling the fourth gate cutout with the two-layer dielectric filling, and Forming a third deep via through the inner dielectric of the two-layer dielectric fill, the third deep via in contact with the silicon layer disposed beneath the STI layer between the fourth gate and the fifth gate, the third deep via in electrical contact with the formed BEOL interconnect and the formed BSPR.

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