Scoreboard, display device and driver control method

Abstract

A display panel, a display device, and a driver control method. The display panel comprises a shift register unit and output control signal lines coupled to the shift register unit, the output control signal lines being arranged between the coupled shift register unit and a display area of ​​the display panel. The shift register unit comprises: a shift register (100) configured to output a cascade signal via a cascaded output terminal (OT); an output circuit (200) coupled to the shift register (100) configured to control a driver output terminal (OUT) and output a gate sample signal in response to a signal from an output control signal terminal (CS) and a signal from a first reference signal terminal (VREF 1), the output control signal terminal (CS) being coupled to one of the output control signal lines.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of display technology, in particular a display board, a display device and a driver control method. BACKGROUND

[0002] With the rapid development of display technology, display panels are trending towards a high degree of integration and low cost. Gate-Driver-on-Array (GOA) technology integrates a driver control circuit onto an array substrate of a display panel to provide a sampling drive for the panel. Currently, the driver control circuit typically consists of cascaded shift register units. SUMMARY OF THE INVENTION

[0003] A display panel provided in some embodiments of the present disclosure comprises: a shift register unit and output control signal lines coupled to the shift register unit, wherein the output control signal lines are arranged between the shift register unit coupled thereto and a display area of ​​the display panel; the shift register unit comprises: a shift register configured to output a cascade signal via a cascaded output terminal; an output circuit coupled to the shift register, configured to control a driver output terminal, to output a gate sampling signal according to a signal from an output control signal terminal and a signal from a first reference signal terminal, wherein the output control signal terminal is coupled to one of the output control signal lines.

[0004] In some possible embodiments provided in the present disclosure, the output circuit comprises: a first output circuit and a second output circuit; wherein the first output circuit is coupled to the cascaded output terminal or a first node in the shift register and is configured to transmit the output control signal terminal signal to the driver output terminal in response to a signal from the cascaded output terminal or the first node; The second output circuit is coupled to a second node in the shift register and is configured to transmit the signal of the first reference signal terminal to the driver output terminal in response to a signal from the second node.

[0005] In some possible embodiments provided in the present disclosure, the first output circuit comprises: a first output transistor; A gate electrode of the first output transistor is coupled to the cascaded output terminal or the first node, a first electrode of the first output transistor is coupled to the output control signal terminal, and a second electrode of the first output transistor is coupled to the driver output terminal.

[0006] In some possible embodiments provided in the present disclosure, the second output circuit comprises: a second output transistor; a gate electrode of the second output transistor is connected to the second node, a first electrode of the second output transistor is connected to the first reference signal terminal, and a second electrode of the second output transistor is connected to the driver output terminal.

[0007] In some possible embodiments provided in the present disclosure, the shift register comprises: an input sub-circuit configured to deliver a signal from an input signal terminal to a third node in response to a signal from a first clock signal terminal; a control circuit configured to control signals from the first node and the second node and to supply a signal from the third node to either the first or the second node; a cascade sub-circuit configured to release the cascade output terminal for output of the cascade signal in response to signals from the first node and the second node.

[0008] In some possible embodiments provided in the present disclosure, the input circuit comprises: a first transistor; A gate electrode of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the third node.

[0009] In some possible embodiments provided in the present disclosure, the control circuit comprises: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; A gate electrode of the second transistor is connected to the third node, a first electrode of the second transistor is connected to the first clock signal terminal, and a second electrode of the second transistor is connected to a fourth node; A gate electrode of the third transistor is coupled to a second reference signal terminal, a first electrode of the third transistor is coupled to the fourth node, and a second electrode of the third transistor is coupled to a gate electrode of the fourth transistor; a first electrode of the fourth transistor is coupled to a second clock signal terminal and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor; One gate electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor is coupled to the first node; A gate electrode of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor; A gate electrode of the seventh transistor is coupled to the second reference signal terminal, and a second electrode of the seventh transistor is coupled to a fifth node; A gate electrode of the eighth transistor is connected to the fifth node, a first electrode of the eighth transistor is connected to the fifth node, and a second electrode of the eighth transistor is coupled to the second node; a gate electrode of the ninth transistor is coupled to the first clock signal terminal, a first electrode of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to a gate electrode of the tenth transistor; A first electrode of the tenth transistor is coupled to a third reference signal terminal, and a second electrode of the tenth transistor is coupled to a sixth node; A gate electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the sixth node, and a second electrode of the eleventh transistor is coupled to the second clock signal terminal; A gate electrode of the twelfth transistor is coupled to a first electrode of the fifteenth transistor, a first electrode of the twelfth transistor is coupled to the first node, and a second electrode of the twelfth transistor is coupled to a fourth reference signal terminal; A gate electrode of the thirteenth transistor is coupled to a fifth reference signal terminal, a first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and a second electrode of the thirteenth transistor is coupled to a first electrode of the fourteenth transistor; A gate electrode of the fourteenth transistor is coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor; A gate electrode of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the second node; A first electrode of the first capacitor is coupled to the gate electrode of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor; A first electrode of the second capacitor is connected to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor; A first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node; A first electrode of the fourth capacitor is coupled to the cascaded output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal.

[0010] In some possible embodiments provided in the present disclosure, the cascade sub-circuit comprises: a first cascaded transistor and a second cascaded transistor; A gate electrode of the first cascaded transistor is coupled to the first node, a first electrode of the first cascaded transistor is coupled to a fourth reference signal terminal, and a second electrode of the first cascaded transistor is coupled to the cascaded output terminal; A gate electrode of the second cascaded transistor is coupled to the second node, a first electrode of the second cascaded transistor is coupled to the cascaded output terminal, and a second electrode of the second cascaded transistor is coupled to the first reference signal terminal.

[0011] In some possible embodiments provided in the present disclosure, the input sub-circuit comprises: a sixteenth transistor and a seventeenth transistor; A gate electrode of the sixteenth transistor is coupled to the first clock signal terminal, a first electrode of the sixteenth transistor is coupled to the input signal terminal, and a second electrode of the sixteenth transistor is coupled to a seventh node; A gate electrode of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node.

[0012] In some possible embodiments provided in the present disclosure, the control circuit comprises: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor and a sixth capacitor; A gate electrode of the eighteenth transistor is coupled to the cascaded output terminal, a first electrode of the eighteenth transistor is coupled to a third clock signal terminal, and a second electrode of the eighteenth transistor is coupled to a seventh node; A gate electrode of the nineteenth transistor is coupled to the input signal terminal, a first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and a second electrode of the nineteenth transistor is coupled to the second node; A gate electrode of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to an eighth node; a gate electrode of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node; A gate electrode of the twenty-second transistor is coupled to the third node, a first electrode of the twenty-second transistor is coupled to the eighth node, and a second electrode of the twenty-second transistor is coupled to a sixth reference signal terminal; A gate electrode of the twenty-third transistor is coupled to a fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal; A first electrode of the fifth capacitor is coupled to the first reference signal terminal, and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty-third transistor; A first electrode of the sixth capacitor is coupled to the cascaded output terminal, and a second electrode of the sixth capacitor is coupled to the first node.

[0013] In some possible embodiments provided in the present disclosure, the cascade sub-circuit comprises: a first cascaded transistor and a second cascaded transistor; A gate electrode of the first cascaded transistor is coupled to the first node, a first electrode of the first cascaded transistor is coupled to the cascaded output terminal, and a second electrode of the first cascaded transistor is coupled to a third clock signal terminal; A gate electrode of the second cascaded transistor is coupled to the second node, a first electrode of the second cascaded transistor is coupled to the first reference signal terminal, and a second electrode of the second cascaded transistor is coupled to the cascaded output terminal.

[0014] In some possible embodiments provided in the present disclosure, the control circuit comprises: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor and an eighth capacitor; A gate electrode of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to a seventh reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the second node; A gate electrode of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal; A gate electrode of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to a first electrode of the twenty-seventh transistor; A gate electrode of the twenty-seventh transistor is coupled to a third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor; A gate electrode of the twenty-eighth transistor is coupled to the seventh reference signal terminal, the first electrode of the twenty-eighth transistor is coupled to the third node, and a second electrode of the twenty-eighth transistor is coupled to the first node; A first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node; A first electrode of the eighth capacitor is coupled to the cascaded output terminal, and a second electrode of the eighth capacitor is coupled to the first node.

[0015] In some possible embodiments provided in the present disclosure, the control circuit further comprises: a twenty-eighth transistor; A first electrode of the twenty-eighth transistor is coupled to the second electrode of the fifth transistor, a second electrode of the twenty-eighth transistor is coupled to the first node, and a gate electrode of the twenty-eighth transistor is coupled to the first reference signal terminal.

[0016] A display panel provided in some embodiments of the present disclosure comprises: a base substrate that includes a display area and a non-display area, the display area includes: Subpixel;

[0017] scanning lines, wherein each row of subpixels is coupled to at least one of the scanning lines, including the non-display area: a gate driver circuit comprising shift register units, wherein a driver output terminal of each of the shift register units is coupled to at least one of the sampling lines.

[0018] In some possible embodiments provided in the present disclosure, the display panel further comprises: output control signal lines coupled to the gate driver circuit, wherein a direction of extension of each of the output control signal lines coincides with an arrangement direction of the shift register units.

[0019] In some possible embodiments provided in the present disclosure, the output control signal lines are arranged between the gate driver circuit coupled thereto and the display area.

[0020] In some possible embodiments provided in the present disclosure, in two adjacent shift register units, an input signal connection of a later of the adjacent shift register units is coupled to a cascaded output connection of an earlier of the adjacent shift register units;

[0021] The output control signal lines comprise: a first output control signal line and a second output control signal line, wherein the first output control signal line is coupled to output control signal terminals of odd-numbered shift register units and the second output control signal line is coupled to output control signal terminals of even-numbered shift register units.

[0022] In some possible embodiments provided in the present disclosure, in two adjacent shift register units, an input signal connection of a later of the adjacent shift register units is coupled to a cascaded output connection of an earlier of the adjacent shift register units;

[0023] The output control signal lines comprise: a first output control signal line and a second output control signal line; eight adjacent shift register units in the shift register units form a shift register unit group, wherein the first output control signal line is coupled to output control signal terminals of shift register units in odd-numbered shift register unit groups and the second output control signal line is coupled to output control signal terminals of shift register units in even-numbered shift register unit groups.

[0024] In some possible embodiments provided in the present disclosure, the display panel further comprises: output control signal auxiliary lines, wherein a first insulating layer is provided between the output control signal auxiliary lines and the output control signal lines; The output control signal auxiliary lines are in a one-to-one correspondence to the output control signal lines, and each of the output control signal auxiliary lines and a corresponding output control signal line are coupled together through a first through-hole through the first insulating layer.

[0025] In some possible embodiments of the present disclosure, the display panel further comprises: clock signal lines coupled to the gate driver circuit, wherein a direction of extension of each of the clock signal lines coincides with the arrangement direction of the shift register units.

[0026] In some possible embodiments provided in the present disclosure, the clock signal lines are arranged on one side of the gate driver circuit that is coupled to the clock signal lines and faces away from the display area.

[0027] In some possible embodiments of the present disclosure, orthographic projections of the output control signal lines on the base substrate are arranged between orthographic projections of the clock signal lines on the base substrate and the display area.

[0028] In some possible embodiments of the present disclosure, an orthographic projection of the gate driver circuit on the base substrate is arranged between orthographic projections of the clock signal lines on the base substrate and orthographic projections of the output control signal lines on the base substrate, and The orthographic projections of the output control signal lines on the base substrate are arranged between the orthographic projection of the gate driver circuit on the base substrate and the display area.

[0029] In some possible embodiments provided in the present disclosure, an orthographic projection of a first output transistor on the base substrate is located between an orthographic projection of a first cascaded transistor on the base substrate and the display area.

[0030] In some possible embodiments of the present disclosure, the width of a channel of a first output transistor is larger than the width of a channel of a first cascaded transistor.

[0031] In some possible embodiments of the present disclosure, the width of the channel of the first output transistor is not less than 100 µm.

[0032] In some possible embodiments of the present disclosure, the width of the channel of the first cascaded transistor is not greater than 60 µm.

[0033] In some possible embodiments of the present disclosure, an orthographic projection of a second output transistor on the base substrate is located between an orthographic projection of a second cascaded transistor on the base substrate and the display area.

[0034] In some possible embodiments of the present disclosure, the width of a channel of a second output transistor is larger than the width of a channel of a second cascaded transistor.

[0035] In some possible embodiments of the present disclosure, the width of the channel of the second output transistor is not less than 100 µm.

[0036] In some possible embodiments of the present disclosure, the width of the channel of the second cascade transistor is no greater than 60 µm.

[0037] A display device provided in some embodiments of the present disclosure comprises: the scoreboard; a driver control circuit coupled to the display panel and configured to input an initial output control signal to the output control signal terminals of the shift register units when a full-screen driver mode is determined to be used, to sequentially output the shift register units' gate sampling signals, drive sampling lines line by line, and to input a second output control signal to the output control signal terminals of the shift register units when a local driver mode is determined to be used, in order to output gate sample signals sequentially to some of the shift register units and to output invalid sample signals to the remaining shift register units.

[0038] A driver control method provided in some embodiments of the present disclosure comprises: Inputting an initial output control signal to the output control signal terminals of shift register units when a full-screen driver mode is determined to be used to sequentially output the shift register units' gate sample signals and drive sample lines line by line; and Inputting a second output control signal to the output control signal terminals of the shift register units when a local driver mode is determined to be used, in order to output some of the shift register units sequentially gate sampling signals and the remaining shift register units output invalid sampling signals to drive some of the sampling lines.

[0039] In some possible embodiments provided in the present disclosure, the first output control signal is a fixed voltage signal with a first electrical level.

[0040] In some possible embodiments of the present disclosure, the second output control signal comprises a fixed voltage signal section with a first electrical level and a fixed voltage signal section with a second electrical level, wherein the fixed voltage signal section with the first electrical level is input to some of the shift register units and the fixed voltage signal section with the second electrical level is input to the remaining shift register units.

[0041] In some possible embodiments of the present disclosure, the first output control signal is a clock signal.

[0042] In some possible embodiments of the present disclosure, the second output control signal comprises a clock signal section and a fixed voltage signal section with a first electrical level; The clock signal section in the second output control signal is fed into some of the shift register units, and the fixed voltage signal section with the first electrical level in the second output control signal is fed into the remaining shift register units.

[0043] In some possible embodiments provided in the present disclosure, the pulse width of an input signal of an input signal terminal of the shift register unit is 18H, the pulse width of a cascade signal output from a cascade signal terminal of the shift register unit is 18H, the pulse width of a gate sample signal output from a driver output terminal of the shift register unit is 18H, and a cascade signal and a valid gate sample signal output from the shift register unit are shifted backward by 2H relative to a cascade signal and a valid gate sample signal output from a previous shift register unit of the shift register units. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are part of this description, illustrate examples that correspond to the description and, together with the description, serve to explain the principle of the description. Fig. Figure 1 is a schematic structure diagram of a shift register unit according to an embodiment of the present disclosure; Fig. 2 is another schematic structure diagram of a shift register unit according to an embodiment of the present disclosure; Fig. Figure 3 is a schematic structure diagram of a display board according to an embodiment of the present disclosure; Fig. Figure 4 is a further schematic structure diagram of a display device according to an embodiment of the present disclosure; Fig. Figure 5 is a flowchart showing a driver control method according to an embodiment of the present disclosure; Fig. 6 is a signal timing diagram according to an embodiment of the present disclosure; Fig. 7 is another signal timing diagram according to an embodiment of the present disclosure; Fig. 8 is another schematic structure diagram of a shift register unit according to an embodiment of the present disclosure; Fig. 9 is another signal timing diagram according to an embodiment of the present disclosure; Fig. 10 is another signal timing diagram according to an embodiment of the present disclosure; Fig. Figure 11 is another schematic structure diagram of a shift register unit according to an embodiment of the present disclosure; Fig. 12 is another signal timing diagram according to an embodiment of the present disclosure; Fig. 13 is another signal timing diagram according to an embodiment of the present disclosure; Fig. Figure 14 is a schematic diagram showing a layout structure of a shift register unit according to an embodiment of the present disclosure; Fig. Figure 15 is a schematic diagram showing a layout structure of a semiconductor layer according to an embodiment of the present disclosure; Fig. Figure 16 is a schematic diagram showing a layout structure of a gate conductive layer according to an embodiment of the present disclosure; Fig. Figure 17 is a schematic diagram showing a layout structure of a capacitor electrode layer according to an embodiment of the present disclosure; Fig. Figure 18 is a schematic diagram showing a layout structure of a cascaded wiring layer according to an embodiment of the present disclosure; Fig. Figure 19 is a schematic diagram showing a layout structure of a transmission wiring layer according to an embodiment of the present disclosure; Fig. Figure 20 is a schematic diagram showing a layout structure of an auxiliary wiring layer according to an embodiment of the present disclosure; Fig. 21 is another schematic structure diagram of a shift register unit according to an embodiment of the present disclosure; Fig. Figure 22 is a schematic structure diagram of a display device according to an embodiment of the present disclosure; Fig. 23 is another signal timing diagram according to an embodiment of the present disclosure; Fig. Figure 24 is another signal timing diagram according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Exemplary embodiments are described in detail herein, with illustrations in the drawings. Where the following descriptions refer to the drawings, identical numbers in different drawings refer to the same or similar elements unless otherwise specified. The embodiments described in the following examples do not represent all embodiments that conform to the description. Rather, they are merely examples of devices and methods that conform to some aspects of the description as detailed in the accompanying claims.

[0046] The terms used in this disclosure serve only to describe certain embodiments and are not intended to limit the scope of this disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the ordinary meaning known to a person skilled in the art in the field of this disclosure. "First," "second," and similar terms used in the description and claims do not represent a sequence, quantity, or meaning, but serve only to distinguish between different components. Likewise, similar articles such as "one," "a," or "a" do not represent a quantity limitation, but mean that at least one is present. "Several," "multiple," or "multiple" mean two or more.Unless otherwise specified, similar words such as "front," "back," "bottom," and / or "top" are used only for the sake of simplicity and are not limited to a specific position or spatial orientation. Similar words such as "including" or "comprising" mean that an element or item preceding "including" or "comprising" includes the elements or items listed after it and their equivalents, without excluding any other elements or items. Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections and may include direct or indirect electrical connections.

[0047] The terms used in the description serve only to describe certain embodiments and are not intended to limit the present disclosure. Terms defined in the description and the attached claims in their singular form as "a / an", "the", and "the" are also intended to include plural forms unless otherwise clearly evident from the context. It should also be understood that the term "and / or" here denotes and includes all possible combinations of one or more of the listed elements connected together.

[0048] The embodiments of the present disclosure provide a shift register unit, as in Fig. 1 shown, which includes the following: a shift register 100 configured to output a cascade signal via a cascaded output terminal OT; an output circuit 200 which is coupled to the shift register 100 and is configured to control a driver output terminal OUT to output a gate sampling signal according to a signal from an output control signal terminal CS and a signal from a first reference signal terminal VREF1.

[0049] The embodiments of the present disclosure provide a shift register unit that outputs a cascade signal through a shift register and controls a gate sampling signal of a driver output terminal in an output circuit by controlling a signal from an output control signal terminal. When the shift register unit is applied to a display panel, the sampling of any area of ​​the display panel can be controlled by controlling the signal from the output control signal terminal, thereby enabling flexible adjustments of the refresh rates of different areas, reducing power consumption, and minimizing losses.

[0050] In some embodiments of the present disclosure, as in Fig. Figure 2 shows that the output circuit 200 comprises: a first output circuit 210 and a second output circuit 220, wherein the first output circuit 210 is coupled to a first node N1 in the shift register 100 and is configured to transmit the signal of the output control signal terminal CS to the driver output terminal OUT in response to a signal from the first node N1; the second output circuit 220 is coupled to a second node N2 in the shift register 100 and is configured to transmit the signal of the first reference signal terminal VREF1 to the driver output terminal OUT in response to a signal from the second node N2.

[0051] In some embodiments of the present disclosure, the first output circuit comprises 210, as in Fig. Figure 2 shows a first output transistor T1, wherein a gate electrode of the first output transistor T1 is coupled to the first node N1, a first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and a second electrode of the first output transistor T1 is coupled to the driver output terminal OUT.

[0052] In some embodiments of the present disclosure, as in Fig. Figure 2 shows the second output circuit 220 comprising: a second output transistor T2, wherein a gate electrode of the second output transistor T2 is coupled to the second node N2, a first electrode of the second output transistor T2 is coupled to the first reference signal terminal VREF1, and a second electrode of the second output transistor T2 is coupled to the driver output terminal OUT.

[0053] Alternatively, the first output circuit can be coupled to the cascaded output terminal in the shift register, and the first output circuit is configured to transmit the signal from the output control signal terminal to the driver output terminal in response to the signal from the cascaded output terminal. Based on this, the gate electrode of the first output transistor is coupled to the cascaded output terminal in the shift register.

[0054] In the embodiments of the present disclosure, the technical effect is better compared to a mode in which the gate electrode of the first output transistor is coupled to the cascaded output terminal in the shift register, and corresponds to the mode in which the gate electrode of the first output transistor is coupled to the first node. Fig. 2. The gate electrode of the first output transistor T1 is coupled to the first node N1, and the voltage of a low-level signal that the driver output terminal OUT can output is VGL. When the gate electrode of the first output transistor is coupled to the cascaded output terminal in the shift register, the voltage of a low-level signal that the cascaded output terminal can output is only VGL, so the voltage of the low-level signal that the driver output terminal OUT can output is only VGL-Vth.

[0055] In some embodiments of the present disclosure, the shift register comprises 100, as in Fig. 2 shown: an input sub-circuit 110 configured to deliver a signal from an input signal terminal IN to a third node N3 in response to a signal from a first clock signal terminal CK1; a control circuit 120 configured to control signals of the first node N1 and the second node N2 and to supply a signal from the third node N3 to the first node N1 or the second node N2; a cascade sub-circuit 130, which is configured to release the cascade output OT to output the cascade signal in response to the signals of the first node N1 and the second node N2.

[0056] In some embodiments of the present disclosure, the input sub-circuit comprises 110, as in Fig. Figure 2 shows a first transistor M1, wherein a gate electrode of the first transistor M1 is coupled to the first clock signal terminal CK1, a first electrode of the first transistor M1 is coupled to the input signal terminal IN, and a second electrode of the first transistor M1 is coupled to the third node N3.

[0057] In some embodiments of the present disclosure, the control circuit 120 comprises, as in Fig. 2 shown, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0058] A gate electrode of the second transistor M2 is coupled to the third node N3, a first electrode of the second transistor M2 is coupled to the first clock signal terminal CK1, and a second electrode of the second transistor M2 is coupled to a fourth node N4; a gate electrode of the third transistor M3 is coupled to a second reference signal terminal VREF2, a first electrode of the third transistor M3 is coupled to the fourth node N4, and a second electrode of the third transistor M3 is coupled to a gate electrode of the fourth transistor M4; a first electrode of the fourth transistor M4 is coupled to a second clock signal terminal CK2, and a second electrode of the fourth transistor M4 is coupled to a first electrode of the fifth transistor M5;A gate electrode of the fifth transistor M5 is coupled to the second clock signal terminal CK2, and a second electrode of the fifth transistor M5 is coupled to the first node N1; a gate electrode of the sixth transistor M6 is coupled to the first clock signal terminal CK1, a first electrode of the sixth transistor M6 is coupled to the input signal terminal IN, and a second electrode of the sixth transistor M6 is coupled to a first electrode of the seventh transistor M7; a gate electrode of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and a second electrode of the seventh transistor M7 is coupled to a fifth node N5; a gate electrode of the eighth transistor M8 is coupled to the fifth node N5, a first electrode of the eighth transistor M8 is coupled to the fifth node N5, and a second electrode of the eighth transistor M8 is coupled to the second node N2;A gate electrode of the ninth transistor M9 is coupled to the first clock signal terminal CK1, a first electrode of the ninth transistor M9 is coupled to the second reference signal terminal VREF2, and a second electrode of the ninth transistor M9 is coupled to a gate electrode of the tenth transistor M10; a first electrode of the tenth transistor M10 is coupled to a third reference signal terminal VREF3, and a second electrode of the tenth transistor M10 is coupled to a sixth node N6; a gate electrode of the eleventh transistor M11 is coupled to the fifth node N5, a first electrode of the eleventh transistor M11 is coupled to the sixth node N6, and a second electrode of the eleventh transistor M11 is coupled to the second clock signal terminal CK2;A gate electrode of the twelfth transistor M12 is coupled to a first electrode of the fifteenth transistor M15, a first electrode of the twelfth transistor M12 is coupled to the first node N1, and a second electrode of the twelfth transistor M12 is coupled to a fourth reference signal terminal VREF4; a gate electrode of the thirteenth transistor M13 is coupled to a fifth reference signal terminal VREF5, a first electrode of the thirteenth transistor M13 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the thirteenth transistor M13 is coupled to a first electrode of the fourteenth transistor M14; a gate electrode of the fourteenth transistor M14 is coupled to the first reference signal terminal VREF1, and a second electrode of the fourteenth transistor M14 is coupled to the first electrode of the fifteenth transistor M15;A gate electrode of the fifteenth transistor M15 is coupled to the first reference signal terminal VREF1, the first electrode of the fifteenth transistor M15 is coupled to the third node N3, and a second electrode of the fifteenth transistor M15 is coupled to the second node N2; a first electrode of the first capacitor C1 is coupled to the gate electrode of the fourth transistor M4, and a second electrode of the first capacitor C1 is coupled to the second electrode of the fourth transistor M4; a first electrode of the second capacitor C2 is coupled to the sixth node N6, and a second electrode of the second capacitor C2 is coupled to the second electrode of the seventh transistor M7; a first electrode of the third capacitor C3 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the third capacitor C3 is coupled to the first node N1;A first electrode of the fourth capacitor C4 is coupled to the cascaded output terminal OT, and a second electrode of the fourth capacitor C4 is coupled to the first reference signal terminal VREF1.

[0059] In some embodiments of the present disclosure, the cascade sub-circuit comprises 130, as shown in Fig. Figure 2 shows a first cascaded transistor T3 and a second cascaded transistor T4, wherein a gate electrode of the first cascaded transistor T3 is coupled to the first node N1, a first electrode of the first cascaded transistor T3 is coupled to the fourth reference signal terminal VREF4, and a second electrode of the first cascaded transistor T3 is coupled to the cascaded output terminal OT; a gate electrode of the second cascaded transistor T4 is coupled to the second node N2, a first electrode of the second cascaded transistor T4 is coupled to the cascaded output terminal OT, and a second electrode of the second cascaded transistor T4 is coupled to the first reference signal terminal VREF1.

[0060] In some embodiments of the present disclosure, the control circuit 120 comprises, as in Fig. 21 shown, furthermore: a twenty-eighth transistor M28.

[0061] A first electrode of the twenty-eighth transistor M28 is coupled to the second electrode of the fifth transistor M5, a second electrode of the twenty-eighth transistor M28 is coupled to the first node N1, and a gate electrode of the twenty-eighth transistor M28 is coupled to the first reference signal terminal VREF1.

[0062] In one example, a valid pulse signal of the cascade signal output from the cascade output terminal can be a high-level signal; a valid pulse signal of the gate sample signal output from the driver output terminal can be a high-level signal; a valid pulse signal of a first reference signal output from the first reference signal terminal can be a low-level signal; a valid pulse signal of a second reference signal output from the second reference signal terminal can be a low-level signal; a valid pulse signal of a third reference signal output from the third reference signal terminal can be a high-level signal; a valid pulse signal of a fourth reference signal output from the fourth reference signal terminal can be a high-level signal.Alternatively, a valid pulse signal of the cascade signal output from the cascaded output terminal can be a low-level signal; a valid pulse signal of the gate sample signal output from the driver output terminal can be a low-level signal; a valid pulse signal of a first reference signal output from the first reference signal terminal can be a high-level signal; a valid pulse signal of a second reference signal output from the second reference signal terminal can be a high-level signal; a valid pulse signal of a third reference signal output from the third reference signal terminal can be a low-level signal; a valid pulse signal of a fourth reference signal output from the fourth reference signal terminal can be a low-level signal.

[0063] In one example, to simplify the manufacturing process, all transistors can be either P-type or N-type transistors, although this is not a limitation here. Furthermore, the N-type transistors are switched on by a high-level signal and switched off by a low-level signal; the P-type transistors are switched off by a high-level signal and switched on by a low-level signal.

[0064] It should be noted that the transistors mentioned in the embodiments of this disclosure can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), and this is not limited here. In a specific embodiment, depending on the transistor type and input signals, the first electrodes of the transistors can be used as the source electrodes and the second electrodes as the drain electrodes, or the first electrodes can be used as the drain electrodes and the second electrodes as the source electrodes, which is not specifically distinguished here.

[0065] The embodiments of the present disclosure provide a display panel, as in Fig. 3 shown, which includes the following: a base substrate 1000 comprising a display area AA and a non-display area BB.

[0066] The AA display area includes: Subpixel SPX; Sampling lines GA, wherein each row of the subpixel SPX is coupled to at least one of the sampling lines GA.

[0067] The non-display area BB includes: a gate driver circuit 10, the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3), wherein a driver output port OUT of each of the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) is coupled to at least one of the scanning lines GA.

[0068] In some embodiments of the present disclosure, the display panel comprises, as in Fig. 3 shown, furthermore: output control signal lines (such as CS-1 and CS-2 in Fig. 3), which are coupled to shift register units in the gate driver circuit 10. An output control signal connection of a shift register unit is coupled to one of the output control signal lines. In addition, a direction of expansion of each of the output control signal lines (such as CS-1 and CS-2 in Fig. 3) corresponding to an arrangement direction of the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) In one example, the expansion direction of each of the output control signal lines (such as CS-1 and CS-2 in Fig. 3) a second direction F2, and the arrangement direction of the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) is also the second direction F2. F1 in Fig. 3 is a first direction.

[0069] In some embodiments of the present disclosure, as in Fig. Figure 3 shows the output control signal lines (such as CS-1 and CS-2 in Fig. 3) arranged between the gate driver circuit 10 coupled to it and the display area AA.

[0070] In some embodiments of the present disclosure, as in Fig. Figure 3 shows two adjacent shift register units in the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) An input signal connection IN of a later of the adjacent shift register units is coupled to a cascaded output connection OT of an earlier of the adjacent shift register units. It should be noted that an input signal connection IN of a first shift register unit SR1 in the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 3) is coupled with a frame start signal connection OT of a cascaded shift register unit.

[0071] In some embodiments of the present disclosure, as in Fig. Figure 3 shows the output control signal lines (such as CS-1 and CS-2 in Fig. 3) comprising a first output control signal line CS-1 and a second output control signal line CS-2, wherein the first output control signal line CS-1 is coupled to output control signal terminals CSs of odd-numbered shift register units and the second output control signal line CS-2 is coupled to output control signal terminals CSs of even-numbered shift register units. In an example, the first output control signal line CS-1 is coupled to output control signal terminals CSs of shift register units SR1, SR3, SR5, and SR7, and the second output control signal line CS-2 is coupled to output control signal terminals CSs of shift register units SR2, SR4, SR6, and SR8.

[0072] In some embodiments of the present disclosure, as in Fig. As shown in Figure 22, the output control signal lines (such as CS-1 and CS-2 in Figure 22) include Fig. 3) a first output control signal line CS-1 and a second output control signal line CS-2, wherein eight adjacent shift register units form a shift register unit group, the first output control signal line CS-1 being coupled to output control signal terminals CSs of shift register units in odd-numbered shift register unit groups, and the second output control signal line CS-2 being coupled to output control signal terminals CSs of shift register units in even-numbered shift register unit groups. In an example, the first output control signal line CS-1 is coupled to output control signal terminals CSs of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8, and the second output control signal line CS-2 is coupled to output control signal terminals CS of shift register units SR9, SR10, SR11, SR12, SR13, SR14, SR15, and SR16.

[0073] In some embodiments of the present disclosure, the display panel comprises, as in Fig. 3 shown, furthermore: clock signal lines (such as clk1 and clk2 in Fig. 3), which are coupled to the gate driver circuit, with one expansion direction for each of the clock signal lines (such as clk1 and clk2 in Fig. 3) matches the arrangement direction of the shift register units.

[0074] In some embodiments of the present disclosure, the display panel comprises, as in Fig. 3 shown, furthermore: output control auxiliary signal lines, wherein a first insulating layer is provided between the output control auxiliary signal lines and the output control signal lines; the output control auxiliary signal lines are in a one-to-one correspondence to the output control signal lines and each of the output control auxiliary signal lines and a corresponding one of the output control signal lines are coupled to each other by a first through-hole through the first insulating layer.

[0075] In some embodiments of the present disclosure, as in Fig. 14 to Fig. As shown in Figure 20, a semiconductor layer 010, a gate conductive layer 020, a capacitor electrode layer 030, a cascaded wiring layer 040, a signal transmission wiring layer 050, and an auxiliary wiring layer 060 are arranged sequentially on the base substrate. Furthermore, an insulating layer is arranged between each pair of adjacent layers in the semiconductor layer 010, the gate conductive layer 020, the capacitor electrode layer 030, the cascaded wiring layer 040, the signal transmission wiring layer 050, and the auxiliary wiring layer 060. Additionally, two layers that require coupling are connected via through-holes that penetrate the insulating layer.

[0076] In one example, semiconductor layer 010 comprises an active layer in each transistor. The semiconductor layer can be formed by structuring a semiconductor material. The semiconductor layer can be configured to create the active layers of transistors. For example, the semiconductor layer could consist of amorphous silicon, polysilicon, an oxide semiconductor material, etc. It should be noted that a source region and a drain region can be conductive areas formed by doping with n-type or p-type impurities.

[0077] In one example, the gate conductor layer 020 comprises a gate electrode and a scan line in each transistor. Gate electrodes from some transistors are reused as one of the electrode plates of capacitors.

[0078] In one example, the capacitor electrode layer 030 includes another electrode plate in each capacitor. Two electrode plates with opposite surfaces form the capacitor.

[0079] In one example, the cascade wiring layer 040 includes cascade wiring configured to couple the input signal terminal IN of the shift register unit to the cascaded output terminal OT of a previous shift register unit.

[0080] In one example, the signal transmission wiring layer 050 includes a clock signal line, an output control signal line, and a source electrode and a drain electrode in each transistor.

[0081] In one example, the auxiliary wiring layer 060 includes output control auxiliary signal lines SC-1 and SC-2, as well as remaining reference signal lines.

[0082] In some embodiments of the present disclosure, as in Fig. Figure 14 shows the clock signal lines clk1 and clk2 arranged on one side of the gate driver circuit coupled to it, which is facing away from the display area.

[0083] In some embodiments of the present disclosure, as in Fig. Figure 14 shows orthographic projections of the output control signal lines (such as CS-1 and CS-2) on the base substrate arranged between orthographic projections of the clock signal lines (such as clk1 and clk2) on the base substrate and the display area.

[0084] In some embodiments of the present disclosure, as in Fig. Figure 14 shows an orthographic projection of a shift register 100 on the base substrate between the orthographic projections of the clock signal lines (such as clk1 and clk2) on the base substrate and the orthographic projections of the output control signal lines (such as CS-1 and CS-2) on the base substrate, and the orthographic projections of the output control signal lines (such as CS-1 and CS-2) on the base substrate are arranged between the orthographic projection of the shift register 100 on the base substrate and the display area.

[0085] In some embodiments of the present disclosure, as in Fig. Figure 14 shows an orthographic projection of a first output transistor on the base substrate between an orthographic projection of a first cascaded transistor on the base substrate and the display area.

[0086] In some embodiments of the present disclosure, as in Fig. As shown in Figure 14, the width of a channel of the first output transistor is greater than the width of a channel of the first cascaded transistor.

[0087] In some embodiments of the present disclosure, the width of the channel of the first output transistor is not less than 100 µm.

[0088] In some embodiments of the present disclosure, the width of the channel of the first cascaded transistor is not greater than 60 µm.

[0089] In some embodiments of the present disclosure, as in Fig. Figure 14 shows an orthographic projection of a second output transistor on the base substrate arranged between an orthographic projection of a second cascaded transistor on the base substrate and the display area.

[0090] In some embodiments of the present disclosure, as in Fig. Figure 14 shows a channel width of the second output transistor larger than a channel width of the second cascaded transistor.

[0091] In some embodiments of the present disclosure, the width of the channel of the second output transistor is not less than 100 µm.

[0092] In some embodiments of the present disclosure, the width of the channel of the second cascaded transistor is not greater than 60 µm.

[0093] The embodiments of the present disclosure provide a display device as described in Fig. 4 shown, which includes the following: a scoreboard; a driver control circuit 11, which is coupled to the display panel and is configured to send a first output control signal to output control signal terminals CS of the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 4) to enter the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 4) to output sequential gate sampling signals, to control sampling lines line by line; a second output control signal to the output control signal terminals CS of the shift register units (such as SR1, SR2, SR3, SR4, SR5, SR6, SR7 and SR8 in Fig. 4) is entered when a local driver mode is set to cause some of the shift register units to output gate sampling signals sequentially, while the remaining shift register units output invalid sampling signals. In an example, the second output control signal is entered to the output control signal terminals CS of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8 to cause shift register units SR1, SR2, SR6, SR7, and SR8 to output gate sampling signals sequentially, while the remaining shift register units SR3, SR4, and SR5 output invalid sampling signals.

[0094] In one example, the gate sampling signals are high-level signals and the invalid sampling signals are low-level signals, or the gate sampling signals are low-level signals and the invalid sampling signals are high-level signals, which is not limited here.

[0095] The embodiments of the present disclosure provide a driver control method as described in Fig. 5 shown, which includes the following:

[0096] In S100, a first output control signal is input to the output control signal terminals of the shift register units when a full-screen display mode is determined to be used in order to sequentially output gate sampling signals to the shift register units, driving the sampling lines line by line.

[0097] In the S200, a second output control signal is fed to the output control signal terminals of the shift register units when a local driver mode is determined to be used, in order to output gate sampling signals sequentially to some of the shift register units, and to output invalid sampling signals to drive some of the sampling lines to the remaining shift register units.

[0098] In some embodiments of the present disclosure, as in Fig. Figure 6 shows the first output control signal cs1 as a fixed voltage signal with a first electrical level V1. In one example, the fixed voltage signal with the first electrical level V1 is at a high level, or the fixed voltage signal with the first electrical level V1 is at a low level, which is not limited here.

[0099] In one example, in full-screen driver mode, the first output control signal cs1 is fed into the output control signal connections of the shift register units via a first output control signal line CS-1 and a second output control signal line CS-2. A signal timing diagram of the signal passing through the scan lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) is shown. Fig. 4) The loaded gate sampling signals out1 to out8 are in Fig. 6 shown.

[0100] As in Fig. Figure 6 shows that "in" denotes an input signal of an input signal terminal IN, ck1 denotes a first clock signal of a first clock signal terminal CK1, ck2 denotes a second clock signal of a second clock signal terminal CK2, cs1 denotes a first output control signal of an output control signal terminal CS, ot1 a cascade signal of a cascade signal terminal OT in a first shift register unit SR1, ot2 a cascade signal of a cascade signal terminal OT in a second shift register unit SR2, ot3 a cascade signal of a cascade signal terminal OT in a third shift register unit SR3, ot4 a cascade signal of a cascade signal terminal OT in a fourth shift register unit SR4, ot5 a cascade signal of a cascade signal terminal OT in a fifth shift register unit SR5, and ot6 a cascade signal of a cascade signal terminal OT in a sixth shift register unit SR6.ot7 represents a cascade signal from a cascade signal connection OT in a seventh shift register unit SR7, ot8 represents a cascade signal from a cascade signal connection OT in an eighth shift register unit SR8, out1 represents a gate sample signal from a driver output connection OUT in the first shift register unit SR1, out2 represents a gate sample signal from a driver output connection OUT in the second shift register unit SR2, out3 represents a gate sample signal from a driver output connection OUT in the third shift register unit SR3, out4 represents a gate sample signal from a driver output connection OUT in the fourth shift register unit SR4, out5 represents a gate sample signal from a driver output connection OUT in the fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in the sixth shift register unit SR6,out7 represents a gate sampling signal from a driver output connection OUT in the seventh shift register unit SR7, and out8 represents a gate sampling signal from a driver output connection OUT in the eighth shift register unit SR8.

[0101] The following describes the working process of a shift register unit provided in the embodiments of the present disclosure, using a shift register unit setup that is described in Fig. 2 is shown, with reference to the in Fig. The signal timing diagram shown in section 6 is described.

[0102] As in Fig. Figure 2 shows, in an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a low-level signal, a valid pulse signal of a second reference signal output from a second reference signal terminal VREF2 is a low-level signal, a valid pulse signal of a third reference signal output from a third reference signal terminal VREF3 is a high-level signal, a valid pulse signal of a fourth reference signal output from a fourth reference signal terminal VREF4 is a high-level signal, a valid pulse signal of a fifth reference signal output from a fifth reference signal terminal VREF5 is a high-level signal, and a fixed voltage signal with a first electrical level V1 of a first output control signal cs1 is a high-level signal.is used for explanation.

[0103] The gate electrodes of the third transistor M3 and the seventh transistor M7 are connected to the second reference signal terminal VREF2, and the second reference signal terminal VREF2 inputs a low-level signal. The gate electrodes of the fourteenth transistor M14 and the fifteenth transistor M15 are connected to the first reference signal terminal VREF1, and the first reference signal terminal VREF1 inputs a low-level signal. Therefore, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are in a normally on state. One gate electrode of the thirteenth transistor M13 is connected to the fifth reference signal terminal VREF5, and the fifth reference signal terminal VREF5 inputs a high-level signal. Therefore, the thirteenth transistor M13 is in a normally off state.To simplify the description, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 at any given time will not be analyzed below.

[0104] In a first stage H1, an input signal "in" provides a high level, a first clock signal ck1 a low level, and a second clock signal ck2 a high level. A first transistor M1 is switched on under the control of the low level of the first clock signal ck1, and the first transistor M1 supplies the high level of the input signal "in" to a third node N3. A second transistor M2 is switched off under the control of the high level of the third node N3. A twelfth transistor M12 is switched off under the control of the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to a second node N2, and a second cascaded transistor T4 and a second output transistor T2 are switched off.A ninth transistor M9 is switched on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 supplies a low level of the second reference signal terminal VREF2 to a fourth node N4. A tenth transistor M10 is switched on under the control of the low level of the fourth node N4, and the tenth transistor M10 supplies a high level of the third reference signal terminal VREF3 to a sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to a gate electrode of a fourth transistor M4, and the fourth transistor M4 is switched on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to a first electrode of a fifth transistor M5, and the fifth transistor M5 is switched off under the control of the high level of the second clock signal ck2. A first cascade transistor T3 and a first output transistor T1 are switched off.A sixth transistor M6 is turned on under the control of the low level of the first clock signal ck1, and the sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal "in" to a fifth node N5. An eighth transistor M8 and an eleventh transistor M11 are turned off under the control of the high level of the fifth node N5. A cascade signal output from a cascade signal terminal OT is held at a low level, and a gate sample signal output from a driver output terminal OUT is held at a low level.

[0105] In a second stage H2, the input signal "in" is low, the first clock signal ck1 is high, and the second clock signal ck2 is low. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 is held high. The second transistor M2 is switched off by the high level of the third node N3. The twelfth transistor M12 is switched off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, and the second cascaded transistor T4 and the second output transistor T2 are switched off. The ninth transistor M9 is switched off by the high level of the first clock signal ck1, and the fourth node N4 is held low.The tenth transistor M10 is turned on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to a first node N1. The first cascade transistor T3 and the first output transistor T1 are turned on by the low level signal from the first node N1.The first cascade transistor, T3, supplies a high level of the fourth reference signal terminal, VREF4, to the cascade signal terminal, OT. The first output transistor, T1, supplies a high level of the first output control signal, cs1, from an output control signal terminal, CS, to the driver output terminal, OUT. The sixth transistor, M6, is turned off under the control of the high level of the first clock signal, ck1, and the fifth node, N5, is held at a high level. The eighth transistor, M8, and the eleventh transistor, M11, are turned off under the control of the high level of the fifth node, N5. The cascade signal output from the cascade signal terminal, OT, is held at a low level, and the gate sampling signal output from the driver output terminal, OUT, is held at a low level.The cascade signal output from the cascade signal terminal OT is at a high level, and the gate sampling signal output from the driver output terminal OUT is at a high level.

[0106] In a third stage H3, the input signal "in" is low-level, the first clock signal ck1 is low-level, and the second clock signal ck2 is high-level. The first transistor M1 is switched on by the low level of the first clock signal ck1, and M1 outputs the low level of the input signal "in" to the third node N3. The second transistor M2 is switched on by the low level of the third node N3, and M2 outputs the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is switched on by the low level of the third node N3, and M12 outputs the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are switched off.The fifteenth transistor, M15, supplies the low level of the third node, N3, to the second node, N2. The second cascaded transistor, T4, and the second output transistor, T2, are turned on under the control of the low level from the second node, N2. The second cascaded transistor, T4, supplies a low level from the first reference signal terminal, VREF1, to the cascade signal terminal, OT. The second output transistor, T2, supplies the low level from the first reference signal terminal, VREF1, to the driver output terminal, OUT. The ninth transistor, M9, is turned on under the control of the low level from the first clock signal, ck1. The ninth transistor, M9, supplies the low level from the second reference signal terminal, VREF2, to the fourth node, N4.The tenth transistor M10 is switched on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is switched on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is switched off by the high level signal of the second clock signal ck2. The first cascaded transistor T3 and the first output transistor T1 are switched off by the high level signal from the first node N1.The sixth transistor, M6, is turned on under the control of the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the low level of the input signal "in" to the fifth node, N5. The eighth transistor, M8, and the eleventh transistor, M11, are turned on under the control of the low level of the fifth node, N5. The eighth transistor, M8, supplies the low level of the fifth node, N5, to the second node, N2, and the eleventh transistor, M11, supplies the high level of the second clock signal, ck2, to the sixth node, N6. The cascade signal, output from the cascade signal terminal OT, is held at a low level, and the gate sample signal, output from the driver output terminal OUT, is also held at a low level.The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the driver output terminal OUT is at a low level.

[0107] In the following time periods, the shift register unit repeats the work processes of stages H1 ~ H3.

[0108] In some embodiments of the present disclosure, as in Fig. As shown in Figure 7, the second output control signal cs2 comprises a fixed voltage signal section with a first electrical level V1 and a fixed voltage signal section with a second electrical level V2, wherein the fixed voltage signal section with the first electrical level V1 is input to some of the shift register units and the fixed voltage signal section with the second electrical level V2 is input to the remaining shift register units.

[0109] In one example, the fixed voltage signal section with the first electrical level V1 of the second output control signal cs2 is fed into the shift register units SR1, SR2, SR6, SR7 and SR8, and the fixed voltage signal section with the second electrical level V2 of the second output control signal cs2 is fed into the shift register units SR3, SR4 and SR5.

[0110] In one example, in local driver mode, the second output control signal cs2 is fed into the output control signal terminals of the shift register units via a first output control signal line CS-1 and a second output control signal line CS-2. A signal timing diagram of the gate sampling signals out1 to out8, which are fed from the sampling lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) in Fig. 4) will be loaded, is in Fig. 7 shown.

[0111] As in Fig. Figure 7 shows that "in" denotes an input signal of an input signal terminal IN, ck1 denotes a first clock signal of a first clock signal terminal CK1, ck2 denotes a second clock signal of a second clock signal terminal CK2, cs2 denotes a second output control signal of an output control signal terminal CS, ot1 is a cascade signal of a cascade signal terminal OT in a first shift register unit SR1, ot2 is a cascade signal of a cascade signal terminal OT in a second shift register unit SR2, ot3 is a cascade signal of a cascade signal terminal OT in a third shift register unit SR3, ot4 is a cascade signal of a cascade signal terminal OT in a fourth shift register unit SR4, ot5 is a cascade signal of a cascade signal terminal OT in a fifth shift register unit SR5, and ot6 is a cascade signal of a cascade signal terminal OT in a sixth shift register unit SR6.ot7 represents a cascade signal from a cascade signal connection OT in a seventh shift register unit SR7, ot8 represents a cascade signal from a cascade signal connection OT in an eighth shift register unit SR8, out1 represents a gate sample signal from a driver output connection OUT in the first shift register unit SR1, out2 represents a gate sample signal from a driver output connection OUT in the second shift register unit SR2, out3 represents a gate sample signal from a driver output connection OUT in the third shift register unit SR3, out4 represents a gate sample signal from a driver output connection OUT in the fourth shift register unit SR4, out5 represents a gate sample signal from a driver output connection OUT in the fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in the sixth shift register unit SR6,out7 represents a gate sampling signal from a driver output connection OUT in the seventh shift register unit SR7, and out8 represents a gate sampling signal from a driver output connection OUT in the eighth shift register unit SR8.

[0112] The following describes the working process of a shift register unit provided in the embodiments of the present disclosure, using a shift register unit setup that is described in Fig. 2 is shown, with reference to the in Fig. The signal timing diagram shown in section 7 is described.

[0113] As in Fig. Figure 2 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a low-level signal, a valid pulse signal of a second reference signal output from a second reference signal terminal VREF2 is a low-level signal, a valid pulse signal of a third reference signal output from a third reference signal terminal VREF3 is a high-level signal, a valid pulse signal of a fourth reference signal output from a fourth reference signal terminal VREF4 is a high-level signal, a valid pulse signal of a fifth reference signal output from a fifth reference signal terminal VREF5 is a high-level signal, and a fixed-voltage signal part with a first electrical level V1, which a second output control signal cs2 has,a high-level signal, and a fixed-voltage signal part with a second electrical level V2, which the second output control signal cs2 has, is a low-level signal.

[0114] The gate electrodes of the third transistor M3 and the seventh transistor M7 are connected to the second reference signal terminal VREF2, and the second reference signal terminal VREF2 inputs a low-level signal. The gate electrodes of the fourteenth transistor M14 and the fifteenth transistor M15 are connected to the first reference signal terminal VREF1, and the first reference signal terminal VREF1 inputs a low-level signal. Therefore, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, and the fifteenth transistor M15 are in a normally on state. One gate electrode of the thirteenth transistor M13 is connected to the fifth reference signal terminal VREF5, and the fifth reference signal terminal VREF5 inputs a high-level signal. Therefore, the thirteenth transistor M13 is in a normally off state.To simplify the description, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 at any given time will not be analyzed below.

[0115] In a first stage H1, an input signal "in" provides a high level, a first clock signal ck1 a low level, and a second clock signal ck2 a high level. A first transistor M1 is switched on under the control of the low level of the first clock signal ck1, and the first transistor M1 supplies the high level of the input signal "in" to a third node N3. A second transistor M2 is switched off under the control of the high level of the third node N3. A twelfth transistor M12 is switched off under the control of the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to a second node N2, and a second cascaded transistor T4 and a second output transistor T2 are switched off.A ninth transistor M9 is turned on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 supplies a low level of the second reference signal terminal VREF2 to a fourth node N4. A tenth transistor M10 is turned on under the control of the low level of the fourth node N4, and the tenth transistor M10 supplies a high level of the third reference signal terminal VREF3 to a sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to a gate electrode of a fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to a first electrode of a fifth transistor M5, and the fifth transistor M5 is turned off under the control of the high level of the second clock signal ck2.A first cascaded transistor T3 and a first output transistor T1 are switched off. A sixth transistor M6 is switched on under the control of the low level of the first clock signal ck1, and the sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal "in" to a fifth node N5. An eighth transistor M8 and an eleventh transistor M11 are switched off under the control of the high level of the fifth node N5. A cascade signal output from a cascade signal terminal OT is held at a low level, and a gate sample signal output from a driver output terminal OUT is held at a low level.

[0116] In a second stage H2, the input signal "in" is low, the first clock signal ck1 is high, and the second clock signal ck2 is low. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 is held high. The second transistor M2 is switched off by the high level of the third node N3. The twelfth transistor M12 is switched off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, and the second cascaded transistor T4 and the second output transistor T2 are switched off. The ninth transistor M9 is switched off by the high level of the first clock signal ck1, and the fourth node N4 is held low.The tenth transistor M10 is turned on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to a first node N1. The first cascade transistor T3 and the first output transistor T1 are turned on by the low level signal from the first node N1.The first cascade transistor, T3, supplies a high level of the fourth reference signal terminal, VREF4, to the cascade signal terminal, OT. The first output transistor, T1, supplies a high level of the first output control signal, cs1, from an output control signal terminal, CS, to the driver output terminal, OUT. The sixth transistor, M6, is turned off under the control of the high level of the first clock signal, ck1, and the fifth node, N5, is held at a high level. The eighth transistor, M8, and the eleventh transistor, M11, are turned off under the control of the high level of the fifth node, N5. The cascade signal output from the cascade signal terminal, OT, is held at a low level, and the gate sampling signal output from the driver output terminal, OUT, is held at a low level.The cascade signal output from the cascade signal terminal OT is at a high level, and the gate sampling signal output from the driver output terminal OUT is at a high level.

[0117] In a third stage H3, the input signal "in" is low-level, the first clock signal ck1 is low-level, and the second clock signal ck2 is high-level. The first transistor M1 is switched on by the low level of the first clock signal ck1, and M1 outputs the low level of the input signal "in" to the third node N3. The second transistor M2 is switched on by the low level of the third node N3, and M2 outputs the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is switched on by the low level of the third node N3, and M12 outputs the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are switched off.The fifteenth transistor, M15, supplies the low level of the third node, N3, to the second node, N2. The second cascaded transistor, T4, and the second output transistor, T2, are turned on under the control of the low level from the second node, N2. The second cascaded transistor, T4, supplies a low level from the first reference signal terminal, VREF1, to the cascade signal terminal, OT. The second output transistor, T2, supplies the low level from the first reference signal terminal, VREF1, to the driver output terminal, OUT. The ninth transistor, M9, is turned on under the control of the low level from the first clock signal, ck1. The ninth transistor, M9, supplies the low level from the second reference signal terminal, VREF2, to the fourth node, N4.The tenth transistor M10 is switched on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is switched on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is switched off by the high level signal of the second clock signal ck2. The first cascaded transistor T3 and the first output transistor T1 are switched off by the high level signal from the first node N1.The sixth transistor, M6, is turned on under the control of the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the low level of the input signal "in" to the fifth node, N5. The eighth transistor, M8, and the eleventh transistor, M11, are turned on under the control of the low level of the fifth node, N5. The eighth transistor, M8, supplies the low level of the fifth node, N5, to the second node, N2, and the eleventh transistor, M11, supplies the high level of the second clock signal, ck2, to the sixth node, N6. The cascade signal, output from the cascade signal terminal OT, is held at a low level, and the gate sample signal, output from the driver output terminal OUT, is also held at a low level.The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the driver output terminal OUT is at a low level.

[0118] In the following time intervals, the shift register unit repeats the work processes of stages H1 ~ H3.

[0119] In the embodiments of the present disclosure, by controlling a signal of an output control signal terminal, a gate sampling signal of a driver output terminal in an output circuit is controlled such that the sampling of any area of ​​a display board is controlled and the non-sampling of any area of ​​the display board is controlled, thereby reducing power consumption and losses.

[0120] The embodiments of the present disclosure further provide another structural scheme of the shift register unit, as shown in Fig. Figure 8 is shown, which is modified for the implementation methods in the embodiments above. Differences between these embodiments and the embodiments above are described below, without repeating similar content here.

[0121] In some other embodiments of the present disclosure, the input sub-circuit comprises 110, as in Fig. Figure 8 shows a sixteenth transistor M16 and a seventeenth transistor M17, wherein a gate electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal CK1, a first electrode of the sixteenth transistor M16 is coupled to the input signal terminal IN, and a second electrode of the sixteenth transistor M16 is coupled to a seventh node N7; a gate electrode of the seventeenth transistor M17 is coupled to the first clock signal terminal CK1, a first electrode of the seventeenth transistor M17 is coupled to the seventh node N7, and a second electrode of the seventeenth transistor M17 is coupled to the third node N3.

[0122] In some other embodiments of the present disclosure, the control circuit 120 comprises, as in Fig. Figure 8 shows: an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a fifth capacitor C5 and a sixth capacitor C6, wherein a gate electrode of the eighteenth transistor M18 is coupled to the cascaded output terminal OT, a first electrode of the eighteenth transistor M18 is coupled to a third clock signal terminal CK3 and a second electrode of the eighteenth transistor M18 is coupled to the seventh node N7; a gate electrode of the nineteenth transistor M19 is coupled to the input signal terminal IN, a first electrode of the nineteenth transistor M19 is coupled to the first reference signal terminal VREF1 and a second electrode of the nineteenth transistor M19 is coupled to the second node N2;A gate electrode of the twentieth transistor M20 is coupled to the second node N2, a first electrode of the twentieth transistor M20 is coupled to the first reference signal terminal VREF1, and a second electrode of the twentieth transistor M20 is coupled to an eighth node N8; a gate electrode of the twenty-first transistor M21 is coupled to the second node N2, a first electrode of the twenty-first transistor M21 is coupled to the eighth node N8, and a second electrode of the twenty-first transistor M21 is coupled to the third node N3; a gate electrode of the twenty-second transistor M22 is coupled to the third node N3, a first electrode of the twenty-second transistor M22 is coupled to the eighth node N8, and a second electrode of the twenty-second transistor M22 is coupled to a sixth reference signal terminal VREF6;A gate electrode of the twenty-third transistor M23 is coupled to a fourth clock signal terminal CK4, a first electrode of the twenty-third transistor M23 is coupled to the second node N2, and a second electrode of the twenty-third transistor M23 is coupled to the sixth reference signal terminal VREF6; a first electrode of the fifth capacitor C5 is coupled to the first reference signal terminal VREF1, and a second electrode of the fifth capacitor C5 is coupled to the first electrode of the twenty-third transistor M23; a first electrode of the sixth capacitor C6 is coupled to the cascaded output terminal OT, and a second electrode of the sixth capacitor C6 is coupled to the first node N1.

[0123] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 8, the cascade sub-circuit 130 comprises: a first cascaded transistor T3 and a second cascaded transistor T4, wherein a gate electrode of the first cascaded transistor T3 is coupled to the first node N1, a first electrode of the first cascaded transistor T3 is coupled to the cascaded output terminal OT, and a second electrode of the first cascaded transistor T3 is coupled to the third clock signal terminal CK3; a gate electrode of the second cascaded transistor T4 is coupled to the second node N2, a first electrode of the second cascaded transistor T4 is coupled to the first reference signal terminal VREF1, and a second electrode of the second cascaded transistor T4 is coupled to the cascaded output terminal OT.

[0124] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 9, the first output control signals cs-1 and cs-2 are clock signals.

[0125] In one example, in full-screen driver mode, the first output control signals cs-1 and cs-2 are fed into the output control signal connections of the shift register units via a first output control signal line CS-1 and a second output control signal line CS-2, respectively. A timing diagram for the gate sampling signals out1 to out8, which are fed from the sampling lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) is shown. Fig. 4) will be loaded, is in Fig. 9 shown.

[0126] As in Fig. Figure 9 shows that "in" denotes an input signal of an input signal terminal IN, ck1 a first clock signal of a first clock signal terminal CK1, ck3 a third clock signal of a third clock signal terminal CK3, ck4 a fourth clock signal of a fourth clock signal terminal CK4, cs-1 a first output control signal on a first output control line CS-1, cs-2 a first output control signal on a second output control line CS-2, out1 a gate sample signal of a driver output terminal OUT in a first shift register unit SR1, out2 a gate sample signal of a driver output terminal OUT in a second shift register unit SR2, out3 a gate sample signal of a driver output terminal OUT in a third shift register unit SR3, and out4 a gate sample signal of a driver output terminal OUT in a fourth shift register unit SR4.out5 represents a gate sample signal from a driver output connection OUT in a fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sample signal from a driver output connection OUT in a seventh shift register unit SR7, and out8 represents a gate sample signal from a driver output connection OUT in an eighth shift register unit SR8.

[0127] A working process of a shift register unit provided in the embodiments of the present disclosure is described below using a Fig. The shift register unit structure shown in section 8 refers to the structure described in [reference to section 8]. Fig. The signal timing diagram shown in section 9 is described.

[0128] As in Fig. Figure 8 illustrates this with an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a high-level signal, and a valid pulse signal of a sixth reference signal output from a sixth reference signal terminal VREF6 is a low-level signal.

[0129] In a first stage H1, an input signal "in" provides a low level, a first clock signal ck1 provides a low level, a third clock signal ck3 provides a high level, a fourth clock signal ck4 provides a high level, a first output control signal cs-1 on a first output control line CS-1 provides a low level, and a first output control signal cs-2 on a second output control line CS-2 provides a high level. A sixteenth transistor M16 is switched on under the control of the low level of the first clock signal ck1, and the sixteenth transistor M16 supplies the low level of the input signal "in" to a seventh node N7. A seventeenth transistor M17 is switched on under the control of the low level of the first clock signal ck1, and the sixteenth transistor M16 supplies the low level of the seventh node N7 to a third node N3 and a first node N1.A twenty-second transistor, M22, is turned on under the control of the low level of the third node, N3, and the twenty-second transistor, M22, supplies a low level of the sixth reference signal terminal, VREF6, to an eighth node, N8. A nineteenth transistor, M19, is turned on under the control of the low level of the input signal "in," and the nineteenth transistor, M19, supplies a high level of the first reference signal terminal, VREF1, to a second node, N2. A twentieth transistor, M20, is turned off under the control of the high level of the second node, N2. A twenty-first transistor, M21, is turned off under the control of the high level of the second node, N2. A twenty-third transistor, M23, is turned off under the control of the high level of the fourth clock signal, ck4.A second cascaded transistor T4 and a second output transistor T2 are switched off by the high level of the second node N2. A first cascade transistor T3 and a first output transistor T1 are switched on by the low level of the first node N1, with the first cascade transistor T3 supplying the high level of the third clock signal ck3 to a cascade signal terminal OT, and the first output transistor T1 supplying a high-level signal at an output control signal terminal CS to a driver output terminal OUT. An eighteenth transistor M18 is switched off by the high level of a cascade signal. A cascade signal output at cascade signal terminal OT is at a high level, and a gate sampling signal output at driver output terminal OUT is at a high level.

[0130] In a second stage H2, the input signal "in" is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the fourth clock signal ck4 is high, the first output control signal cs-1 on the first output control line CS-1 is high, and the first output control signal cs-2 on the second output control line CS-2 is low. Under the control of the high level of the first clock signal ck1, the sixteenth transistor M16 is switched off, and the seventh node N7 is held at a low level. Under the control of the high level of the first clock signal ck1, the seventeenth transistor M17 is switched off, and the third node N3 and the first node N1 are held at a low level.The twenty-second transistor, M22, is switched on by the low level signal of the third node, N3, and the twenty-second transistor, M22, supplies the low level of the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is switched off by the high level of the input signal "in," and the second node, N2, is held at a high level. The twentieth transistor, M20, is switched off by the high level signal of the second node, N2. The twenty-first transistor, M21, is switched off by the high level signal of the second node, N2. The twenty-third transistor, M23, is switched off by the high level signal of the fourth clock signal, ck4. The second cascaded transistor, T4, and the second output transistor, T2, are switched off by the high level signal of the second node, N2.The first cascaded transistor T3 and the first output transistor T1 are turned on under the control of the low level from the first node N1. The first cascaded transistor T3 supplies the low level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies a low-level signal from its output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned on under the control of a low level from the cascade signal, and the eighteenth transistor M18 supplies the low level of the third clock signal ck3 to the seventh node N7. The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the driver output terminal OUT is at a low level.

[0131] In a third stage H3, the input signal "in" is high, the first clock signal ck1 is high, the third clock signal ck3 is high, the fourth clock signal ck4 is low, the first output control signal cs-1 on the first output control line CS-1 is low, and the first output control signal cs-2 on the second output control line CS-2 is high. Under the control of the high level of the first clock signal ck1, the sixteenth transistor M16 is switched off, and the seventh node N7 is held at a low level. Under the control of the high level of the first clock signal ck1, the seventeenth transistor M17 is switched off, and the third node N3 and the first node N1 are held at a low level.The twenty-second transistor, M22, is turned on by the low level signal from the third node, N3, and supplies the low level signal from the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is turned off by the high level signal from the input "in", and the second node, N2, is held at a high level. The twentieth transistor, M20, is turned off by the high level signal from the second node, N2. The twenty-first transistor, M21, is turned off by the high level signal from the second node, N2. The twenty-third transistor, M23, is turned on by the low level signal from the fourth clock signal, ck4.The second cascaded transistor T4 and the second output transistor T2 are switched on by the low level signal of the second node N2. The second cascaded transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The first cascaded transistor T3 and the first output transistor T1 are switched on by the low level signal of the first node N1. The first cascaded transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high level signal at the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is switched off by the high level signal of the cascade signal.The cascade signal output from the cascade signal terminal OT is at a high level, and the gate sampling signal output from the driver output terminal OUT is at a high level.

[0132] In the following time intervals, the shift register unit repeats the work processes of stages H1 ~ H3.

[0133] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 10, the second output control signals cs-1' and cs-2' comprise a clock signal segment and a fixed voltage signal segment with a first electrical level V1. The clock signal segment in the second output control signals cs-1' and cs-2' is fed to some of the shift register units, and the fixed voltage signal segment with the first electrical level in the second output control signals cs-1' and cs-2' is fed to the remaining shift register units. In one example, the clock signal segment in the second output control signals cs-1' and cs-2' is fed to shift register units SR1, SR2, SR6, SR7, and SR8, and the fixed voltage signal segment with the first electrical level V1 in the second output control signals cs-1' and cs-2' is fed to shift register units SR3, SR4, and SR5.

[0134] In one example, in local driver mode, the second output control signals cs-1' and cs-2' are fed into the output control signal connections of the shift register units via a first output control signal line CS-1 and a second output control signal line CS-2, respectively. A signal timing diagram of the signals through the scan lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) is shown. Fig. 4) The loaded gate sampling signals out1 to out8 are in Fig. 10 shown.

[0135] As in Fig. Figure 10 shows that "in" denotes an input signal of an input signal terminal IN, ck1 a first clock signal of a first clock signal terminal CK1, ck3 a third clock signal of a third clock signal terminal CK3, ck4 a fourth clock signal of a fourth clock signal terminal CK4, cs-1' a second output control signal on a first output control line CS-1, cs-2' a second output control signal on a second output control line CS-2, out1 a gate sample signal of a driver output terminal OUT in a first shift register unit SR1, out2 a gate sample signal of a driver output terminal OUT in a second shift register unit SR2, out3 a gate sample signal of a driver output terminal OUT in a third shift register unit SR3, and out4 a gate sample signal of a driver output terminal OUT in a fourth shift register unit SR4.out5 represents a gate sample signal from a driver output connection OUT in a fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sample signal from a driver output connection OUT in a seventh shift register unit SR7, and out8 represents a gate sample signal from a driver output connection OUT in an eighth shift register unit SR8.

[0136] A working process of a shift register unit provided in the embodiments of the present disclosure is described below using a Fig. The shift register unit structure shown in section 8 refers to the structure described in [reference to section 8]. Fig. The signal timing diagram shown in section 10 is described.

[0137] As in Fig. Figure 8 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a high-level signal, and a valid pulse signal of a sixth reference signal output from a sixth reference signal terminal VREF6 is a low-level signal.

[0138] In a first stage H1, an input signal "in" provides a low level, a first clock signal ck1 provides a low level, a third clock signal ck3 provides a high level, a fourth clock signal ck4 provides a high level, a second output control signal cs-1' on a first output control line CS-1 provides a low level, and a second output control signal cs-2' on a second output control line CS-2 provides a high level. A sixteenth transistor M16 is switched on under the control of the low level of the first clock signal ck1, and the sixteenth transistor M16 supplies the low level of the input signal "in" to a seventh node N7. A seventeenth transistor M17 is switched on under the control of the low level of the first clock signal ck1, and the sixteenth transistor M16 supplies the low level of the seventh node N7 to a third node N3 and a first node N1.A twenty-second transistor, M22, is turned on by the low level of the third node, N3, and outputs a low level from the sixth reference signal terminal, VREF6, to an eighth node, N8. A nineteenth transistor, M19, is turned on by the low level of the input signal "in," and outputs a high level from the first reference signal terminal, VREF1, to a second node, N2. A twentieth transistor, M20, is turned off by the high level of the second node, N2. A twenty-first transistor, M21, is turned off by the high level of the second node, N2. A twenty-third transistor, M23, is turned off by the high level of the fourth clock signal, ck4.A second cascaded transistor T4 and a second output transistor T2 are switched off by the high level of the second node N2. A first cascade transistor T3 and a first output transistor T1 are switched on by the low level of the first node N1, with the first cascade transistor T3 supplying the high level of the third clock signal ck3 to a cascade signal terminal OT, and the first output transistor T1 supplying a high-level signal at an output control signal terminal CS to a driver output terminal OUT. An eighteenth transistor M18 is switched off by the high level of a cascade signal. A cascade signal output at cascade signal terminal OT is at a high level, and a gate sampling signal output at driver output terminal OUT is at a high level.

[0139] In a second stage H2, the input signal "in" is high, the first clock signal, ck1, is high, the third clock signal, ck3, is low, the fourth clock signal, ck4, is high, the second output control signal, cs-1', on the first output control line, CS-1, is high, and the second output control signal, cs-2', on the second output control line, CS-2, is low. Under the control of the high level of the first clock signal, ck1, the sixteenth transistor, M16, is turned off, and the seventh node, N7, is held at a low level. Under the control of the high level of the first clock signal, ck1, the seventeenth transistor, M17, is turned off, and the third node, N3, and the first node, N1, are held at a low level.The twenty-second transistor, M22, is switched on by the low level signal of the third node, N3, and the twenty-second transistor, M22, supplies the low level of the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is switched off by the high level of the input signal "in," and the second node, N2, is held at a high level. The twentieth transistor, M20, is switched off by the high level signal of the second node, N2. The twenty-first transistor, M21, is switched off by the high level signal of the second node, N2. The twenty-third transistor, M23, is switched off by the high level signal of the fourth clock signal, ck4. The second cascaded transistor, T4, and the second output transistor, T2, are switched off by the high level signal of the second node, N2.The first cascaded transistor T3 and the first output transistor T1 are turned on under the control of the low level from the first node N1. The first cascaded transistor T3 supplies the low level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies a low-level signal from the output control terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is turned on under the control of a low level from the cascade signal, and the eighteenth transistor M18 supplies the low level of the third clock signal ck3 to the seventh node N7. The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the driver output terminal OUT is at a low level.

[0140] In a third stage H3, the input signal "in" is high, the first clock signal ck1 is high, the third clock signal ck3 is high, the fourth clock signal ck4 is low, the second output control signal cs-1' on the first output control line CS-1 is low, and the second output control signal cs-2' on the second output control line CS-2 is high. Under the control of the high level of the first clock signal ck1, the sixteenth transistor M16 is turned off, and the seventh node N7 is held at a low level. Under the control of the high level of the first clock signal ck1, the seventeenth transistor M17 is turned off, and the third node N3 and the first node N1 are held at a low level.The twenty-second transistor, M22, is turned on by the low level signal from the third node, N3, and supplies the low level signal from the sixth reference signal terminal, VREF6, to the eighth node, N8. The nineteenth transistor, M19, is turned off by the high level signal from the input "in", and the second node, N2, is held at a high level. The twentieth transistor, M20, is turned off by the high level signal from the second node, N2. The twenty-first transistor, M21, is turned off by the high level signal from the second node, N2. The twenty-third transistor, M23, is turned on by the low level signal from the fourth clock signal, ck4.The second cascaded transistor T4 and the second output transistor T2 are switched on by the low level signal of the second node N2. The second cascaded transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The first cascaded transistor T3 and the first output transistor T1 are switched on by the low level signal of the first node N1. The first cascaded transistor T3 supplies the high level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies the high level signal at the output control signal terminal CS to the driver output terminal OUT. The eighteenth transistor M18 is switched off by the high level signal of the cascade signal.The cascade signal output from the cascade signal terminal OT is at a high level, and the gate sampling signal output from the driver output terminal OUT is at a high level.

[0141] In the following time intervals, the shift register unit repeats the work processes of stages H1 ~ H3.

[0142] In the embodiments of the present disclosure, by controlling a signal of an output control signal terminal, a gate sampling signal of a driver output terminal in an output circuit is controlled such that the sampling of any area of ​​a display board is controlled and the non-sampling of any area of ​​the display board is controlled, thereby reducing power consumption and losses.

[0143] The embodiments of the present disclosure further provide another structural scheme of the shift register unit, as shown in Fig. Figure 11 shows the embodiments modified for the embodiments described above. Differences between these embodiments and the embodiments described above are explained below, and similar content is not repeated here.

[0144] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 11, the first output circuit 210 is coupled to the cascaded output terminal OT in the shift register 100, and the output control circuit 220 is configured to transmit the signal of the output control signal terminal CS to the driver output terminal OUT in response to a signal from the cascaded output terminal OT.

[0145] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 11, the gate electrode of the first output transistor T1 is coupled to the cascaded output terminal OT, the first electrode of the first output transistor T1 is coupled to the output control signal terminal CS, and the second electrode of the first output transistor T1 is coupled to the driver output terminal OUT.

[0146] In some other embodiments of the present disclosure, the control circuit comprises, as in Fig. Figure 11 shows a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a seventh capacitor C7, and an eighth capacitor C8, wherein a gate electrode of the twenty-fourth transistor M24 is coupled to the first clock signal terminal CK1, a first electrode of the twenty-fourth transistor M24 is coupled to a seventh reference signal terminal VREF7, and a second electrode of the twenty-fourth transistor M24 is coupled to the second node N2; a gate electrode of the twenty-fifth transistor M25 is coupled to the third node N3, a first electrode of the twenty-fifth transistor M25 is coupled to the second node N2, and a second electrode of the twenty-fifth transistor M25 is coupled to the first clock signal terminal CK1;A gate electrode of the twenty-sixth transistor M26 is coupled to the second node N2, a first electrode of the twenty-sixth transistor M26 is coupled to the first reference signal terminal VREF1, and a second electrode of the twenty-sixth transistor M26 is coupled to a first electrode of the twenty-seventh transistor M27; a gate electrode of the twenty-seventh transistor M27 is coupled to the third clock signal terminal CK3, and a second electrode of the twenty-seventh transistor M27 is coupled to a first electrode of the twenty-eighth transistor M28; a gate electrode of the twenty-eighth transistor M28 is coupled to the seventh reference signal terminal VREF7, the first electrode of the twenty-eighth transistor M28 is coupled to the third node N3, and a second electrode of the twenty-eighth transistor M28 is coupled to the first node N1;A first electrode of the seventh capacitor C7 is coupled to the first reference signal terminal VREF1, and a second electrode of the seventh capacitor C7 is coupled to the first node N1; a first electrode of the eighth capacitor C8 is coupled to the cascaded output terminal OT, and a second electrode of the eighth capacitor C8 is coupled to the first node N1.

[0147] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 12, the first output control signals cs-1 and cs-2 are clock signals.

[0148] In one example, in full-screen driver mode, the first output control signals cs-1 and cs-2 are fed to the output control signal connections of the shift register units via a first output control signal line CS-1 and a second output control signal line CS-2, respectively. A signal timing diagram of the gate sampling signals out1 to out8, which are fed from the sampling lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) is shown. Fig. 4) will be loaded, is in Fig. 12 shown.

[0149] As in Fig. Figure 12 shows that "in" denotes an input signal of an input signal terminal IN, ck1 denotes a first clock signal of a first clock signal terminal CK1, ck3 denotes a third clock signal of a third clock signal terminal CK3, cs-1 denotes a first output control signal on a first output control line CS-1, cs-2 denotes a first output control signal on a second output control line CS-2, out1 is a gate sample signal of a driver output terminal OUT in a first shift register unit SR1, out2 is a gate sample signal of a driver output terminal OUT in a second shift register unit SR2, out3 is a gate sample signal of a driver output terminal OUT in a third shift register unit SR3, out4 is a gate sample signal of a driver output terminal OUT in a fourth shift register unit SR4, and out5 is a gate sample signal of a driver output terminal OUT in a fifth shift register unit SR5.out6 represents a gate sampling signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sampling signal from a driver output connection OUT in a seventh shift register unit SR7, and out8 represents a gate sampling signal from a driver output connection OUT in an eighth shift register unit SR8.

[0150] A working process of a shift register unit provided in the embodiments of the present disclosure is described below using a Fig. 11 shift register unit structure shown with reference to the one in Fig. The signal timing diagram shown in section 12 is described.

[0151] As in Fig. Figure 11 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a high-level signal, and a valid pulse signal of a seventh reference signal output from a seventh reference signal terminal VREF7 is a low-level signal.

[0152] A twenty-eighth transistor, M28, is coupled to the seventh reference signal terminal, VREF7, and the seventh reference signal terminal, VREF7, inputs a low-level signal. Therefore, the twenty-eighth transistor, M28, is normally in an on-state. For the sake of simplicity, the state of the twenty-eighth transistor, M28, at any given time will not be analyzed below.

[0153] In a first stage H1, an input signal "in" provides a low level, a first clock signal ck1 provides a low level, a third clock signal ck3 provides a high level, a first output control signal cs-1 on a first output control line CS-1 provides a low level, and a first output control signal cs-2 on a second output control line CS-2 provides a high level. A first transistor M1 is switched on under the control of the low level of the first clock signal ck1, and the first transistor M1 supplies the low level of the input signal "in" to a third node N3. The 28 transistor M28 supplies the low level of the third node N3 to a first node N1.A first cascade transistor T3 and a first output transistor T1 are switched on under the control of the low level of the first node N1. The first cascade transistor T3 supplies the high level of the third clock signal ck3 to a cascade signal terminal OT, and the first output transistor T1 supplies a high-level signal at an output control terminal CS to a driver output terminal OUT. A twenty-fifth transistor M25 is switched on under the control of the low level of the third node N3, and the twenty-fifth transistor M25 supplies the low level of the first clock signal ck1 to a second node N2. A twenty-fourth transistor M24 is switched on under the control of the low level of the first clock signal ck1, and the twenty-fourth transistor M24 supplies a low level of the seventh reference signal terminal VREF7 to the second node N2.A twenty-sixth transistor, M26, is switched on under the control of the low level of the second node, N2. This transistor then supplies a high level from the first reference signal terminal, VREF1, to the first electrode of a twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off under the control of the high level of the third clock signal, ck3. A second cascade transistor, T4, and a second output transistor, T2, are switched on under the control of the low level of the second node, N2. The second cascade transistor, T4, supplies the high level from the first reference signal terminal, VREF1, to the cascade signal terminal, OT, and the second output transistor, T2, supplies the high level from the first reference signal terminal, VREF1, to the driver output terminal, OUT.A cascade signal output from the cascade signal terminal OT is at a high level, and a gate sample signal output from the driver output terminal OUT is at a high level.

[0154] In a second stage H1, the input signal "in" is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the first output control signal cs-1 on the first output control line CS-1 is high, and the first output control signal cs-2 on the second output control line CS-2 is low. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 is held at a low level. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1.The first cascade transistor T3 supplies the low level of the third clock signal ck3 to the cascade signal terminal OT, and the first output transistor T1 supplies a low-level signal from the output control signal terminal CS to the driver output terminal OUT. The twenty-fourth transistor M24 is switched off under the control of the high level of the first clock signal ck1, and the second node N2 is held at a low level. The twenty-fifth transistor M25 is switched on under the control of the low level of the third node N3; the twenty-fifth transistor M25 supplies the high level of the first clock signal ck1 to the second node N2, and the second node N2 is held at a high level.The twenty-sixth transistor, M26, is switched off by the high level of the second node, N2, and the twenty-seventh transistor, M27, is switched on by the low level of the third clock signal, ck3. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The cascade signal output from the cascade signal terminal, OT, is at a low level, and the gate sampling signal output from the driver output terminal, OUT, is at a low level.

[0155] In a third stage H1, the input signal "in" is high, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 on the first output control line CS-1 is low, and the first output control signal cs-2 on the second output control line CS-2 is high. The first transistor M1 is turned on by the low level of the first clock signal ck1, and transistor M1 outputs the high level of the input signal "in" to the third node N3. The twenty-eighth transistor M28 outputs the high level of the third node N3 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1.The twenty-fifth transistor, M25, is switched off by the high level of the third node, N3. The twenty-fourth transistor, M24, is switched on by the low level of the first clock signal, ck1, and the twenty-fourth transistor, M24, supplies the low level of the seventh reference signal terminal, VREF7, to the second node, N2. The twenty-sixth transistor, M26, is switched on by the low level of the second node, N2, and the twenty-sixth transistor, M26, supplies the high level of the first reference signal terminal, VREF1, to the first electrode of the twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off by the high level of the third clock signal, ck3.The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The cascade signal output at cascade signal terminal OT is at a high level, and the gate sampling signal output at driver output terminal OUT is at a high level.

[0156] In the following time intervals, the shift register unit repeats the work processes of stages H1 ~ H3.

[0157] In some other embodiments of the present disclosure, as in Fig. As shown in Figure 13, the second output control signals cs-1' and cs-2' comprise a clock signal section and a fixed voltage signal section with a first electrical level V1. The clock signal section in the second output control signals cs-1' and cs-2' is input to some of the shift register units, and the fixed voltage signal section with the first electrical level in the second output control signals cs-1' and cs-2' is input to the remaining shift register units. In one example, the clock signal section in the second output control signals cs-1' and cs-2' is input to shift register units SR1, SR2, SR6, SR7, and SR8, and the fixed voltage signal section with the first electrical level V1 in the second output control signals cs-1' and cs-2' is input to shift register units SR3, SR4, and SR5.

[0158] In the following time periods, the shift register unit repeats the work processes of stages H1 ~ H3.

[0159] In one example, in local driver mode, the second output control signals cs-1' and cs-2' are fed into the output control terminals of the shift register units via a first output control line CS-1 and a second output control line CS-2, respectively. A signal timing diagram of the signals from the scan lines (such as GA1, GA2, GA3, GA4, GA5, GA6, GA7, and GA8) is shown. Fig. 4) The loaded gate sampling signals out1 to out8 are in Fig. 13 shown.

[0160] As in Fig. Figure 13 shows that "in" denotes an input signal of an input signal terminal IN, ck1 denotes a first clock signal of a first clock signal terminal CK1, ck3 denotes a third clock signal of a third clock signal terminal CK3, cs-1' denotes a second output control signal on a first output control line CS-1, cs-2' denotes a second output control signal on a second output control line CS-2, out1 represents a gate sample signal of a driver output terminal OUT in a first shift register unit SR1, out2 represents a gate sample signal of a driver output terminal OUT in a second shift register unit SR2, out3 represents a gate sample signal of a driver output terminal OUT in a third shift register unit SR3, and out4 represents a gate sample signal of a driver output terminal OUT in a fourth shift register unit SR4.out5 represents a gate sample signal from a driver output connection OUT in a fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sample signal from a driver output connection OUT in a seventh shift register unit SR7, and out8 represents a gate sample signal from a driver output connection OUT in an eighth shift register unit SR8.

[0161] A working process of a shift register unit provided in the embodiments of the present disclosure is described below using a Fig. 11 shift register unit structure shown with reference to the one in Fig. The signal timing diagram shown in section 13 is described.

[0162] As in Fig. Figure 11 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a high-level signal, and a valid pulse signal of a seventh reference signal output from a seventh reference signal terminal VREF7 is a low-level signal.

[0163] A twenty-eighth transistor, M28, is coupled to the seventh reference signal terminal, VREF7, and the seventh reference signal terminal, VREF7, inputs a low-level signal. Therefore, the twenty-eighth transistor, M28, is normally in an on-state. For the sake of simplicity, the state of the twenty-eighth transistor, M28, at any given time will not be analyzed below.

[0164] In a first stage H1, an input signal "in" provides a low level, a first clock signal ck1 provides a low level, a third clock signal ck3 provides a high level, a first output control signal cs-1 on a first output control line CS-1 provides a low level, and a first output control signal cs-2 on a second output control line CS-2 provides a high level. A first transistor M1 is switched on under the control of the low level of the first clock signal ck1, and the first transistor M1 supplies the low level of the input signal "in" to a third node N3. The twenty-eighth transistor M28 supplies the low level of the third node N3 to a first node N1.A first cascade transistor T3 and a first output transistor T1 are switched on under the control of the low level of the first node N1. The first cascade transistor T3 supplies the high level of the third clock signal ck3 to a cascade signal terminal OT, and the first output transistor T1 supplies a high-level signal at an output control signal terminal CS to a driver output terminal OUT. A twenty-fifth transistor M25 is switched on under the control of the low level of the third node N3, and the twenty-fifth transistor M25 supplies the low level of the first clock signal ck1 to a second node N2. A twenty-fourth transistor M24 is switched on under the control of the low level of the first clock signal ck1, and the twenty-fourth transistor M24 supplies a low level of the seventh reference signal terminal VREF7 to the second node N2.A twenty-sixth transistor, M26, is switched on under the control of the low level of the second node, N2. This transistor then supplies a high level from the first reference signal terminal, VREF1, to the first electrode of a twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off under the control of the high level of the third clock signal, ck3. A second cascaded transistor, T4, and a second output transistor, T2, are switched on under the control of the low level of the second node, N2. The second cascaded transistor, T4, supplies the high level from the first reference signal terminal, VREF1, to the cascade signal terminal, OT, and the second output transistor, T2, supplies the high level from the first reference signal terminal, VREF1, to the driver output terminal, OUT.A cascade signal output from the cascade signal terminal OT is at a high level, and a gate sample signal output from the driver output terminal OUT is at a high level.

[0165] In a second stage H1, the input signal "in" is high, the first clock signal ck1 is high, the third clock signal ck3 is low, the first output control signal cs-1 on the first output control line CS-1 is high, and the first output control signal cs-2 on the second output control line CS-2 is low. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 is held at a low level. The twenty-eighth transistor M28 supplies the low level of the third node N3 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are switched off by the high level of the first node N1.The first cascaded transistor, T3, supplies the low level of the third clock signal, ck3, to the cascade signal terminal OT, and the first output transistor, T1, supplies a low-level signal from the output control terminal CS to the driver output terminal OUT. The twenty-fourth transistor, M24, is switched off under the control of the high level of the first clock signal, ck1, and the second node, N2, is held at a low level. The twenty-fifth transistor, M25, is switched on under the control of the low level of the third node, N3. The twenty-fifth transistor, M25, supplies the high level of the first clock signal, ck1, to the second node, N2, and the second node, N2, is held at a high level.The twenty-sixth transistor, M26, is switched off by the high level of the second node, N2, and the twenty-seventh transistor, M27, is switched on by the low level of the third clock signal, ck3. The second cascade transistor, T4, and the second output transistor, T2, are switched off by the high level of the second node, N2. The cascade signal output from the cascade signal terminal, OT, is at a low level, and the gate sampling signal output from the driver output terminal, OUT, is at a low level.

[0166] In a third stage H1, the input signal "in" is high, the first clock signal ck1 is low, the third clock signal ck3 is high, the first output control signal cs-1 on the first output control line CS-1 is low, and the first output control signal cs-2 on the second output control line CS-2 is high. The first transistor M1 is turned on by the low level of the first clock signal ck1, and transistor M1 outputs the high level of the input signal "in" to the third node N3. The twenty-eighth transistor M28 outputs the high level of the third node N3 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are turned off by the high level of the first node N1.The twenty-fifth transistor, M25, is switched off by the high level of the third node, N3. The twenty-fourth transistor, M24, is switched on by the low level of the first clock signal, ck1, and the twenty-fourth transistor, M24, supplies the low level of the seventh reference signal terminal, VREF7, to the second node, N2. The twenty-sixth transistor, M26, is switched on by the low level of the second node, N2, and the twenty-sixth transistor, M26, supplies the high level of the first reference signal terminal, VREF1, to the first electrode of the twenty-seventh transistor, M27. The twenty-seventh transistor, M27, is switched off by the high level of the third clock signal, ck3.The second cascade transistor T4 and the second output transistor T2 are switched on by the low level of the second node N2. The second cascade transistor T4 supplies the high level of the first reference signal terminal VREF1 to the cascade signal terminal OT, and the second output transistor T2 supplies the high level of the first reference signal terminal VREF1 to the driver output terminal OUT. The cascade signal output at cascade signal terminal OT is at a high level, and the gate sampling signal output at driver output terminal OUT is at a high level.

[0167] In the following time periods, the shift register unit repeats the work processes of stages H1 ~ H3.

[0168] As in Fig. Figure 6 shows that "in" denotes an input signal of an input signal terminal IN, ck1 denotes a first clock signal of a first clock signal terminal CK1, ck2 denotes a second clock signal of a second clock signal terminal CK2, cs1 denotes a first output control signal of an output control signal terminal CS, ot1 a cascade signal of a cascade signal terminal OT in a first shift register unit SR1, ot2 a cascade signal of a cascade signal terminal OT in a second shift register unit SR2, ot3 a cascade signal of a cascade signal terminal OT in a third shift register unit SR3, ot4 a cascade signal of a cascade signal terminal OT in a fourth shift register unit SR4, ot5 a cascade signal of a cascade signal terminal OT in a fifth shift register unit SR5, and ot6 a cascade signal of a cascade signal terminal OT in a sixth shift register unit SR6.ot7 represents a cascade signal from a cascade signal connection OT in a seventh shift register unit SR7, ot8 represents a cascade signal from a cascade signal connection OT in an eighth shift register unit SR8, out1 represents a gate sample signal from a driver output connection OUT in the first shift register unit SR1, out2 represents a gate sample signal from a driver output connection OUT in the second shift register unit SR2, out3 represents a gate sample signal from a driver output connection OUT in the third shift register unit SR3, out4 represents a gate sample signal from a driver output connection OUT in the fourth shift register unit SR4, out5 represents a gate sample signal from a driver output connection OUT in the fifth shift register unit SR5, out6 represents a gate sample signal from a driver output connection OUT in the sixth shift register unit SR6,out7 represents a gate sampling signal from a driver output connection OUT in the seventh shift register unit SR7, and out8 represents a gate sampling signal from a driver output connection OUT in the eighth shift register unit SR8.

[0169] The following describes the working process of a shift register unit provided in the embodiments of the present disclosure, using a Fig. 21 shift register unit structure shown with reference to the one in Fig. The signal timing diagram shown in section 6 is described.

[0170] As in Fig. Figure 21 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a low-level signal, a valid pulse signal of a second reference signal output from a second reference signal terminal VREF2 is a low-level signal, a valid pulse signal of a third reference signal output from a third reference signal terminal VREF3 is a high-level signal, a valid pulse signal of a fourth reference signal output from a fourth reference signal terminal VREF4 is a high-level signal, a valid pulse signal of a fifth reference signal output from a fifth reference signal terminal VREF5 is a high-level signal, and a fixed voltage signal with a first electrical level V1.which has a first output control signal cs1, a high-level signal.

[0171] The gate electrodes of the third transistor M3 and the seventh transistor M7 are connected to the second reference signal terminal VREF2, and the second reference signal terminal VREF2 inputs a low-level signal. The gate electrodes of the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are connected to the first reference signal terminal VREF1, and the first reference signal terminal VREF1 inputs a low-level signal. Therefore, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are in a normally on state. A gate electrode of the thirteenth transistor M13 is connected to the fifth reference signal terminal VREF5, and the fifth reference signal terminal VREF5 inputs a high-level signal.Therefore, the thirteenth transistor M13 is in a normally off state. For the sake of simplicity, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given time will not be analyzed below.

[0172] In a first stage H1, an input signal "in" provides a high level, a first clock signal ck1 a low level, and a second clock signal ck2 a high level. A first transistor M1 is switched on under the control of the low level of the first clock signal ck1, and the first transistor M1 supplies the high level of the input signal "in" to a third node N3. A second transistor M2 is switched off under the control of the high level of the third node N3. A twelfth transistor M12 is switched off under the control of the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to a second node N2, and a second cascaded transistor T4 and a second output transistor T2 are switched off.A ninth transistor M9 is turned on under the control of the low level of the first clock signal ck1, and the ninth transistor M9 supplies a low level of the second reference signal terminal VREF2 to a fourth node N4. A tenth transistor M10 is turned on under the control of the low level of the fourth node N4, and the tenth transistor M10 supplies a high level of the third reference signal terminal VREF3 to a sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to a gate electrode of a fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to a first electrode of a fifth transistor M5, and the fifth transistor M5 is turned off under the control of the high level of the second clock signal ck2.A first cascaded transistor T3 and a first output transistor T1 are switched off. A sixth transistor M6 is switched on under the control of the low level of the first clock signal ck1, and the sixth transistor M6 and the seventh transistor M7 supply the high level of the input signal "in" to a fifth node N5. An eighth transistor M8 and an eleventh transistor M11 are switched off under the control of the high level of the fifth node N5. A cascade signal output from a cascade signal terminal OT is held at a low level, and a gate sample signal output from a driver output terminal OUT is held at a low level.

[0173] In a second stage H2, the input signal "in" is low, the first clock signal ck1 is high, and the second clock signal ck2 is low. The first transistor M1 is switched off by the high level of the first clock signal ck1, and the third node N3 is held high. The second transistor M2 is switched off by the high level of the third node N3. The twelfth transistor M12 is switched off by the high level of the third node N3. The fifteenth transistor M15 supplies the high level of the third node N3 to the second node N2, and the second cascaded transistor T4 and the second output transistor T2 are switched off. The ninth transistor M9 is switched off by the high level of the first clock signal ck1, and the fourth node N4 is held low.The tenth transistor M10 is turned on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the low level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is turned on by the low level of the second clock signal ck2. The fifth transistor M5 supplies the low level of the first electrode to a first node N1. The first cascade transistor T3 and the first output transistor T1 are turned on by the low level signal from the first node N1.The first cascade transistor, T3, supplies a high level of the fourth reference signal terminal, VREF4-, to the cascade signal terminal, OT. The first output transistor, T1, supplies a high level of the first output control signal, cs1, from an output control signal terminal, CS, to the driver output terminal, OUT. The sixth transistor, M6, is turned off under the control of the high level of the first clock signal, ck1, and the fifth node, N5, is held at a high level. The eighth transistor, M8, and the eleventh transistor, M11, are turned off under the control of the high level of the fifth node, N5. The cascade signal output from the cascade signal terminal, OT, is held at a low level, and the gate sampling signal output from the driver output terminal, OUT, is held at a low level.The cascade signal output from the cascade signal terminal OT is at a high level, and the gate sampling signal output from the driver output terminal OUT is at a high level.

[0174] In a third stage H3, the input signal "in" is low-level, the first clock signal ck1 is low-level, and the second clock signal ck2 is high-level. The first transistor M1 is switched on by the low level of the first clock signal ck1, and M1 outputs the low level of the input signal "in" to the third node N3. The second transistor M2 is switched on by the low level of the third node N3, and M2 outputs the low level of the first clock signal ck1 to the fourth node N4. The twelfth transistor M12 is switched on by the low level of the third node N3, and M12 outputs the high level of the fourth reference signal terminal VREF4 to the first node N1. The first cascaded transistor T3 and the first output transistor T1 are switched off.The fifteenth transistor, M15, supplies the low level of the third node, N3, to the second node, N2. The second cascaded transistor, T4, and the second output transistor, T2, are turned on under the control of the low level from the second node, N2. The second cascaded transistor, T4, supplies a low level from the first reference signal terminal, VREF1, to the cascade signal terminal, OT. The second output transistor, T2, supplies the low level from the first reference signal terminal, VREF1, to the driver output terminal, OUT. The ninth transistor, M9, is turned on under the control of the low level from the first clock signal, ck1. The ninth transistor, M9, supplies the low level from the second reference signal terminal, VREF2, to the fourth node, N4.The tenth transistor M10 is turned on by the low level signal from the fourth node N4, and transistor M10 supplies the high level of the third reference signal terminal VREF3 to the sixth node N6. The third transistor M3 supplies the low level of the fourth node N4 to the gate electrode of the fourth transistor M4, and the fourth transistor M4 is turned on. The fourth transistor M4 supplies the high level of the second clock signal ck2 to the first electrode of the fifth transistor M5, and the fifth transistor M5 is turned off by the high level signal of the second clock signal ck2. The first cascaded transistor, T3, and the first output transistor T1 are turned off by the high level signal from the first node N1.The sixth transistor, M6, is turned on under the control of the low level of the first clock signal, ck1. The sixth transistor, M6, and the seventh transistor, M7, supply the low level of the input signal "in" to the fifth node, N5. The eighth transistor, M8, and the eleventh transistor, M11, are turned on under the control of the low level of the fifth node, N5. The eighth transistor, M8, supplies the low level of the fifth node, N5, to the second node, N2, and the eleventh transistor, M11, supplies the high level of the second clock signal, ck2, to the sixth node, N6. The cascade signal, output from the cascade signal terminal OT, is held at a low level, and the gate sample signal, output from the driver output terminal OUT, is also held at a low level.The cascade signal output from the cascade signal terminal OT is at a low level, and the gate sampling signal output from the driver output terminal OUT is at a low level.

[0175] In the following time periods, the shift register unit repeats the work processes of stages H1 ~ H3.

[0176] As in Fig. 21 and Fig. As shown in Figure 22, the output control signal lines (such as CS-1 and CS-2 in Figure 22) include Fig. 3) a first output control signal line CS-1 and a second output control signal line CS-2, wherein eight adjacent shift register units in the shift register units form a shift register unit group, the first output control signal line CS-1 being coupled to output control signal terminals CSs of shift register units in odd-numbered shift register unit groups, and the second output control signal line CS-2 being coupled to output control signal terminals CSs of shift register units in even-numbered shift register unit groups. In an example, the first output control signal line CS-1 is coupled to output control signal terminals CSs of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8, and the second output control signal line CS-2 is coupled to output control signal terminals CSs of shift register units SR9, SR10, SR11, SR12, SR13, SR14,SR15 and SR16 are coupled. "in" represents an input signal from an input signal terminal IN, ck1 represents a first clock signal from a first clock signal terminal CK1, ck2 represents a second clock signal from a second clock signal terminal CK2, cs1 represents a first output control signal from an output control signal terminal CS, out1 represents a gate sample signal from a driver output terminal OUT in a first shift register unit SR1, out2 represents a gate sample signal from a driver output terminal OUT in a second shift register unit SR2, out3 represents a gate sample signal from a driver output terminal OUT in a third shift register unit SR3, out4 represents a gate sample signal from a driver output terminal OUT in a fourth shift register unit SR4, and out5 represents a gate sample signal from a driver output terminal OUT in a fifth shift register unit SR5.out6 represents a gate sample signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sample signal from a driver output connection OUT in a seventh shift register unit SR7, out8 represents a gate sample signal from a driver output connection OUT in an eighth shift register unit SR8, out9 represents a gate sample signal from a driver output connection OUT in a ninth shift register unit SR9, out10 represents a gate sample signal from a driver output connection OUT in a tenth shift register unit SR10, out11 represents a gate sample signal from a driver output connection OUT in an eleventh shift register unit SR11, out12 represents a gate sample signal from a driver output connection OUT in a twelfth shift register unit SR12, out13 represents a gate sample signal from a driver output connection OUT in a thirteenth shift register unit SR13,out14 represents a gate sample signal from a driver output terminal OUT in a fourteenth shift register unit SR14, out15 represents a gate sample signal from a driver output terminal OUT in a fifteenth shift register unit SR15, out16 represents a gate sample signal from a driver output terminal OUT in a sixteenth shift register unit SR16, and out17 represents a gate sample signal from a driver output terminal OUT in a seventeenth shift register unit SR17. The pulse width of the input signal "in" is 18H, the pulse width of a high-level segment or a low-level segment of each clock signal terminal is 2H, and the pulse widths of a valid gate sample signal output from a driver output terminal OUT and of a valid cascade signal output from a cascaded output terminal OT are 18H.

[0177] The following describes the working process of a shift register unit provided in the embodiments of the present disclosure, using a shift register unit setup that is described in Fig. 21 is shown, with reference to the in Fig. The signal timing diagram shown in section 23 is described.

[0178] As in Fig. Figure 21 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a low-level signal, a valid pulse signal of a second reference signal output from a second reference signal terminal VREF2 is a low-level signal, a valid pulse signal of a third reference signal output from a third reference signal terminal VREF3 is a high-level signal, a valid pulse signal of a fourth reference signal output from a fourth reference signal terminal VREF4 is a high-level signal, a valid pulse signal of a fifth reference signal output from a fifth reference signal terminal VREF5 is a high-level signal, and a fixed voltage signal with a first electrical level V1 is shown.which has a first output control signal cs-1, a high-level signal, and a fixed voltage signal with a first electrical level V1, which has a first output control signal cs-2, is a high-level signal.

[0179] The gate electrodes of the third transistor M3 and the seventh transistor M7 are connected to the second reference signal terminal VREF2, and the second reference signal terminal VREF2 inputs a low-level signal. The gate electrodes of the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are connected to the first reference signal terminal VREF1, and the first reference signal terminal VREF1 inputs a low-level signal. Therefore, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are in a normally on state. One gate electrode of the thirteenth transistor M13 is connected to the fifth reference signal terminal VREF5, and the fifth reference signal terminal VREF5 inputs a high-level signal.Therefore, the thirteenth transistor M13 is in a normally off state. For the sake of simplicity, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given time will not be analyzed below.

[0180] In the first stage H1, an input signal "in" is a low-level signal, and a second clock signal ck2 and a first clock signal ck1 are periodically switched between high and low levels. A third node N3 is connected only to an input signal terminal IN, so that the third node N3 is always held at a low level. Controlling a potential of the third node N3, a twelfth transistor M12 is switched on, the third node N3 is connected to the fourth reference signal terminal VREF4, and the third node N3 is held at a high level. Controlling the potential of the third node N3, a first output transistor T1 and a first cascaded transistor T3 are switched off, the fourth reference signal terminal VREF4 is not connected to a cascaded output terminal OT, and an output control signal terminal CS is not connected to a driver output terminal OUT.Under the control of the potential of the third node N3, a second cascade transistor T4 and a second output transistor T2 are switched on, the first reference signal terminal VREF1 is connected to the cascade output terminal OT, and the first reference signal terminal VREF 1 is connected to the driver output terminal OUT. The cascade output terminal OT outputs a low-level signal, and the driver output terminal OUT also outputs a low-level signal.

[0181] In a second stage H2, the input signal "in" is a high-level signal, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-voltage signal. A first transistor M1 and a sixth transistor M6 are switched on, and the third node N3 is held in a high-level state. Controlled by the potential of the third node N3, a second transistor M2, the twelfth transistor M12, the second cascaded transistor T4, and the second output transistor T2 are switched off. The second cascaded transistor T4 and the second output transistor T2 are switched off, the first reference signal terminal VREF1 is not connected to the cascade output terminal OT, and the first reference signal terminal VREF1 is not connected to the driver output terminal OUT.Under the control of the first clock signal ck1, a ninth transistor M9 is switched on, the second reference signal terminal VREF2 is connected to a fourth node N4, and the fourth node N4 is held at a low level. Under the control of the fourth node N4, a fourth transistor M4 is switched on. Under the control of the second clock signal ck2, a fifth transistor M5 is switched off. A first node N1 is held at a high level. The first cascaded transistor T3 and the first output transistor T1 are switched off. The fourth reference signal terminal VREF4 is not connected to the cascaded output terminal OT. The output signal control terminal CS is not connected to the driver output terminal OUT. The cascaded output terminal OT is held to output a low-level signal, and the driver output terminal OUT is held to output a low-level signal.

[0182] In the third stage H3, the input signal "in" is a high-level signal, and the second clock signal ck2 and the first clock signal ck1 are periodically switched between high and low levels. In a startup stage of the third stage H3, the second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. In this case, under the control of the first clock signal ck1, the first transistor M1 and the sixth transistor M6 are switched between on and off. The third node N3 is held in a high-level state. The second cascaded transistor T4 and the second output transistor T2 are off. The first reference signal terminal VREF1 is not connected to the cascaded output terminal OT, and the first reference signal terminal VREF1 is not connected to the driver output terminal OUT. Under the control of the third node N3, the second transistor M2 is held off.Under the control of the first clock signal ck1, the ninth transistor M9 is switched between on and off, and the fourth node N4 is held in a low-level state. Under the control of the fourth node N4, the fourth transistor M4 is held in a high-level state. When the second clock signal ck2 is switched to a low level, the fifth transistor M5 is switched on, a second clock signal terminal CK2 is connected to the first node N1, and the first node N1 is pulled to a low level. The first cascade transistor T3 and the first output transistor T1 are switched on, the fourth reference signal terminal VREF4 is connected to the cascaded output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascaded output terminal OT outputs a high-level signal, and the driver output terminal OUT also outputs a high-level signal.When the second clock signal ck2 is switched to a high level, the fifth transistor M5 is switched off and the first node N1 is held at a low level. The first cascaded transistor T3 and the first output transistor T1 are switched on, the fourth reference signal terminal VREF4 is connected to the cascaded output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascaded output terminal OT is held high, and the driver output terminal OUT is held high.

[0183] In the fourth stage H4, the input signal "in" is a low-level signal. The second clock signal, ck2, is a low-level signal, and the first clock signal, ck1, is a high-level signal. In this case, the first transistor, M1, and the sixth transistor, M6, are off, and the third node, N3, is held high. The second cascaded transistor, T4, and the second output transistor, T2, are off. The first reference signal terminal, VREF1, is not connected to the cascaded output terminal, OT, and the first reference signal terminal, VREF1, is not connected to the driver output terminal, OUT. The fourth node, N4, is held low. Under the control of the fourth node, N4, the fourth transistor, M4, is held on. The second clock signal, ck2, is low. The fifth transistor, M5, is turned on.The second clock signal, ck2, is connected to the first node, N1. The first node, N1, is set to a low level. The first cascaded transistor, T3, and the first output transistor, T1, are switched on. The fourth reference signal terminal, VREF4, is connected to the cascaded output terminal, OT, and the output signal control terminal, CS, is connected to the driver output terminal, OUT. The cascaded output terminal, OT, outputs a high-level signal, and the driver output terminal, OUT, also outputs a high-level signal.

[0184] In the fifth stage H5, the second clock signal ck2 and the first clock signal ck1 are periodically switched between a high and a low level. In a startup stage of the fifth stage H5, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. In this case, the first transistor M1 and the sixth transistor M6 are switched on, and the third node N3 is at a low level. Under control of the potential of the third node N3, the twelfth transistor M12 is switched on, the first node N1 is connected to the fourth reference signal terminal VREF4, and the first node N1 is held at a high level.Under the control of a potential at the first node N1, the first cascaded transistor T3 and the first output transistor T1 are switched off, the fourth reference signal terminal VREF4 is not connected to the cascaded output terminal OT, and the output signal control terminal CS is not connected to the driver output terminal OUT. Under the control of the potential at the third node N3, the second cascaded transistor T4 and the second output transistor T2 are switched on, the first reference signal terminal VREF1 is connected to the cascaded output terminal OT, and the first reference signal terminal VREF1 is connected to the driver output terminal OUT. The cascaded output terminal OT outputs a low-level signal, and the driver output terminal OUT also outputs a low-level signal.In a subsequent stage, the third node N3 is held at a level, the cascaded output terminal OT is held so that it outputs a low-level signal, and the driver output terminal OUT is held so that it outputs a low-level signal.

[0185] The high-level signal output by the cascaded output terminal OT is passed to the input terminal IN of the next cascaded GOA unit as the input signal "in" of the next cascaded GOA unit. Therefore, the next GOA unit proceeds through stages H2-H5. A valid gate sample signal output by a driver output terminal OUT and a valid cascade signal output by a cascaded output OT of the next GOA unit are shifted 2H backward relative to a valid gate sample signal output by a driver output terminal OUT and a valid cascade signal output by a cascaded output OT of a previous GOA unit. The high-level signal output by the driver output terminal OUT is a valid gate sample signal. A full-frame sample is performed analogously.

[0186] As in Fig. 21 and Fig. As shown in Figure 22, the output control signal lines (such as CS-1 and CS-2 in Figure 22) include Fig. 3) a first output control signal line CS-1 and a second output control signal line CS-2, wherein eight adjacent shift register units in the shift register units form a shift register unit group, the first output control signal line CS-1 being coupled to output control signal terminals CSs of shift register units in odd-numbered shift register unit groups, and the second output control signal line CS-2 being coupled to output control signal terminals CSs of shift register units in even-numbered shift register unit groups. In an example, the first output control signal line CS-1 is coupled to output control signal terminals CSs of shift register units SR1, SR2, SR3, SR4, SR5, SR6, SR7, and SR8, and the second output control signal line CS-2 is coupled to output control signal terminals CSs of shift register units SR9, SR10, SR11, SR12, SR13, SR14,SR15 and SR16 are coupled. "in" represents an input signal from an input signal terminal IN, ck1 represents a first clock signal from a first clock signal terminal CK1, ck2 represents a second clock signal from a second clock signal terminal CK2, cs1 represents a first output control signal from an output control signal terminal CS, out1 represents a gate sample signal from a driver output terminal OUT in a first shift register unit SR1, out2 represents a gate sample signal from a driver output terminal OUT in a second shift register unit SR2, out3 represents a gate sample signal from a driver output terminal OUT in a third shift register unit SR3, out4 represents a gate sample signal from a driver output terminal OUT in a fourth shift register unit SR4, and out5 represents a gate sample signal from a driver output terminal OUT in a fifth shift register unit SR5.out6 represents a gate sample signal from a driver output connection OUT in a sixth shift register unit SR6, out7 represents a gate sample signal from a driver output connection OUT in a seventh shift register unit SR7, out8 represents a gate sample signal from a driver output connection OUT in an eighth shift register unit SR8, out9 represents a gate sample signal from a driver output connection OUT in a ninth shift register unit SR9, out10 represents a gate sample signal from a driver output connection OUT in a tenth shift register unit SR10, out11 represents a gate sample signal from a driver output connection OUT in an eleventh shift register unit SR11, out12 represents a gate sample signal from a driver output connection OUT in a twelfth shift register unit SR12, out13 represents a gate sample signal from a driver output connection OUT in a thirteenth shift register unit SR13,out14 represents a gate sample signal from a driver output terminal OUT in a fourteenth shift register unit SR14, out15 represents a gate sample signal from a driver output terminal OUT in a fifteenth shift register unit SR15, out16 represents a gate sample signal from a driver output terminal OUT in a sixteenth shift register unit SR16, and out17 represents a gate sample signal from a driver output terminal OUT in a seventeenth shift register unit SR17. The pulse width of the input signal "in" is 18H, the pulse width of a high-level segment or a low-level segment of each clock signal terminal is 2H, and the pulse widths of a valid gate sample signal output from a driver output terminal OUT and of a valid cascade signal output from a cascaded output terminal OT are 18H.

[0187] The following describes the working process of a shift register unit provided in the embodiments of the present disclosure, using a shift register unit structure according to Fig. 21 with reference to the in Fig. The signal timing diagram shown in section 24 is described.

[0188] As in Fig.Figure 21 shows an example where all transistors are P-type transistors, a valid pulse signal of a first reference signal output from a first reference signal terminal VREF1 is a low-level signal, a valid pulse signal of a second reference signal output from a second reference signal terminal VREF2 is a low-level signal, a valid pulse signal of a third reference signal output from a third reference signal terminal VREF3 is a high-level signal, a valid pulse signal of a fourth reference signal output from a fourth reference signal terminal VREF4 is a high-level signal, a valid pulse signal of a fifth reference signal output from a fifth reference signal terminal VREF5 is a high-level signal, and a fixed voltage signal with a first electrical level V1 is also used.which has a second output control signal cs-1', is a high-level signal, and a fixed voltage signal with a second electrical level V2, which the second output control signal cs-1' has, is a low-level signal, a fixed voltage signal with a first electrical level V1, which a second output control signal cs-2' has, is a high-level signal, and a fixed voltage signal with a second electrical level V2, which the second output control signal cs-2' has, is a low-level signal.

[0189] The gate electrodes of a third transistor M3 and a seventh transistor M7 are coupled to the second reference signal terminal VREF2, and the second reference signal terminal VREF2 inputs a low-level signal. The gate electrodes of a fourteenth transistor M14, a fifteenth transistor M15, and a twenty-eighth transistor M28 are coupled to the first reference signal terminal VREF1, and the first reference signal terminal VREF1 inputs a low-level signal. Therefore, the third transistor M3, the seventh transistor M7, the fourteenth transistor M14, the fifteenth transistor M15, and the twenty-eighth transistor M28 are in a normally-on state. One gate electrode of a thirteenth transistor M13 is coupled to the fifth reference signal terminal VREF5, and the fifth reference signal terminal VREF5 inputs a high-level signal.Therefore, the thirteenth transistor M13 is in a normally off state. For the sake of simplicity, the states of the third transistor M3, the seventh transistor M7, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 at any given time will not be analyzed below.

[0190] In the first stage H1, an input signal "in" is a low-level signal, and a second clock signal ck2 and a first clock signal ck1 are periodically switched between high and low levels. A third node N3 is connected only to an input signal terminal IN, so that the third node N3 is always held at a low level. Controlling a potential of the third node N3, a twelfth transistor M12 is switched on, the third node N3 is connected to the fourth reference signal terminal VREF4, and the third node N3 is held at a high level. Controlling the potential of the third node N3, a first output transistor T1 and a first cascaded transistor T3 are switched off, the fourth reference signal terminal VREF4 is not connected to a cascaded output terminal OT, and an output control signal terminal CS is not connected to a driver output terminal OUT.Under the control of the potential of the third node N3, a second cascade transistor T4 and a second output transistor T2 are switched on, the first reference signal terminal VREF1 is connected to the cascade output terminal OT, and the first reference signal terminal VREF1 is connected to the driver output terminal OUT. The cascade output terminal OT outputs a low-level signal, and the driver output terminal OUT also outputs a low-level signal.

[0191] In a second stage H2, the input signal "in" is a high-level signal, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. A first transistor M1 and a sixth transistor M6 are switched on, and the third node N3 is held in a high-level state. Controlled by the potential of the third node N3, a second transistor M2, the twelfth transistor M12, the second cascade transistor T4, and the second output transistor T2 are switched off. The first reference signal terminal VREF1 is not connected to the cascade output terminal OT, and the first reference signal terminal VREF1 is not connected to the driver output terminal OUT.Under the control of the first clock signal ck1, a ninth transistor M9 is switched on, the second reference signal terminal VREF2 is connected to a fourth node N4, and the fourth node N4 is held at a low level. Under the control of the fourth node N4, a fourth transistor M4 is switched on. Under the control of the second clock signal ck2, a fifth transistor M5 is switched off. A first node N1 is held at a high level. The first cascaded transistor T3 and the first output transistor T1 are switched off. The fourth reference signal terminal VREF4 is not connected to the cascaded output terminal OT. The output signal control terminal CS is not connected to the driver output terminal OUT. The cascaded output terminal OT is held to output a low-level signal, and the driver output terminal OUT is held to output a low-level signal.

[0192] In the third stage H3, the input signal "in" is a high-level signal, and the second clock signal ck2 and the first clock signal ck1 are periodically switched between high and low levels. In a startup stage of the third stage H3, the second clock signal ck2 provides a low-level signal, and the first clock signal ck1 provides a high-level signal. In this case, under the control of the first clock signal ck1, the first transistor M1 and the sixth transistor M6 are switched between on and off. The third node N3 is held in a high-level state. The second cascaded transistor T4 and the second output transistor T2 are off. The first reference signal terminal VREF1 is not connected to the cascaded output terminal OT, and the first reference signal terminal VREF1 is not connected to the driver output terminal OUT. Under the control of the third node N3, the second transistor M2 is held off.Under the control of the first clock signal ck1, the ninth transistor M9 is switched between on and off, and the fourth node N4 is held in a low-level state. Under the control of the fourth node N4, the fourth transistor M4 is held in a high-level state. When the second clock signal ck2 is switched to a low level, the fifth transistor M5 is switched on, a second clock signal terminal CK2 is connected to the first node N1, and the first node N1 is pulled to a low level. The first cascade transistor T3 and the first output transistor T1 are switched on, the fourth reference signal terminal VREF4 is connected to the cascade output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascade output terminal OT outputs a high-level signal, and the driver output terminal OUT also outputs a high-level signal.When the second clock signal ck2 is switched to a high level, the fifth transistor M5 is switched off and the first node N1 is held at a low level. The first cascaded transistor T3 and the first output transistor T1 are switched on, the fourth reference signal terminal VREF4 is connected to the cascaded output terminal OT, and the output signal control terminal CS is connected to the driver output terminal OUT. The cascaded output terminal OT is held high, and the driver output terminal OUT is held high.

[0193] In the fourth stage H4, the input signal "in" is a low-level signal. The second clock signal, ck2, is a low-level signal, and the first clock signal, ck1, is a high-level signal. In this case, the first transistor, M1, and the sixth transistor, M6, are off, and the third node, N3, is held high. The second cascaded transistor, T4, and the second output transistor, T2, are off. The first reference signal terminal, VREF1, is not connected to the cascaded output terminal, OT, and the first reference signal terminal, VREF1, is not connected to the driver output terminal, OUT. The fourth node, N4, is held low. Under the control of the fourth node, N4, the fourth transistor, M4, is held on. The second clock signal, ck2, is low. The fifth transistor, M5, is turned on.The second clock signal, ck2, is connected to the first node, N1. The first node, N1, is set to a low level. The first cascaded transistor, T3, and the first output transistor, T1, are switched on. The fourth reference signal terminal, VREF4, is connected to the cascaded output terminal, OT, and the output signal control terminal, CS, is connected to the driver output terminal, OUT. The cascaded output terminal, OT, outputs a high-level signal, and the driver output terminal, OUT, also outputs a high-level signal.

[0194] In the fifth stage H5, the second clock signal ck2 and the first clock signal ck1 are periodically switched between a high and a low level. In a startup stage of the fifth stage H5, the second clock signal ck2 provides a high-level signal, and the first clock signal ck1 provides a low-level signal. In this case, the first transistor M1 and the sixth transistor M6 are switched on, and the third node N3 is at a low level. Under control of the potential of the third node N3, the twelfth transistor M12 is switched on, the first node N1 is connected to the fourth reference signal terminal VREF4, and the first node N1 is held at a high level.Under the control of a potential at the first node N1, the first cascaded transistor T3 and the first output transistor T1 are switched off, the fourth reference signal terminal VREF4 is not connected to the cascaded output terminal OT, and the output signal control terminal CS is not connected to the driver output terminal OUT. Under the control of the potential at the third node N3, the second cascaded transistor T4 and the second output transistor T2 are switched on, the first reference signal terminal VREF1 is connected to the cascaded output terminal OT, and the first reference signal terminal VREF1 is connected to the driver output terminal OUT. The cascaded output terminal OT outputs a low-level signal, and the driver output terminal OUT also outputs a low-level signal.In a subsequent stage, the third node N3 is held at a level, the cascaded output terminal OT is held so that it outputs a low-level signal, and the driver output terminal OUT is held so that it outputs a low-level signal.

[0195] The high-level signal output from the cascaded output terminal OT is passed as the input signal "in" of the next cascaded GOA unit to an input signal terminal IN of the next cascaded GOA unit. Therefore, the next GOA unit proceeds through stages H2-H5. A valid gate sample signal output from a driver output terminal OUT and a valid cascade signal output from a cascaded output OT of the next GOA unit are shifted backward by 2H in the cascaded output e compared to a valid gate sample signal output from a driver output terminal OUT and a valid cascade signal output from a cascaded output OT of a previous GOA unit. The high-level signal output from the driver output terminal OUT is a valid gate sample signal.After a first shift register unit group has output a valid gate sample signal, and an eighth shift register unit SR8 has output a complete valid gate sample signal of 18H, the second output control signal cs-1' switches from a high level V1 to a low level V2, and then the odd-numbered shift register unit groups output an invalid gate sample signal. After a second shift register unit group has output a valid gate sample signal, and a sixteenth shift register unit SR16 has output a complete valid gate sample signal of 18H, the second output control signal cs-2' switches from a high level V1 to a low level V2, and then the even-numbered shift register unit groups output an invalid gate sample signal. So far, each shift register unit outputs either a complete gate sample signal of 18H or a complete invalid sample signal of 18H.The situation where a valid gate sample signal is output below 18H does not occur, thus ensuring the display quality of the scoreboard. Meanwhile, the output of a gate sample signal for one of the odd-numbered groups can be set using the second output control signal cs-1', and the output of a gate sample signal for one of the even-numbered groups can be set using the second output control signal cs-2'. By combining these two groups, a setting can be made for each area of ​​the scoreboard, thus enabling partial updates.

[0196] For example, in a display panel with 1024 pixel lines, there are a total of 512 shift register units, with each shift register unit controlling two pixel lines. Eight adjacent shift register units form a group, and there are a total of 64 groups. The output control signal terminals CS of the shift register units in the odd-numbered groups are coupled to a first output control signal line CS-1, and the output control signal terminals CS of the shift register units in the even-numbered groups are coupled to a second output control signal line CS-2.When the first output control signal line CS-1 and the second output control signal line CS-2 are controlled to output a second output control signal, the shift register units in the first through thirty-third groups are activated in each of the 120 frames to output a valid gate sample signal, and the shift register units in the thirty-third through sixty-fourth groups are activated in every second frame of the 120 frames to output a valid gate sample signal. A range controlled by the first 512 pixel rows in the display panel can be 120 Hz, and a range controlled by the last 512 pixel rows in the display panel can be 60 Hz, thus implementing partition updates.Naturally, the first output control signal line CS-1 and the second output control signal line CS-2 can be controlled to output a second output control signal, so that each group in each frame outputs a valid gate sample signal or an invalid gate sample signal t to implement a partition update of the display panel.

[0197] In the embodiments of the present disclosure, by controlling a signal of an output control signal terminal, a gate sampling signal of a driver output terminal in an output circuit is controlled such that the sampling of any area of ​​a display board is controlled and the non-sampling of any area of ​​the display board is controlled, thereby reducing power consumption and losses.

[0198] Other embodiments of the specification will be readily apparent to a person skilled in the art upon consideration of the specification and application of the invention as claimed herein. The description is intended to cover all variations, uses, or adaptations of the description that follow the general principle of the description and include common knowledge or conventional technical means in this field that are not explicitly claimed in the description. The description and examples are to be considered illustrative only. The actual scope and spirit of the description are set forth in the following claims.

[0199] It is understood that the description is not limited to the exact structures described and illustrated in the drawings, and that various modifications and changes can be made without altering its scope. The scope of the description is limited only by the accompanying claims.

[0200] The foregoing descriptions are merely preferred embodiments and are not intended to limit the scope of the description. All modifications, equivalent replacements, improvements, etc., made in accordance with the spirit and intent of the description, fall within the scope of protection afforded by the description.

Claims

[1] Display field, comprising: a shift register unit and a plurality of output control signal lines coupled to the shift register unit, wherein the plurality of output control signal lines are located between the shift register unit coupled thereto and a display area of ​​the display field; the shift register unit comprises: a shift register configured to output a cascade signal via a cascaded output terminal; an output circuit coupled to the shift register, configured to control a driver output terminal, to output a gate sampling signal according to a signal from an output control signal terminal and a signal from a first reference signal terminal, wherein the output control signal terminal is coupled to one of the plurality of output control signal lines. [2] Display field according to claim 1, wherein the output circuit comprises: a first output circuit and a second output circuit; wherein the first output circuit is coupled to the cascaded output terminal or a first node in the shift register and is configured to transmit the output control signal terminal signal to the driver output terminal in response to a signal from the cascaded output terminal or the first node; wherein the second output circuit is coupled to a second node in the shift register and is configured to transmit the signal of the first reference signal terminal to the driver output terminal in response to a signal from the second node. [3] Display panel according to claim 2, wherein the first output circuit comprises: a first output transistor; wherein a gate electrode of the first output transistor is coupled to the cascaded output terminal or the first node, a first electrode of the first output transistor is coupled to the output control signal terminal, and a second electrode of the first output transistor is coupled to the driver output terminal. [4] Display field according to claim 2, wherein the second output circuit comprises: a second output transistor; wherein a gate electrode of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the first reference signal terminal, and a second electrode of the second output transistor is coupled to the driver output terminal. [5] Display field according to any one of claims 1 to 4, wherein the shift register comprises: an input sub-circuit configured to deliver a signal from an input signal terminal to a third node in response to a signal from a first clock signal terminal; a control circuit configured to control signals from the first node and the second node and to supply a signal from the third node to either the first or the second node; a cascade sub-circuit configured to release the cascade output terminal for output of the cascade signal in response to signals from the first node and the second node. [6] Display panel according to claim 5, wherein the input sub-circuit comprises: a first transistor; wherein a gate electrode of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the input signal terminal, and a second electrode of the first transistor is coupled to the third node. [7] Display panel according to claim 5, wherein the control circuit comprises: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; wherein: a gate electrode of the second transistor is coupled to the third node, a first electrode of the second transistor is coupled to the first clock signal terminal, and a second electrode of the second transistor is coupled to a fourth node; a gate electrode of the third transistor is coupled to a second reference signal terminal, a first electrode of the third transistor is coupled to the fourth node, and a second electrode of the third transistor is coupled to a gate electrode of the fourth transistor; a first electrode of the fourth transistor is coupled to a second clock signal terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the fifth transistor; a gate electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor is coupled to the first node; a gate electrode of the sixth transistor is coupled to the first clock signal terminal, a first electrode of the sixth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to a first electrode of the seventh transistor; a gate electrode of the seventh transistor is coupled to the second reference signal terminal, and a second electrode of the seventh transistor is coupled to a fifth node; a gate electrode of the eighth transistor is connected to the fifth node, a first electrode of the eighth transistor is connected to the fifth node, and a second electrode of the eighth transistor is connected to the second node; a gate electrode of the ninth transistor is coupled to the first clock signal terminal, a first electrode of the ninth transistor is coupled to the second reference signal terminal, and a second electrode of the ninth transistor is coupled to a gate electrode of the tenth transistor; a first electrode of the tenth transistor is coupled to a third reference signal terminal, and a second electrode of the tenth transistor is coupled to a sixth node; a gate electrode of the eleventh transistor is coupled to the fifth node, a first electrode of the eleventh transistor is coupled to the sixth node, and a second electrode of the eleventh transistor is coupled to the second clock signal terminal; a gate electrode of the twelfth transistor is coupled to a first electrode of the fifteenth transistor, a first electrode of the twelfth transistor is coupled to the first node, and a second electrode of the twelfth transistor is coupled to a fourth reference signal terminal; a gate electrode of the thirteenth transistor is coupled to a fifth reference signal terminal, a first electrode of the thirteenth transistor is coupled to the fourth reference signal terminal, and a second electrode of the thirteenth transistor is coupled to a first electrode of the fourteenth transistor; a gate electrode of the fourteenth transistor is coupled to the first reference signal terminal, and a second electrode of the fourteenth transistor is coupled to the first electrode of the fifteenth transistor; a gate electrode of the fifteenth transistor is coupled to the first reference signal terminal, the first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the second node; a first electrode of the first capacitor is coupled to the gate electrode of the fourth transistor, and a second electrode of the first capacitor is coupled to the second electrode of the fourth transistor; a first electrode of the second capacitor is coupled to the sixth node, and a second electrode of the second capacitor is coupled to the second electrode of the seventh transistor; a first electrode of the third capacitor is coupled to the fourth reference signal terminal, and a second electrode of the third capacitor is coupled to the first node; a first electrode of the fourth capacitor is coupled to the cascaded output terminal, and a second electrode of the fourth capacitor is coupled to the first reference signal terminal. [8] Display field according to claim 5, wherein the cascade sub-circuit comprises: a first cascaded transistor and a second cascaded transistor; where a gate electrode of the first cascaded transistor is coupled to the first node, a first electrode of the first cascaded transistor is coupled to a fourth reference signal terminal, and a second electrode of the first cascaded transistor is coupled to the cascaded output terminal; a gate electrode of the second cascaded transistor is coupled to the second node, a first electrode of the second cascaded transistor is coupled to the cascaded output terminal, and a second electrode of the second cascaded transistor is coupled to the first reference signal terminal. [9] Display panel according to claim 5, wherein the input sub-circuit comprises: a sixteenth transistor and a seventeenth transistor; where a gate electrode of the sixteenth transistor is coupled to the first clock signal terminal, a first electrode of the sixteenth transistor is coupled to the input signal terminal, and a second electrode of the sixteenth transistor is coupled to a seventh node; a gate electrode of the seventeenth transistor is coupled to the first clock signal terminal, a first electrode of the seventeenth transistor is coupled to the seventh node, and a second electrode of the seventeenth transistor is coupled to the third node. [10] Display panel according to claim 5, wherein the control circuit comprises: an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a fifth capacitor and a sixth capacitor; where a gate electrode of the eighteenth transistor is coupled to the cascaded output terminal, a first electrode of the eighteenth transistor is coupled to a third clock signal terminal, and a second electrode of the eighteenth transistor is coupled to a seventh node; a gate electrode of the nineteenth transistor is coupled to the input signal terminal, a first electrode of the nineteenth transistor is coupled to the first reference signal terminal, and a second electrode of the nineteenth transistor is coupled to the second node; a gate electrode of the twentieth transistor is coupled to the second node, a first electrode of the twentieth transistor is coupled to the first reference signal terminal, and a second electrode of the twentieth transistor is coupled to an eighth node; a gate electrode of the twenty-first transistor is coupled to the second node, a first electrode of the twenty-first transistor is coupled to the eighth node, and a second electrode of the twenty-first transistor is coupled to the third node; a gate electrode of the twenty-second transistor is coupled to the third node, a first electrode of the twenty-second transistor is coupled to the eighth node, and a second electrode of the twenty-second transistor is coupled to a sixth reference signal terminal; a gate electrode of the twenty-third transistor is coupled to a fourth clock signal terminal, a first electrode of the twenty-third transistor is coupled to the second node, and a second electrode of the twenty-third transistor is coupled to the sixth reference signal terminal; a first electrode of the fifth capacitor is coupled to the first reference signal terminal, and a second electrode of the fifth capacitor is coupled to the first electrode of the twenty-third transistor; a first electrode of the sixth capacitor is coupled to the cascaded output terminal, and a second electrode of the sixth capacitor is coupled to the first node. [11] Display field according to claim 5, wherein the cascade sub-circuit comprises: a first cascaded transistor and a second cascaded transistor; where a gate electrode of the first cascaded transistor is coupled to the first node, a first electrode of the first cascaded transistor is coupled to the cascaded output terminal, and a second electrode of the first cascaded transistor is coupled to a third clock signal terminal; a gate electrode of the second cascaded transistor is coupled to the second node, a first electrode of the second cascaded transistor is coupled to the first reference signal terminal, and a second electrode of the second cascaded transistor is coupled to the cascaded output terminal. [12] Display panel according to claim 5, wherein the control circuit comprises: a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a seventh capacitor and an eighth capacitor; where a gate electrode of the twenty-fourth transistor is coupled to the first clock signal terminal, a first electrode of the twenty-fourth transistor is coupled to a seventh reference signal terminal, and a second electrode of the twenty-fourth transistor is coupled to the second node; a gate electrode of the twenty-fifth transistor is coupled to the third node, a first electrode of the twenty-fifth transistor is coupled to the second node, and a second electrode of the twenty-fifth transistor is coupled to the first clock signal terminal; a gate electrode of the twenty-sixth transistor is coupled to the second node, a first electrode of the twenty-sixth transistor is coupled to the first reference signal terminal, and a second electrode of the twenty-sixth transistor is coupled to a first electrode of the twenty-seventh transistor; a gate electrode of the twenty-seventh transistor is coupled to a third clock signal terminal, and a second electrode of the twenty-seventh transistor is coupled to a first electrode of the twenty-eighth transistor; a gate electrode of the twenty-eighth transistor is coupled to the seventh reference signal terminal, the first electrode of the twenty-eighth transistor is coupled to the third node, and a second electrode of the twenty-eighth transistor is coupled to the first node; a first electrode of the seventh capacitor is coupled to the first reference signal terminal, and a second electrode of the seventh capacitor is coupled to the first node; a first electrode of the eighth capacitor is coupled to the cascaded output terminal, and a second electrode of the eighth capacitor is coupled to the first node. [13] Display panel according to claim 7, wherein the control circuit further comprises: a twenty-eighth transistor; wherein a first electrode of the twenty-eighth transistor is coupled to the second electrode of the fifth transistor, a second electrode of the twenty-eighth transistor is coupled to the first node, and a gate electrode of the twenty-eighth transistor is coupled to the first reference signal terminal. [14] Display field, comprising: a base substrate that includes a display area and a non-display area, the display area includes: a large number of subpixels; a plurality of scanning lines, wherein each row of the plurality of subpixels is coupled to at least one of the plurality of scanning lines, including the non-display area: a gate driver circuit comprising a plurality of shift register units in the display field according to any one of claims 1 to 13, wherein a driver output connection of each of the plurality of shift register units is coupled to at least one of the plurality of sampling lines. [15] Display field according to claim 14, further comprising: a plurality of output control signal lines coupled to the gate driver circuit, wherein a direction of extension of each of the plurality of output control signal lines coincides with an arrangement direction of the plurality of shift register units. [16] Display field according to claim 15, wherein the plurality of output control signal lines are located between the gate driver circuit coupled thereto and the display area. [17] Display field according to claim 16, wherein in two adjacent shift register units in the plurality of shift register units an input signal connection of a later of the adjacent shift register units is coupled to a cascaded output connection of an earlier of the adjacent shift register units; wherein the plurality of output control signal lines comprise: a first output control signal line and a second output control signal line, wherein the first output control signal line is coupled to output control signal connections of odd-numbered shift register units, and the second output control signal line is coupled to output control signal connections of even-numbered shift register units. [18] Display field according to claim 16, wherein in two adjacent shift register units in the plurality of shift register units, an input signal connection of a later of the adjacent shift register units is coupled to a cascaded output connection of an earlier of the adjacent shift register units; wherein the plurality of output control signal lines comprise: a first output control signal line and a second output control signal line, wherein all eight adjacent shift register units in the shift register units form a shift register unit group, wherein the first output control signal line is coupled to output control signal connections of shift register units in odd-numbered shift register unit groups, and the second output control signal line is coupled to output control signal connections of shift register units in even-numbered shift register unit groups. [19] Display field according to claim 15, further comprising: a plurality of output control signal auxiliary lines, wherein a first insulating layer is provided between the plurality of output control signal auxiliary lines and the plurality of output control signal lines; the plurality of output control auxiliary signal lines being in a one-to-one correspondence with the plurality of output control signal lines, and each of the output control auxiliary signal lines and a corresponding one of the output control signal lines being coupled to each other by means of a first through-hole penetrating the first insulating layer. [20] Display field according to one of claims 14 to 19, further comprising: a plurality of clock signal lines coupled to the gate driver circuit, wherein a direction of extension of each of the plurality of clock signal lines coincides with an arrangement direction of the plurality of shift register units. [21] Display field according to claim 20, wherein the plurality of clock signal lines are arranged on a side of the gate driver circuit facing away from the display area, which is coupled to the clock signal lines. [22] Display field according to claim 20, wherein orthographic projections of the plurality of output control signal lines on the base substrate are arranged between orthographic projections of the plurality of clock signal lines on the base substrate and the display area. [23] Display field according to claim 20, wherein an orthographic projection of the gate driver circuit on the base substrate is arranged between orthographic projections of the plurality of clock signal lines on the base substrate and orthographic projections of the plurality of output control signal lines on the base substrate, and the orthographic projections of the plurality of output control signal lines on the base substrate are arranged between the orthographic projection of the gate driver circuit on the base substrate and the display area. [24] Display field according to one of claims 14 to 19, wherein an orthographic projection of a first output transistor on the base substrate is arranged between an orthographic projection of a first cascade transistor on the base substrate and the display area. [25] Display field according to one of claims 14 to 19, wherein a width of a channel of a first output transistor is greater than a width of a channel of a first cascaded transistor. [26] Display field according to claim 25, wherein the width of the channel of the first output transistor is not less than 100 µm. [27] Display field according to claim 25, wherein the width of the channel of the first cascaded transistor is not greater than 60 µm. [28] Display field according to one of claims 14 to 19, wherein an orthographic projection of a second output transistor on the base substrate is arranged between an orthographic projection of a second cascaded transistor on the base substrate and the display area. [29] Display field according to one of claims 14 to 19, wherein a width of a channel of a second output transistor is greater than a width of a channel of a second cascaded transistor. [30] Display field according to claim 29, wherein the width of the channel of the second output transistor is not less than 100 µm. [31] Display field according to claim 29, wherein the width of the channel of the second cascaded transistor is not greater than 60 µm. [32] Display device comprising: the display field according to one of claims 14 to 31; a driver control circuit coupled to the display panel and configured to input an initial output control signal to the output control signal terminals of the plurality of shift register units when a full-screen driver mode is determined to be used to sequentially output gate sample signals to the plurality of shift register units, drive sample lines line by line, and which is configured to input a second output control signal to the output control signal terminals of the plurality of shift register units when a local driver mode is determined to be used to output some of the plurality of shift register units sequentially gate sample signals and the remaining shift register units output invalid sample signals. [33] Driver control methods, including: Inputting an initial output control signal to the output control signal terminals of the plurality of shift register units when a full-screen driver mode is determined to be used to sequentially output the plurality of shift register units gate sample signals and drive sample lines line by line; and Inputting a second output control signal to the output control signal terminals of the plurality of shift register units when a local driver mode is determined to be used to sequentially output gate sampling signals to some of the plurality of shift register units and to output invalid sampling signals to the remaining shift register units to drive some of the sampling lines. [34] Driver control method according to claim 33, wherein the first output control signal is a fixed voltage signal with a first electrical level. [35] Driver control method according to claim 33 or 34, wherein the second output control signal comprises a fixed voltage signal section with a first electrical level and a fixed voltage signal section with a second electrical level, wherein the fixed voltage signal section with the first electrical level is input to some of the shift register units, and the fixed voltage signal section with the second electrical level is input to the remaining shift register units. [36] Driver control method according to claim 33, wherein the first output control signal is a clock signal. [37] Driver control method according to claim 33 or 36, wherein the second output control signal comprises a clock signal section and a fixed voltage signal section with a first electrical level; wherein the clock signal section in the second output control signal is fed into some of the shift register units, and the fixed voltage signal section with the first electrical level in the second output control signal is fed into the remaining shift register units. [38] Driver control method according to claim 33, wherein a pulse width of an input signal of an input signal terminal of the shift register unit is 18H, a pulse width of a cascade signal output from a cascade signal terminal of the shift register unit is 18H, a pulse width of a gate sample signal output from a driver output terminal of the shift register unit is 18H, and a cascade signal and a valid gate sample signal output from the next shift register unit of the plurality of shift register units are shifted backward by 2H relative to a cascade signal and a valid gate sample signal output from a previous shift register unit of the plurality of shift register units.

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