SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is disclosed which includes a backward-conducting IGBT with an IGBT and a diode provided on the same semiconductor substrate.

Description

Technical field

[0001] The present invention relates to a semiconductor device comprising an IGBT and a diode in the same semiconductor device. Background of the invention

[0002] In a reverse-conducting IGBT (RC-IGBT), where an IGBT (insulated gate bipolar transistor) and a diode connected antiparallel to the IGBT are mounted on the same semiconductor device, a peripheral voltage-resistant structure can be shared by one chip.

[0003] As a result, the RC-IGBT can reduce the area of ​​the chip compared to the area of ​​the IGBT and diode chips manufactured separately.

[0004] Since the RC-IGBT also dissipates heat generated in an IGBT region to a diode side and heat generated in a diode region to an IGBT side, the RC-IGBT can be operated with a higher current density and heat generation density than before.

[0005] On the other hand, in order to prevent the breakdown of an element even when the current density becomes high, it is simultaneously required to improve a reverse bias safe operating area (RBSOA), which is an index that indicates the current interrupting capability of the IGBT.

[0006] For example, Publication 1 describes how, by forming a p+-type contact layer of an IGBT such that it penetrates into a p-type well layer in an outer circumferential region, a section in which the p+-type contact layer and the p-type well layer overlap becomes low-resistance, a potential increase is less likely, an influx of hole current to an n+-type emitter layer is reduced, and a reduction in the reverse bias safe operating area (RBSOA) can be minimized. List of printed materials and patent literature

[0007] Patent Literature 1: JP 2022-59487 A Summary of the invention: Technical problem

[0008] However, although the configuration described in patent literature 1 has an effect of preventing a reduction of the RBSOA in the boundary region between the IGBT and the outer circumferential region, patent literature 1 does not propose a method to prevent a reduction of the RBSOA in the IGBT active region, which occupies a large area in the RC-IGBT.

[0009] To solve the problem described above, it is an object of the present invention to provide a semiconductor device with an RC-IGBT that has an improved blocking safety operating area RBSOA.

[0010] The aforementioned and other objectives of the present invention, as well as the new features of the present invention, are clarified by the description of the present specification and the accompanying drawings. Solution to the problem

[0011] A semiconductor device of the present invention is a semiconductor device comprising a backward-conducting IGBT with an IGBT and a diode provided on the same semiconductor substrate.

[0012] The semiconductor device according to the present invention comprises: the semiconductor substrate of a first conductivity type; a first electrode that is in contact with a front surface of the semiconductor substrate; a second electrode that is in contact with a rear surface of the semiconductor substrate; a multitude of grooves provided on one side of the front surface of the semiconductor substrate; an insulating film provided in each of the trenches; and a third electrode covered by the insulating film.

[0013] A semiconductor device according to the present invention further comprises: a first semiconductor layer of a second conductivity type, wherein the first semiconductor layer is in contact with the second electrode in an IGBT area in which the IGBT is provided; a second semiconductor layer of a first conductivity type, wherein the second semiconductor layer is in contact with the second electrode in a diode region in which the diode is provided; a third semiconductor layer of the first conductivity type, wherein the third semiconductor layer is in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, wherein the fourth semiconductor layer is in contact with the first electrode and the insulating film in the trench; and fifth semiconductor layers of the first conductivity type, wherein each of the fifth semiconductor layers in the IGBT area is in contact with the first electrode and the insulating film in the trench and is surrounded by the fourth semiconductor layer.

[0014] The semiconductor device of the first aspect of the present invention further comprises: a low lifetime region provided in the semiconductor substrate of an IGBT cell in a section near the center of the IGBT region.

[0015] Furthermore, the semiconductor device of the second aspect of the present invention is configured such that the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area. Advantageous effects of the invention

[0016] According to the configuration of the semiconductor device of the first aspect of the present invention, a low lifetime region is provided in the semiconductor substrate of an IGBT cell in a section near the center of the IGBT region.

[0017] In the IGBT cell, in the section near the middle of the IGBT region, the accumulation of carriers is reduced due to a conductivity modulation effect through the low lifetime region, and thus a base current supplied to a parasitic thyristor inherent in the IGBT can be reduced by reducing the total amount of carriers discharged during a turn-off process.

[0018] Accordingly, it is possible to prevent latch-up destruction in the IGBT area and to improve a barrier safety work area (RBSOA).

[0019] According to the configuration of the semiconductor device of the second aspect of the present invention, the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area. Since the fifth semiconductor layers are not provided in the IGBT cell in the section near the center of the IGBT area, no parasitic thyristor is provided in the IGBT.

[0020] Accordingly, it is possible to prevent latch-up destruction in the IGBT area and to improve a barrier safety work area (RBSOA).

[0021] Problems, configurations and effects other than those described above are clarified by the following description of embodiments. Brief description of the drawings Fig. Figure 1 is an enlarged cross-sectional view of a main part of a semiconductor device according to Example 1. Fig. Figure 2 is an enlarged cross-sectional view of a main part of a semiconductor device according to Example 2. Fig. Figure 3 is an enlarged cross-sectional view of a main part of a semiconductor device according to Example 3. Fig. Figure 4 is an enlarged cross-sectional view of a main part of a semiconductor device according to Example 4. Fig. Figure 5 is a horizontal cross-sectional view along line XX' in Fig. 4. Fig. Figure 6 is an enlarged cross-sectional view of a main part of a semiconductor device with a conventional backward-conducting IGBT. Fig. Figure 7 is a horizontal cross-sectional view along line XX' in Fig. 6. Description of embodiments

[0022] Embodiments and examples according to the present invention are described below with reference to descriptions or drawings.

[0023] It should be noted that the structures, materials and other specific configurations and the like shown in the present invention are not limited to the embodiments and examples described herein and can be suitably combined or improved without changing the core of the present invention.

[0024] Furthermore, components that are not directly related to the present invention are not shown.

[0025] A semiconductor device of the present invention is a semiconductor device comprising a backward-conducting IGBT with an IGBT and a diode provided on the same semiconductor substrate.

[0026] The semiconductor device according to the present invention comprises: the semiconductor substrate of a first conductivity type; a first electrode that is in contact with a front surface of the semiconductor substrate; a second electrode that is in contact with a rear surface of the semiconductor substrate; a multitude of grooves provided on one side of the front surface of the semiconductor substrate; an insulating film provided in each of the trenches; and a third electrode covered by the insulating film.

[0027] A semiconductor device according to the present invention further comprises: a first semiconductor layer of a second conductivity type, wherein the first semiconductor layer is in contact with the second electrode in an IGBT region in which the IGBT is provided; a second semiconductor layer of a first conductivity type, wherein the second semiconductor layer is in contact with the second electrode in a diode region in which the diode is provided; a third semiconductor layer of the first conductivity type, wherein the third semiconductor layer is in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, wherein the fourth semiconductor layer is in contact with the first electrode and the insulating film in the trench; and fifth semiconductor layers of the first conductivity type, wherein each of the fifth semiconductor layers in the IGBT area is in contact with the first electrode and the insulating film in the trench and is surrounded by the fourth semiconductor layer.

[0028] The semiconductor device of the first aspect of the present invention further comprises: a low lifetime region provided in the semiconductor substrate of an IGBT cell in a section near the center of the IGBT region.

[0029] Furthermore, the semiconductor device of the second aspect of the present invention is configured such that the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area.

[0030] According to the configuration of the semiconductor device of the first aspect of the present invention, a low lifetime region is provided in the semiconductor substrate of an IGBT cell in a section near the center of the IGBT region.

[0031] Since the short-life region in the semiconductor substrate of the IGBT cell is located in the section near the center of the IGBT region, an accumulation of carriers can occur due to the conductivity modulation effect by the The short lifetime area in the IGBT cell is reduced in the section near the middle of the IGBT area.

[0032] Since the amount of carriers that accumulate can be reduced, the total amount of carriers discharged during a turn-off process is reduced, and the base current supplied to a pnpn-type parasitic thyristor inherent in the IGBT is reduced. Consequently, it is possible to prevent latch-up destruction in the IGBT region due to the base current and to improve the blocking safety operating range (RBSOA).

[0033] According to the configuration of the semiconductor device of the second aspect of the present invention, the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area.

[0034] Since the fifth semiconductor layers in the IGBT cell are not provided in the section near the middle of the IGBT area, no parasitic thyristor is provided in the IGBT.

[0035] Accordingly, it is possible to prevent latch-up destruction in the IGBT area due to the base current of the parasitic thyristor and to improve the blocking safety operating range RBSOA.

[0036] The semiconductor device of the first aspect of the present invention can be configured such that the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in a section other than the section near the center of the IGBT area.

[0037] According to this configuration, since the impurity concentration of the first semiconductor layer in the section near the middle of the IGBT area is lower than that of the first semiconductor layer in the other section of the IGBT area, the injection quantity of minority carriers at the time of forward current conduction is reduced.

[0038] As a result, during the turn-off process, minority carriers discharged to the body layer (fourth semiconductor layer) in the section near the center of the IGBT area are reduced, the base current of the parasitic thyristor is suppressed, and the RBSOA can be further improved.

[0039] The semiconductor device of the first aspect of the present invention can be configured such that the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area.

[0040] According to this configuration, similar to the semiconductor device of the second aspect of the present invention, the parasitic thyristor is not provided in the IGBT in the IGBT cell in the section near the middle of the IGBT area.

[0041] Accordingly, it is possible to prevent latch-up destruction in the IGBT area due to the base current of the parasitic thyristor and to further improve the blocking safety operating range RBSOA.

[0042] The semiconductor device of the first aspect of the present invention can be configured such that the number of fifth semiconductor layers in an IGBT cell in the section near the center of the IGBT area is smaller than in an IGBT cell in a section other than the section near the center of the IGBT area. According to this configuration, the number of fifth semiconductor layers in the IGBT cell in the section near the center of the IGBT area is smaller than in the IGBT cell in a section other than the section near the center of the IGBT area, and a parasitic thyristor structure is less likely to form, and latch-up destruction can be suppressed. As a result, the blocking safety operating area (RBSOA) can be further improved.

[0043] The semiconductor device of the second aspect of the present invention can be configured such that the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in a section other than the section near the center of the IGBT area.

[0044] According to this configuration, since the impurity concentration of the first semiconductor layer in the section near the center of the IGBT region is lower than that of the first semiconductor layer in the other section of the IGBT region, the amount of minority carriers injected at the time of forward current conduction is reduced. Consequently, during the turn-off process, minority carriers discharged to the body layer (fourth semiconductor layer) in the section near the center of the IGBT region are reduced, the base current of the parasitic thyristor is suppressed, and the RBSOA can be further improved. Examples

[0045] Next, specific examples of the semiconductor device will be described. (Example 1)

[0046] Below is a configuration of a semiconductor device from Example 1 with reference to Fig. 1 described.

[0047] Fig. Figure 1 is an enlarged cross-sectional view of a main part of the semiconductor device according to Example 1.

[0048] Fig. Figure 1 is an enlarged cross-sectional view of an IGBT area and a diode area in a semiconductor device containing a reverse-conducting IGBT (RC-IGBT).

[0049] This example shows a case in which the semiconductor device of the present invention is applied to a trench IGBT.

[0050] As in Fig. As shown in Figure 1, the semiconductor device of the present example has a configuration comprising an adjacent IGBT section 100 and a diode section 200. One IGBT is provided in the IGBT section 100. A diode is provided in the diode section 200.

[0051] The semiconductor device of the present example comprises a semiconductor substrate 1 of the first conductivity type, an emitter electrode 10 in contact with the front surface of the semiconductor substrate 1, a collector electrode 11 in contact with the rear surface of the semiconductor substrate 1, a collector layer 2 of the second conductivity type, a cathode layer 3 of the first conductivity type and a buffer layer 4 of the first conductivity type.

[0052] The emitter electrode 10 and the collector electrode 11 are each provided via the IGBT area 100 and the diode area 200.

[0053] The collector layer 2 of the second conductivity type (for example, p-type) is provided in a section of the IGBT area 100 on one side of the rear surface of the semiconductor substrate 1 and is in contact with the collector electrode 11.

[0054] The cathode layer 3 of the first conductivity type (for example, n-type) is provided in a section of the diode region 200 on one side of the rear surface of the semiconductor substrate 1 and is in contact with the collector electrode 11.

[0055] The buffer layer 4 of the first conductivity type (for example, n-type) is arranged such that it is in contact with surfaces of the collector layer 2 and the cathode layer 3, which are opposite surfaces that are in contact with the collector electrode 11.

[0056] In both the IGBT area 100 and the diode area 200, a body layer 5 of the second conductivity type (for example, p-type) is provided in a section on the side of the front surface of the semiconductor substrate 1.

[0057] In the IGBT area 100, emitter layers 6 of the first conductivity type (for example, n-type) are provided in sections on the side of the front surface of the body layer 5.

[0058] In the semiconductor substrate 1, a section between the buffer layer 4 and the body layer 5 is a barrier layer 7 of a first conductivity type (for example, n-type).

[0059] The barrier layer 7 of the first conductivity type acts as a hole barrier layer in a case where the first conductivity type is n-type, and acts as an electron barrier layer in a case where the first conductivity type is p-type.

[0060] The semiconductor device according to the present example further comprises grooves 20, which are provided in each of the IGBT region 100 and the diode region 200 from the front surface to the rear surface of the semiconductor substrate 1. The grooves 20 extend from the front surface of the semiconductor substrate 1 through the body layer 5 to an upper section of the barrier layer 7.

[0061] An insulating film 21 and a gate electrode 12, which is provided within the insulating film 21, are arranged within each of the trenches 20 of the IGBT area 100.

[0062] An insulating film 21 and an in-trench emitter electrode 13, which is provided within the insulating film 21, are arranged within each of the trenches 20 of the diode area 200.

[0063] The emitter layers 6 of the first conductivity type in the IGBT area 100 are each provided in contact with the outside of the trenches 20 on the left and right sides.

[0064] The gate electrode 12 and the in-trench emitter electrode 13 within the trenches 20 are electrically separated from the emitter electrode 10 by an intermediate layer insulating film 22, which is provided on the trench 20.

[0065] Here, the movement of carriers in the semiconductor device, which includes the IGBT range 100 and the diode range 200, is described as in Fig. Figure 1 contains and describes the following. Here, a description is given assuming that the first conductivity type is n-type, the second conductivity type is p-type, majority carriers are electrons, and minority carriers are holes.

[0066] Due to the conductivity modulation effect, the holes, as minority carriers, are injected into the semiconductor substrate 1 in the IGBT region 100 during forward current conduction, and carriers (electrons and holes) accumulate in the semiconductor substrate 1. During the turn-off process to switch from a conduction state to an open state, the holes in the carriers that have accumulated in the IGBT region 100 flow through the body layer 5 of the IGBT cell into the emitter electrodes 10.

[0067] Since some of the accumulated holes also flow into the body layer 5 on one side of the diode region 200, the number of holes discharged from the body layer 5 in the IGBT cell in the section near the diode region 200 decreases, and the base current of the parasitic thyristor structure (emitter layer 6 / body layer 5 / semiconductor substrate 1 and buffer layer 4 / collector layer 2) inherent in the IGBT decreases.

[0068] In the IGBT cell, in the section near diode range 200, the reverse recovery safety operating area (RBSOA) is improved because the base current, which causes the latch-up of the parasitic thyristor structure, is reduced. On the other hand, in the IGBT cell, in the section near the center of IGBT range 100 (the left end in Fig. 1) which is located far from diode area 200, the effect of some of the holes flowing to body layer 5 of diode area 200 is not achieved. Therefore, in the IGBT cell in the section near the center 100C of IGBT area 100, the blocking safety working area (RBSOA) is not improved, and destruction can occur in a concentrated manner.

[0069] Therefore, in the present example, as in Fig. Figure 1 shows a low-life region 300, in which the lifetime of the carriers is shortened, in the semiconductor substrate 1 of the IGBT cell in the section near the center 100C of the IGBT region 100 (that is, an IGBT cell located in a central section of the IGBT region 100). The low-life region 300 has the characteristic that the lifetime of the carrier is shorter than in the other sections of the semiconductor substrate 1, and holes and electrons disappear as carriers in a short time.

[0070] Since the lifetime of the carriers is shortened by providing the short-life region 300, the carriers that accumulate in the IGBT region 100 at the time of current conduction can be reduced. Because the accumulated carriers are reduced, the carriers flowing from body layer 5 to the emitter electrode 10 in the IGBT cell in the section near the middle of the IGBT region 100 are reduced during the turn-off process, and the base current of the parasitic thyristor is also reduced.

[0071] This makes it possible to prevent latch-up destruction in the section near the middle 100C of the IGBT area 100.

[0072] Even in a configuration where the first conductivity type is p-type, the second conductivity type is n-type, the majority carriers are holes, and the minority carriers are electrons, the low-life region 300 can be similarly provided in the semiconductor substrate 1 in the section near the center 100C of the IGBT region 100. By providing the low-life region 300, it is possible to prevent latch-up failure in the section near the center 100C of the IGBT region 100.

[0073] The low lifetime region 300 can be produced, for example, by providing a mask on the side of the back surface that is not a section where the low lifetime region 300 is formed, and by implanting light ions such as protons into the semiconductor substrate 1. Since the light ions are implanted into the semiconductor substrate 1, lattice defects are introduced into the implanted section of the semiconductor substrate 1, and the lifetime of the substrate is shortened.

[0074] According to the semiconductor device of the present example, the low lifetime region 300, in which the lifetime of the carrier is shortened, is provided in the semiconductor substrate 1 of the IGBT cell in the section near the center 100C of the IGBT region 100.

[0075] Since the lifetime of the carriers is shortened by the low lifetime range 300, the carriers that accumulate in the IGBT range 100 at the time of power transmission can be reduced.

[0076] As a result, the carriers flowing from the body layer 5 to the emitter electrode 10 in the IGBT cell in the section near the center 100C of the IGBT area 100 are reduced during the switch-off process, and the base current of the parasitic thyristor is also reduced, thus preventing latch-up destruction in the section near the center 100C of the IGBT area 100. (Example 2)

[0077] Next, a configuration of a semiconductor device from Example 2 will be described with reference to Fig. 2 described.

[0078] Fig. Figure 2 is an enlarged cross-sectional view of a main part of the semiconductor device according to Example 2. The same components are used here as in [reference missing]. Fig. Example 1 is labelled with the same reference symbols, and a redundant description is omitted.

[0079] As in Fig. 2 shown, according to the semiconductor device of the present example, similar to Example 1, the device in Fig. Figure 1 shows the low lifetime range 300, in which the lifetime of the carriers is shortened, in which the semiconductor substrate 1 of the IGBT cell is provided in the section near the center 100C of the IGBT range 100.

[0080] Furthermore, in the semiconductor device of the present example, as in Fig. Figure 2 shows that collector layer 2 is a low-concentration collector layer 2a located in the section near the center of IGBT area 100 (that is, the central section of IGBT area 100), and a high-concentration collector layer 2b is located in the other section of IGBT area 100. The high-concentration collector layer 2b has the same impurity concentration as that of collector layer 2 in Example 1, and the low-concentration collector layer 2a has an impurity concentration that is lower than that of collector layer 2 in Example 1.

[0081] According to the semiconductor device of the present example, since the collector layer is the low-concentration collector layer 2a in the section near the center 100C of the IGBT area 100, it is possible to reduce the injection quantity of minority carriers at the time of forward current conduction. As a result, during the turn-off process, minority carriers (for example, holes) discharged to the body layer 5 in the section near the center 100C of the IGBT area 100 are reduced, the base current of the parasitic thyristor is suppressed, and the RBSOA can be further improved. (Example 3)

[0082] Next, a configuration of a semiconductor device from Example 3 will be described with reference to Fig. 3 described.

[0083] Fig. Figure 3 is an enlarged cross-sectional view of a main part of the semiconductor device according to Example 3. The same components are used here as in [Example 3]. Fig. Example 1 is labelled with the same reference symbols, and a redundant description is omitted.

[0084] As in Fig. As shown in 3, according to the semiconductor device of the present example, similar to Example 1, the device in Fig. Figure 1 shows the low lifetime region 300, in which the lifetime of the carriers is shortened, in which the semiconductor substrate 1 of the IGBT cell is provided in the section near the center 100C of the IGBT region 100 (that is, an IGBT cell that is located in a middle section of the IGBT region 100).

[0085] Furthermore, as shown in Fig. Figure 3 shows the semiconductor device of the present example in a configuration in which the IGBT cell in the section near the center 100C of the IGBT area 100 (that is, the IGBT cell that is located in the center of the IGBT area 100) does not have the emitter layer 6.

[0086] In the IGBT cell in the section near the middle 100C of the IGBT area 100, while the risk of destruction in the RBSOA is high as described above, no latch-up destruction occurs because the parasitic thyristor structure is not formed due to the absence of emitter layer 6.

[0087] Here, the IGBT cell, at a position closer to the diode region 200 than to the center 100C of the IGBT region 100, has a configuration in which the emitter layers 6, covered by the body layer 5, are each in contact with the insulating films 21, as in Example 1, which is shown in Fig. 1 is shown.

[0088] According to the semiconductor device of the present example, since the IGBT cell lacks emitter layer 6 in the section near the center 100C of the IGBT area 100, the parasitic thyristor structure is not formed, and therefore latch-up destruction does not occur. Consequently, the RBSOA can be further improved.

[0089] As a modification of Example 3, it is also possible to combine the configuration in which the emitter layer 6 of Example 3 is not included with the configuration in which the low-concentration collector layer 2a of Example 2 is included. The RBSOA can be further improved by combining this with the configuration in which the low-concentration collector layer 2a of Example 2 is included.

[0090] In Example 3, similar to the semiconductor device from Example 1, which was used in Fig. Figure 1 shows the configuration in which the low lifetime region 300 is provided in the semiconductor substrate 1 of the IGBT cell in the section near the center 100C of the IGBT region 100, combined with the configuration in which the emitter layer 6 is not provided in the IGBT cell.

[0091] On the other hand, as a further modification of Example 3, it is also possible to assume a configuration in which the low-life region 300 is not included and the emitter layer 6 is not included in the IGBT cell in the section near the center 100C of the IGBT region 100. This configuration also allows for an improvement in the RBSOA.

[0092] Furthermore, the configuration in which the low-concentration collector layer 2a from Example 2 is provided can be combined with the configuration in which the low lifetime range 300 from Example 3 is removed.

[0093] Example 3 showed how in Fig. Figure 3 shows the IGBT cell in the section near the middle 100C of the IGBT area 100 a configuration without the emitter layer 6.

[0094] On the other hand, in the IGBT cell in the section near the middle 100C of the IGBT range 100, it is possible to improve the RBSOA by making the number of emitter layers 6 smaller than that in the IGBT cell in the other section of the IGBT range 100. This case is described below as Example 4. (Conventional structure)

[0095] Before describing the semiconductor device of Example 4, a semiconductor device of a conventional structure is presented here for comparison, with reference to Fig. 6 to Fig. 7 described.

[0096] Fig. Figure 6 is an enlarged cross-sectional view of a main part of a semiconductor device with a conventional backward-conducting IGBT. Fig. Figure 7 is a horizontal cross-sectional view along line XX' in Fig. 6 (a view in which a horizontal plane is drawn along line XX' in Fig. 6 (viewed from above).

[0097] The in Fig. The conventional structure shown in Figure 6 is such that the low-life range 300 is derived from the structure of Example 1, which is shown in Fig. 1 is shown, removed.

[0098] As in Fig. As shown in Figure 7, a specific number of emitter layers 6 of the first conductivity type are provided in the IGBT range 100. That is, both the IGBT cell in the section near the center 100C of the IGBT range 100 in Fig. Both the 6 and the IGBT cell in the section near a boundary to the diode area 200 of the IGBT area 100 have the same structure, and the number of emitter layers 6 is the same.

[0099] In the traditional structure, which in Fig. 6 to Fig. As shown in 7, they will be, since the one in Fig. Since the short-life region 300 shown in Figure 1 is not formed, in the IGBT cell, in the section near the center 100C of the IGBT region 100, carriers that accumulated in the semiconductor substrate 1 at the time of current conduction are hardly removed at the time of switch-off. Furthermore, in the IGBT cell, in the section near the center 100C of the IGBT region 100, the base current of the parasitic thyristor structure (emitter layer 6 / body layer 5 / semiconductor substrate 1 and buffer layer 4 / collector layer 2), which is inherent to the IGBT, causes a latch-up.

[0100] Therefore, in the conventional structure, which in Fig. 6 to Fig. As shown in Figure 7, in the IGBT cell in the section near the center 100C of the IGBT area 100, the barrier safety working area (RBSOA) is not improved, and destruction can occur in a concentrated manner. (Example 4)

[0101] Next, a configuration of a semiconductor device from Example 4 will be described with reference to Fig. 4 to Fig. 5 described.

[0102] Fig. Figure 4 is an enlarged cross-sectional view of a main part of the semiconductor device from Example 4. The enlarged cross-sectional view of Fig. Figure 4 shows the same structure as the enlarged cross-sectional view in Fig. 1 of Example 1.

[0103] Fig. Figure 5 is a horizontal cross-sectional view along line XX' in Fig. 4 (a view in which a horizontal plane is drawn along line XX' in Fig. 4 (viewed from above).

[0104] The same components are used here as in Fig. Example 1 is labelled with the same reference symbols, and a redundant description is omitted.

[0105] As in Fig. As shown in 4, according to the semiconductor device of the present example, similar to Example 1, the device in Fig. Figure 1 shows the low lifetime region 300, in which the lifetime of the carriers is shortened, in which the semiconductor substrate 1 of the IGBT cell is provided in the section near the center 100C of the IGBT region 100 (that is, an IGBT cell that is located in a middle section of the IGBT region 100).

[0106] Furthermore, as shown in Fig. Figure 5 shows the semiconductor device of the present example in a configuration in which the number of emitter layers 6 in the IGBT cell in the section near the center 100C of the IGBT area 100 (that is, the IGBT cell located in the center of the IGBT area 100) is smaller than in the IGBT cell in the other section of the IGBT area 100. Fig. 5 is achieved in the IGBT cell in the section near the center 100C of the IGBT area 100 by increasing the distances between the emitter layers 6 in the vertical direction in Fig. 5 the number of emitter layers 6 reduced to two thirds of those in the IGBT cells in the other section of the IGBT area 100.

[0107] Here, the ratio of emitter layers 6 in the IGBT cell in the section near the center 100C of the IGBT range 100 and the IGBT cell in the other section of the IGBT range 100 is not 2:3, as in Fig. 5 is shown, limited, and may be a different ratio.

[0108] According to the semiconductor device of the present example, since the IGBT cell in the section near the center 100C of the IGBT area 100 is configured to have emitter layers 6 in a number that is lower than that of the IGBT cell in the other section of the IGBT area 100, a parasitic thyristor structure is less likely to be formed, and latch-up destruction can be suppressed.

[0109] Consequently, it is possible to combine the RBSOA with the one in Fig. to further improve the 4 shown low lifetime range 300.

[0110] As a modification of Example 4, it is also possible to combine the configuration in which the number of emitter layer 6 from Example 4 is small with the configuration in which the low-concentration collector layer 2a from Example 2 is provided.

[0111] The RBSOA can be further improved by combining it with the configuration in which the low-concentration collector layer 2a of Example 2 is provided.

[0112] It should be noted that the present invention is not limited to the embodiments and examples described above and includes various modifications.

[0113] For example, the embodiments and examples described above have been described in detail for the ease of understanding of the present invention and are not necessarily limited to those that have all the described configurations. Reference symbol list 1 Semiconductor substrate 2 Collector layer 2a low concentration collector layer 2b highly concentrated collector layer 3 Cathode layer 4 Buffer layer 5 body layers 6 emitter layer 7 Barrier layer 10 Emitter electrode 11 Collector electrode 12 Gate electrode 13 In-trench emitter electrode 20 trenches 21 Insulating film 22 Interlayer insulating film 100 IGBT range 100°C Mid-range of the IGBT 200 diode range 300 Low lifespan range QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-59487 A

[0007]

Claims

[1] A semiconductor device comprising a backward-conducting IGBT, which includes an IGBT and a diode mounted on the same semiconductor substrate, the semiconductor device comprising: the semiconductor substrate of a first conductivity type; a first electrode that is in contact with a front surface of the semiconductor substrate; a second electrode that is in contact with a rear surface of the semiconductor substrate; a multitude of grooves provided on one side of the front surface of the semiconductor substrate; an insulating film that is provided in each of the trenches; a third electrode covered by the insulating film; a first semiconductor layer of a second conductivity type, wherein the first semiconductor layer is in contact with the second electrode in an IGBT area where the IGBT is provided; a second semiconductor layer of a first conductivity type, wherein the second semiconductor layer is in contact with the second electrode in a diode region in which the diode is provided; a third semiconductor layer of the first conductivity type, wherein the third semiconductor layer is in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, wherein the fourth semiconductor layer is in contact with the first electrode and the insulating film in the trench; fifth semiconductor layers of the first conductivity type, each of the fifth semiconductor layers in the IGBT area being in contact with the first electrode and the insulating film in the trench and surrounded by the fourth semiconductor layer; and a low lifetime region provided in the semiconductor substrate of an IGBT cell in a section near the center of the IGBT region. [2] The semiconductor device according to claim 1, wherein the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in a section other than the section near the center of the IGBT area. [3] The semiconductor device according to claim 1, wherein the fifth semiconductor layers in an IGBT cell are provided in a section other than the section near the center of the IGBT area, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT area. [4] The semiconductor device according to claim 3, wherein the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in the section other than the section near the center of the IGBT area. [5] The semiconductor device according to claim 1, wherein the number of fifth semiconductor layers in an IGBT cell in the section near the center of the IGBT area is smaller than in an IGBT cell in a section other than the section near the center of the IGBT area. [6] The semiconductor device according to claim 5, wherein the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in the section other than the section near the center of the IGBT area. [7] A semiconductor device comprising a backward-conducting IGBT, which includes an IGBT and a diode mounted on the same semiconductor substrate, the semiconductor device comprising: the semiconductor substrate of a first conductivity type; a first electrode that is in contact with a front surface of the semiconductor substrate; a second electrode that is in contact with a rear surface of the semiconductor substrate; a multitude of grooves provided on one side of the front surface of the semiconductor substrate; an insulating film that is provided in each of the trenches; a third electrode, which is covered by the insulating film; a first semiconductor layer of a second conductivity type, wherein the first semiconductor layer is in contact with the second electrode in an IGBT area in which the IGBT is provided; a second semiconductor layer of a first conductivity type, wherein the second semiconductor layer is in contact with the second electrode in a diode region in which the diode is provided; a third semiconductor layer of the first conductivity type, wherein the third semiconductor layer is in contact with the upper surfaces of the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, wherein the fourth semiconductor layer is in contact with the first electrode and the insulating film in the trench; and fifth semiconductor layers of the first conductivity type, wherein each of the fifth semiconductor layers in the IGBT region is in contact with the first electrode and the insulating film in the trench and is surrounded by the fourth semiconductor layer, wherein the fifth semiconductor layers in an IGBT cell are provided in a section other than a section near a center of the IGBT region, and no fifth semiconductor layer is provided in an IGBT cell in the section near the center of the IGBT region. [8] The semiconductor device according to claim 7, wherein the impurity concentration of the first semiconductor layer in the section near the center of the IGBT area is lower than the impurity concentration of the first semiconductor layer in the section other than the section near the center of the IGBT area.

Images